musl/arch/i386/atomic_arch.h
Rich Felker 5c3412d225 fix regression disabling use of pause instruction for x86 a_spin
commits e24984efd5 and
16b55298dc inadvertently disabled the
a_spin implementations for i386, x86_64, and x32 by defining a macro
named a_pause instead of a_spin. this should not have caused any
functional regression, but it inhibited cpu relaxation while spinning
for locks.

bug reported by George Kulakowski.
2016-03-29 21:27:28 -04:00

102 lines
1.9 KiB
C

#define a_cas a_cas
static inline int a_cas(volatile int *p, int t, int s)
{
__asm__ __volatile__ (
"lock ; cmpxchg %3, %1"
: "=a"(t), "=m"(*p) : "a"(t), "r"(s) : "memory" );
return t;
}
#define a_swap a_swap
static inline int a_swap(volatile int *p, int v)
{
__asm__ __volatile__(
"xchg %0, %1"
: "=r"(v), "=m"(*p) : "0"(v) : "memory" );
return v;
}
#define a_fetch_add a_fetch_add
static inline int a_fetch_add(volatile int *p, int v)
{
__asm__ __volatile__(
"lock ; xadd %0, %1"
: "=r"(v), "=m"(*p) : "0"(v) : "memory" );
return v;
}
#define a_and a_and
static inline void a_and(volatile int *p, int v)
{
__asm__ __volatile__(
"lock ; and %1, %0"
: "=m"(*p) : "r"(v) : "memory" );
}
#define a_or a_or
static inline void a_or(volatile int *p, int v)
{
__asm__ __volatile__(
"lock ; or %1, %0"
: "=m"(*p) : "r"(v) : "memory" );
}
#define a_inc a_inc
static inline void a_inc(volatile int *p)
{
__asm__ __volatile__(
"lock ; incl %0"
: "=m"(*p) : "m"(*p) : "memory" );
}
#define a_dec a_dec
static inline void a_dec(volatile int *p)
{
__asm__ __volatile__(
"lock ; decl %0"
: "=m"(*p) : "m"(*p) : "memory" );
}
#define a_store a_store
static inline void a_store(volatile int *p, int x)
{
__asm__ __volatile__(
"mov %1, %0 ; lock ; orl $0,(%%esp)"
: "=m"(*p) : "r"(x) : "memory" );
}
#define a_barrier a_barrier
static inline void a_barrier()
{
__asm__ __volatile__( "" : : : "memory" );
}
#define a_spin a_spin
static inline void a_spin()
{
__asm__ __volatile__( "pause" : : : "memory" );
}
#define a_crash a_crash
static inline void a_crash()
{
__asm__ __volatile__( "hlt" : : : "memory" );
}
#define a_ctz_64 a_ctz_64
static inline int a_ctz_64(uint64_t x)
{
int r;
__asm__( "bsf %1,%0 ; jnz 1f ; bsf %2,%0 ; add $32,%0\n1:"
: "=&r"(r) : "r"((unsigned)x), "r"((unsigned)(x>>32)) );
return r;
}
#define a_ctz_l a_ctz_l
static inline int a_ctz_l(unsigned long x)
{
long r;
__asm__( "bsf %1,%0" : "=r"(r) : "r"(x) );
return r;
}