mirror of
git://git.musl-libc.org/musl
synced 2025-03-01 09:10:25 +00:00
884cc0c7e2
as far as I can tell, microblaze is strongly ordered, but this does not seem to be well-documented and the assumption may need revisiting. even with strong ordering, however, a volatile C assignment is not sufficient to implement atomic store, since it does not preclude reordering by the compiler with respect to non-volatile stores and loads. simply flanking a C store with empty volatile asm blocks with memory clobbers would achieve the desired result, but is likely to result in worse code generation, since the address and value for the store may need to be spilled. actually writing the store in asm, so that there's only one asm block, should give optimal code generation while satisfying the requirement for having a compiler barrier.
146 lines
2.6 KiB
C
146 lines
2.6 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_l(unsigned long x)
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{
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static const char debruijn32[32] = {
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0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13,
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31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14
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};
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return debruijn32[(x&-x)*0x076be629 >> 27];
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}
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static inline int a_ctz_64(uint64_t x)
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{
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uint32_t y = x;
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if (!y) {
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y = x>>32;
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return 32 + a_ctz_l(y);
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}
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return a_ctz_l(y);
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}
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static inline int a_cas(volatile int *p, int t, int s)
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{
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register int old, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" rsubk %1, %0, %3\n"
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" bnei %1, 1f\n"
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" swx %4, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(t), "r"(s)
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: "cc", "memory" );
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return old;
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}
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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return (void *)a_cas(p, (int)t, (int)s);
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}
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static inline long a_cas_l(volatile void *p, long t, long s)
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{
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return a_cas(p, t, s);
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}
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static inline int a_swap(volatile int *x, int v)
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{
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register int old, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" swx %3, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(old), "=&r"(tmp)
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: "r"(x), "r"(v)
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: "cc", "memory" );
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return old;
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}
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static inline int a_fetch_add(volatile int *x, int v)
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{
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register int new, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" addk %0, %0, %3\n"
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" swx %0, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(new), "=&r"(tmp)
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: "r"(x), "r"(v)
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: "cc", "memory" );
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return new-v;
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}
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static inline void a_inc(volatile int *x)
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{
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a_fetch_add(x, 1);
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}
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static inline void a_dec(volatile int *x)
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{
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a_fetch_add(x, -1);
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}
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static inline void a_store(volatile int *p, int x)
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{
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__asm__ __volatile__ (
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"swi %1, %0"
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: "=m"(*p) : "r"(x) : "memory" );
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}
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static inline void a_spin()
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{
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}
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static inline void a_crash()
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{
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*(volatile char *)0=0;
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}
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static inline void a_and(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (a_cas(p, old, old&v) != old);
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}
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static inline void a_or(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (a_cas(p, old, old|v) != old);
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}
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static inline void a_or_l(volatile void *p, long v)
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{
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a_or(p, v);
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_and((int *)p, u.r[0]);
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a_and((int *)p+1, u.r[1]);
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_or((int *)p, u.r[0]);
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a_or((int *)p+1, u.r[1]);
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}
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#endif
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