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fix Radeon/Rage128 vidix with I420 colorspace (U/V were inverted) 

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@23672 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
ben 2007-06-26 17:07:30 +00:00
parent 85f88efe84
commit 88f6f92c54
1 changed files with 10 additions and 9 deletions
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15
vidix/radeon_vid.c
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@ -3054,11 +3054,19 @@ static int radeon_vid_init_video( vidix_playback_t *config )
besr.vid_buf_base_adrs_u[i]=0; besr.vid_buf_base_adrs_u[i]=0;
} }
else else
{
if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
{
besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
}
else
{ {
besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
} }
} }
}
config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off;
if(is_400) if(is_400)
{ {
@ -3070,13 +3078,6 @@ static int radeon_vid_init_video( vidix_playback_t *config )
config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
} }
if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
{
uint32_t tmp;
tmp = config->offset.u;
config->offset.u = config->offset.v;
config->offset.v = tmp;
}
} }
else else
{ {