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lavu/riscv: fix compilation without Vector support
The half-baked assembler in Clang 16 and earlier can't process our RISC-V assembler. This adds yet another work around that. If you must use Clang, please use version 17 or later.
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@ -56,7 +56,6 @@ static inline size_t ff_get_rv_vlenb(void)
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".option pop\n" : "=r" (vlenb));
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return vlenb;
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}
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#endif
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/**
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* Checks that the vector bit-size is at least the given value.
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@ -78,3 +77,4 @@ static inline bool ff_rv_vlen_least(unsigned int bits)
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return bits <= (8 * ff_get_rv_vlenb());
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}
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#endif
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#endif /* HAVE_RVV */
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