From e29432e6bbb6184d3ff2c7d1e070e9424cb25fe6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Sun, 17 Nov 2024 11:15:01 +0200
Subject: [PATCH] lavu/riscv: fix compilation without Vector support

The half-baked assembler in Clang 16 and earlier can't process our
RISC-V assembler. This adds yet another work around that.

If you must use Clang, please use version 17 or later.
---
 libavutil/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libavutil/riscv/cpu.h b/libavutil/riscv/cpu.h
index 191e4478c5..f2e6b7b430 100644
--- a/libavutil/riscv/cpu.h
+++ b/libavutil/riscv/cpu.h
@@ -56,7 +56,6 @@ static inline size_t ff_get_rv_vlenb(void)
         ".option pop\n" : "=r" (vlenb));
     return vlenb;
 }
-#endif
 
 /**
  * Checks that the vector bit-size is at least the given value.
@@ -78,3 +77,4 @@ static inline bool ff_rv_vlen_least(unsigned int bits)
     return bits <= (8 * ff_get_rv_vlenb());
 }
 #endif
+#endif /* HAVE_RVV */