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lavu/riscv: fix compilation without Vector support 

The half-baked assembler in Clang 16 and earlier can't process our
RISC-V assembler. This adds yet another work around that.

If you must use Clang, please use version 17 or later.

(cherry picked from commit e29432e6bb)
This commit is contained in:
Rémi Denis-Courmont 2024-11-17 11:15:01 +02:00
parent b016aae662
commit 20c8a3f5ff
1 changed files with 1 additions and 1 deletions
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2
libavutil/riscv/cpu.h
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@ -56,7 +56,6 @@ static inline size_t ff_get_rv_vlenb(void)
".option pop\n" : "=r" (vlenb)); ".option pop\n" : "=r" (vlenb));
return vlenb; return vlenb;
} }
#endif
/** /**
* Checks that the vector bit-size is at least the given value. * Checks that the vector bit-size is at least the given value.
@ -78,3 +77,4 @@ static inline bool ff_rv_vlen_least(unsigned int bits)
return bits <= (8 * ff_get_rv_vlenb()); return bits <= (8 * ff_get_rv_vlenb());
} }
#endif #endif
#endif /* HAVE_RVV */