diff --git a/main/linux-headers/0003-remove-inclusion-of-sysinfo.h-in-kernel.h.patch b/main/linux-headers/0003-remove-inclusion-of-sysinfo.h-in-kernel.h.patch new file mode 100644 index 0000000..f3381c4 --- /dev/null +++ b/main/linux-headers/0003-remove-inclusion-of-sysinfo.h-in-kernel.h.patch @@ -0,0 +1,29 @@ +From 8e69b663d6ddef132041a1186f081fdd74d4a31d Mon Sep 17 00:00:00 2001 +From: rofl0r +Date: Mon, 20 Jan 2014 21:31:34 +0100 +Subject: [PATCH 3/3] remove inclusion of sysinfo.h in kernel.h + +the declaration of struct sysinfo clashes with userspace. +it's not quite clear why that header was included from kernel.h, +as none of its functionality is needed. +--- +Signed-off-by: Khem Raj +Upstream-Status: Submitted + + include/uapi/linux/kernel.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/uapi/linux/kernel.h b/include/uapi/linux/kernel.h +index fadf2db71fe8..813800ed141f 100644 +--- a/include/uapi/linux/kernel.h ++++ b/include/uapi/linux/kernel.h +@@ -2,7 +2,9 @@ + #ifndef _UAPI_LINUX_KERNEL_H + #define _UAPI_LINUX_KERNEL_H + ++#ifdef __GLIBC__ + #include ++#endif + #include + + #endif /* _UAPI_LINUX_KERNEL_H */ diff --git a/main/linux-headers/APKBUILD b/main/linux-headers/APKBUILD new file mode 100644 index 0000000..296c859 --- /dev/null +++ b/main/linux-headers/APKBUILD @@ -0,0 +1,73 @@ +# Contributor: Natanael Copa +# Contributor: Alex Denes +# Maintainer: Alex Denes + + pkgname=linux-headers + _kver=5.13 + _kpatch=13 + pkgver=$_kver.$_kpatch + pkgrel=0 + +source=" + https://cdn.kernel.org/pub/linux/kernel/v${pkgver%%.*}.x/linux-$pkgver.tar.xz + include-uapi-linux-swab-Fix-potentially-missing-__always_inline.patch + 0003-remove-inclusion-of-sysinfo.h-in-kernel.h.patch +" + +_kabi= _klocalver= _kconfig= _kbdmain= _kbddev= _kflavor= +_kdir_src="$srcdir/linux-$pkgver" + +arch="noarch" +_depends_dev=" + perl + gmp-dev + elfutils-dev + bash + flex + bison +" +makedepends=" + $_depends_dev + sed + installkernel + bc + openssl-dev + diffutils + findutils +" + +pkgdesc="Linux Kernel - Headers" +url="https://www.kernel.org" +license="GPL-2.0" +options="!strip" +builddir="$_kdir_src" + +_carch=${CARCH} # abuild to kernel arch mapping +case "$_carch" in + aarch64*) _carch="arm64" ;; + arm*) _carch="arm" ;; + mips*) _carch="mips" ;; + ppc*) _carch="powerpc" ;; + s390*) _carch="s390" ;; +esac + +package() { + + local _outdir="$pkgdir/usr" + mkdir -p "$_outdir" + + cd "$_kdir_src" + make headers_install \ + ARCH="$_carch" \ + INSTALL_HDR_PATH="$_outdir" + + rm -f **/.install **/install.cmd + + rm -rf "$_outdir/include/drm" # provided by libdrm-dev +} + +sha512sums=" +67c3d0ef8fc378616a318a0d6796acf839dcda4accee3dc815c0f0697694cf178474fe15d98fa9bb7871dfa353aee416212430be5af85bf74647e3968b5c1b71 linux-5.13.13.tar.xz +7cfa786144009c52d682e307bb512156e4812d7abe03b3fed99651a02d80567d47ee6f347f88d083c1b9805e0c09625fc3df08a8d0ae96b169d24eb5b83917b7 include-uapi-linux-swab-Fix-potentially-missing-__always_inline.patch +607c074d72aca88fea9ecdbd62198d8f7857daca75e5d027966e0a9997338d6ac8ce0a1e9114b19232b390751d05acca09e28b0cfad2a12d5942f5575a9f4684 0003-remove-inclusion-of-sysinfo.h-in-kernel.h.patch +" diff --git a/main/linux-headers/include-uapi-linux-swab-Fix-potentially-missing-__always_inline.patch b/main/linux-headers/include-uapi-linux-swab-Fix-potentially-missing-__always_inline.patch new file mode 100644 index 0000000..3ef4477 --- /dev/null +++ b/main/linux-headers/include-uapi-linux-swab-Fix-potentially-missing-__always_inline.patch @@ -0,0 +1,55 @@ +From 2b7d2ece0b60b8f450f29119f28668dc74bb692e Mon Sep 17 00:00:00 2001 +From: Matt Redfearn +Date: Wed, 3 Jan 2018 09:57:30 +0000 +Subject: [PATCH] include/uapi/linux/swab: Fix potentially missing + __always_inline +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Commit bc27fb68aaad ("include/uapi/linux/byteorder, swab: force inlining +of some byteswap operations") added __always_inline to swab functions +and commit 283d75737837 ("uapi/linux/stddef.h: Provide __always_inline to +userspace headers") added a definition of __always_inline for use in +exported headers when the kernel's compiler.h is not available. + +However, since swab.h does not include stddef.h, if the header soup does +not indirectly include it, the definition of __always_inline is missing, +resulting in a compilation failure, which was observed compiling the +perf tool using exported headers containing this commit: + +In file included from /usr/include/linux/byteorder/little_endian.h:12:0, + from /usr/include/asm/byteorder.h:14, + from tools/include/uapi/linux/perf_event.h:20, + from perf.h:8, + from builtin-bench.c:18: +/usr/include/linux/swab.h:160:8: error: unknown type name ‘__always_inline’ + static __always_inline __u16 __swab16p(const __u16 *p) + +Fix this by replacing the inclusion of linux/compiler.h with +linux/stddef.h to ensure that we pick up that definition if required, +without relying on it's indirect inclusion. compiler.h is then included +indirectly, via stddef.h. + +Fixes: 283d75737837 ("uapi/linux/stddef.h: Provide __always_inline to userspace headers") +Signed-off-by: Matt Redfearn +--- + include/uapi/linux/swab.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/uapi/linux/swab.h b/include/uapi/linux/swab.h +index 7272f85d6d6a..3736f2fe1541 100644 +--- a/include/uapi/linux/swab.h ++++ b/include/uapi/linux/swab.h +@@ -3,7 +3,7 @@ + #define _UAPI_LINUX_SWAB_H + + #include +-#include ++#include + #include + #include + +-- +2.27.0 + diff --git a/main/linux/APKBUILD b/main/linux/APKBUILD new file mode 100644 index 0000000..678430f --- /dev/null +++ b/main/linux/APKBUILD @@ -0,0 +1,238 @@ +# Contributor: Natanael Copa +# Contributor: Alex Denes +# Maintainer: Alex Denes + + pkgname=linux + _kver=5.15 + _kpatch=12 + pkgver=$_kver.$_kpatch + pkgrel=2 + +_configs=" + config-full.x86_64 + config-slim.x86_64 + + config-rockpro64.aarch64 +" + +source=" + https://cdn.kernel.org/pub/linux/kernel/v${pkgver%%.*}.x/linux-$pkgver.tar.xz + $_configs + rtw89-add-Realtek-802.11ax-driver.patch +" + +_kabi= _klocalver= _kconfig= _kbdmain= _kbddev= _kflavor= +_kdir_src="$srcdir/linux-$pkgver" + +arch="noarch" +_depends_dev=" + perl + gmp-dev + elfutils-dev + bash + flex + bison +" +makedepends=" + $_depends_dev + sed + linux-headers + installkernel + bc + openssl-dev + diffutils + findutils +" + +pkgdesc="Linux Kernel - Metapackage" +url="https://www.kernel.org" +license="GPL-2.0" +options="!strip" +builddir="$_kdir_src" + +_carch=${CARCH} # abuild to kernel arch mapping +case "$_carch" in + aarch64*) _carch="arm64" ;; + arm*) _carch="arm" ;; + mips*) _carch="mips" ;; + ppc*) _carch="powerpc" ;; + s390*) _carch="s390" ;; +esac + +_archflavors() { + for i in $_configs; do + local _nocfg="${i#config-}" + local _arch="${_nocfg#*.}" + local _flavour="${_nocfg%.*}" + [ "$_arch" == "$CARCH" ] && echo "$_flavour" + done +} + +_bvars() { + _kconfig="config-$_kflavor.$CARCH" + _kdir_main="$srcdir/build-$_kflavor.$CARCH" + _kdir_dev="$srcdir/build-$_kflavor-dev.$CARCH" + + _ksaf="$_kflavor" + _kabi="$pkgver-$pkgrel-$_ksaf" + _klocalver="-$pkgrel-$_ksaf" +} + +_spvars() { + _kflavor="$(echo $subpkgname | cut -d- -f2)" +} + +for _kflavor in $(_archflavors); do + + _bvars + + subpackages=" + $subpackages + $pkgname-$_ksaf:_pkg_kernel:$CBUILD_ARCH + $pkgname-$_ksaf-dev:_pkg_extmod:$CBUILD_ARCH + " +done + +export KBUILD_BUILD_TIMESTAMP="$(date -Ru${SOURCE_DATE_EPOCH:+d @$SOURCE_DATE_EPOCH})" + +prepare() { + default_prepare + + for _kflavor in $(_archflavors); do + + _bvars + + for _kbuilddir in "$_kdir_main" "$_kdir_dev"; do + + mkdir -p "$_kbuilddir" + echo "$_klocalver" > "$_kbuilddir"/localversion-alpine \ + || return 1 + + cp "$srcdir"/"$_kconfig" "$_kbuilddir"/.config + + make -C "$_kdir_src" \ + O="$_kbuilddir" \ + ARCH="$_carch" \ + olddefconfig + + done + done +} + +build() { + unset LDFLAGS + + for _kflavor in $(_archflavors); do + + _bvars + + # Build kernel and modules + msg "Building $_kflavor for $CARCH" + cd "$_kdir_main" + make \ + ARCH="$_carch" \ + CC="${CC:-gcc}" \ + KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-Alpine" + + # Build out-of-tree builder + msg "Building $_kflavor-dev for $CARCH" + cd "$_kdir_dev" + make syncconfig \ + ARCH="$_carch" + make prepare \ + ARCH="$_carch" + make modules_prepare \ + ARCH="$_carch" + make scripts \ + ARCH="$_carch" + + done +} + +package() { + mkdir -p "$pkgdir" +} + +_pkg_kernel() { + + _spvars + _bvars + + local _install= + case "$CARCH" in + arm*|aarch64) _install="zinstall dtbs_install";; + *) _install=install;; + esac + + local _outdir="$subpkgdir" + mkdir -p "$_outdir"/boot "$_outdir"/lib/modules + + cd "$_kdir_main" + # Install modules + make modules_install \ + ARCH="$_carch" \ + INSTALL_MOD_PATH="$_outdir" + + # Install kernel + make $_install \ + ARCH="$_carch" \ + INSTALL_PATH="$_outdir"/boot \ + INSTALL_DTBS_PATH="$_outdir/boot/dtbs-$_ksaf" + + # Remove incorrect build-time symlinks + rm -f "$_outdir"/lib/modules/"$_kabi"/build \ + "$_outdir"/lib/modules/"$_kabi"/source + rm -rf "$_outdir"/lib/firmware + + # Install release file + install -D -m644 include/config/kernel.release \ + "$_outdir"/usr/share/kernel/"$_kflavor"/kernel.release +} + +_pkg_extmod() { + + _spvars + _bvars + + depends="$_depends_dev" + + local _outdir="$subpkgdir/usr/src/linux-headers-$_kabi" _builddir="$subpkgdir/lib/modules/$_kabi" + mkdir -p "$_outdir" + + cd "$_kdir_dev" + msg "Copying kernel out-of-tree build files" + rm Makefile source + cp -a . "$_outdir" + + cd "$_kdir_src" + msg "Copying kernel out-of-tree build tree" + cp -a scripts include "$_outdir" + find . \ + -path './include/*' -prune -o \ + -path './scripts/*' -prune -o \ + -type f \( \ + -name 'Makefile*' -o \ + -name 'Kconfig*' -o \ + -name 'Kbuild*' -o \ + -name '*.sh' -o \ + -name '*.pl' -o \ + -name '*.lds' -o \ + -name 'Platform' \ + \) -print | \ + cpio -pdm "$_outdir" + find ./arch \ + -path './arch/*/include/*' \ + -type f -print | \ + cpio -pdm "$_outdir" + + mkdir -p "$_builddir" + ln -sf "/usr/src/linux-headers-$_kabi" "$_builddir"/build +} + +sha512sums=" +8b79f30c26a865578d771b0c1a8273ecbf19135e4844210cb31c81784311601b8f7adfe1b3a9bc75c6bed99dcad9a5ff5e1976494b64f0de45be3a6570336890 linux-5.15.12.tar.xz +0db424b64b50a1ffda7a8591526eb3d4d77b97b74aeee49810ef05730f95622573775026073ce57e43b4389c5c2ba075be42c49b5c3fd5e745d8c6b948a77b62 config-full.x86_64 +acc7f183a6773d3de0e10c808cbfadb7b54b6f9fcf891234473adef449f87e04a486ed6ec3fae106d0ff10f0c4bc3224971319aeba03fbcaafb1590e89c5ae84 config-slim.x86_64 +ad69e8a63a9aae01191e751520dc50ed43397770b90b154e9b4fc5129765f29d93d36f219ee62dda9f3826fdc0e2b312aaaac2edc998c1a073efb1200ada1338 config-rockpro64.aarch64 +8c97361cf0b8cf8b4630198b69e318413bedd63c34ec8cc62604f4198cc66cdffb029ed9f719fa946e97aacece327cf72b1dc5bbf3c6b4c0391bf51be96135e2 rtw89-add-Realtek-802.11ax-driver.patch +" diff --git a/main/linux/config-full.x86_64 b/main/linux/config-full.x86_64 new file mode 100644 index 0000000..ca8f31f --- /dev/null +++ b/main/linux/config-full.x86_64 @@ -0,0 +1,9498 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86 5.15.12 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="gcc (Alpine 11.2.1_git20211128) 11.2.1 20211128" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=110201 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23700 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23700 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# CONFIG_BPF_LSM is not set +# end of BPF subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_SCHED_CORE is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +# CONFIG_NUMA_BALANCING is not set +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_NR_GPIO=1024 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_AUDIT_ARCH=y +CONFIG_HAVE_INTEL_TXT=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +CONFIG_X86_X2APIC=y +CONFIG_X86_MPPARSE=y +# CONFIG_GOLDFISH is not set +CONFIG_RETPOLINE=y +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_EXTENDED_PLATFORM=y +# CONFIG_X86_NUMACHIP is not set +# CONFIG_X86_VSMP is not set +# CONFIG_X86_GOLDFISH is not set +# CONFIG_X86_INTEL_MID is not set +CONFIG_X86_INTEL_LPSS=y +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_IOSF_MBI=y +# CONFIG_IOSF_MBI_DEBUG is not set +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +CONFIG_PARAVIRT_XXL=y +# CONFIG_PARAVIRT_DEBUG is not set +# CONFIG_PARAVIRT_SPINLOCKS is not set +CONFIG_X86_HV_CALLBACK_VECTOR=y +CONFIG_XEN=y +CONFIG_XEN_PV=y +CONFIG_XEN_512GB=y +CONFIG_XEN_PV_SMP=y +CONFIG_XEN_PV_DOM0=y +CONFIG_XEN_PVHVM=y +CONFIG_XEN_PVHVM_SMP=y +CONFIG_XEN_PVHVM_GUEST=y +CONFIG_XEN_SAVE_RESTORE=y +# CONFIG_XEN_DEBUG_FS is not set +CONFIG_XEN_PVH=y +CONFIG_XEN_DOM0=y +CONFIG_KVM_GUEST=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y +CONFIG_PVH=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_JAILHOUSE_GUEST is not set +# CONFIG_ACRN_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y +# CONFIG_PROCESSOR_SELECT is not set +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +CONFIG_GART_IOMMU=y +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=256 +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_AMD=y +CONFIG_X86_MCE_THRESHOLD=y +# CONFIG_X86_MCE_INJECT is not set + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=m +CONFIG_PERF_EVENTS_INTEL_CSTATE=m +CONFIG_PERF_EVENTS_AMD_POWER=m +CONFIG_PERF_EVENTS_AMD_UNCORE=y +# end of Performance monitoring + +# CONFIG_X86_16BIT is not set +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_IOPL_IOPERM=y +CONFIG_I8K=m +CONFIG_MICROCODE=y +CONFIG_MICROCODE_INTEL=y +CONFIG_MICROCODE_AMD=y +CONFIG_MICROCODE_OLD_INTERFACE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_X86_CPA_STATISTICS is not set +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +# CONFIG_NUMA_EMU is not set +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_X86_PMEM_LEGACY_DEVICE=y +CONFIG_X86_PMEM_LEGACY=y +# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_X86_PAT=y +CONFIG_ARCH_USES_PG_UNCACHED=y +CONFIG_ARCH_RANDOM=y +CONFIG_X86_SMAP=y +CONFIG_X86_UMIP=y +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +# CONFIG_X86_INTEL_TSX_MODE_OFF is not set +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +CONFIG_X86_INTEL_TSX_MODE_AUTO=y +# CONFIG_X86_SGX is not set +CONFIG_EFI=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_MIXED is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 +CONFIG_SCHED_HRTICK=y +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_X86_NEED_RELOCS=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_DYNAMIC_MEMORY_LAYOUT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0x0 +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_COMPAT_VDSO is not set +# CONFIG_LEGACY_VSYSCALL_EMULATE is not set +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +CONFIG_LEGACY_VSYSCALL_NONE=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_HAVE_LIVEPATCH=y +CONFIG_LIVEPATCH=y +# end of Processor type and features + +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y + +# +# Power management and ACPI options +# +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_SNAPSHOT_DEV is not set +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_SLEEP=y +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_EC_DEBUGFS=y +CONFIG_ACPI_AC=m +CONFIG_ACPI_BATTERY=m +CONFIG_ACPI_BUTTON=m +CONFIG_ACPI_TINY_POWER_BUTTON=m +CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38 +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_FAN=m +CONFIG_ACPI_TAD=m +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_IPMI=m +CONFIG_ACPI_HOTPLUG_CPU=y +# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set +CONFIG_ACPI_THERMAL=m +CONFIG_ACPI_PLATFORM_PROFILE=m +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=m +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_BGRT=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +CONFIG_ACPI_NUMA=y +# CONFIG_ACPI_HMAT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_APEI=y +# CONFIG_ACPI_APEI_GHES is not set +CONFIG_ACPI_APEI_PCIEAER=y +# CONFIG_ACPI_APEI_EINJ is not set +CONFIG_ACPI_APEI_ERST_DEBUG=y +# CONFIG_ACPI_DPTF is not set +CONFIG_ACPI_WATCHDOG=y +CONFIG_ACPI_EXTLOG=y +CONFIG_ACPI_ADXL=y +CONFIG_ACPI_CONFIGFS=m +CONFIG_PMIC_OPREGION=y +CONFIG_BXT_WC_PMIC_OPREGION=y +# CONFIG_CHT_DC_TI_PMIC_OPREGION is not set +CONFIG_X86_PM_TIMER=y +CONFIG_ACPI_PRMT=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +CONFIG_X86_PCC_CPUFREQ=m +CONFIG_X86_ACPI_CPUFREQ=m +CONFIG_X86_ACPI_CPUFREQ_CPB=y +CONFIG_X86_POWERNOW_K8=m +CONFIG_X86_AMD_FREQ_SENSITIVITY=m +CONFIG_X86_SPEEDSTEP_CENTRINO=m +CONFIG_X86_P4_CLOCKMOD=m + +# +# shared options +# +CONFIG_X86_SPEEDSTEP_LIB=m +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_HALTPOLL_CPUIDLE=y +# end of CPU Idle + +CONFIG_INTEL_IDLE=y +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_XEN=y +CONFIG_MMCONF_FAM10H=y +CONFIG_PCI_CNB20LE_QUIRK=y +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +CONFIG_AMD_NB=y +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +CONFIG_IA32_EMULATION=y +# CONFIG_X86_X32 is not set +CONFIG_COMPAT_32=y +CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_SYSVIPC_COMPAT=y +# end of Binary Emulations + +CONFIG_HAVE_KVM=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_ASYNC_PF=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_KVM_VFIO=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_COMPAT=y +CONFIG_HAVE_KVM_IRQ_BYPASS=y +CONFIG_HAVE_KVM_NO_POLL=y +CONFIG_KVM_XFER_TO_GUEST_WORK=y +CONFIG_HAVE_KVM_PM_NOTIFIER=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=m +# CONFIG_KVM_WERROR is not set +CONFIG_KVM_INTEL=m +CONFIG_KVM_AMD=m +CONFIG_KVM_AMD_SEV=y +# CONFIG_KVM_XEN is not set +# CONFIG_KVM_MMU_AUDIT is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y +CONFIG_AS_TPAUSE=y + +# +# General architecture-dependent options +# +CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set +CONFIG_OPTPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_KRETPROBES=y +CONFIG_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_ISA_BUS_API=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=m +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_MQ_RDMA=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_THP_SWAP=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZPOOL=m +# CONFIG_ZBUD is not set +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +CONFIG_VMAP_PFN=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_HAS_PKEYS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_MAPPING_DIRTY_HELPERS=y +CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +# CONFIG_XFRM_USER_COMPAT is not set +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +# CONFIG_SMC is not set +CONFIG_XDP_SOCKETS=y +# CONFIG_XDP_SOCKETS_DIAG is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +# CONFIG_IP_PIMSM_V1 is not set +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +# CONFIG_NFT_OBJREF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +# CONFIG_NFT_XFRM is not set +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +# CONFIG_NFT_REJECT_NETDEV is not set +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +# CONFIG_IP_VS_TWOS is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +# end of DECnet: Netfilter Configuration + +CONFIG_NF_TABLES_BRIDGE=m +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +# CONFIG_BPFILTER is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +# CONFIG_RDS_RDMA is not set +# CONFIG_RDS_TCP is not set +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +# CONFIG_L2TP_DEBUGFS is not set +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +# CONFIG_NET_DSA_TAG_AR9331 is not set +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +# CONFIG_NET_DSA_TAG_HELLCREEK is not set +# CONFIG_NET_DSA_TAG_GSWIP is not set +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +# CONFIG_NET_DSA_TAG_MTK is not set +# CONFIG_NET_DSA_TAG_KSZ is not set +CONFIG_NET_DSA_TAG_RTL4_A=m +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set +CONFIG_NET_DSA_TAG_QCA=m +# CONFIG_NET_DSA_TAG_LAN9303 is not set +# CONFIG_NET_DSA_TAG_SJA1105 is not set +CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_XRS700X is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_DECNET=m +CONFIG_DECNET_ROUTER=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_SAMPLE is not set +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VMWARE_VMCI_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +# CONFIG_HYPERV_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +# CONFIG_HSR is not set +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +# CONFIG_QRTR_SMD is not set +# CONFIG_QRTR_TUN is not set +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +# CONFIG_NCSI_OEM_CMD_GET_MAC is not set +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +# CONFIG_CAN_J1939 is not set +# CONFIG_CAN_ISOTP is not set + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_DEV=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_JANZ_ICAN3 is not set +# CONFIG_CAN_KVASER_PCIEFD is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_M_CAN is not set +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +# CONFIG_CAN_EMS_PCMCIA is not set +# CONFIG_CAN_F81601 is not set +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +# CONFIG_CAN_PEAK_PCMCIA is not set +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_SOFTING_CS is not set + +# +# CAN SPI interfaces +# +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +# CONFIG_CAN_ETAS_ES58X is not set +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set +# end of CAN Device Drivers + +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_CMTP=m +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_6LOWPAN is not set +CONFIG_BT_LEDS=y +# CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_FEATURE_DEBUG is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_BT_MTKSDIO is not set +CONFIG_BT_HCIRSI=m +# CONFIG_BT_VIRTIO is not set +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +# CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +# CONFIG_RFKILL_INPUT is not set +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_MEI_PHY=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +# CONFIG_NFC_VIRTUAL_NCI is not set +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN544_MEI=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MICROREAD_MEI=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +# CONFIG_NFC_NXP_NCI is not set +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +# CONFIG_NFC_ST95HF is not set +# end of Near Field Communication (NFC) devices + +# CONFIG_PSAMPLE is not set +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=m +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=m +CONFIG_PCI_PF_STUB=m +CONFIG_XEN_PCIDEV_FRONTEND=m +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_HYPERV=m +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m +CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_VMD=m +CONFIG_PCI_HYPERV_INTERFACE=m + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +# CONFIG_CXL_BUS is not set +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +CONFIG_DEBUG_DEVRES=y +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_SYS_HYPERVISOR=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_MMIO=m +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +# CONFIG_MHI_BUS_PCI_GENERIC is not set +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_EDD=m +# CONFIG_EDD_OFF is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_ISCSI_IBFT is not set +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=m +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +CONFIG_APPLE_PROPERTIES=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_EFI_DEV_PATH_PARSER=y +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +CONFIG_SM_FTL=m +CONFIG_MTD_OOPS=m +CONFIG_MTD_SWAP=m +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set +CONFIG_MTD_SBC_GXX=m +CONFIG_MTD_AMD76XROM=m +CONFIG_MTD_ICHXROM=m +CONFIG_MTD_ESB2ROM=m +CONFIG_MTD_CK804XROM=m +CONFIG_MTD_SCB2_FLASH=m +CONFIG_MTD_NETtel=m +CONFIG_MTD_L440GX=m +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +CONFIG_MTD_DATAFLASH=m +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +# CONFIG_SPI_INTEL_SPI_PCI is not set +# CONFIG_SPI_INTEL_SPI_PLATFORM is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_PC_PCMCIA=m +CONFIG_PARPORT_AX88796=m +# CONFIG_PARPORT_1284 is not set +CONFIG_PARPORT_NOT_PC=y +CONFIG_PNP=y +# CONFIG_PNP_DEBUG_MESSAGES is not set + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_BLK_DEV_FD=m +CONFIG_CDROM=m +# CONFIG_PARIDE is not set +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_WRITEBACK is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_SX8=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RSXX=m +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_PASSTHRU is not set +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +# CONFIG_NVME_TARGET_FC is not set +# CONFIG_NVME_TARGET_TCP is not set +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +# CONFIG_DUMMY_IRQ is not set +CONFIG_IBM_ASM=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_HP_ILO=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +CONFIG_VMWARE_BALLOON=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +CONFIG_MISC_RTSX=m +CONFIG_C2PORT=m +CONFIG_C2PORT_DURAMAR_2150=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +CONFIG_EEPROM_93XX46=m +# CONFIG_EEPROM_IDT_89HPESX is not set +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_I2C=m + +# +# Altera FPGA firmware download module (requires I2C) +# +CONFIG_ALTERA_STAPL=m +CONFIG_INTEL_MEI=m +CONFIG_INTEL_MEI_ME=m +CONFIG_INTEL_MEI_TXE=m +CONFIG_INTEL_MEI_HDCP=m +CONFIG_VMWARE_VMCI=m +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set +CONFIG_AIC7XXX_DEBUG_ENABLE=y +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +# CONFIG_AIC79XX_BUILD_FIRMWARE is not set +CONFIG_AIC79XX_DEBUG_ENABLE=y +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +CONFIG_SCSI_MVSAS_DEBUG=y +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_DPT_I2O=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +# CONFIG_SCSI_MPI3MR is not set +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +# CONFIG_SCSI_UFSHCD_PLATFORM is not set +# CONFIG_SCSI_UFS_BSG is not set +# CONFIG_SCSI_UFS_HPB is not set +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_VMWARE_PVSCSI=m +CONFIG_XEN_SCSI_FRONTEND=m +CONFIG_HYPERV_STORAGE=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_FCOE_FNIC=m +# CONFIG_SCSI_SNIC is not set +CONFIG_SCSI_DMX3191D=m +# CONFIG_SCSI_FDOMAIN_PCI is not set +CONFIG_SCSI_ISCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +# CONFIG_SCSI_PPA is not set +# CONFIG_SCSI_IMM is not set +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +# CONFIG_SCSI_IPR_DUMP is not set +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +# CONFIG_QEDI is not set +# CONFIG_QEDF is not set +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +# CONFIG_SCSI_EFCT is not set +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PM8001=m +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_VIRTIO=m +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=m +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=m +CONFIG_SATA_MOBILE_LPM_POLICY=3 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +# CONFIG_SATA_DWC is not set +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_HPT3X3_DMA=y +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PLATFORM=m +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_PATA_ACPI=m +CONFIG_ATA_GENERIC=m +CONFIG_PATA_LEGACY=m +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +# CONFIG_MD_AUTODETECT is not set +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +# CONFIG_MD_CLUSTER is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +# CONFIG_NET_FC is not set +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +# CONFIG_IPVTAP is not set +CONFIG_VXLAN=m +CONFIG_GENEVE=m +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +# CONFIG_VSOCKMON is not set +# CONFIG_MHI_NET is not set +CONFIG_SUNGEM_PHY=m +CONFIG_ARCNET=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RIM_I=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_ARCNET_COM20020_CS=m +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FIRESTREAM=m +CONFIG_ATM_ZATM=m +# CONFIG_ATM_ZATM_DEBUG is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_AMBASSADOR=m +# CONFIG_ATM_AMBASSADOR_DEBUG is not set +CONFIG_ATM_HORIZON=m +# CONFIG_ATM_HORIZON_DEBUG is not set +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +# CONFIG_B53_SERDES is not set +CONFIG_NET_DSA_BCM_SF2=m +# CONFIG_NET_DSA_LOOP is not set +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +# CONFIG_NET_DSA_MT7530 is not set +CONFIG_NET_DSA_MV88E6060=m +# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +# CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_XRS700X_I2C is not set +# CONFIG_NET_DSA_XRS700X_MDIO is not set +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_REALTEK_SMI=m +# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set +# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_ET131X is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_ALTERA_TSE=m +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +# CONFIG_AMD_XGBE is not set +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +# CONFIG_SYSTEMPORT is not set +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +# CONFIG_MACB_PCI is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_CX_ECAT is not set +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_DE4X5=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_E1000E_HWTS=y +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGB_DCA=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCA=y +CONFIG_IXGBEVF=m +CONFIG_I40E=m +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +# CONFIG_FM10K is not set +CONFIG_IGC=m +CONFIG_NET_VENDOR_MICROSOFT=y +# CONFIG_MICROSOFT_MANA is not set +CONFIG_JME=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +# CONFIG_PRESTERA is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_SAMPLE=y +# CONFIG_MLX5_CORE_IPOIB is not set +CONFIG_MLX5_SW_STEERING=y +# CONFIG_MLX5_SF is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +# CONFIG_NET_VENDOR_MICROSEMI is not set +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_MYRI10GE_DCA=y +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_VXGE=m +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +# CONFIG_NFP_APP_FLOWER is not set +# CONFIG_NFP_APP_ABM_NIC is not set +# CONFIG_NFP_DEBUG is not set +# CONFIG_NET_VENDOR_NI is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +# CONFIG_NET_VENDOR_QUALCOMM is not set +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_ATP=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +# CONFIG_NET_VENDOR_SAMSUNG is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +# CONFIG_SFC_FALCON is not set +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +# CONFIG_STMMAC_PLATFORM is not set +CONFIG_DWMAC_INTEL=m +# CONFIG_DWMAC_LOONGSON is not set +# CONFIG_STMMAC_PCI is not set +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +# CONFIG_VIA_RHINE_MMIO is not set +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=y +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_NET_SB1000=m +CONFIG_PHYLINK=m +CONFIG_PHYLIB=m +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=m +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +# CONFIG_ADIN_PHY is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +# CONFIG_BCM54140_PHY is not set +CONFIG_BCM7XXX_PHY=m +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +# CONFIG_CORTINA_PHY is not set +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=m +# CONFIG_MOTORCOMM_PHY is not set +CONFIG_NATIONAL_PHY=m +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +# CONFIG_DP83TC811_PHY is not set +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_DP83869_PHY is not set +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +CONFIG_MDIO_DEVICE=m +CONFIG_MDIO_BUS=m +CONFIG_FWNODE_MDIO=m +CONFIG_ACPI_MDIO=m +CONFIG_MDIO_DEVRES=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +# CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_AHB=y +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH9K_RFKILL=y +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +# CONFIG_ATH9K_PCI_NO_EEPROM is not set +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +# CONFIG_ATH9K_HWRNG is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_ATH6KL_DEBUG=y +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +# CONFIG_WIL6210_TRACING is not set +CONFIG_WIL6210_DEBUGFS=y +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +# CONFIG_ATH11K_TRACING is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +CONFIG_B43LEGACY_DEBUG=y +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO=m +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +# CONFIG_IPW2200_DEBUG is not set +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y +# CONFIG_IWLWIFI_BCAST_FILTERING is not set + +# +# Debugging Options +# +# CONFIG_IWLWIFI_DEBUG is not set +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +# CONFIG_HERMES_PRISM is not set +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +# CONFIG_P54_SPI_DEFAULT_EEPROM is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +# CONFIG_MT76x0E is not set +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +# CONFIG_MT7921E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +# CONFIG_RT2800PCI_RT35XX is not set +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +# CONFIG_RT2800USB_RT35XX is not set +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW89=m +CONFIG_RTW89_CORE=m +CONFIG_RTW89_PCI=m +CONFIG_RTW89_8852AE=m +# CONFIG_RTW89_DEBUGMSG is not set +# CONFIG_RTW89_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +CONFIG_RSI_DEBUGFS=y +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +CONFIG_WLCORE_SDIO=m +CONFIG_WILINK_PLATFORM_DATA=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_QTNFMAC_PCIE is not set +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_ADF7242=m +# CONFIG_IEEE802154_CA8210 is not set +CONFIG_IEEE802154_MCR20A=m +# CONFIG_IEEE802154_HWSIM is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + +CONFIG_XEN_NETDEV_FRONTEND=y +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_VMXNET3=m +CONFIG_FUJITSU_ES=m +CONFIG_HYPERV_NET=m +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=m +CONFIG_ISDN=y +CONFIG_ISDN_CAPI=y +CONFIG_CAPI_TRACE=y +CONFIG_ISDN_CAPI_MIDDLEWARE=y +CONFIG_MISDN=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_L1OIP=m + +# +# mISDN hardware drivers +# +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_MISDN_HFCUSB=m +CONFIG_MISDN_AVMFRITZ=m +# CONFIG_MISDN_SPEEDFAX is not set +# CONFIG_MISDN_INFINEON is not set +# CONFIG_MISDN_W6692 is not set +# CONFIG_MISDN_NETJET is not set +CONFIG_MISDN_IPAC=m + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_APPLESPI=m +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_GPIO_POLLED=m +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +# CONFIG_MOUSE_PS2_BYD is not set +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_VMMOUSE=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADC is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_DB9 is not set +# CONFIG_JOYSTICK_GAMECON is not set +# CONFIG_JOYSTICK_TURBOGRAFX is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +# CONFIG_JOYSTICK_WALKERA0701 is not set +# CONFIG_JOYSTICK_PSXPAD_SPI is not set +# CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set +# CONFIG_JOYSTICK_FSIA6B is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +# CONFIG_TOUCHSCREEN_ADC is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +CONFIG_TOUCHSCREEN_BU21013=m +# CONFIG_TOUCHSCREEN_BU21029 is not set +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +CONFIG_TOUCHSCREEN_CY8CTMG110=m +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +# CONFIG_TOUCHSCREEN_EXC3000 is not set +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_UCB1400=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +# CONFIG_TOUCHSCREEN_USB_EASYTOUCH is not set +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m +# CONFIG_TOUCHSCREEN_SX8654 is not set +CONFIG_TOUCHSCREEN_TPS6507X=m +# CONFIG_TOUCHSCREEN_ZET6223 is not set +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +# CONFIG_INPUT_BMA150 is not set +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_APANEL=m +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +CONFIG_INPUT_ATLAS_BTNS=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF50633_PMU=m +CONFIG_INPUT_PCF8574=m +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +# CONFIG_INPUT_DA7280_HAPTICS is not set +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m +# CONFIG_INPUT_DRV260X_HAPTICS is not set +CONFIG_INPUT_DRV2665_HAPTICS=m +# CONFIG_INPUT_DRV2667_HAPTICS is not set +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +# CONFIG_RMI4_F3A is not set +# CONFIG_RMI4_F54 is not set +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_CT82C710=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_HYPERV_KEYBOARD=m +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LDISC_AUTOLOAD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_LPSS=m +CONFIG_SERIAL_8250_MID=m + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MAX3100=m +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_LANTIQ is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 +CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +# CONFIG_N_GSM is not set +CONFIG_NOZOMI=m +# CONFIG_NULL_TTY is not set +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=m +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_PLAT_DATA=y +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_HW_RANDOM=m +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_INTEL=m +CONFIG_HW_RANDOM_AMD=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIA=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_APPLICOM=m + +# +# PCMCIA character devices +# +CONFIG_SYNCLINK_CS=m +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +# CONFIG_SCR24X is not set +CONFIG_IPWIRELESS=m +# end of PCMCIA character devices + +CONFIG_MWAVE=m +CONFIG_DEVMEM=y +CONFIG_NVRAM=m +CONFIG_DEVPORT=y +CONFIG_HPET=y +# CONFIG_HPET_MMAP is not set +CONFIG_HANGCHECK_TIMER=m +CONFIG_TCG_TPM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=m +CONFIG_TCG_TIS=m +# CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_CR50 is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +# CONFIG_TCG_TIS_I2C_INFINEON is not set +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +CONFIG_TCG_NSC=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_INFINEON=m +CONFIG_TCG_XEN=m +CONFIG_TCG_CRB=m +# CONFIG_TCG_VTPM_PROXY is not set +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +CONFIG_TELCLOCK=m +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD756_S4882=m +CONFIG_I2C_AMD8111=m +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_ISMT=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NFORCE2_S4985=m +# CONFIG_I2C_NVIDIA_GPU is not set +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m + +# +# ACPI drivers +# +CONFIG_I2C_SCMI=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=m +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_XILINX=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +# CONFIG_I2C_CP2615 is not set +CONFIG_I2C_PARPORT=m +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# CONFIG_I2C_VIRTIO is not set +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +CONFIG_SPI_BUTTERFLY=m +# CONFIG_SPI_CADENCE is not set +CONFIG_SPI_DESIGNWARE=m +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_PCI=m +# CONFIG_SPI_DW_MMIO is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +CONFIG_SPI_GPIO=m +CONFIG_SPI_LM70_LLP=m +# CONFIG_SPI_LANTIQ_SSC is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_PXA2XX=m +CONFIG_SPI_PXA2XX_PCI=m +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +CONFIG_SPI_XCOMM=m +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_TLE62X0=m +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_DYNAMIC=y +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_DP83640_PHY=m +# CONFIG_PTP_1588_CLOCK_INES is not set +CONFIG_PTP_1588_CLOCK_KVM=m +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +CONFIG_PTP_1588_CLOCK_VMW=m +# CONFIG_PTP_1588_CLOCK_OCP is not set +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AMD=y +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_BAYTRAIL=y +CONFIG_PINCTRL_CHERRYVIEW=y +# CONFIG_PINCTRL_LYNXPOINT is not set +CONFIG_PINCTRL_INTEL=y +# CONFIG_PINCTRL_ALDERLAKE is not set +# CONFIG_PINCTRL_BROXTON is not set +CONFIG_PINCTRL_CANNONLAKE=m +CONFIG_PINCTRL_CEDARFORK=m +# CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_ELKHARTLAKE is not set +# CONFIG_PINCTRL_EMMITSBURG is not set +# CONFIG_PINCTRL_GEMINILAKE is not set +CONFIG_PINCTRL_ICELAKE=m +# CONFIG_PINCTRL_JASPERLAKE is not set +# CONFIG_PINCTRL_LAKEFIELD is not set +# CONFIG_PINCTRL_LEWISBURG is not set +CONFIG_PINCTRL_SUNRISEPOINT=m +# CONFIG_PINCTRL_TIGERLAKE is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIO_ACPI=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_MAX730X=m + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +CONFIG_GPIO_ICH=m +# CONFIG_GPIO_MB86S7X is not set +CONFIG_GPIO_VX855=m +CONFIG_GPIO_AMD_FCH=m +# end of Memory mapped GPIO drivers + +# +# Port-mapped I/O GPIO drivers +# +# CONFIG_GPIO_F7188X is not set +# CONFIG_GPIO_IT87 is not set +CONFIG_GPIO_SCH=m +# CONFIG_GPIO_SCH311X is not set +CONFIG_GPIO_WINBOND=m +CONFIG_GPIO_WS16C48=m +# end of Port-mapped I/O GPIO drivers + +# +# I2C GPIO expanders +# +CONFIG_GPIO_ADP5588=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +CONFIG_GPIO_PCF857X=m +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_JANZ_TTL=m +CONFIG_GPIO_UCB1400=m +CONFIG_GPIO_WHISKEY_COVE=m +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +CONFIG_GPIO_AMD8111=m +CONFIG_GPIO_BT8XX=m +CONFIG_GPIO_ML_IOH=m +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +CONFIG_GPIO_RDC321X=m +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX3191X is not set +CONFIG_GPIO_MAX7301=m +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set +# end of Virtual GPIO drivers + +# CONFIG_W1 is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_GENERIC_ADC_BATTERY=m +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_PCF50633 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=m +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_ABITUGURU=m +CONFIG_SENSORS_ABITUGURU3=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +# CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_FAM15H_POWER=m +CONFIG_SENSORS_APPLESMC=m +CONFIG_SENSORS_ASB100=m +# CONFIG_SENSORS_ASPEED is not set +CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DRIVETEMP is not set +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DELL_SMM=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FSCHMD=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_HIH6130 is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_I5500=m +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +CONFIG_SENSORS_LTC2990=m +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX31722=m +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MLXREG_FAN=m +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_MR75203 is not set +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_ADM1266 is not set +CONFIG_SENSORS_ADM1275=m +# CONFIG_SENSORS_BEL_PFE is not set +# CONFIG_SENSORS_BPA_RS600 is not set +# CONFIG_SENSORS_FSP_3Y is not set +# CONFIG_SENSORS_IBM_CFFPS is not set +# CONFIG_SENSORS_DPS920AB is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +# CONFIG_SENSORS_MAX16601 is not set +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +# CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_PIM4328 is not set +# CONFIG_SENSORS_PM6764TR is not set +# CONFIG_SENSORS_PXE1610 is not set +# CONFIG_SENSORS_Q54SJ108A2 is not set +# CONFIG_SENSORS_STPDDC60 is not set +CONFIG_SENSORS_TPS40422=m +# CONFIG_SENSORS_TPS53679 is not set +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +# CONFIG_SENSORS_XDPE122 is not set +CONFIG_SENSORS_ZL6100=m +# CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +# CONFIG_SENSORS_STTS751 is not set +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +# CONFIG_SENSORS_INA2XX is not set +CONFIG_SENSORS_INA3221=m +# CONFIG_SENSORS_TC74 is not set +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +# CONFIG_SENSORS_TMP108 is not set +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP513 is not set +CONFIG_SENSORS_VIA_CPUTEMP=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83795_FANCTRL=y +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +# CONFIG_SENSORS_XGENE is not set + +# +# ACPI drivers +# +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_SENSORS_ATK0110=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_DEVFREQ_THERMAL is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +CONFIG_INTEL_POWERCLAMP=m +CONFIG_X86_THERMAL_VECTOR=y +CONFIG_X86_PKG_TEMP_THERMAL=m +CONFIG_INTEL_SOC_DTS_IOSF_CORE=m +CONFIG_INTEL_SOC_DTS_THERMAL=m + +# +# ACPI INT340X thermal drivers +# +CONFIG_INT340X_THERMAL=m +CONFIG_ACPI_THERMAL_REL=m +CONFIG_INT3406_THERMAL=m +CONFIG_PROC_THERMAL_MMIO_RAPL=m +# end of ACPI INT340X thermal drivers + +CONFIG_INTEL_BXT_PMIC_THERMAL=m +CONFIG_INTEL_PCH_THERMAL=m +# CONFIG_INTEL_TCC_COOLING is not set +CONFIG_INTEL_MENLOW=m +# end of Intel thermal drivers + +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +CONFIG_WATCHDOG_SYSFS=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_WDAT_WDT=m +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_MLX_WDT is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_MAX63XX_WATCHDOG=m +CONFIG_ACQUIRE_WDT=m +CONFIG_ADVANTECH_WDT=m +CONFIG_ALIM1535_WDT=m +CONFIG_ALIM7101_WDT=m +CONFIG_EBC_C384_WDT=m +CONFIG_F71808E_WDT=m +CONFIG_SP5100_TCO=m +# CONFIG_SBC_FITPC2_WATCHDOG is not set +CONFIG_EUROTECH_WDT=m +CONFIG_IB700_WDT=m +CONFIG_IBMASR=m +CONFIG_WAFER_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_IE6XX_WDT=m +CONFIG_ITCO_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +CONFIG_IT8712F_WDT=m +CONFIG_IT87_WDT=m +# CONFIG_HP_WATCHDOG is not set +CONFIG_SC1200_WDT=m +CONFIG_PC87413_WDT=m +CONFIG_NV_TCO=m +CONFIG_60XX_WDT=m +CONFIG_CPU5_WDT=m +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_SMSC37B787_WDT=m +# CONFIG_TQMX86_WDT is not set +CONFIG_VIA_WDT=m +CONFIG_W83627HF_WDT=m +CONFIG_W83877F_WDT=m +CONFIG_W83977F_WDT=m +CONFIG_MACHZ_WDT=m +CONFIG_SBC_EPX_C3_WATCHDOG=m +CONFIG_INTEL_MEI_WDT=m +# CONFIG_NI903X_WDT is not set +# CONFIG_NIC7018_WDT is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_XEN_WDT=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=m +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +CONFIG_HTC_PASIC3=m +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_INTEL_SOC_PMIC_BXTWC=m +CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m +CONFIG_MFD_INTEL_LPSS=m +CONFIG_MFD_INTEL_LPSS_ACPI=m +CONFIG_MFD_INTEL_LPSS_PCI=m +CONFIG_MFD_INTEL_PMC_BXT=m +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set +CONFIG_MFD_JANZ_CMODIO=m +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +CONFIG_MFD_PCF50633=m +CONFIG_PCF50633_ADC=m +CONFIG_PCF50633_GPIO=m +CONFIG_UCB1400_CORE=m +CONFIG_MFD_RDC321X=m +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SM501=m +# CONFIG_MFD_SM501_GPIO is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +CONFIG_MFD_WL1273_CORE=m +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +CONFIG_MFD_VX855=m +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PCF50633 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_RC_CORE=m +CONFIG_RC_MAP=m +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_IR_IMON_DECODER=m +# CONFIG_IR_RCMM_DECODER is not set +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_ENE=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_FINTEK=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_LOOPBACK=m +CONFIG_IR_SERIAL=m +# CONFIG_IR_SERIAL_TRANSMITTER is not set +# CONFIG_IR_SIR is not set +# CONFIG_RC_XBOX_DVD is not set +# CONFIG_IR_TOY is not set +CONFIG_CEC_CORE=m +# CONFIG_MEDIA_CEC_RC is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=m +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +CONFIG_VIDEOBUF_VMALLOC=m +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +# CONFIG_USB_GSPCA_KONICA is not set +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +# CONFIG_USB_GSPCA_SPCA1528 is not set +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m + +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_CXUSB_ANALOG is not set +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +# CONFIG_DVB_USB_ZD1301 is not set +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +# CONFIG_SMS_USB_DRV is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_MEYE=m +CONFIG_VIDEO_SOLO6X10=m +# CONFIG_VIDEO_TW5864 is not set +# CONFIG_VIDEO_TW68 is not set +CONFIG_VIDEO_TW686X=m + +# +# Media capture/analog TV support +# +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_DT3155 is not set + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +# CONFIG_VIDEO_BT848 is not set +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7164=m +# CONFIG_VIDEO_COBALT is not set + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_PT1=m +# CONFIG_DVB_PT3 is not set +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_VIDEO_IPU3_CIO2=m +# CONFIG_CIO2_BRIDGE is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +# CONFIG_RADIO_WL128X is not set +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=m + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +CONFIG_VIDEO_SAA711X=m +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips + +# +# Camera sensor devices +# +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set +CONFIG_VIDEO_OV2640=m +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +CONFIG_VIDEO_MT9V011=m +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +# CONFIG_MEDIA_TUNER_MSI001 is not set +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +# CONFIG_MEDIA_TUNER_MXL301RF is not set +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP887X is not set +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +# CONFIG_DVB_S5H1432 is not set +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_SI2168=m +# CONFIG_DVB_ZD1301_DEMOD is not set +CONFIG_DVB_GP8PSK_FE=m +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51211 is not set +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m +# CONFIG_DVB_MN88443X is not set + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +# CONFIG_DVB_LNBH29 is not set +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +# CONFIG_DVB_LGS8GL5 is not set +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_AGP=m +CONFIG_AGP_AMD64=m +CONFIG_AGP_INTEL=m +CONFIG_AGP_SIS=m +CONFIG_AGP_VIA=m +CONFIG_INTEL_GTT=m +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_SWITCHEROO=y +CONFIG_DRM=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_CHARDEV=y +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN=y +CONFIG_DRM_AMD_DC_HDCP=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set +# end of Display Engine Configuration + +CONFIG_HSA_AMD=y +CONFIG_DRM_NOUVEAU=m +CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_I915=m +CONFIG_DRM_I915_FORCE_PROBE="" +CONFIG_DRM_I915_CAPTURE_ERROR=y +CONFIG_DRM_I915_COMPRESS_ERROR=y +CONFIG_DRM_I915_USERPTR=y +CONFIG_DRM_I915_GVT=y + +# +# drm/i915 Debugging +# +# CONFIG_DRM_I915_WERROR is not set +# CONFIG_DRM_I915_DEBUG is not set +# CONFIG_DRM_I915_DEBUG_MMIO is not set +# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set +# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set +# CONFIG_DRM_I915_DEBUG_GUC is not set +# CONFIG_DRM_I915_SELFTEST is not set +# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set +# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set +# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set +# end of drm/i915 Debugging + +# +# drm/i915 Profile Guided Optimisation +# +CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 +CONFIG_DRM_I915_FENCE_TIMEOUT=10000 +CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 +CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 +CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 +CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 +CONFIG_DRM_I915_STOP_TIMEOUT=100 +CONFIG_DRM_I915_TIMESLICE_DURATION=1 +# end of drm/i915 Profile Guided Optimisation + +CONFIG_DRM_VGEM=m +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_VMWGFX=m +CONFIG_DRM_VMWGFX_FBCON=y +# CONFIG_DRM_VMWGFX_MKSSTATS is not set +CONFIG_DRM_GMA500=m +# CONFIG_DRM_UDL is not set +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_XEN_FRONTEND is not set +CONFIG_DRM_VBOXVIDEO=m +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HYPERV is not set +CONFIG_DRM_LEGACY=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_I810 is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_SIS is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DDC=m +CONFIG_FB_BOOT_VESA_SUPPORT=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_HECUBA=m +CONFIG_FB_SVGALIB=m +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +CONFIG_FB_CIRRUS=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_CYBER2000=m +CONFIG_FB_CYBER2000_DDC=y +CONFIG_FB_ARC=m +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_VGA16=m +CONFIG_FB_UVESA=m +CONFIG_FB_VESA=y +CONFIG_FB_EFI=y +CONFIG_FB_N411=m +CONFIG_FB_HGA=m +# CONFIG_FB_OPENCORES is not set +CONFIG_FB_S1D13XXX=m +CONFIG_FB_NVIDIA=m +CONFIG_FB_NVIDIA_I2C=y +# CONFIG_FB_NVIDIA_DEBUG is not set +CONFIG_FB_NVIDIA_BACKLIGHT=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_I2C=y +# CONFIG_FB_RIVA_DEBUG is not set +CONFIG_FB_RIVA_BACKLIGHT=y +# CONFIG_FB_I740 is not set +CONFIG_FB_LE80578=m +CONFIG_FB_CARILLO_RANCH=m +CONFIG_FB_INTEL=m +# CONFIG_FB_INTEL_DEBUG is not set +CONFIG_FB_INTEL_I2C=y +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_RADEON=m +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_ATY128=m +CONFIG_FB_ATY128_BACKLIGHT=y +CONFIG_FB_ATY=m +CONFIG_FB_ATY_CT=y +CONFIG_FB_ATY_GENERIC_LCD=y +CONFIG_FB_ATY_GX=y +CONFIG_FB_ATY_BACKLIGHT=y +CONFIG_FB_S3=m +CONFIG_FB_S3_DDC=y +CONFIG_FB_SAVAGE=m +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SAVAGE_ACCEL=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_VIA=m +# CONFIG_FB_VIA_DIRECT_PROCFS is not set +CONFIG_FB_VIA_X_COMPATIBILITY=y +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_KYRO=m +CONFIG_FB_3DFX=m +CONFIG_FB_3DFX_ACCEL=y +CONFIG_FB_3DFX_I2C=y +CONFIG_FB_VOODOO1=m +CONFIG_FB_VT8623=m +CONFIG_FB_TRIDENT=m +CONFIG_FB_ARK=m +CONFIG_FB_PM3=m +CONFIG_FB_CARMINE=m +CONFIG_FB_CARMINE_DRAM_EVAL=y +# CONFIG_CARMINE_DRAM_CUSTOM is not set +CONFIG_FB_SM501=m +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_XEN_FBDEV_FRONTEND=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +CONFIG_FB_HYPERV=m +CONFIG_FB_SIMPLE=y +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_L4F00242T03=m +CONFIG_LCD_LMS283GF05=m +CONFIG_LCD_LTV350QV=m +# CONFIG_LCD_ILI922X is not set +CONFIG_LCD_ILI9320=m +CONFIG_LCD_TDO24M=m +CONFIG_LCD_VGG2432A4=m +CONFIG_LCD_PLATFORM=m +CONFIG_LCD_AMS369FG06=m +CONFIG_LCD_LMS501KF03=m +CONFIG_LCD_HX8357=m +# CONFIG_LCD_OTM3225A is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +CONFIG_BACKLIGHT_CARILLO_RANCH=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_APPLE=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BACKLIGHT_SAHARA=m +CONFIG_BACKLIGHT_ADP8860=m +# CONFIG_BACKLIGHT_ADP8870 is not set +CONFIG_BACKLIGHT_PCF50633=m +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_DMA_SGBUF=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_PCSP=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_SB_COMMON=m +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ASIHPI=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1_SEQ=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +# CONFIG_SND_ES1968_RADIO is not set +CONFIG_SND_FM801=m +# CONFIG_SND_FM801_TEA575X_BOOL is not set +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +# CONFIG_SND_HDA_CODEC_CS8409 is not set +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_I915=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_PREALLOC_SIZE=0 +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +# CONFIG_SND_INTEL_BYT_PREFER_SOF is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_CAIAQ=m +# CONFIG_SND_USB_CAIAQ_INPUT is not set +CONFIG_SND_USB_US122L=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +# CONFIG_SND_BCD2000 is not set +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +# CONFIG_SND_FIREWIRE_DIGI00X is not set +# CONFIG_SND_FIREWIRE_TASCAM is not set +# CONFIG_SND_FIREWIRE_MOTU is not set +# CONFIG_SND_FIREFACE is not set +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_TOPOLOGY=y +CONFIG_SND_SOC_ACPI=m +# CONFIG_SND_SOC_ADI is not set +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_ACP3x=m +CONFIG_SND_SOC_AMD_RENOIR=m +CONFIG_SND_SOC_AMD_RENOIR_MACH=m +CONFIG_SND_SOC_AMD_ACP5x=m +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y +CONFIG_SND_SOC_INTEL_SST=m +CONFIG_SND_SOC_INTEL_CATPT=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m +CONFIG_SND_SOC_INTEL_SKYLAKE=m +CONFIG_SND_SOC_INTEL_SKL=m +CONFIG_SND_SOC_INTEL_APL=m +CONFIG_SND_SOC_INTEL_KBL=m +CONFIG_SND_SOC_INTEL_GLK=m +CONFIG_SND_SOC_INTEL_CNL=m +CONFIG_SND_SOC_INTEL_CFL=m +# CONFIG_SND_SOC_INTEL_CML_H is not set +# CONFIG_SND_SOC_INTEL_CML_LP is not set +CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m +CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y +CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m +CONFIG_SND_SOC_ACPI_INTEL_MATCH=m +CONFIG_SND_SOC_INTEL_MACH=y +# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m +# CONFIG_SND_SOC_INTEL_HASWELL_MACH is not set +# CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH is not set +CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m +CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m +# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set +CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m +# CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set +CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m +CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m +CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m +CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m +CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m +# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set +CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m +# CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH is not set +CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m +CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m +# CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH is not set +CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m +CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m +CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m +CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m +# CONFIG_SND_SOC_MTK_BTCVSD is not set +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI_DEV=m +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_ACPI=m +CONFIG_SND_SOC_SOF_ACPI_DEV=m +# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set +# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set +CONFIG_SND_SOC_SOF=m +CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y +CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y +CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m +CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m +CONFIG_SND_SOC_SOF_INTEL_COMMON=m +CONFIG_SND_SOC_SOF_BAYTRAIL=m +CONFIG_SND_SOC_SOF_BROADWELL=m +CONFIG_SND_SOC_SOF_MERRIFIELD=m +CONFIG_SND_SOC_SOF_INTEL_APL=m +CONFIG_SND_SOC_SOF_APOLLOLAKE=m +CONFIG_SND_SOC_SOF_GEMINILAKE=m +CONFIG_SND_SOC_SOF_INTEL_CNL=m +CONFIG_SND_SOC_SOF_CANNONLAKE=m +CONFIG_SND_SOC_SOF_COFFEELAKE=m +CONFIG_SND_SOC_SOF_COMETLAKE=m +CONFIG_SND_SOC_SOF_INTEL_ICL=m +CONFIG_SND_SOC_SOF_ICELAKE=m +CONFIG_SND_SOC_SOF_JASPERLAKE=m +CONFIG_SND_SOC_SOF_INTEL_TGL=m +CONFIG_SND_SOC_SOF_TIGERLAKE=m +CONFIG_SND_SOC_SOF_ELKHARTLAKE=m +CONFIG_SND_SOC_SOF_ALDERLAKE=m +CONFIG_SND_SOC_SOF_HDA_COMMON=m +CONFIG_SND_SOC_SOF_HDA_LINK=y +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y +CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_HDA=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m +CONFIG_SND_SOC_SOF_XTENSA=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +CONFIG_SND_SOC_ADAU7002=m +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +CONFIG_SND_SOC_AK4458=m +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +CONFIG_SND_SOC_AK5558=m +# CONFIG_SND_SOC_ALC5623 is not set +CONFIG_SND_SOC_BD28623=m +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +CONFIG_SND_SOC_DA7219=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_HDMI_CODEC=m +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +CONFIG_SND_SOC_HDAC_HDMI=m +CONFIG_SND_SOC_HDAC_HDA=m +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +CONFIG_SND_SOC_MAX98357A=m +# CONFIG_SND_SOC_MAX98504 is not set +CONFIG_SND_SOC_MAX9867=m +# CONFIG_SND_SOC_MAX98927 is not set +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +# CONFIG_SND_SOC_MAX98373_SDW is not set +CONFIG_SND_SOC_MAX98390=m +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RL6347A=m +CONFIG_SND_SOC_RT286=m +CONFIG_SND_SOC_RT298=m +CONFIG_SND_SOC_RT1011=m +CONFIG_SND_SOC_RT1015=m +CONFIG_SND_SOC_RT1015P=m +# CONFIG_SND_SOC_RT1308_SDW is not set +# CONFIG_SND_SOC_RT1316_SDW is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5651=m +# CONFIG_SND_SOC_RT5659 is not set +CONFIG_SND_SOC_RT5660=m +CONFIG_SND_SOC_RT5670=m +CONFIG_SND_SOC_RT5677=m +CONFIG_SND_SOC_RT5677_SPI=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_I2C=m +# CONFIG_SND_SOC_RT5682_SDW is not set +# CONFIG_SND_SOC_RT700_SDW is not set +# CONFIG_SND_SOC_RT711_SDW is not set +# CONFIG_SND_SOC_RT711_SDCA_SDW is not set +# CONFIG_SND_SOC_RT715_SDW is not set +# CONFIG_SND_SOC_RT715_SDCA_SDW is not set +# CONFIG_SND_SOC_SDW_MOCKUP is not set +# CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +# CONFIG_SND_SOC_SIMPLE_MUX is not set +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +CONFIG_SND_SOC_SSM4567=m +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TS3A227E is not set +CONFIG_SND_SOC_TSCS42XX=m +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WCD938X_SDW is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_WSA881X is not set +# CONFIG_SND_SOC_ZL38060 is not set +CONFIG_SND_SOC_MAX9759=m +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_NAU8825=m +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_X86=y +# CONFIG_HDMI_LPE_AUDIO is not set +CONFIG_SND_SYNTH_EMUX=m +# CONFIG_SND_XEN_FRONTEND is not set +# CONFIG_SND_VIRTIO is not set +CONFIG_AC97_BUS=m + +# +# HID support +# +CONFIG_HID=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=m +# CONFIG_HID_APPLEIR is not set +CONFIG_HID_ASUS=m +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +CONFIG_HID_BETOP_FF=m +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=m +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +CONFIG_HID_COUGAR=m +# CONFIG_HID_MACALLY is not set +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +CONFIG_HID_ELAN=m +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_FT260 is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +# CONFIG_HID_KYE is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +CONFIG_HID_ICADE=m +# CONFIG_HID_ITE is not set +CONFIG_HID_JABRA=m +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=m +# CONFIG_HID_MONTEREY is not set +CONFIG_HID_MULTITOUCH=m +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +CONFIG_HID_ORTEK=m +# CONFIG_HID_PANTHERLORD is not set +CONFIG_HID_PENMOUNT=m +# CONFIG_HID_PETALYNX is not set +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +# CONFIG_HID_PLAYSTATION is not set +CONFIG_HID_PRIMAX=m +# CONFIG_HID_RETRODE is not set +CONFIG_HID_ROCCAT=m +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +CONFIG_HID_RMI=m +# CONFIG_HID_GREENASIA is not set +CONFIG_HID_HYPERV_MOUSE=m +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +CONFIG_HID_THINGM=m +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_U2FZERO is not set +# CONFIG_HID_WACOM is not set +CONFIG_HID_WIIMOTE=m +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_ALPS=m +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID_ACPI is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +CONFIG_INTEL_ISH_HID=m +# CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set +# end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_FSM is not set +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +# CONFIG_USB_HCD_BCMA is not set +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +# CONFIG_USBIP_DEBUG is not set +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +CONFIG_USB_SERIAL_QT2=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +# CONFIG_USB_LEGOTOWER is not set +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +# CONFIG_USB_TRANCEVIBRATOR is not set +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_YUREX is not set +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +# CONFIG_USB_LINK_LAYER_TEST is not set +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +CONFIG_USB_GPIO_VBUS=m +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +CONFIG_TYPEC=m +# CONFIG_TYPEC_TCPM is not set +# CONFIG_TYPEC_UCSI is not set +CONFIG_TYPEC_TPS6598X=m +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_STUSB160X is not set + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_INTEL_PMC=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_USB_ROLES_INTEL_XHCI=m +CONFIG_MMC=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +CONFIG_MMC_TEST=m + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_ACPI=m +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_F_SDH30=m +CONFIG_MMC_WBSD=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +# CONFIG_MMC_SDHCI_XENON is not set +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +CONFIG_LEDS_APU=m +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +# CONFIG_LEDS_LP50XX is not set +CONFIG_LEDS_CLEVO_MAIL=m +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +CONFIG_LEDS_REGULATOR=m +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_INTEL_SS4200=m +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_MLXCPLD=m +CONFIG_LEDS_MLXREG=m +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_NIC78BX is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AS3645A is not set +CONFIG_LEDS_LM3601X=m +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LEDS_TRIGGER_AUDIO=m +# CONFIG_LEDS_TRIGGER_TTY is not set +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +# CONFIG_INFINIBAND_QIB is not set +CONFIG_INFINIBAND_CXGB4=m +# CONFIG_INFINIBAND_EFA is not set +# CONFIG_INFINIBAND_IRDMA is not set +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +# CONFIG_INFINIBAND_OCRDMA is not set +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +# CONFIG_INFINIBAND_USNIC is not set +CONFIG_INFINIBAND_HFI1=m +# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set +# CONFIG_SDMA_VERBOSITY is not set +# CONFIG_INFINIBAND_QEDR is not set +CONFIG_INFINIBAND_RDMAVT=m +CONFIG_RDMA_RXE=m +# CONFIG_RDMA_SIW is not set +CONFIG_INFINIBAND_IPOIB=m +# CONFIG_INFINIBAND_IPOIB_CM is not set +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +# CONFIG_INFINIBAND_ISERT is not set +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +# CONFIG_INFINIBAND_OPA_VNIC is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_DECODE_MCE=y +CONFIG_EDAC_AMD64=m +CONFIG_EDAC_E752X=m +CONFIG_EDAC_I82975X=m +CONFIG_EDAC_I3000=m +CONFIG_EDAC_I3200=m +CONFIG_EDAC_IE31200=m +CONFIG_EDAC_X38=m +CONFIG_EDAC_I5400=m +CONFIG_EDAC_I7CORE=m +CONFIG_EDAC_I5000=m +CONFIG_EDAC_I5100=m +CONFIG_EDAC_I7300=m +CONFIG_EDAC_SBRIDGE=m +CONFIG_EDAC_SKX=m +# CONFIG_EDAC_I10NM is not set +CONFIG_EDAC_PND2=m +# CONFIG_EDAC_IGEN6 is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_TEST=m + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV8803=m +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_I2C_AND_SPI=m + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV3029_HWMON=y +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_STK17TA8=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_BQ4802=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_V3020=m +CONFIG_RTC_DRV_PCF50633=m + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_GOLDFISH is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=m +CONFIG_DMA_ACPI=y +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_INTEL_IDMA64=m +# CONFIG_INTEL_IDXD is not set +# CONFIG_INTEL_IDXD_COMPAT is not set +CONFIG_INTEL_IOATDMA=m +# CONFIG_PLX_DMA is not set +# CONFIG_AMD_PTDMA is not set +CONFIG_QCOM_HIDMA_MGMT=m +# CONFIG_QCOM_HIDMA is not set +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +CONFIG_HSU_DMA=m +# CONFIG_SF_PDMA is not set +# CONFIG_INTEL_LDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +CONFIG_DMATEST=m +CONFIG_DMA_ENGINE_RAID=y + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_DCA=m +CONFIG_AUXDISPLAY=y +# CONFIG_HD44780 is not set +CONFIG_KS0108=m +CONFIG_KS0108_PORT=0x378 +CONFIG_KS0108_DELAY=2 +CONFIG_CFAG12864B=m +CONFIG_CFAG12864B_RATE=20 +# CONFIG_IMG_ASCII_LCD is not set +# CONFIG_LCD2S is not set +# CONFIG_PARPORT_PANEL is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_PANEL is not set +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_UIO_DMEM_GENIRQ is not set +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_HV_GENERIC is not set +CONFIG_VFIO=m +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_VIRQFD=m +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_VGA=y +CONFIG_VFIO_PCI_IGD=y +# CONFIG_VFIO_MDEV is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VBOXGUEST=m +CONFIG_NITRO_ENCLAVES=m +CONFIG_VIRTIO=m +CONFIG_VIRTIO_PCI_LIB=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=m +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +# CONFIG_VIRTIO_PMEM is not set +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +# CONFIG_VDPA_USER is not set +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_VP_VDPA is not set +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_HYPERV=m +CONFIG_HYPERV_TIMER=y +CONFIG_HYPERV_UTILS=m +CONFIG_HYPERV_BALLOON=m +# end of Microsoft Hyper-V guest support + +# +# Xen driver support +# +CONFIG_XEN_BALLOON=y +CONFIG_XEN_SCRUB_PAGES_DEFAULT=y +CONFIG_XEN_DEV_EVTCHN=m +CONFIG_XEN_BACKEND=y +CONFIG_XENFS=m +CONFIG_XEN_COMPAT_XENFS=y +CONFIG_XEN_SYS_HYPERVISOR=y +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XEN_GNTDEV=m +CONFIG_XEN_GRANT_DEV_ALLOC=m +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_SWIOTLB_XEN=y +CONFIG_XEN_PCIDEV_BACKEND=m +CONFIG_XEN_PVCALLS_FRONTEND=m +# CONFIG_XEN_PVCALLS_BACKEND is not set +CONFIG_XEN_SCSI_BACKEND=m +CONFIG_XEN_PRIVCMD=m +CONFIG_XEN_ACPI_PROCESSOR=m +# CONFIG_XEN_MCE_LOG is not set +CONFIG_XEN_HAVE_PVMMU=y +CONFIG_XEN_EFI=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_ACPI=y +# CONFIG_XEN_SYMS is not set +CONFIG_XEN_HAVE_VPMU=y +# end of Xen driver support + +# CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_RTL8192U is not set +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +# CONFIG_RTL8192E is not set +CONFIG_RTL8723BS=m +# CONFIG_R8712U is not set +CONFIG_R8188EU=m +CONFIG_88EU_AP_MODE=y +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# CONFIG_AD7280 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Capacitance to digital converters +# +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +# CONFIG_FB_SM750 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ASHMEM=y +# end of Android + +# CONFIG_LTE_GDM724X is not set +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_FB_TFT is not set +# CONFIG_KS7010 is not set +# CONFIG_PI433 is not set +# CONFIG_FIELDBUS_DEV is not set +CONFIG_QLGE=m +# CONFIG_WFX is not set +CONFIG_X86_PLATFORM_DEVICES=y +CONFIG_ACPI_WMI=m +CONFIG_WMI_BMOF=m +# CONFIG_HUAWEI_WMI is not set +CONFIG_MXM_WMI=m +# CONFIG_PEAQ_WMI is not set +# CONFIG_XIAOMI_WMI is not set +# CONFIG_GIGABYTE_WMI is not set +CONFIG_ACERHDF=m +CONFIG_ACER_WIRELESS=m +CONFIG_ACER_WMI=m +# CONFIG_AMD_PMC is not set +# CONFIG_ADV_SWBUTTON is not set +CONFIG_APPLE_GMUX=m +CONFIG_ASUS_LAPTOP=m +CONFIG_ASUS_WIRELESS=m +CONFIG_ASUS_WMI=m +CONFIG_ASUS_NB_WMI=m +# CONFIG_MERAKI_MX100 is not set +CONFIG_EEEPC_LAPTOP=m +CONFIG_EEEPC_WMI=m +# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set +CONFIG_AMILO_RFKILL=m +CONFIG_FUJITSU_LAPTOP=m +# CONFIG_FUJITSU_TABLET is not set +CONFIG_GPD_POCKET_FAN=m +CONFIG_HP_ACCEL=m +# CONFIG_WIRELESS_HOTKEY is not set +CONFIG_HP_WMI=m +# CONFIG_IBM_RTL is not set +CONFIG_IDEAPAD_LAPTOP=m +CONFIG_SENSORS_HDAPS=m +CONFIG_THINKPAD_ACPI=m +CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y +# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set +# CONFIG_THINKPAD_ACPI_DEBUG is not set +# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set +CONFIG_THINKPAD_ACPI_VIDEO=y +CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y +# CONFIG_THINKPAD_LMI is not set +CONFIG_INTEL_ATOMISP2_PDX86=y +# CONFIG_INTEL_ATOMISP2_LED is not set +CONFIG_INTEL_ATOMISP2_PM=m +# CONFIG_INTEL_SAR_INT1092 is not set +# CONFIG_INTEL_SKL_INT3472 is not set +CONFIG_INTEL_PMC_CORE=y + +# +# Intel Speed Select Technology interface support +# +# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set +# end of Intel Speed Select Technology interface support + +CONFIG_INTEL_TELEMETRY=m +CONFIG_INTEL_WMI=y +# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set +CONFIG_INTEL_WMI_THUNDERBOLT=m +CONFIG_INTEL_HID_EVENT=m +CONFIG_INTEL_VBTN=m +# CONFIG_INTEL_INT0002_VGPIO is not set +CONFIG_INTEL_OAKTRAIL=m +CONFIG_INTEL_BXTWC_PMIC_TMU=m +CONFIG_INTEL_CHTDC_TI_PWRBTN=m +CONFIG_INTEL_PUNIT_IPC=m +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_TURBO_MAX_3 is not set +CONFIG_INTEL_UNCORE_FREQ_CONTROL=m +CONFIG_MSI_LAPTOP=m +CONFIG_MSI_WMI=m +CONFIG_PCENGINES_APU2=m +# CONFIG_SAMSUNG_LAPTOP is not set +# CONFIG_SAMSUNG_Q10 is not set +# CONFIG_ACPI_TOSHIBA is not set +CONFIG_TOSHIBA_BT_RFKILL=m +CONFIG_TOSHIBA_HAPS=m +# CONFIG_TOSHIBA_WMI is not set +CONFIG_ACPI_CMPC=m +CONFIG_COMPAL_LAPTOP=m +# CONFIG_LG_LAPTOP is not set +CONFIG_PANASONIC_LAPTOP=m +CONFIG_SONY_LAPTOP=m +# CONFIG_SONYPI_COMPAT is not set +CONFIG_SYSTEM76_ACPI=m +# CONFIG_TOPSTAR_LAPTOP is not set +CONFIG_I2C_MULTI_INSTANTIATE=m +CONFIG_MLX_PLATFORM=m +# CONFIG_INTEL_IPS is not set +CONFIG_INTEL_SCU_IPC=y +# CONFIG_INTEL_SCU_PCI is not set +# CONFIG_INTEL_SCU_PLATFORM is not set +CONFIG_PMC_ATOM=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHROMEOS_LAPTOP=m +CONFIG_CHROMEOS_PSTORE=m +# CONFIG_CHROMEOS_TBMC is not set +# CONFIG_CROS_EC is not set +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_MELLANOX_PLATFORM=y +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE3_WMI is not set +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_HOTPLUG is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_XILINX_VCU=m +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_V2=m +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SVM is not set +# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +CONFIG_IRQ_REMAP=y +CONFIG_HYPERV_IOMMU=y +# CONFIG_VIRTIO_IOMMU is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_CHAR is not set +CONFIG_RPMSG_NS=m +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_CADENCE=m +CONFIG_SOUNDWIRE_INTEL=m +# CONFIG_SOUNDWIRE_QCOM is not set +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# end of Enable LiteX SoC Builder specific drivers + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_INTEL_INT3496 is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +CONFIG_MEMORY=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +# CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_DMA is not set +# CONFIG_IIO_BUFFER_DMAENGINE is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_SW_DEVICE is not set +# CONFIG_IIO_SW_TRIGGER is not set +# CONFIG_IIO_TRIGGERED_EVENT is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set +CONFIG_HID_SENSOR_ACCEL_3D=m +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7091R5 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set +# CONFIG_XILINX_XADC is not set +# end of Analog to digital converters + +# +# Analog Front Ends +# +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_VZ89X is not set +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORS_COMMONS is not set +CONFIG_IIO_SSP_SENSORHUB=m +# end of SSP Sensor Common + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# end of IIO dummy driver + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set +CONFIG_HID_SENSOR_GYRO_3D=m +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set +CONFIG_HID_SENSOR_HUMIDITY=m +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set +# end of Inertial measurement units + +# +# Light sensors +# +# CONFIG_ACPI_ALS is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors + +# +# Magnetometer sensors +# +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +# CONFIG_AD5110 is not set +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set +# end of Digital potentiometers + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set +# end of Digital potentiostats + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_PING is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +# CONFIG_LTC2983 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +CONFIG_NTB=m +# CONFIG_NTB_MSI is not set +CONFIG_NTB_AMD=m +# CONFIG_NTB_IDT is not set +CONFIG_NTB_INTEL=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +CONFIG_NTB_PINGPONG=m +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +CONFIG_NTB_TRANSPORT=m +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_DWC is not set +CONFIG_PWM_LPSS=m +CONFIG_PWM_LPSS_PCI=m +CONFIG_PWM_LPSS_PLATFORM=m +CONFIG_PWM_PCA9685=m + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_USB_LGM_PHY is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_INTEL_RAPL_CORE=m +CONFIG_INTEL_RAPL=m +# CONFIG_IDLE_INJECT is not set +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_USB4 is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +# CONFIG_ANDROID_BINDERFS is not set +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDER_IPC_SELFTEST=y +# end of Android + +CONFIG_LIBNVDIMM=y +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_BLK=y +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=y +CONFIG_BTT=y +CONFIG_DAX_DRIVER=y +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +CONFIG_UNISYS_VISORBUS=m +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=m +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=m +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +# CONFIG_REISERFS_FS_SECURITY is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_XFS_ONLINE_SCRUB=y +# CONFIG_XFS_ONLINE_REPAIR is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +# CONFIG_F2FS_STAT_FS is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=m +CONFIG_FS_VERITY=y +# CONFIG_FS_VERITY_DEBUG is not set +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# CONFIG_NTFS3_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_FREE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=m +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +CONFIG_ORANGEFS_FS=m +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_UBIFS_FS=m +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +# CONFIG_UBIFS_ATIME_SUPPORT is not set +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_SECURITY=y +# CONFIG_UBIFS_FS_AUTHENTICATION is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PSTORE_BLK is not set +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +# CONFIG_EROFS_FS is not set +CONFIG_VBOXSF_FS=m +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=m +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +# CONFIG_NFSD_V4_2_INTER_SSC is not set +# CONFIG_NFSD_V4_SECURITY_LABEL is not set +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y +# CONFIG_SUNRPC_DEBUG is not set +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +# CONFIG_CIFS_SWN_UPCALL is not set +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +# CONFIG_9P_FS_SECURITY is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +CONFIG_TRUSTED_KEYS=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +# CONFIG_INTEL_TXT is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_FALLBACK=y +# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set +# CONFIG_INTEGRITY is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=m +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_SIMD=m +CONFIG_CRYPTO_ENGINE=m + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_X86=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +# CONFIG_CRYPTO_OFB is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_NHPOLY1305=m +CONFIG_CRYPTO_NHPOLY1305_SSE2=m +CONFIG_CRYPTO_NHPOLY1305_AVX2=m +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=m + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_CRC32C_INTEL=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32_PCLMUL=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_BLAKE2S_X86=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_POLY1305_X86_64=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_SSSE3=m +CONFIG_CRYPTO_SHA256_SSSE3=m +CONFIG_CRYPTO_SHA512_SSSE3=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AES_NI_INTEL=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_BLOWFISH_X86_64=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAMELLIA_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST5_AVX_X86_64=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST6_AVX_X86_64=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20_X86_64=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m +CONFIG_CRYPTO_SM4=m +# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_TWOFISH_X86_64=m +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m +CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=m +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=m +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=m +CONFIG_CRYPTO_JITTERENTROPY=m +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SM4=m +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_PADLOCK=m +CONFIG_CRYPTO_DEV_PADLOCK_AES=m +CONFIG_CRYPTO_DEV_PADLOCK_SHA=m +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_DD=m +CONFIG_CRYPTO_DEV_SP_CCP=y +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +CONFIG_CRYPTO_DEV_SP_PSP=y +# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +# CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=m +# CONFIG_CRC4 is not set +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=m +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=m +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_IOMMU_HELPER=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_MEMREGION=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_COPY_MC=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# end of Library routines + +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_FRAME_WARN=1280 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_STACK_VALIDATION=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +CONFIG_HAVE_KCSAN_COMPILER=y +# CONFIG_KCSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +# CONFIG_FUNCTION_PROFILER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set +CONFIG_MMIOTRACE=y +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_CC=y +# CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# x86 Debugging +# +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_IOMMU_DEBUG is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +CONFIG_X86_DECODER_SELFTEST=y +CONFIG_IO_DELAY_0X80=y +# CONFIG_IO_DELAY_0XED is not set +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +CONFIG_DEBUG_NMI_SELFTEST=y +CONFIG_X86_DEBUG_FPU=y +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y +# CONFIG_MEMTEST is not set +# CONFIG_HYPERV_TESTING is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/main/linux/config-rockpro64.aarch64 b/main/linux/config-rockpro64.aarch64 new file mode 100644 index 0000000..1cf2ba9 --- /dev/null +++ b/main/linux/config-rockpro64.aarch64 @@ -0,0 +1,6786 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.15.12 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="gcc (Alpine 10.2.1_git20210328) 10.2.1 20210328" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100201 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23502 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23502 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +# CONFIG_BPF_SYSCALL is not set +# CONFIG_BPF_JIT is not set +# end of BPF subsystem + +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_SCHED_THERMAL_PRESSURE=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +# CONFIG_IKCONFIG is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +# CONFIG_CGROUP_DEVICE is not set +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_MISC is not set +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +CONFIG_TIME_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_FHANDLE is not set +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_AIO is not set +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_ROCKCHIP=y +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1508412=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_HISILICON_ERRATUM_161600802=y +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SCHED_MC=y +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +# CONFIG_NUMA is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_COMPAT=y +CONFIG_KUSER_HELPERS=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LDAPR=y +CONFIG_AS_HAS_LSE_ATOMICS=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +# end of ARMv8.3 architectural features + +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_AS_HAS_ARMV8_5=y +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +CONFIG_ARM64_AS_HAS_MTE=y +CONFIG_ARM64_MTE=y +# end of ARMv8.5 architectural features + +# +# ARMv8.7 architectural features +# +CONFIG_ARM64_EPAN=y +# end of ARMv8.7 architectural features + +CONFIG_ARM64_SVE=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_RELOCATABLE=y +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y +# end of Boot options + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_DT_IDLE_STATES=y + +# +# ARM CPU Idle Drivers +# +CONFIG_ARM_CPUIDLE=y +# CONFIG_ARM_PSCI_CPUIDLE is not set +# end of ARM CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# end of CPU Frequency scaling +# end of CPU Power Management + +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +# CONFIG_VIRTUALIZATION is not set +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA256_ARM64=y +# CONFIG_CRYPTO_SHA512_ARM64 is not set +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +# CONFIG_CRYPTO_SHA3_ARM64 is not set +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_POLY1305_NEON is not set +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +# CONFIG_CRYPTO_AES_ARM64_BS is not set + +# +# General architecture-dependent options +# +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_DEV_BSG_COMMON=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_CMDLINE_PARTITION=y +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_COREDUMP is not set +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +CONFIG_NET_UDP_TUNNEL=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_DIAG_DESTROY=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_LOG_SYSLOG=y +CONFIG_NETFILTER_CONNCOUNT=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_NAT=y +CONFIG_NETFILTER_XT_TARGET_NETMAP=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ECN=y +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_L2TP=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=y +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_SOCKET_IPV4=y +CONFIG_NF_TPROXY_IPV4=y +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=y +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=y +CONFIG_NF_TPROXY_IPV6=y +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +CONFIG_NF_LOG_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RPFILTER=y +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +# CONFIG_BRIDGE_EBT_T_FILTER is not set +# CONFIG_BRIDGE_EBT_T_NAT is not set +# CONFIG_BRIDGE_EBT_802_3 is not set +# CONFIG_BRIDGE_EBT_AMONG is not set +# CONFIG_BRIDGE_EBT_ARP is not set +# CONFIG_BRIDGE_EBT_IP is not set +# CONFIG_BRIDGE_EBT_IP6 is not set +# CONFIG_BRIDGE_EBT_LIMIT is not set +# CONFIG_BRIDGE_EBT_MARK is not set +# CONFIG_BRIDGE_EBT_PKTTYPE is not set +# CONFIG_BRIDGE_EBT_STP is not set +# CONFIG_BRIDGE_EBT_VLAN is not set +# CONFIG_BRIDGE_EBT_ARPREPLY is not set +# CONFIG_BRIDGE_EBT_DNAT is not set +# CONFIG_BRIDGE_EBT_MARK_T is not set +# CONFIG_BRIDGE_EBT_REDIRECT is not set +# CONFIG_BRIDGE_EBT_SNAT is not set +# CONFIG_BRIDGE_EBT_LOG is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_L2TP=y +# CONFIG_L2TP_DEBUGFS is not set +# CONFIG_L2TP_V3 is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +CONFIG_NET_SCH_HTB=y +# CONFIG_NET_SCH_HFSC is not set +CONFIG_NET_SCH_PRIO=y +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +CONFIG_NET_CLS_FLOW=y +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_CTINFO is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +# CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set +CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_FEATURE_DEBUG is not set + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_AG6XX is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_MTKSDIO is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_PAGE_POOL=y +# CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_POWERSAVE=y +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +# CONFIG_PCIE_ROCKCHIP_HOST is not set +# CONFIG_PCIE_MICROCHIP_HOST is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_CXL_BUS is not set +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +# CONFIG_DEVTMPFS_MOUNT is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_MHI_BUS is not set +# end of Bus devices + +# CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_DW_XDATA_PCIE is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPI3MR is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +CONFIG_DM_VERITY=y +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_NET_VENDOR_MICROSOFT=y +# CONFIG_JME is not set +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_LITEX_LITEETH is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_ROCKCHIP=y +# CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_DWMAC_LOONGSON is not set +# CONFIG_STMMAC_PCI is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +CONFIG_AX88796B_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +CONFIG_ROCKCHIP_PHY=y +CONFIG_SMSC_PHY=y +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=y +# end of PCS device drivers + +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_SLIP=y +CONFIG_SLHC=y +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_SMART is not set +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_CATC=y +CONFIG_USB_KAWETH=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8150=y +CONFIG_USB_RTL8152=y +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_CDC_EEM=y +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +CONFIG_USB_NET_CDC_MBIM=y +CONFIG_USB_NET_DM9601=y +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=y +CONFIG_USB_NET_NET1080=y +CONFIG_USB_NET_PLUSB=y +CONFIG_USB_NET_MCS7830=y +CONFIG_USB_NET_RNDIS_HOST=y +CONFIG_USB_NET_CDC_SUBSET_ENABLE=y +CONFIG_USB_NET_CDC_SUBSET=y +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=y +CONFIG_USB_NET_CX82310_ETH=y +CONFIG_USB_NET_KALMIA=y +CONFIG_USB_NET_QMI_WWAN=y +CONFIG_USB_HSO=y +CONFIG_USB_NET_INT51X1=y +CONFIG_USB_IPHETH=y +CONFIG_USB_SIERRA_NET=y +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +# CONFIG_ADM8211 is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +# CONFIG_ATH10K is not set +# CONFIG_WCN36XX is not set +CONFIG_WLAN_VENDOR_ATMEL=y +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLWIFI is not set +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_MWIFIEX is not set +# CONFIG_MWL8K is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +# CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x0E is not set +# CONFIG_MT76x2E is not set +# CONFIG_MT76x2U is not set +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +# CONFIG_MT7921E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_RALINK=y +# CONFIG_RT2X00 is not set +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTL8XXXU is not set +# CONFIG_RTW88 is not set +# CONFIG_RTW89 is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_ZD1211RW is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_QTNFMAC_PCIE is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADC is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +# CONFIG_JOYSTICK_PSXPAD_SPI is not set +# CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_QWIIC is not set +# CONFIG_JOYSTICK_FSIA6B is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +# CONFIG_TABLET_USB_PEGASUS is not set +# CONFIG_TABLET_SERIAL_WACOM4 is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_RK805_PWRKEY is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_16550A_VARIANTS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=5 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_OF_PLATFORM is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_HVC_DCC is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +# CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_RK3X=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_VIRTIO is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MEM is not set + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_ROCKCHIP=y +# CONFIG_SPI_ROCKCHIP_SFC is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_KVM=y +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_RK805 is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +CONFIG_GPIO_ROCKCHIP=y +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + +# CONFIG_W1 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +CONFIG_REBOOT_MODE=y +CONFIG_SYSCON_REBOOT_MODE=y +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_TEST_POWER=y +# CONFIG_CHARGER_ADP5061 is not set +CONFIG_BATTERY_CW2015=y +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_MMIO is not set +CONFIG_ROCKCHIP_THERMAL=y +# CONFIG_GENERIC_ADC_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=y +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_ACT8865=y +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=y +# CONFIG_REGULATOR_FAN53880 is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +CONFIG_REGULATOR_RK808=y +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VCTRL is not set +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +# CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set +# CONFIG_RC_DEVICES is not set +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_CEC_CH7322 is not set +# CONFIG_CEC_GPIO is not set +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set +CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_V4L2_H264=m +CONFIG_V4L2_MEM2MEM_DEV=m +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y + +# +# Please notice that the enabled Media controller Request API is EXPERIMENTAL +# +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_TM6000 is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_USB_V2 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_ASPEED is not set +# CONFIG_VIDEO_MUX is not set +# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set +# CONFIG_VIDEO_XILINX is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=y + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips + +# +# Camera sensor devices +# +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=y +# CONFIG_MEDIA_TUNER_TDA18250 is not set +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +# CONFIG_MEDIA_TUNER_MSI001 is not set +CONFIG_MEDIA_TUNER_MT20XX=y +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +CONFIG_MEDIA_TUNER_MC44S803=y +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +# CONFIG_DVB_RTL2832_SDR is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set +# CONFIG_DVB_MXL692 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set + +# +# Common Interface (EN50221) controller drivers +# +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_BUS=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_SCHED=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_ROCKCHIP=y +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_LVDS=y +# CONFIG_ROCKCHIP_RGB is not set +# CONFIG_ROCKCHIP_RK3066_HDMI is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_VIRTIO_GPU is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +CONFIG_DRM_ANALOGIX_DP=y +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +CONFIG_DRM_DW_HDMI=y +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +CONFIG_DRM_DW_HDMI_I2S_AUDIO=y +# CONFIG_DRM_DW_HDMI_CEC is not set +CONFIG_DRM_DW_MIPI_DSI=y +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_LIMA is not set +CONFIG_DRM_PANFROST=y +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_VIRTUAL=m +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_FB_SIMPLE=m +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set +# end of Backlight & LCD device support + +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +# end of Console display driver support + +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# end of Graphics support + +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_PCI is not set + +# +# HD-Audio +# +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +CONFIG_SND_SOC_ROCKCHIP=y +CONFIG_SND_SOC_ROCKCHIP_I2S=y +# CONFIG_SND_SOC_ROCKCHIP_PDM is not set +CONFIG_SND_SOC_ROCKCHIP_SPDIF=y +# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set +# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set +# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +CONFIG_SND_SOC_BT_SCO=y +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +CONFIG_SND_SOC_CX2072X=y +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8316=y +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +CONFIG_SND_SOC_RK3328=y +# CONFIG_SND_SOC_RK817 is not set +CONFIG_SND_SOC_RL6231=y +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5640=y +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +CONFIG_SND_SOC_SPDIF=y +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +# CONFIG_SND_AUDIO_GRAPH_CARD is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_APPLEIR=y +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=y +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +CONFIG_HID_PRODIKEYS=y +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +# CONFIG_HID_ELAN is not set +CONFIG_HID_ELECOM=y +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +CONFIG_HID_HOLTEK=y +# CONFIG_HOLTEK_FF is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_GT683R is not set +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +# CONFIG_HID_VIEWSONIC is not set +CONFIG_HID_GYRATION=y +CONFIG_HID_ICADE=y +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LED=y +CONFIG_HID_LENOVO=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_HID_LOGITECH_HIDPP=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +# CONFIG_HID_NTI is not set +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +# CONFIG_HID_PENMOUNT is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +# CONFIG_HID_PICOLCD_FB is not set +# CONFIG_HID_PICOLCD_BACKLIGHT is not set +# CONFIG_HID_PICOLCD_LEDS is not set +# CONFIG_HID_PICOLCD_CIR is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PLAYSTATION is not set +CONFIG_HID_PRIMAX=y +# CONFIG_HID_RETRODE is not set +CONFIG_HID_ROCCAT=y +CONFIG_HID_SAITEK=y +CONFIG_HID_SAMSUNG=y +# CONFIG_HID_SEMITEK is not set +CONFIG_HID_SONY=y +# CONFIG_SONY_FF is not set +CONFIG_HID_SPEEDLINK=y +# CONFIG_HID_STEAM is not set +CONFIG_HID_STEELSERIES=y +CONFIG_HID_SUNPLUS=y +# CONFIG_HID_RMI is not set +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THINGM=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_HID_UDRAW_PS3 is not set +CONFIG_HID_WACOM=y +CONFIG_HID_WIIMOTE=y +# CONFIG_HID_XINMO is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_HID_ZYDACRON=y +# CONFIG_HID_SENSOR_HUB is not set +CONFIG_HID_ALPS=y +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_GOODIX is not set +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PCI is not set +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_STORAGE_ENE_UB6250=y +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=y +CONFIG_USB_DWC3_OF_SIMPLE=y +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +CONFIG_USB_TRANCEVIBRATOR=y +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_U_SERIAL_CONSOLE is not set + +# +# USB Peripheral Controller +# +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_MAX3420_UDC is not set +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_F_ACM=y +CONFIG_USB_U_SERIAL=y +CONFIG_USB_U_ETHER=y +CONFIG_USB_F_RNDIS=y +CONFIG_USB_F_MASS_STORAGE=y +CONFIG_USB_F_FS=y +CONFIG_USB_F_MIDI=y +CONFIG_USB_CONFIGFS=y +# CONFIG_USB_CONFIGFS_SERIAL is not set +CONFIG_USB_CONFIGFS_ACM=y +# CONFIG_USB_CONFIGFS_OBEX is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +CONFIG_USB_CONFIGFS_RNDIS=y +# CONFIG_USB_CONFIGFS_EEM is not set +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +CONFIG_USB_CONFIGFS_F_FS=y +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +CONFIG_USB_CONFIGFS_F_MIDI=y +# CONFIG_USB_CONFIGFS_F_HID is not set +# CONFIG_USB_CONFIGFS_F_UVC is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + +# CONFIG_TYPEC is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RK808=y +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_GOLDFISH is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_MV_XOR_V2 is not set +CONFIG_PL330_DMA=y +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL8723BS is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# CONFIG_AD7280 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Capacitance to digital converters +# +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +# CONFIG_FB_SM750 is not set +CONFIG_STAGING_MEDIA=y +# CONFIG_VIDEO_HANTRO is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_DVB_AV7110 is not set + +# +# Android +# +CONFIG_ASHMEM=y +# end of Android + +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_FB_TFT is not set +# CONFIG_KS7010 is not set +# CONFIG_PI433 is not set +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_QLGE is not set +# CONFIG_WFX is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +CONFIG_COMMON_CLK_RK808=y +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_XGENE is not set +CONFIG_COMMON_CLK_PWM=y +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_CLK_PX30=y +CONFIG_CLK_RK3308=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3368=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3568=y +# CONFIG_XILINX_VCU is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_ROCKCHIP_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_OF_IOMMU=y +CONFIG_IOMMU_DMA=y +CONFIG_ROCKCHIP_IOMMU=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +CONFIG_ROCKCHIP_GRF=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +# CONFIG_IIO_BUFFER_DMA is not set +# CONFIG_IIO_BUFFER_DMAENGINE is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGERED_BUFFER=y +# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_SW_DEVICE is not set +# CONFIG_IIO_SW_TRIGGER is not set +# CONFIG_IIO_TRIGGERED_EVENT is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMI088_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7091R5 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_ADI_AXI_ADC is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_ENVELOPE_DETECTOR is not set +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +CONFIG_ROCKCHIP_SARADC=y +# CONFIG_SD_ADC_MODULATOR is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set +# CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set +# end of Analog to digital converters + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_VZ89X is not set +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +# end of Hid Sensor IIO Common + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# end of IIO dummy driver + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set +# CONFIG_IIO_ST_LSM9DS0 is not set +# end of Inertial measurement units + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM3605 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors + +# +# Magnetometer sensors +# +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +# CONFIG_IIO_MUX is not set +# end of Multiplexers + +# +# Inclinometer sensors +# +# end of Inclinometer sensors + +# +# Triggers - standalone +# +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +# CONFIG_AD5110 is not set +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set +# end of Digital potentiometers + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set +# end of Digital potentiostats + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set +# CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_PING is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +# CONFIG_LTC2983 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TMP117 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_ROCKCHIP=y + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_PHY_XGENE is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_ROCKCHIP_DP=y +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USB=y +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_USB4 is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +# CONFIG_ANDROID_BINDERFS is not set +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_ROCKCHIP_EFUSE=y +# CONFIG_ROCKCHIP_OTP is not set +# CONFIG_NVMEM_RMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_F2FS_FS=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +# CONFIG_F2FS_FS_POSIX_ACL is not set +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +# CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +# CONFIG_PSTORE_BLK is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +CONFIG_CIFS_STATS2=y +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set +# CONFIG_CIFS_ROOT is not set +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=4096 +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_FALLBACK=y +# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set +# CONFIG_SECURITY_SELINUX_DISABLE is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_SIMD=y + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=y + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=y +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD160 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set +CONFIG_CRYPTO_DEV_ROCKCHIP=y +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_INDIRECT_PIO is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZSTD_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# end of Library routines + +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +# CONFIG_DEBUG_INFO_BTF is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set +CONFIG_ENABLE_DEFAULT_TRACERS=y +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SAMPLES is not set +# CONFIG_STRICT_DEVMEM is not set + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/main/linux/config-slim.x86_64 b/main/linux/config-slim.x86_64 new file mode 100644 index 0000000..f2219f6 --- /dev/null +++ b/main/linux/config-slim.x86_64 @@ -0,0 +1,4888 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86_64 5.10.52 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="gcc (Alpine 10.3.1_git20210625) 10.3.1 20210625" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100301 +CONFIG_LD_VERSION=235020000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_LSM is not set +CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_PRELOAD is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ZONE_DMA32=y +CONFIG_AUDIT_ARCH=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_HAVE_INTEL_TXT=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_ZONE_DMA=y +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +CONFIG_X86_X2APIC=y +# CONFIG_X86_MPPARSE is not set +# CONFIG_GOLDFISH is not set +CONFIG_RETPOLINE=y +# CONFIG_X86_CPU_RESCTRL is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_X86_INTEL_LPSS is not set +# CONFIG_X86_AMD_PLATFORM_DEVICE is not set +# CONFIG_IOSF_MBI is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +CONFIG_PARAVIRT_XXL=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +CONFIG_X86_HV_CALLBACK_VECTOR=y +CONFIG_XEN=y +CONFIG_XEN_PV=y +CONFIG_XEN_PV_SMP=y +CONFIG_XEN_DOM0=y +CONFIG_XEN_PVHVM=y +CONFIG_XEN_PVHVM_SMP=y +CONFIG_XEN_512GB=y +CONFIG_XEN_SAVE_RESTORE=y +# CONFIG_XEN_DEBUG_FS is not set +CONFIG_XEN_PVH=y +CONFIG_KVM_GUEST=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y +CONFIG_PVH=y +CONFIG_PARAVIRT_TIME_ACCOUNTING=y +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_JAILHOUSE_GUEST is not set +# CONFIG_ACRN_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y +# CONFIG_PROCESSOR_SELECT is not set +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +# CONFIG_GART_IOMMU is not set +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=256 +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set +# CONFIG_X86_MCE is not set + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +# CONFIG_PERF_EVENTS_INTEL_RAPL is not set +# CONFIG_PERF_EVENTS_INTEL_CSTATE is not set +# CONFIG_PERF_EVENTS_AMD_POWER is not set +# end of Performance monitoring + +CONFIG_X86_16BIT=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_IOPL_IOPERM=y +# CONFIG_I8K is not set +# CONFIG_MICROCODE is not set +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_X86_CPA_STATISTICS is not set +# CONFIG_AMD_MEM_ENCRYPT is not set +# CONFIG_NUMA is not set +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_X86_PMEM_LEGACY is not set +# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set +CONFIG_X86_RESERVE_LOW=64 +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_X86_PAT=y +CONFIG_ARCH_USES_PG_UNCACHED=y +CONFIG_ARCH_RANDOM=y +# CONFIG_X86_SMAP is not set +CONFIG_X86_UMIP=y +# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +CONFIG_EFI=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_MIXED is not set +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_X86_NEED_RELOCS=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_DYNAMIC_MEMORY_LAYOUT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_COMPAT_VDSO is not set +# CONFIG_LEGACY_VSYSCALL_EMULATE is not set +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +CONFIG_LEGACY_VSYSCALL_NONE=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_HAVE_LIVEPATCH=y +# end of Processor type and features + +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y + +# +# Power management and ACPI options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_SLEEP=y +# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set +CONFIG_ACPI_EC_DEBUGFS=y +CONFIG_ACPI_AC=m +CONFIG_ACPI_BATTERY=m +CONFIG_ACPI_BUTTON=m +CONFIG_ACPI_TINY_POWER_BUTTON=m +CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38 +CONFIG_ACPI_FAN=m +# CONFIG_ACPI_TAD is not set +# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_THERMAL=m +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_TABLE_UPGRADE is not set +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=m +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_BGRT=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_APEI=y +# CONFIG_ACPI_APEI_GHES is not set +# CONFIG_ACPI_APEI_EINJ is not set +CONFIG_ACPI_APEI_ERST_DEBUG=y +# CONFIG_ACPI_DPTF is not set +# CONFIG_ACPI_CONFIGFS is not set +# CONFIG_PMIC_OPREGION is not set +CONFIG_X86_PM_TIMER=y +# CONFIG_SFI is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_PCC_CPUFREQ is not set +# CONFIG_X86_ACPI_CPUFREQ is not set +# CONFIG_X86_SPEEDSTEP_CENTRINO is not set +# CONFIG_X86_P4_CLOCKMOD is not set + +# +# shared options +# +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_HALTPOLL_CPUIDLE=y +# end of CPU Idle + +# CONFIG_INTEL_IDLE is not set +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_XEN=y +CONFIG_MMCONF_FAM10H=y +CONFIG_PCI_CNB20LE_QUIRK=y +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +CONFIG_AMD_NB=y +CONFIG_X86_SYSFB=y +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +CONFIG_IA32_EMULATION=y +# CONFIG_X86_X32 is not set +CONFIG_COMPAT_32=y +CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_SYSVIPC_COMPAT=y +# end of Binary Emulations + +# +# Firmware Drivers +# +# CONFIG_EDD is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_ISCSI_IBFT is not set +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=m +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +CONFIG_APPLE_PROPERTIES=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_EFI_DEV_PATH_PARSER=y +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_HAVE_KVM=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_ASYNC_PF=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_KVM_VFIO=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_COMPAT=y +CONFIG_HAVE_KVM_IRQ_BYPASS=y +CONFIG_HAVE_KVM_NO_POLL=y +CONFIG_KVM_XFER_TO_GUEST_WORK=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=m +CONFIG_KVM_WERROR=y +CONFIG_KVM_INTEL=m +CONFIG_KVM_AMD=m +CONFIG_KVM_AMD_SEV=y +# CONFIG_KVM_MMU_AUDIT is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y +CONFIG_AS_TPAUSE=y + +# +# General architecture-dependent options +# +CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y +CONFIG_OPROFILE=m +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_OPROFILE_NMI_TIMER=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set +CONFIG_OPTPROBES=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_KRETPROBES=y +CONFIG_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_ALL=y +CONFIG_MODULE_SIG_SHA1=y +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SIG_HASH="sha1" +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=m +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_IOCOST is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +# CONFIG_TRANSPARENT_HUGEPAGE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_CLEANCACHE=y +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZPOOL=m +# CONFIG_ZBUD is not set +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +# CONFIG_ZONE_DEVICE is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_MAPPING_DIRTY_HELPERS=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=m +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +# CONFIG_XFRM_USER_COMPAT is not set +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XDP_SOCKETS=y +# CONFIG_XDP_SOCKETS_DIAG is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +# CONFIG_IP_PIMSM_V1 is not set +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +# CONFIG_NFT_CONNLIMIT is not set +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_OBJREF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +# CONFIG_NFT_XFRM is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +# CONFIG_BPFILTER is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_INET_SCTP_DIAG=m +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_L2TP=m +# CONFIG_L2TP_DEBUGFS is not set +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +CONFIG_LLC2=m +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +# CONFIG_NET_SCH_SKBPRIO is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_SAMPLE is not set +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VMWARE_VMCI_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +# CONFIG_HYPERV_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_L3_MASTER_DEV=y +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=m +# CONFIG_PCI_PF_STUB is not set +CONFIG_XEN_PCIDEV_FRONTEND=y +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_HYPERV=m +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# PCI controller drivers +# +# CONFIG_VMD is not set +CONFIG_PCI_HYPERV_INTERFACE=m + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=m +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_SYS_HYPERVISOR=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_MHI_BUS is not set +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_PNP=y +# CONFIG_PNP_DEBUG_MESSAGES is not set + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_BLK_DEV_FD=m +CONFIG_CDROM=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_ZRAM=m +# CONFIG_ZRAM_WRITEBACK is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +# CONFIG_NVME_HWMON is not set +CONFIG_NVME_FABRICS=m +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_PASSTHRU is not set +CONFIG_NVME_TARGET_LOOP=m +# CONFIG_NVME_TARGET_FC is not set +# CONFIG_NVME_TARGET_TCP is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +CONFIG_VMWARE_BALLOON=m +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module (requires I2C) +# +# CONFIG_ALTERA_STAPL is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +CONFIG_VMWARE_VMCI=m +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# end of Misc devices + +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_VMWARE_PVSCSI=y +CONFIG_XEN_SCSI_FRONTEND=m +CONFIG_HYPERV_STORAGE=m +# CONFIG_LIBFC is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_VIRTIO=m +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_SX4 is not set +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_PATA_ACPI is not set +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +# CONFIG_MD_AUTODETECT is not set +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +# CONFIG_MD_CLUSTER is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_MULTIPATH_HST is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +# CONFIG_TCM_IBLOCK is not set +# CONFIG_TCM_FILEIO is not set +# CONFIG_TCM_PSCSI is not set +# CONFIG_LOOPBACK_TARGET is not set +# CONFIG_ISCSI_TARGET is not set +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +# CONFIG_IPVTAP is not set +CONFIG_VXLAN=m +CONFIG_GENEVE=m +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_CX_ECAT is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +CONFIG_E1000=m +# CONFIG_E1000E is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +CONFIG_IXGBEVF=m +# CONFIG_I40E is not set +CONFIG_IAVF=m +CONFIG_I40EVF=m +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_LAN743X is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +CONFIG_PHYLIB=m +# CONFIG_FIXED_PHY is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +CONFIG_MDIO_DEVICE=m +CONFIG_MDIO_BUS=m +CONFIG_MDIO_DEVRES=m +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +# CONFIG_PPPOE is not set +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +CONFIG_XEN_NETDEV_FRONTEND=y +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_VMXNET3=m +# CONFIG_FUJITSU_ES is not set +CONFIG_HYPERV_NET=m +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +# CONFIG_MOUSE_PS2_ALPS is not set +# CONFIG_MOUSE_PS2_BYD is not set +# CONFIG_MOUSE_PS2_LOGIPS2PP is not set +# CONFIG_MOUSE_PS2_SYNAPTICS is not set +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_CYPRESS is not set +# CONFIG_MOUSE_PS2_LIFEBOOK is not set +# CONFIG_MOUSE_PS2_TRACKPOINT is not set +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_PS2_FOCALTECH is not set +CONFIG_MOUSE_PS2_VMMOUSE=y +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_ATLAS_BTNS is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_CMA3000 is not set +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y +# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_HYPERV_KEYBOARD=m +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LDISC_AUTOLOAD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_8250_LPSS is not set +# CONFIG_SERIAL_8250_MID is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_LANTIQ is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 +CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_VIRTIO_CONSOLE=m +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_INTEL is not set +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_VIA is not set +CONFIG_HW_RANDOM_VIRTIO=m +# CONFIG_HW_RANDOM_XIPHERA is not set +# CONFIG_APPLICOM is not set +# CONFIG_MWAVE is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +CONFIG_NVRAM=m +# CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y +# CONFIG_HPET is not set +CONFIG_HANGCHECK_TIMER=m +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_PCA9541=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +CONFIG_I2C_PIIX4=m +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +# CONFIG_DP83640_PHY is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +CONFIG_PTP_1588_CLOCK_KVM=m +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +CONFIG_PTP_1588_CLOCK_VMW=m +# end of PTP clock support + +# CONFIG_PINCTRL is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_K8TEMP is not set +# CONFIG_SENSORS_K10TEMP is not set +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_AMD_ENERGY is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_DELL_SMM is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_XGENE is not set + +# +# ACPI drivers +# +CONFIG_SENSORS_ACPI_POWER=m +# CONFIG_SENSORS_ATK0110 is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +# CONFIG_INTEL_POWERCLAMP is not set +# CONFIG_INTEL_SOC_DTS_THERMAL is not set + +# +# ACPI INT340X thermal drivers +# +# CONFIG_INT340X_THERMAL is not set +# end of ACPI INT340X thermal drivers + +# CONFIG_INTEL_PCH_THERMAL is not set +# end of Intel thermal drivers + +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +CONFIG_WATCHDOG_SYSFS=y + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDAT_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_EBC_C384_WDT is not set +# CONFIG_F71808E_WDT is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_IBMASR is not set +# CONFIG_WAFER_WDT is not set +CONFIG_I6300ESB_WDT=m +# CONFIG_IE6XX_WDT is not set +# CONFIG_ITCO_WDT is not set +# CONFIG_IT8712F_WDT is not set +# CONFIG_IT87_WDT is not set +# CONFIG_HP_WATCHDOG is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_NV_TCO is not set +# CONFIG_60XX_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_SMSC_SCH311X_WDT is not set +# CONFIG_SMSC37B787_WDT is not set +# CONFIG_TQMX86_WDT is not set +# CONFIG_VIA_WDT is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +# CONFIG_NI903X_WDT is not set +# CONFIG_NIC7018_WDT is not set +CONFIG_XEN_WDT=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_LPSS_ACPI is not set +# CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8994 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_AGP is not set +# CONFIG_VGA_ARB is not set +CONFIG_DRM=m +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=m +CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_DMA_PAGE_POOL=y +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_I915 is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_VMWGFX=m +CONFIG_DRM_VMWGFX_FBCON=y +# CONFIG_DRM_GMA500 is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_CIRRUS_QEMU=m +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_XEN is not set +CONFIG_DRM_VBOXVIDEO=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=m +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +CONFIG_FB_VGA16=m +CONFIG_FB_UVESA=m +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_XEN_FBDEV_FRONTEND=m +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_FB_HYPERV=m +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=m +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +CONFIG_HID_CHERRY=m +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +CONFIG_HID_HYPERV_MOUSE=m +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +# CONFIG_INTEL_ISH_HID is not set +# end of Intel ISH HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +# CONFIG_USB_ULPI_BUS is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +# CONFIG_USB_XHCI_PCI_RENESAS is not set +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_PCI=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_TEST=m + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_I2C_AND_SPI=m + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD is not set +CONFIG_INTEL_IOATDMA=m +# CONFIG_PLX_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +CONFIG_QCOM_HIDMA=m +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ENGINE_RAID=y + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + +CONFIG_DCA=m +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VBOXGUEST=m +CONFIG_NITRO_ENCLAVES=m +CONFIG_VIRTIO=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=m +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_IFCVF=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +# CONFIG_VHOST_SCSI is not set +# CONFIG_VHOST_VSOCK is not set +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_HYPERV=m +CONFIG_HYPERV_TIMER=y +CONFIG_HYPERV_UTILS=m +CONFIG_HYPERV_BALLOON=m +# end of Microsoft Hyper-V guest support + +# +# Xen driver support +# +CONFIG_XEN_BALLOON=y +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG=y +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT=512 +CONFIG_XEN_SCRUB_PAGES_DEFAULT=y +CONFIG_XEN_DEV_EVTCHN=m +CONFIG_XEN_BACKEND=y +CONFIG_XENFS=y +CONFIG_XEN_COMPAT_XENFS=y +CONFIG_XEN_SYS_HYPERVISOR=y +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XEN_GNTDEV=m +CONFIG_XEN_GRANT_DEV_ALLOC=m +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_SWIOTLB_XEN=y +CONFIG_XEN_PCIDEV_BACKEND=m +CONFIG_XEN_PVCALLS_FRONTEND=m +# CONFIG_XEN_PVCALLS_BACKEND is not set +CONFIG_XEN_SCSI_BACKEND=m +CONFIG_XEN_PRIVCMD=y +CONFIG_XEN_ACPI_PROCESSOR=m +CONFIG_XEN_HAVE_PVMMU=y +CONFIG_XEN_EFI=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_ACPI=y +# CONFIG_XEN_SYMS is not set +CONFIG_XEN_HAVE_VPMU=y +# end of Xen driver support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +CONFIG_PMC_ATOM=y +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +# CONFIG_AMD_IOMMU is not set +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SVM is not set +# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +CONFIG_IRQ_REMAP=y +CONFIG_HYPERV_IOMMU=y + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +# CONFIG_RPMSG_CHAR is not set +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +CONFIG_MEMORY=y +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +# CONFIG_RAS is not set +# CONFIG_USB4 is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +CONFIG_DAX=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_TEE is not set +# CONFIG_UNISYS_VISORBUS is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=m +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=m +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +# CONFIG_REISERFS_FS_SECURITY is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_XFS_ONLINE_SCRUB=y +# CONFIG_XFS_ONLINE_REPAIR is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_FS_LZORLE=y +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +# CONFIG_MANDATORY_FILE_LOCKING is not set +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=m +CONFIG_FS_VERITY=y +# CONFIG_FS_VERITY_DEBUG is not set +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=m +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=m +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=m +CONFIG_CRAMFS=m +# CONFIG_CRAMFS_BLOCKDEV is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +# CONFIG_EROFS_FS is not set +CONFIG_VBOXSF_FS=m +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=m +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +# CONFIG_NFSD_V4_2_INTER_SSC is not set +# CONFIG_NFSD_V4_SECURITY_LABEL is not set +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y +# CONFIG_SUNRPC_DEBUG is not set +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_WEAK_PW_HASH is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +# CONFIG_9P_FS_SECURITY is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +CONFIG_ENCRYPTED_KEYS=m +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +# CONFIG_INTEL_TXT is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_FALLBACK=y +# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +# CONFIG_SECURITY_LOCKDOWN_LSM_EARLY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_EVM is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=m +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_SIMD=m +CONFIG_CRYPTO_GLUE_HELPER_X86=m +CONFIG_CRYPTO_ENGINE=m + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_X86=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +# CONFIG_CRYPTO_OFB is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_KEYWRAP=m +# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=m + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_CRC32C_INTEL=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32_PCLMUL=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_BLAKE2S_X86=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_POLY1305_X86_64=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_SSSE3=m +CONFIG_CRYPTO_SHA256_SSSE3=m +CONFIG_CRYPTO_SHA512_SSSE3=m +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AES_NI_INTEL=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_BLOWFISH_X86_64=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAMELLIA_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST5_AVX_X86_64=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST6_AVX_X86_64=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20_X86_64=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_TWOFISH_X86_64=m +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m +CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=m +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=m +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=m +CONFIG_CRYPTO_JITTERENTROPY=m +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_PADLOCK=m +CONFIG_CRYPTO_DEV_PADLOCK_AES=m +CONFIG_CRYPTO_DEV_PADLOCK_SHA=m +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_DD=m +CONFIG_CRYPTO_DEV_SP_CCP=y +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +CONFIG_CRYPTO_DEV_SP_PSP=y +# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +CONFIG_CRYPTO_DEV_QAT=m +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_CRYPTO_DEV_VIRTIO=m +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=m +# CONFIG_CRC4 is not set +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=m +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_INTERVAL_TREE=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_COPY_MC=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1280 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_STACK_VALIDATION=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +# end of Memory Debugging + +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_MMIOTRACE is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_KPROBE_EVENTS=y +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# x86 Debugging +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_TLBFLUSH is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +# CONFIG_X86_DECODER_SELFTEST is not set +CONFIG_IO_DELAY_0X80=y +# CONFIG_IO_DELAY_0XED is not set +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +CONFIG_DEBUG_NMI_SELFTEST=y +CONFIG_X86_DEBUG_FPU=y +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_MEMTEST is not set +# CONFIG_HYPERV_TESTING is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/main/linux/rtw89-add-Realtek-802.11ax-driver.patch b/main/linux/rtw89-add-Realtek-802.11ax-driver.patch new file mode 100644 index 0000000..6766b2d --- /dev/null +++ b/main/linux/rtw89-add-Realtek-802.11ax-driver.patch @@ -0,0 +1,93890 @@ +From patchwork Fri Aug 20 04:35:15 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448361 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 71A2BC432BE + for ; + Fri, 20 Aug 2021 04:36:39 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 5239560EB5 + for ; + Fri, 20 Aug 2021 04:36:39 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S232531AbhHTEhP (ORCPT + ); + Fri, 20 Aug 2021 00:37:15 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39207 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S231148AbhHTEhO (ORCPT + ); + Fri, 20 Aug 2021 00:37:14 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4aWssD003747, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4aWssD003747 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:32 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:32 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:31 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 01/24] rtw89: add CAM files +Date: Fri, 20 Aug 2021 12:35:15 +0800 +Message-ID: <20210820043538.12424-2-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Three kinds of CAM, security, address and bssid, are implemented in the +chip, and then we control them via H2C commands. + +Every vif contains one address and one bssid CAM entries, and both are +allocated while vif is adding. Once any state is changed, driver notices +firmware. For example, add/remove vif, sta assoc/disassoc, and changed +security key. + +When connecting to an AP with security, a security CAM entry is allocated +from security CAM pool and filled key values, and then attached to the +address CAM that contains seven keys entries for unicast, group and BIP +keys. Since the functions of these seven keys are predefined by firmware, +we should attach key to proper position depends on security entry mode and +key type. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/cam.c | 700 +++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/cam.h | 165 ++++++ + 2 files changed, 865 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/cam.c + create mode 100644 drivers/net/wireless/realtek/rtw89/cam.h + +diff --git a/drivers/net/wireless/realtek/rtw89/cam.c b/drivers/net/wireless/realtek/rtw89/cam.c +new file mode 100644 +index 000000000000..fac5b6e99089 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/cam.c +@@ -0,0 +1,700 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++ ++static struct sk_buff * ++rtw89_cam_get_sec_key_cmd(struct rtw89_dev *rtwdev, ++ struct rtw89_sec_cam_entry *sec_cam, ++ bool ext_key) ++{ ++ struct sk_buff *skb; ++ u32 cmd_len = H2C_SEC_CAM_LEN; ++ u32 key32[4]; ++ u8 *cmd; ++ int i, j; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(cmd_len); ++ if (!skb) ++ return NULL; ++ ++ skb_put_zero(skb, cmd_len); ++ ++ for (i = 0; i < 4; i++) { ++ j = i * 4; ++ j += ext_key ? 16 : 0; ++ key32[i] = FIELD_PREP(GENMASK(7, 0), sec_cam->key[j + 0]) | ++ FIELD_PREP(GENMASK(15, 8), sec_cam->key[j + 1]) | ++ FIELD_PREP(GENMASK(23, 16), sec_cam->key[j + 2]) | ++ FIELD_PREP(GENMASK(31, 24), sec_cam->key[j + 3]); ++ } ++ ++ cmd = skb->data; ++ RTW89_SET_FWCMD_SEC_IDX(cmd, sec_cam->sec_cam_idx + (ext_key ? 1 : 0)); ++ RTW89_SET_FWCMD_SEC_OFFSET(cmd, sec_cam->offset); ++ RTW89_SET_FWCMD_SEC_LEN(cmd, sec_cam->len); ++ RTW89_SET_FWCMD_SEC_TYPE(cmd, sec_cam->type); ++ RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, ext_key); ++ RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, sec_cam->spp_mode); ++ RTW89_SET_FWCMD_SEC_KEY0(cmd, key32[0]); ++ RTW89_SET_FWCMD_SEC_KEY1(cmd, key32[1]); ++ RTW89_SET_FWCMD_SEC_KEY2(cmd, key32[2]); ++ RTW89_SET_FWCMD_SEC_KEY3(cmd, key32[3]); ++ ++ return skb; ++} ++ ++static int rtw89_cam_send_sec_key_cmd(struct rtw89_dev *rtwdev, ++ struct rtw89_sec_cam_entry *sec_cam) ++{ ++ struct sk_buff *skb, *ext_skb; ++ int ret; ++ ++ skb = rtw89_cam_get_sec_key_cmd(rtwdev, sec_cam, false); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to get sec key command\n"); ++ return -ENOMEM; ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, ++ FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_SEC_CAM, ++ H2C_FUNC_MAC_SEC_UPD, 1, 0, ++ H2C_SEC_CAM_LEN); ++ ret = rtw89_h2c_tx(rtwdev, skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send sec key h2c: %d\n", ret); ++ dev_kfree_skb(skb); ++ return ret; ++ } ++ ++ if (!sec_cam->ext_key) ++ return 0; ++ ++ ext_skb = rtw89_cam_get_sec_key_cmd(rtwdev, sec_cam, true); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to get ext sec key command\n"); ++ return -ENOMEM; ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, ext_skb, ++ FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_SEC_CAM, ++ H2C_FUNC_MAC_SEC_UPD, ++ 1, 0, H2C_SEC_CAM_LEN); ++ ret = rtw89_h2c_tx(rtwdev, ext_skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send ext sec key h2c: %d\n", ret); ++ dev_kfree_skb(ext_skb); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_avail_sec_cam(struct rtw89_dev *rtwdev, ++ u8 *sec_cam_idx, bool ext_key) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 sec_cam_num = chip->scam_num; ++ u8 idx = 0; ++ ++ if (!ext_key) { ++ idx = find_first_zero_bit(cam_info->sec_cam_map, sec_cam_num); ++ if (idx >= sec_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->sec_cam_map); ++ *sec_cam_idx = idx; ++ ++ return 0; ++ } ++ ++again: ++ idx = find_next_zero_bit(cam_info->sec_cam_map, sec_cam_num, idx); ++ if (idx >= sec_cam_num - 1) ++ return -EBUSY; ++ /* ext keys need two cam entries for 256-bit key */ ++ if (test_bit(idx + 1, cam_info->sec_cam_map)) { ++ idx++; ++ goto again; ++ } ++ ++ set_bit(idx, cam_info->sec_cam_map); ++ set_bit(idx + 1, cam_info->sec_cam_map); ++ *sec_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_addr_cam_key_idx(struct rtw89_addr_cam_entry *addr_cam, ++ struct rtw89_sec_cam_entry *sec_cam, ++ struct ieee80211_key_conf *key, ++ u8 *key_idx) ++{ ++ u8 idx; ++ ++ /* RTW89_ADDR_CAM_SEC_NONE : not enabled ++ * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast ++ * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP ++ * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP ++ */ ++ switch (addr_cam->sec_ent_mode) { ++ case RTW89_ADDR_CAM_SEC_NONE: ++ return -EINVAL; ++ case RTW89_ADDR_CAM_SEC_ALL_UNI: ++ if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) ++ return -EINVAL; ++ idx = find_first_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM); ++ if (idx >= RTW89_SEC_CAM_IN_ADDR_CAM) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ case RTW89_ADDR_CAM_SEC_NORMAL: ++ if (sec_cam->type == RTW89_SEC_KEY_TYPE_BIP_CCMP128) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 5); ++ if (idx > 6) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 0); ++ if (idx > 1) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ /* Group keys */ ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 2); ++ if (idx > 4) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ case RTW89_ADDR_CAM_SEC_4GROUP: ++ if (sec_cam->type == RTW89_SEC_KEY_TYPE_BIP_CCMP128) { ++ if (test_bit(6, addr_cam->sec_cam_map)) ++ return -EINVAL; ++ *key_idx = 6; ++ break; ++ } ++ ++ if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 0); ++ if (idx > 1) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ /* Group keys */ ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 2); ++ if (idx > 5) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ struct rtw89_sec_cam_entry *sec_cam) ++{ ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ u8 key_idx = 0; ++ int ret; ++ ++ if (!vif) { ++ rtw89_err(rtwdev, "No iface for adding sec cam\n"); ++ return -EINVAL; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ ret = rtw89_cam_get_addr_cam_key_idx(addr_cam, sec_cam, key, &key_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get addr cam key idx %d, %d\n", ++ addr_cam->sec_ent_mode, sec_cam->type); ++ return ret; ++ } ++ ++ key->hw_key_idx = key_idx; ++ addr_cam->sec_ent_keyid[key_idx] = key->keyidx; ++ addr_cam->sec_ent[key_idx] = sec_cam->sec_cam_idx; ++ addr_cam->sec_entries[key_idx] = sec_cam; ++ set_bit(key_idx, addr_cam->sec_cam_map); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update addr cam sec entry: %d\n", ++ ret); ++ clear_bit(key_idx, addr_cam->sec_cam_map); ++ addr_cam->sec_entries[key_idx] = NULL; ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_sec_key_install(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ u8 hw_key_type, bool ext_key) ++{ ++ struct rtw89_sec_cam_entry *sec_cam = NULL; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 sec_cam_idx; ++ int ret; ++ ++ /* maximum key length 256-bit */ ++ if (key->keylen > 32) { ++ rtw89_err(rtwdev, "invalid sec key length %d\n", key->keylen); ++ return -EINVAL; ++ } ++ ++ ret = rtw89_cam_get_avail_sec_cam(rtwdev, &sec_cam_idx, ext_key); ++ if (ret) { ++ rtw89_warn(rtwdev, "no available sec cam: %d ext: %d\n", ++ ret, ext_key); ++ return ret; ++ } ++ ++ sec_cam = kzalloc(sizeof(*sec_cam), GFP_KERNEL); ++ if (!sec_cam) { ++ ret = -ENOMEM; ++ goto err_release_cam; ++ } ++ ++ sec_cam->sec_cam_idx = sec_cam_idx; ++ sec_cam->type = hw_key_type; ++ sec_cam->len = RTW89_SEC_CAM_LEN; ++ sec_cam->ext_key = ext_key; ++ memcpy(sec_cam->key, key->key, key->keylen); ++ ret = rtw89_cam_send_sec_key_cmd(rtwdev, sec_cam); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send sec key cmd: %d\n", ret); ++ goto err_release_cam; ++ } ++ ++ /* associate with addr cam */ ++ ret = rtw89_cam_attach_sec_cam(rtwdev, vif, sta, key, sec_cam); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to attach sec cam: %d\n", ret); ++ goto err_release_cam; ++ } ++ ++ return 0; ++ ++err_release_cam: ++ kfree(sec_cam); ++ clear_bit(sec_cam_idx, cam_info->sec_cam_map); ++ if (ext_key) ++ clear_bit(sec_cam_idx + 1, cam_info->sec_cam_map); ++ ++ return ret; ++} ++ ++int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key) ++{ ++ u8 hw_key_type; ++ bool ext_key = false; ++ int ret; ++ ++ switch (key->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ hw_key_type = RTW89_SEC_KEY_TYPE_WEP40; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ hw_key_type = RTW89_SEC_KEY_TYPE_WEP104; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ hw_key_type = RTW89_SEC_KEY_TYPE_CCMP128; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP_256: ++ hw_key_type = RTW89_SEC_KEY_TYPE_CCMP256; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ ext_key = true; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP: ++ hw_key_type = RTW89_SEC_KEY_TYPE_GCMP128; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP_256: ++ hw_key_type = RTW89_SEC_KEY_TYPE_GCMP256; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ ext_key = true; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ case WLAN_CIPHER_SUITE_AES_CMAC: ++ case WLAN_CIPHER_SUITE_BIP_CMAC_256: ++ case WLAN_CIPHER_SUITE_BIP_GMAC_128: ++ case WLAN_CIPHER_SUITE_BIP_GMAC_256: ++ /* suppress error messages */ ++ return -EOPNOTSUPP; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; ++ ++ ret = rtw89_cam_sec_key_install(rtwdev, vif, sta, key, hw_key_type, ++ ext_key); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to install key type %d ext %d: %d\n", ++ hw_key_type, ext_key, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ bool inform_fw) ++{ ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ struct rtw89_sec_cam_entry *sec_cam; ++ u8 key_idx = key->hw_key_idx; ++ u8 sec_cam_idx; ++ int ret = 0; ++ ++ if (!vif) { ++ rtw89_err(rtwdev, "No iface for deleting sec cam\n"); ++ return -EINVAL; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ sec_cam = addr_cam->sec_entries[key_idx]; ++ ++ /* detach sec cam from addr cam */ ++ clear_bit(key_idx, addr_cam->sec_cam_map); ++ addr_cam->sec_entries[key_idx] = NULL; ++ if (inform_fw) { ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ rtw89_err(rtwdev, "failed to update cam del key: %d\n", ret); ++ } ++ ++ /* clear valid bit in addr cam will disable sec cam, ++ * so we don't need to send H2C command again ++ */ ++ sec_cam_idx = sec_cam->sec_cam_idx; ++ clear_bit(sec_cam_idx, cam_info->sec_cam_map); ++ if (sec_cam->ext_key) ++ clear_bit(sec_cam_idx + 1, cam_info->sec_cam_map); ++ ++ kfree(sec_cam); ++ ++ return ret; ++} ++ ++static void rtw89_cam_reset_key_iter(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ void *data) ++{ ++ struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ rtw89_cam_sec_key_del(rtwdev, vif, sta, key, false); ++ rtw89_cam_deinit(rtwdev, rtwvif); ++} ++ ++void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ ++ addr_cam->valid = false; ++ bssid_cam->valid = false; ++ clear_bit(addr_cam->addr_cam_idx, cam_info->addr_cam_map); ++ clear_bit(bssid_cam->bssid_cam_idx, cam_info->bssid_cam_map); ++} ++ ++void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev) ++{ ++ rcu_read_lock(); ++ ieee80211_iter_keys_rcu(rtwdev->hw, NULL, rtw89_cam_reset_key_iter, rtwdev); ++ rcu_read_unlock(); ++} ++ ++static int rtw89_cam_get_avail_addr_cam(struct rtw89_dev *rtwdev, ++ u8 *addr_cam_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 addr_cam_num = chip->acam_num; ++ u8 idx; ++ ++ idx = find_first_zero_bit(cam_info->addr_cam_map, addr_cam_num); ++ if (idx >= addr_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->addr_cam_map); ++ *addr_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_init_addr_cam(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ u8 addr_cam_idx; ++ int i; ++ int ret; ++ ++ ret = rtw89_cam_get_avail_addr_cam(rtwdev, &addr_cam_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get available addr cam\n"); ++ return ret; ++ } ++ ++ addr_cam->addr_cam_idx = addr_cam_idx; ++ addr_cam->len = ADDR_CAM_ENT_SIZE; ++ addr_cam->offset = 0; ++ addr_cam->valid = true; ++ addr_cam->addr_mask = 0; ++ addr_cam->mask_sel = RTW89_NO_MSK; ++ bitmap_zero(addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); ++ ether_addr_copy(addr_cam->sma, rtwvif->mac_addr); ++ ++ for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { ++ addr_cam->sec_ent_keyid[i] = 0; ++ addr_cam->sec_ent[i] = 0; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_avail_bssid_cam(struct rtw89_dev *rtwdev, ++ u8 *bssid_cam_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 bssid_cam_num = chip->bcam_num; ++ u8 idx; ++ ++ idx = find_first_zero_bit(cam_info->bssid_cam_map, bssid_cam_num); ++ if (idx >= bssid_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->bssid_cam_map); ++ *bssid_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_init_bssid_cam(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ u8 bssid_cam_idx; ++ int ret; ++ ++ ret = rtw89_cam_get_avail_bssid_cam(rtwdev, &bssid_cam_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get available bssid cam\n"); ++ return ret; ++ } ++ ++ bssid_cam->bssid_cam_idx = bssid_cam_idx; ++ bssid_cam->phy_idx = rtwvif->phy_idx; ++ bssid_cam->len = BSSID_CAM_ENT_SIZE; ++ bssid_cam->offset = 0; ++ bssid_cam->valid = true; ++ ether_addr_copy(bssid_cam->bssid, rtwvif->bssid); ++ ++ return 0; ++} ++ ++void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ ether_addr_copy(addr_cam->tma, rtwvif->bssid); ++ ether_addr_copy(bssid_cam->bssid, rtwvif->bssid); ++} ++ ++int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ int ret; ++ ++ ret = rtw89_cam_init_addr_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init addr cam\n"); ++ return ret; ++ } ++ ++ ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init bssid cam\n"); ++ return ret; ++ } ++ ++ /* associate addr cam with bssid cam */ ++ addr_cam->bssid_cam_idx = bssid_cam->bssid_cam_idx; ++ ++ return 0; ++} ++ ++int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u8 *cmd) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ u8 bss_color = vif->bss_conf.he_bss_color.color; ++ ++ FWCMD_SET_ADDR_BSSID_IDX(cmd, bssid_cam->bssid_cam_idx); ++ FWCMD_SET_ADDR_BSSID_OFFSET(cmd, bssid_cam->offset); ++ FWCMD_SET_ADDR_BSSID_LEN(cmd, bssid_cam->len); ++ FWCMD_SET_ADDR_BSSID_VALID(cmd, bssid_cam->valid); ++ FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, bssid_cam->phy_idx); ++ FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, bss_color); ++ ++ FWCMD_SET_ADDR_BSSID_BSSID0(cmd, bssid_cam->bssid[0]); ++ FWCMD_SET_ADDR_BSSID_BSSID1(cmd, bssid_cam->bssid[1]); ++ FWCMD_SET_ADDR_BSSID_BSSID2(cmd, bssid_cam->bssid[2]); ++ FWCMD_SET_ADDR_BSSID_BSSID3(cmd, bssid_cam->bssid[3]); ++ FWCMD_SET_ADDR_BSSID_BSSID4(cmd, bssid_cam->bssid[4]); ++ FWCMD_SET_ADDR_BSSID_BSSID5(cmd, bssid_cam->bssid[5]); ++ ++ return 0; ++} ++ ++static u8 rtw89_cam_addr_hash(u8 start, u8 *addr) ++{ ++ u8 hash = 0; ++ u8 i; ++ ++ for (i = start; i < ETH_ALEN; i++) ++ hash ^= addr[i]; ++ ++ return hash; ++} ++ ++void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ u8 *cmd) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct ieee80211_sta *sta; ++ struct rtw89_sta *rtwsta; ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ u8 sma_hash, tma_hash, addr_msk_start; ++ u8 sma_start = 0; ++ u8 tma_start = 0; ++ ++ if (addr_cam->addr_mask != 0) { ++ addr_msk_start = __ffs(addr_cam->addr_mask); ++ if (addr_cam->mask_sel == RTW89_SMA) ++ sma_start = addr_msk_start; ++ else if (addr_cam->mask_sel == RTW89_TMA) ++ tma_start = addr_msk_start; ++ } ++ sma_hash = rtw89_cam_addr_hash(sma_start, rtwvif->mac_addr); ++ tma_hash = rtw89_cam_addr_hash(tma_start, addr_cam->tma); ++ ++ FWCMD_SET_ADDR_IDX(cmd, addr_cam->addr_cam_idx); ++ FWCMD_SET_ADDR_OFFSET(cmd, addr_cam->offset); ++ FWCMD_SET_ADDR_LEN(cmd, addr_cam->len); ++ ++ FWCMD_SET_ADDR_VALID(cmd, addr_cam->valid); ++ FWCMD_SET_ADDR_NET_TYPE(cmd, rtwvif->net_type); ++ FWCMD_SET_ADDR_BCN_HIT_COND(cmd, rtwvif->bcn_hit_cond); ++ FWCMD_SET_ADDR_HIT_RULE(cmd, rtwvif->hit_rule); ++ FWCMD_SET_ADDR_BB_SEL(cmd, rtwvif->phy_idx); ++ FWCMD_SET_ADDR_ADDR_MASK(cmd, addr_cam->addr_mask); ++ FWCMD_SET_ADDR_MASK_SEL(cmd, addr_cam->mask_sel); ++ FWCMD_SET_ADDR_SMA_HASH(cmd, sma_hash); ++ FWCMD_SET_ADDR_TMA_HASH(cmd, tma_hash); ++ ++ FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, addr_cam->bssid_cam_idx); ++ ++ FWCMD_SET_ADDR_SMA0(cmd, rtwvif->mac_addr[0]); ++ FWCMD_SET_ADDR_SMA1(cmd, rtwvif->mac_addr[1]); ++ FWCMD_SET_ADDR_SMA2(cmd, rtwvif->mac_addr[2]); ++ FWCMD_SET_ADDR_SMA3(cmd, rtwvif->mac_addr[3]); ++ FWCMD_SET_ADDR_SMA4(cmd, rtwvif->mac_addr[4]); ++ FWCMD_SET_ADDR_SMA5(cmd, rtwvif->mac_addr[5]); ++ ++ FWCMD_SET_ADDR_TMA0(cmd, addr_cam->tma[0]); ++ FWCMD_SET_ADDR_TMA1(cmd, addr_cam->tma[1]); ++ FWCMD_SET_ADDR_TMA2(cmd, addr_cam->tma[2]); ++ FWCMD_SET_ADDR_TMA3(cmd, addr_cam->tma[3]); ++ FWCMD_SET_ADDR_TMA4(cmd, addr_cam->tma[4]); ++ FWCMD_SET_ADDR_TMA5(cmd, addr_cam->tma[5]); ++ ++ FWCMD_SET_ADDR_PORT_INT(cmd, rtwvif->port); ++ FWCMD_SET_ADDR_TSF_SYNC(cmd, rtwvif->port); ++ FWCMD_SET_ADDR_TF_TRS(cmd, rtwvif->trigger); ++ FWCMD_SET_ADDR_LSIG_TXOP(cmd, rtwvif->lsig_txop); ++ FWCMD_SET_ADDR_TGT_IND(cmd, rtwvif->tgt_ind); ++ FWCMD_SET_ADDR_FRM_TGT_IND(cmd, rtwvif->frm_tgt_ind); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ sta = rtwvif->mgd.ap; ++ if (sta) { ++ rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ FWCMD_SET_ADDR_MACID(cmd, rtwsta->mac_id); ++ FWCMD_SET_ADDR_AID12(cmd, vif->bss_conf.aid & 0xfff); ++ } ++ } ++ FWCMD_SET_ADDR_WOL_PATTERN(cmd, rtwvif->wowlan_pattern); ++ FWCMD_SET_ADDR_WOL_UC(cmd, rtwvif->wowlan_uc); ++ FWCMD_SET_ADDR_WOL_MAGIC(cmd, rtwvif->wowlan_magic); ++ FWCMD_SET_ADDR_WAPI(cmd, addr_cam->wapi); ++ FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, addr_cam->sec_ent_mode); ++ FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, addr_cam->sec_ent_keyid[0]); ++ FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, addr_cam->sec_ent_keyid[1]); ++ FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, addr_cam->sec_ent_keyid[2]); ++ FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, addr_cam->sec_ent_keyid[3]); ++ FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, addr_cam->sec_ent_keyid[4]); ++ FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, addr_cam->sec_ent_keyid[5]); ++ FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, addr_cam->sec_ent_keyid[6]); ++ ++ FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, addr_cam->sec_cam_map[0] & 0xff); ++ FWCMD_SET_ADDR_SEC_ENT0(cmd, addr_cam->sec_ent[0]); ++ FWCMD_SET_ADDR_SEC_ENT1(cmd, addr_cam->sec_ent[1]); ++ FWCMD_SET_ADDR_SEC_ENT2(cmd, addr_cam->sec_ent[2]); ++ FWCMD_SET_ADDR_SEC_ENT3(cmd, addr_cam->sec_ent[3]); ++ FWCMD_SET_ADDR_SEC_ENT4(cmd, addr_cam->sec_ent[4]); ++ FWCMD_SET_ADDR_SEC_ENT5(cmd, addr_cam->sec_ent[5]); ++ FWCMD_SET_ADDR_SEC_ENT6(cmd, addr_cam->sec_ent[6]); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/cam.h b/drivers/net/wireless/realtek/rtw89/cam.h +new file mode 100644 +index 000000000000..90a20a5375c6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/cam.h +@@ -0,0 +1,165 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_CAM_H__ ++#define __RTW89_CAM_H__ ++ ++#include "core.h" ++ ++#define RTW89_SEC_CAM_LEN 20 ++ ++#define FWCMD_SET_ADDR_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_OFFSET(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_LEN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)) ++#define FWCMD_SET_ADDR_NET_TYPE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)) ++#define FWCMD_SET_ADDR_BCN_HIT_COND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)) ++#define FWCMD_SET_ADDR_HIT_RULE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)) ++#define FWCMD_SET_ADDR_BB_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(7)) ++#define FWCMD_SET_ADDR_ADDR_MASK(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)) ++#define FWCMD_SET_ADDR_MASK_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14)) ++#define FWCMD_SET_ADDR_SMA_HASH(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA_HASH(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)) ++#define FWCMD_SET_ADDR_SMA0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SMA1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SMA2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SMA3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_SMA4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SMA5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_TMA0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_TMA2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_TMA3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_TMA4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_MACID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_PORT_INT(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(10, 8)) ++#define FWCMD_SET_ADDR_TSF_SYNC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(13, 11)) ++#define FWCMD_SET_ADDR_TF_TRS(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(14)) ++#define FWCMD_SET_ADDR_LSIG_TXOP(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(15)) ++#define FWCMD_SET_ADDR_TGT_IND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(26, 24)) ++#define FWCMD_SET_ADDR_FRM_TGT_IND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(29, 27)) ++#define FWCMD_SET_ADDR_AID12(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 0)) ++#define FWCMD_SET_ADDR_AID12_0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_AID12_1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 8)) ++#define FWCMD_SET_ADDR_WOL_PATTERN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(12)) ++#define FWCMD_SET_ADDR_WOL_UC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(13)) ++#define FWCMD_SET_ADDR_WOL_MAGIC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(14)) ++#define FWCMD_SET_ADDR_WAPI(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(15)) ++#define FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(17, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(19, 18)) ++#define FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(21, 20)) ++#define FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(23, 22)) ++#define FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(25, 24)) ++#define FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(27, 26)) ++#define FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(29, 28)) ++#define FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(31, 30)) ++#define FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SEC_ENT0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SEC_ENT1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_SEC_ENT3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SEC_ENT4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SEC_ENT5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT6(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_BSSID_OFFSET(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_BSSID_LEN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(0)) ++#define FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(1)) ++#define FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(13, 8)) ++#define FWCMD_SET_ADDR_BSSID_BSSID0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_BSSID1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_BSSID2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_BSSID_BSSID3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_BSSID_BSSID4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_BSSID5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(31, 24)) ++ ++int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *vif, u8 *cmd); ++int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *vif, u8 *cmd); ++int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key); ++int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ bool inform_fw); ++void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif); ++void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev); ++#endif + +From patchwork Fri Aug 20 04:35:16 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448363 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id C5265C4338F + for ; + Fri, 20 Aug 2021 04:36:44 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 8BF4160EB5 + for ; + Fri, 20 Aug 2021 04:36:44 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233108AbhHTEhU (ORCPT + ); + Fri, 20 Aug 2021 00:37:20 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39211 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S231148AbhHTEhT (ORCPT + ); + Fri, 20 Aug 2021 00:37:19 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4abVlB003752, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4abVlB003752 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:37 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:36 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:35 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 02/24] rtw89: add BT coexistence files +Date: Fri, 20 Aug 2021 12:35:16 +0800 +Message-ID: <20210820043538.12424-3-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_all_Bitcoin, bb} +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +BT coexistence uses TDMA-based mechanism to coordinate with WiFi and BT. +Now, we implement basic coexistence features for wide use cases, such as +HID and A2DP. More will be supported later. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/coex.c | 5743 +++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/coex.h | 179 + + 2 files changed, 5922 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/coex.c + create mode 100644 drivers/net/wireless/realtek/rtw89/coex.h + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +new file mode 100644 +index 000000000000..34117acfe71a +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -0,0 +1,5743 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++ ++#define FCXDEF_STEP 50 /* MUST <= FCXMAX_STEP and match with wl fw*/ ++ ++enum btc_fbtc_tdma_template { ++ CXTD_OFF = 0x0, ++ CXTD_OFF_B2, ++ CXTD_OFF_EXT, ++ CXTD_FIX, ++ CXTD_PFIX, ++ CXTD_AUTO, ++ CXTD_PAUTO, ++ CXTD_AUTO2, ++ CXTD_PAUTO2, ++ CXTD_MAX, ++}; ++ ++enum btc_fbtc_tdma_type { ++ CXTDMA_OFF = 0x0, ++ CXTDMA_FIX = 0x1, ++ CXTDMA_AUTO = 0x2, ++ CXTDMA_AUTO2 = 0x3, ++ CXTDMA_MAX ++}; ++ ++enum btc_fbtc_tdma_rx_flow_ctrl { ++ CXFLC_OFF = 0x0, ++ CXFLC_NULLP = 0x1, ++ CXFLC_QOSNULL = 0x2, ++ CXFLC_CTS = 0x3, ++ CXFLC_MAX ++}; ++ ++enum btc_fbtc_tdma_wlan_tx_pause { ++ CXTPS_OFF = 0x0, /* no wl tx pause*/ ++ CXTPS_ON = 0x1, ++ CXTPS_MAX ++}; ++ ++enum btc_mlme_state { ++ MLME_NO_LINK, ++ MLME_LINKING, ++ MLME_LINKED, ++}; ++ ++#define FCXONESLOT_VER 1 ++struct btc_fbtc_1slot { ++ u8 fver; ++ u8 sid; /* slot id */ ++ struct rtw89_btc_fbtc_slot slot; ++} __packed; ++ ++static const struct rtw89_btc_fbtc_tdma t_def[] = { ++ [CXTD_OFF] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_OFF_B2] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0}, ++ [CXTD_OFF_EXT] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 3, 0, 0}, ++ [CXTD_FIX] = { CXTDMA_FIX, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PFIX] = { CXTDMA_FIX, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, ++ [CXTD_AUTO] = { CXTDMA_AUTO, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PAUTO] = { CXTDMA_AUTO, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, ++ [CXTD_AUTO2] = {CXTDMA_AUTO2, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PAUTO2] = {CXTDMA_AUTO2, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0} ++}; ++ ++#define __DEF_FBTC_SLOT(__dur, __cxtbl, __cxtype) \ ++ { .dur = cpu_to_le16(__dur), .cxtbl = cpu_to_le32(__cxtbl), \ ++ .cxtype = cpu_to_le16(__cxtype),} ++ ++static const struct rtw89_btc_fbtc_slot s_def[] = { ++ [CXST_OFF] = __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX), ++ [CXST_B2W] = __DEF_FBTC_SLOT(5, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_W1] = __DEF_FBTC_SLOT(70, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_W2] = __DEF_FBTC_SLOT(70, 0x5a5a5aaa, SLOT_ISO), ++ [CXST_W2B] = __DEF_FBTC_SLOT(15, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_B1] = __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX), ++ [CXST_B2] = __DEF_FBTC_SLOT(7, 0x6a5a5a5a, SLOT_MIX), ++ [CXST_B3] = __DEF_FBTC_SLOT(5, 0x55555555, SLOT_MIX), ++ [CXST_B4] = __DEF_FBTC_SLOT(50, 0x55555555, SLOT_MIX), ++ [CXST_LK] = __DEF_FBTC_SLOT(20, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_BLK] = __DEF_FBTC_SLOT(250, 0x55555555, SLOT_MIX), ++ [CXST_E2G] = __DEF_FBTC_SLOT(20, 0x6a5a5a5a, SLOT_MIX), ++ [CXST_E5G] = __DEF_FBTC_SLOT(20, 0xffffffff, SLOT_MIX), ++ [CXST_EBT] = __DEF_FBTC_SLOT(20, 0x55555555, SLOT_MIX), ++ [CXST_ENULL] = __DEF_FBTC_SLOT(7, 0xaaaaaaaa, SLOT_ISO), ++ [CXST_WLK] = __DEF_FBTC_SLOT(250, 0x6a5a6a5a, SLOT_MIX), ++ [CXST_W1FDD] = __DEF_FBTC_SLOT(35, 0xfafafafa, SLOT_ISO), ++ [CXST_B1FDD] = __DEF_FBTC_SLOT(100, 0xffffffff, SLOT_MIX), ++}; ++ ++static const u32 cxtbl[] = { ++ 0xffffffff, /* 0 */ ++ 0xaaaaaaaa, /* 1 */ ++ 0x55555555, /* 2 */ ++ 0x66555555, /* 3 */ ++ 0x66556655, /* 4 */ ++ 0x5a5a5a5a, /* 5 */ ++ 0x5a5a5aaa, /* 6 */ ++ 0xaa5a5a5a, /* 7 */ ++ 0x6a5a5a5a, /* 8 */ ++ 0x6a5a5aaa, /* 9 */ ++ 0x6a5a6a5a, /* 10 */ ++ 0x6a5a6aaa, /* 11 */ ++ 0x6afa5afa, /* 12 */ ++ 0xaaaa5aaa, /* 13 */ ++ 0xaaffffaa, /* 14 */ ++ 0xaa5555aa, /* 15 */ ++ 0xfafafafa, /* 16 */ ++ 0xffffddff, /* 17 */ ++ 0xdaffdaff, /* 18 */ ++ 0xfafadafa /* 19 */ ++}; ++ ++struct rtw89_btc_btf_tlv { ++ u8 type; ++ u8 len; ++ u8 val[1]; ++} __packed; ++ ++enum btc_btf_set_report_en { ++ RPT_EN_TDMA = BIT(0), ++ RPT_EN_CYCLE = BIT(1), ++ RPT_EN_MREG = BIT(2), ++ RPT_EN_BT_VER_INFO = BIT(3), ++ RPT_EN_BT_SCAN_INFO = BIT(4), ++ RPT_EN_BT_AFH_MAP = BIT(5), ++ RPT_EN_BT_DEVICE_INFO = BIT(6), ++ RPT_EN_WL_ALL = GENMASK(2, 0), ++ RPT_EN_BT_ALL = GENMASK(6, 3), ++ RPT_EN_ALL = GENMASK(6, 0), ++}; ++ ++#define BTF_SET_REPORT_VER 1 ++struct rtw89_btc_btf_set_report { ++ u8 fver; ++ __le32 enable; ++ __le32 para; ++} __packed; ++ ++#define BTF_SET_SLOT_TABLE_VER 1 ++struct rtw89_btc_btf_set_slot_table { ++ u8 fver; ++ u8 tbl_num; ++ u8 buf[]; ++} __packed; ++ ++#define BTF_SET_MON_REG_VER 1 ++struct rtw89_btc_btf_set_mon_reg { ++ u8 fver; ++ u8 reg_num; ++ u8 buf[]; ++} __packed; ++ ++enum btc_btf_set_cx_policy { ++ CXPOLICY_TDMA = 0x0, ++ CXPOLICY_SLOT = 0x1, ++ CXPOLICY_TYPE = 0x2, ++ CXPOLICY_MAX, ++}; ++ ++enum btc_b2w_scoreboard { ++ BTC_BSCB_ACT = BIT(0), ++ BTC_BSCB_ON = BIT(1), ++ BTC_BSCB_WHQL = BIT(2), ++ BTC_BSCB_BT_S1 = BIT(3), ++ BTC_BSCB_A2DP_ACT = BIT(4), ++ BTC_BSCB_RFK_RUN = BIT(5), ++ BTC_BSCB_RFK_REQ = BIT(6), ++ BTC_BSCB_LPS = BIT(7), ++ BTC_BSCB_WLRFK = BIT(11), ++ BTC_BSCB_BT_HILNA = BIT(13), ++ BTC_BSCB_BT_CONNECT = BIT(16), ++ BTC_BSCB_PATCH_CODE = BIT(30), ++ BTC_BSCB_ALL = GENMASK(30, 0), ++}; ++ ++enum btc_phymap { ++ BTC_PHY_0 = BIT(0), ++ BTC_PHY_1 = BIT(1), ++ BTC_PHY_ALL = BIT(0) | BIT(1), ++}; ++ ++enum btc_cx_state_map { ++ BTC_WIDLE = 0, ++ BTC_WBUSY_BNOSCAN, ++ BTC_WBUSY_BSCAN, ++ BTC_WSCAN_BNOSCAN, ++ BTC_WSCAN_BSCAN, ++ BTC_WLINKING ++}; ++ ++enum btc_ant_phase { ++ BTC_ANT_WPOWERON = 0, ++ BTC_ANT_WINIT, ++ BTC_ANT_WONLY, ++ BTC_ANT_WOFF, ++ BTC_ANT_W2G, ++ BTC_ANT_W5G, ++ BTC_ANT_W25G, ++ BTC_ANT_FREERUN, ++ BTC_ANT_WRFK, ++ BTC_ANT_BRFK, ++ BTC_ANT_MAX ++}; ++ ++enum btc_plt { ++ BTC_PLT_NONE = 0, ++ BTC_PLT_LTE_RX = BIT(0), ++ BTC_PLT_GNT_BT_TX = BIT(1), ++ BTC_PLT_GNT_BT_RX = BIT(2), ++ BTC_PLT_GNT_WL = BIT(3), ++ BTC_PLT_BT = BIT(1) | BIT(2), ++ BTC_PLT_ALL = 0xf ++}; ++ ++enum btc_cx_poicy_main_type { ++ BTC_CXP_OFF = 0, ++ BTC_CXP_OFFB, ++ BTC_CXP_OFFE, ++ BTC_CXP_FIX, ++ BTC_CXP_PFIX, ++ BTC_CXP_AUTO, ++ BTC_CXP_PAUTO, ++ BTC_CXP_AUTO2, ++ BTC_CXP_PAUTO2, ++ BTC_CXP_MANUAL, ++ BTC_CXP_USERDEF0, ++ BTC_CXP_MAIN_MAX ++}; ++ ++enum btc_cx_poicy_type { ++ /* TDMA off + pri: BT > WL */ ++ BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0, ++ ++ /* TDMA off + pri: WL > BT */ ++ BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1, ++ ++ /* TDMA off + pri: BT = WL */ ++ BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2, ++ ++ /* TDMA off + pri: BT = WL > BT_Lo */ ++ BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3, ++ ++ /* TDMA off + pri: WL = BT, BT_Rx > WL_Lo_Tx */ ++ BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4, ++ ++ /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ ++ BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5, ++ ++ /* TDMA off + pri: BT_Hi > WL > BT_Lo */ ++ BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6, ++ ++ /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */ ++ BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7, ++ ++ /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/ ++ BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0, ++ ++ /* TDMA off + Ext-Ctrl + pri: default */ ++ BTC_CXP_OFFE_DEF = (BTC_CXP_OFFE << 8) | 0, ++ ++ /* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */ ++ BTC_CXP_OFFE_DEF2 = (BTC_CXP_OFFE << 8) | 1, ++ ++ /* TDMA Fix slot-0: W1:B1 = 30:30 */ ++ BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0, ++ ++ /* TDMA Fix slot-1: W1:B1 = 50:50 */ ++ BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1, ++ ++ /* TDMA Fix slot-2: W1:B1 = 20:30 */ ++ BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2, ++ ++ /* TDMA Fix slot-3: W1:B1 = 40:10 */ ++ BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3, ++ ++ /* TDMA Fix slot-4: W1:B1 = 70:10 */ ++ BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4, ++ ++ /* TDMA Fix slot-5: W1:B1 = 20:60 */ ++ BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5, ++ ++ /* TDMA Fix slot-6: W1:B1 = 30:60 */ ++ BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6, ++ ++ /* TDMA Fix slot-7: W1:B1 = 20:80 */ ++ BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7, ++ ++ /* TDMA Fix slot-8: W1:B1 = user-define */ ++ BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8, ++ ++ /* TDMA Fix slot-9: W1:B1 = 40:20 */ ++ BTC_CXP_FIX_TD4020 = (BTC_CXP_FIX << 8) | 9, ++ ++ /* PS-TDMA Fix slot-0: W1:B1 = 30:30 */ ++ BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0, ++ ++ /* PS-TDMA Fix slot-1: W1:B1 = 50:50 */ ++ BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1, ++ ++ /* PS-TDMA Fix slot-2: W1:B1 = 20:30 */ ++ BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2, ++ ++ /* PS-TDMA Fix slot-3: W1:B1 = 20:60 */ ++ BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3, ++ ++ /* PS-TDMA Fix slot-4: W1:B1 = 30:70 */ ++ BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4, ++ ++ /* PS-TDMA Fix slot-5: W1:B1 = 20:80 */ ++ BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5, ++ ++ /* PS-TDMA Fix slot-6: W1:B1 = user-define */ ++ BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6, ++ ++ /* TDMA Auto slot-0: W1:B1 = 50:200 */ ++ BTC_CXP_AUTO_TD50200 = (BTC_CXP_AUTO << 8) | 0, ++ ++ /* TDMA Auto slot-1: W1:B1 = 60:200 */ ++ BTC_CXP_AUTO_TD60200 = (BTC_CXP_AUTO << 8) | 1, ++ ++ /* TDMA Auto slot-2: W1:B1 = 20:200 */ ++ BTC_CXP_AUTO_TD20200 = (BTC_CXP_AUTO << 8) | 2, ++ ++ /* TDMA Auto slot-3: W1:B1 = user-define */ ++ BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3, ++ ++ /* PS-TDMA Auto slot-0: W1:B1 = 50:200 */ ++ BTC_CXP_PAUTO_TD50200 = (BTC_CXP_PAUTO << 8) | 0, ++ ++ /* PS-TDMA Auto slot-1: W1:B1 = 60:200 */ ++ BTC_CXP_PAUTO_TD60200 = (BTC_CXP_PAUTO << 8) | 1, ++ ++ /* PS-TDMA Auto slot-2: W1:B1 = 20:200 */ ++ BTC_CXP_PAUTO_TD20200 = (BTC_CXP_PAUTO << 8) | 2, ++ ++ /* PS-TDMA Auto slot-3: W1:B1 = user-define */ ++ BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3, ++ ++ /* TDMA Auto slot2-0: W1:B4 = 30:50 */ ++ BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0, ++ ++ /* TDMA Auto slot2-1: W1:B4 = 30:70 */ ++ BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1, ++ ++ /* TDMA Auto slot2-2: W1:B4 = 50:50 */ ++ BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2, ++ ++ /* TDMA Auto slot2-3: W1:B4 = 60:60 */ ++ BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3, ++ ++ /* TDMA Auto slot2-4: W1:B4 = 20:80 */ ++ BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4, ++ ++ /* TDMA Auto slot2-5: W1:B4 = user-define */ ++ BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5, ++ ++ /* PS-TDMA Auto slot2-0: W1:B4 = 30:50 */ ++ BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0, ++ ++ /* PS-TDMA Auto slot2-1: W1:B4 = 30:70 */ ++ BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1, ++ ++ /* PS-TDMA Auto slot2-2: W1:B4 = 50:50 */ ++ BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2, ++ ++ /* PS-TDMA Auto slot2-3: W1:B4 = 60:60 */ ++ BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3, ++ ++ /* PS-TDMA Auto slot2-4: W1:B4 = 20:80 */ ++ BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4, ++ ++ /* PS-TDMA Auto slot2-5: W1:B4 = user-define */ ++ BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5, ++ ++ BTC_CXP_MAX = 0xffff ++}; ++ ++enum btc_wl_rfk_result { ++ BTC_WRFK_REJECT = 0, ++ BTC_WRFK_ALLOW = 1, ++}; ++ ++enum btc_coex_info_map_en { ++ BTC_COEX_INFO_CX = BIT(0), ++ BTC_COEX_INFO_WL = BIT(1), ++ BTC_COEX_INFO_BT = BIT(2), ++ BTC_COEX_INFO_DM = BIT(3), ++ BTC_COEX_INFO_MREG = BIT(4), ++ BTC_COEX_INFO_SUMMARY = BIT(5), ++ BTC_COEX_INFO_ALL = GENMASK(7, 0), ++}; ++ ++#define BTC_CXP_MASK GENMASK(15, 8) ++ ++enum btc_w2b_scoreboard { ++ BTC_WSCB_ACTIVE = BIT(0), ++ BTC_WSCB_ON = BIT(1), ++ BTC_WSCB_SCAN = BIT(2), ++ BTC_WSCB_UNDERTEST = BIT(3), ++ BTC_WSCB_RXGAIN = BIT(4), ++ BTC_WSCB_WLBUSY = BIT(7), ++ BTC_WSCB_EXTFEM = BIT(8), ++ BTC_WSCB_TDMA = BIT(9), ++ BTC_WSCB_FIX2M = BIT(10), ++ BTC_WSCB_WLRFK = BIT(11), ++ BTC_WSCB_BTRFK_GNT = BIT(12), /* not used, use mailbox to inform BT */ ++ BTC_WSCB_BT_HILNA = BIT(13), ++ BTC_WSCB_BTLOG = BIT(14), ++ BTC_WSCB_ALL = GENMASK(23, 0), ++}; ++ ++enum btc_wl_link_mode { ++ BTC_WLINK_NOLINK = 0x0, ++ BTC_WLINK_2G_STA, ++ BTC_WLINK_2G_AP, ++ BTC_WLINK_2G_GO, ++ BTC_WLINK_2G_GC, ++ BTC_WLINK_2G_SCC, ++ BTC_WLINK_2G_MCC, ++ BTC_WLINK_25G_MCC, ++ BTC_WLINK_25G_DBCC, ++ BTC_WLINK_5G, ++ BTC_WLINK_2G_NAN, ++ BTC_WLINK_OTHER, ++ BTC_WLINK_MAX ++}; ++ ++enum btc_bt_hid_type { ++ BTC_HID_218 = BIT(0), ++ BTC_HID_418 = BIT(1), ++ BTC_HID_BLE = BIT(2), ++ BTC_HID_RCU = BIT(3), ++ BTC_HID_RCU_VOICE = BIT(4), ++ BTC_HID_OTHER_LEGACY = BIT(5) ++}; ++ ++enum btc_reset_module { ++ BTC_RESET_CX = BIT(0), ++ BTC_RESET_DM = BIT(1), ++ BTC_RESET_CTRL = BIT(2), ++ BTC_RESET_CXDM = BIT(0) | BIT(1), ++ BTC_RESET_BTINFO = BIT(3), ++ BTC_RESET_MDINFO = BIT(4), ++ BTC_RESET_ALL = GENMASK(7, 0), ++}; ++ ++enum btc_gnt_state { ++ BTC_GNT_HW = 0, ++ BTC_GNT_SW_LO, ++ BTC_GNT_SW_HI, ++ BTC_GNT_MAX ++}; ++ ++enum btc_wl_max_tx_time { ++ BTC_MAX_TX_TIME_L1 = 500, ++ BTC_MAX_TX_TIME_L2 = 1000, ++ BTC_MAX_TX_TIME_L3 = 2000, ++ BTC_MAX_TX_TIME_DEF = 5280 ++}; ++ ++enum btc_wl_max_tx_retry { ++ BTC_MAX_TX_RETRY_L1 = 7, ++ BTC_MAX_TX_RETRY_L2 = 15, ++ BTC_MAX_TX_RETRY_DEF = 31, ++}; ++ ++enum btc_reason_and_action { ++ BTC_RSN_NONE, ++ BTC_RSN_NTFY_INIT, ++ BTC_RSN_NTFY_SWBAND, ++ BTC_RSN_NTFY_WL_STA, ++ BTC_RSN_NTFY_RADIO_STATE, ++ BTC_RSN_UPDATE_BT_SCBD, ++ BTC_RSN_NTFY_WL_RFK, ++ BTC_RSN_UPDATE_BT_INFO, ++ BTC_RSN_NTFY_SCAN_START, ++ BTC_RSN_NTFY_SCAN_FINISH, ++ BTC_RSN_NTFY_SPECIFIC_PACKET, ++ BTC_RSN_NTFY_POWEROFF, ++ BTC_RSN_NTFY_ROLE_INFO, ++ BTC_RSN_CMD_SET_COEX, ++ BTC_RSN_ACT1_WORK, ++ BTC_RSN_BT_DEVINFO_WORK, ++ BTC_RSN_RFK_CHK_WORK, ++ BTC_RSN_NUM, ++ BTC_ACT_NONE = 100, ++ BTC_ACT_WL_ONLY, ++ BTC_ACT_WL_5G, ++ BTC_ACT_WL_OTHER, ++ BTC_ACT_WL_IDLE, ++ BTC_ACT_WL_NC, ++ BTC_ACT_WL_RFK, ++ BTC_ACT_WL_INIT, ++ BTC_ACT_WL_OFF, ++ BTC_ACT_FREERUN, ++ BTC_ACT_BT_WHQL, ++ BTC_ACT_BT_RFK, ++ BTC_ACT_BT_OFF, ++ BTC_ACT_BT_IDLE, ++ BTC_ACT_BT_HFP, ++ BTC_ACT_BT_HID, ++ BTC_ACT_BT_A2DP, ++ BTC_ACT_BT_A2DPSINK, ++ BTC_ACT_BT_PAN, ++ BTC_ACT_BT_A2DP_HID, ++ BTC_ACT_BT_A2DP_PAN, ++ BTC_ACT_BT_PAN_HID, ++ BTC_ACT_BT_A2DP_PAN_HID, ++ BTC_ACT_WL_25G_MCC, ++ BTC_ACT_WL_2G_MCC, ++ BTC_ACT_WL_2G_SCC, ++ BTC_ACT_WL_2G_AP, ++ BTC_ACT_WL_2G_GO, ++ BTC_ACT_WL_2G_GC, ++ BTC_ACT_WL_2G_NAN, ++ BTC_ACT_LAST, ++ BTC_ACT_NUM = BTC_ACT_LAST - BTC_ACT_NONE, ++ BTC_ACT_EXT_BIT = BIT(14), ++ BTC_POLICY_EXT_BIT = BIT(15), ++}; ++ ++#define BTC_FREERUN_ANTISO_MIN 30 ++#define BTC_TDMA_BTHID_MAX 2 ++#define BTC_BLINK_NOCONNECT 0 ++ ++static void _run_coex(struct rtw89_dev *rtwdev, ++ enum btc_reason_and_action reason); ++static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state); ++static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update); ++ ++static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, ++ void *param, u16 len) ++{ ++ rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, ++ false, true); ++} ++ ++static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); ++ ++ if (type & BTC_RESET_CX) ++ memset(cx, 0, sizeof(*cx)); ++ else if (type & BTC_RESET_BTINFO) /* only for BT enable */ ++ memset(bt, 0, sizeof(*bt)); ++ ++ if (type & BTC_RESET_CTRL) { ++ memset(&btc->ctrl, 0, sizeof(btc->ctrl)); ++ btc->ctrl.trace_step = FCXDEF_STEP; ++ } ++ ++ /* Init Coex variables that are not zero */ ++ if (type & BTC_RESET_DM) { ++ memset(&btc->dm, 0, sizeof(btc->dm)); ++ memset(bt_linfo->rssi_state, 0, sizeof(bt_linfo->rssi_state)); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) ++ memset(wl_linfo[i].rssi_state, 0, ++ sizeof(wl_linfo[i].rssi_state)); ++ ++ /* set the slot_now table to original */ ++ btc->dm.tdma_now = t_def[CXTD_OFF]; ++ btc->dm.tdma = t_def[CXTD_OFF]; ++ memcpy(&btc->dm.slot_now, s_def, sizeof(btc->dm.slot_now)); ++ memcpy(&btc->dm.slot, s_def, sizeof(btc->dm.slot)); ++ ++ btc->policy_len = 0; ++ btc->bt_req_len = 0; ++ ++ btc->dm.coex_info_map = BTC_COEX_INFO_ALL; ++ btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF; ++ btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } ++ ++ if (type & BTC_RESET_MDINFO) ++ memset(&btc->mdinfo, 0, sizeof(btc->mdinfo)); ++} ++ ++#define BTC_FWINFO_BUF 1024 ++ ++#define BTC_RPT_HDR_SIZE 3 ++#define BTC_CHK_WLSLOT_DRIFT_MAX 15 ++#define BTC_CHK_HANG_MAX 3 ++ ++static void _chk_btc_err(struct rtw89_dev *rtwdev, u8 type, u32 cnt) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): type:%d cnt:%d\n", ++ __func__, type, cnt); ++ ++ switch (type) { ++ case BTC_DCNT_RPT_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map) ++ dm->cnt_dm[BTC_DCNT_RPT_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_RPT_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_RPT_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.wl_fw_hang = true; ++ else ++ dm->error.map.wl_fw_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_RPT] = cnt; ++ break; ++ case BTC_DCNT_CYCLE_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt && ++ (dm->tdma_now.type != CXTDMA_OFF || ++ dm->tdma_now.ext_ctrl == CXECTL_EXT)) ++ dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.cycle_hang = true; ++ else ++ dm->error.map.cycle_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_CYCLE] = cnt; ++ break; ++ case BTC_DCNT_W1_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_W1] == cnt && ++ dm->tdma_now.type != CXTDMA_OFF) ++ dm->cnt_dm[BTC_DCNT_W1_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_W1_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_W1_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.w1_hang = true; ++ else ++ dm->error.map.w1_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_W1] = cnt; ++ break; ++ case BTC_DCNT_B1_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_B1] == cnt && ++ dm->tdma_now.type != CXTDMA_OFF) ++ dm->cnt_dm[BTC_DCNT_B1_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_B1_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_B1_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.b1_hang = true; ++ else ++ dm->error.map.b1_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_B1] = cnt; ++ break; ++ case BTC_DCNT_TDMA_NONSYNC: ++ if (cnt != 0) /* if tdma not sync between drv/fw */ ++ dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++; ++ else ++ dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX) ++ dm->error.map.tdma_no_sync = true; ++ else ++ dm->error.map.tdma_no_sync = false; ++ break; ++ case BTC_DCNT_SLOT_NONSYNC: ++ if (cnt != 0) /* if slot not sync between drv/fw */ ++ dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++; ++ else ++ dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX) ++ dm->error.map.tdma_no_sync = true; ++ else ++ dm->error.map.tdma_no_sync = false; ++ break; ++ case BTC_DCNT_BTCNT_FREEZE: ++ cnt = cx->cnt_bt[BTC_BCNT_HIPRI_RX] + ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX] + ++ cx->cnt_bt[BTC_BCNT_LOPRI_RX] + ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX]; ++ ++ if (cnt == 0) ++ dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] = 0; ++ ++ if ((dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX && ++ bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] && ++ !bt->enable.now)) ++ _update_bt_scbd(rtwdev, false); ++ break; ++ case BTC_DCNT_WL_SLOT_DRIFT: ++ if (cnt >= BTC_CHK_WLSLOT_DRIFT_MAX) ++ dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++; ++ else ++ dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) ++ dm->error.map.wl_slot_drift = true; ++ else ++ dm->error.map.wl_slot_drift = false; ++ break; ++ } ++} ++ ++static void _update_bt_report(struct rtw89_dev *rtwdev, u8 rpt_type, u8 *pfinfo) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &bt_linfo->a2dp_desc; ++ struct rtw89_btc_fbtc_btver *pver = NULL; ++ struct rtw89_btc_fbtc_btscan *pscan = NULL; ++ struct rtw89_btc_fbtc_btafh *pafh = NULL; ++ struct rtw89_btc_fbtc_btdevinfo *pdev = NULL; ++ ++ pver = (struct rtw89_btc_fbtc_btver *)pfinfo; ++ pscan = (struct rtw89_btc_fbtc_btscan *)pfinfo; ++ pafh = (struct rtw89_btc_fbtc_btafh *)pfinfo; ++ pdev = (struct rtw89_btc_fbtc_btdevinfo *)pfinfo; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_type:%d\n", ++ __func__, rpt_type); ++ ++ switch (rpt_type) { ++ case BTC_RPT_TYPE_BT_VER: ++ bt->ver_info.fw = le32_to_cpu(pver->fw_ver); ++ bt->ver_info.fw_coex = le32_get_bits(pver->coex_ver, GENMASK(7, 0)); ++ bt->feature = le32_to_cpu(pver->feature); ++ break; ++ case BTC_RPT_TYPE_BT_SCAN: ++ memcpy(bt->scan_info, pscan->scan, BTC_SCAN_MAX1); ++ break; ++ case BTC_RPT_TYPE_BT_AFH: ++ memcpy(&bt_linfo->afh_map[0], pafh->afh_l, 4); ++ memcpy(&bt_linfo->afh_map[4], pafh->afh_m, 4); ++ memcpy(&bt_linfo->afh_map[8], pafh->afh_h, 2); ++ break; ++ case BTC_RPT_TYPE_BT_DEVICE: ++ a2dp->device_name = le32_to_cpu(pdev->dev_name); ++ a2dp->vendor_id = le16_to_cpu(pdev->vendor_id); ++ a2dp->flush_time = le32_to_cpu(pdev->flush_time); ++ break; ++ default: ++ break; ++ } ++} ++ ++struct rtw89_btc_fbtc_cysta_cpu { ++ u8 fver; ++ u8 rsvd; ++ u16 cycles; ++ u16 cycles_a2dp[CXT_FLCTRL_MAX]; ++ u16 a2dpept; ++ u16 a2dpeptto; ++ u16 tavg_cycle[CXT_MAX]; ++ u16 tmax_cycle[CXT_MAX]; ++ u16 tmaxdiff_cycle[CXT_MAX]; ++ u16 tavg_a2dp[CXT_FLCTRL_MAX]; ++ u16 tmax_a2dp[CXT_FLCTRL_MAX]; ++ u16 tavg_a2dpept; ++ u16 tmax_a2dpept; ++ u16 tavg_lk; ++ u16 tmax_lk; ++ u32 slot_cnt[CXST_MAX]; ++ u32 bcn_cnt[CXBCN_MAX]; ++ u32 leakrx_cnt; ++ u32 collision_cnt; ++ u32 skip_cnt; ++ u32 exception; ++ u32 except_cnt; ++#if (FCXCYSTA_VER > 1) ++ u16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; ++#endif ++}; ++ ++static void rtw89_btc_fbtc_cysta_to_cpu(const struct rtw89_btc_fbtc_cysta *src, ++ struct rtw89_btc_fbtc_cysta_cpu *dst) ++{ ++ static_assert(sizeof(*src) == sizeof(*dst)); ++ ++#define __CPY_U8(_x) ({dst->_x = src->_x; }) ++#define __CPY_LE16(_x) ({dst->_x = le16_to_cpu(src->_x); }) ++#define __CPY_LE16S(_x) ({int _i; for (_i = 0; _i < ARRAY_SIZE(dst->_x); _i++) \ ++ dst->_x[_i] = le16_to_cpu(src->_x[_i]); }) ++#define __CPY_LE32(_x) ({dst->_x = le32_to_cpu(src->_x); }) ++#define __CPY_LE32S(_x) ({int _i; for (_i = 0; _i < ARRAY_SIZE(dst->_x); _i++) \ ++ dst->_x[_i] = le32_to_cpu(src->_x[_i]); }) ++ ++ __CPY_U8(fver); ++ __CPY_U8(rsvd); ++ __CPY_LE16(cycles); ++ __CPY_LE16S(cycles_a2dp); ++ __CPY_LE16(a2dpept); ++ __CPY_LE16(a2dpeptto); ++ __CPY_LE16S(tavg_cycle); ++ __CPY_LE16S(tmax_cycle); ++ __CPY_LE16S(tmaxdiff_cycle); ++ __CPY_LE16S(tavg_a2dp); ++ __CPY_LE16S(tmax_a2dp); ++ __CPY_LE16(tavg_a2dpept); ++ __CPY_LE16(tmax_a2dpept); ++ __CPY_LE16(tavg_lk); ++ __CPY_LE16(tmax_lk); ++ __CPY_LE32S(slot_cnt); ++ __CPY_LE32S(bcn_cnt); ++ __CPY_LE32(leakrx_cnt); ++ __CPY_LE32(collision_cnt); ++ __CPY_LE32(skip_cnt); ++ __CPY_LE32(exception); ++ __CPY_LE32(except_cnt); ++#if (FCXCYSTA_VER > 1) ++ __CPY_LE16S(tslot_cycle); ++#endif ++ ++#undef __CPY_U8 ++#undef __CPY_LE16 ++#undef __CPY_LE16S ++#undef __CPY_LE32 ++#undef __CPY_LE32S ++} ++ ++#define BTC_LEAK_AP_TH 10 ++#define BTC_CYSTA_CHK_PERIOD 100 ++ ++struct rtw89_btc_prpt { ++ u8 type; ++ __le16 len; ++ u8 content[]; ++} __packed; ++ ++static u32 _chk_btc_report(struct rtw89_dev *rtwdev, ++ struct rtw89_btc_btf_fwinfo *pfwinfo, ++ u8 *prptbuf, u32 index) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_fbtc_rpt_ctrl *prpt = NULL; ++ struct rtw89_btc_fbtc_cysta *pcysta_le32 = NULL; ++ struct rtw89_btc_fbtc_cysta_cpu pcysta[1]; ++ struct rtw89_btc_prpt *btc_prpt = NULL; ++ struct rtw89_btc_fbtc_slot *rtp_slot = NULL; ++ u8 rpt_type = 0, *rpt_content = NULL, *pfinfo = NULL; ++ u16 wl_slot_set = 0; ++ u32 trace_step = btc->ctrl.trace_step, rpt_len = 0, diff_t; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): index:%d\n", ++ __func__, index); ++ ++ if (!prptbuf) { ++ pfwinfo->err[BTFRE_INVALID_INPUT]++; ++ return 0; ++ } ++ ++ btc_prpt = (struct rtw89_btc_prpt *)&prptbuf[index]; ++ rpt_type = btc_prpt->type; ++ rpt_len = le16_to_cpu(btc_prpt->len); ++ rpt_content = btc_prpt->content; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_type:%d\n", ++ __func__, rpt_type); ++ ++ switch (rpt_type) { ++ case BTC_RPT_TYPE_CTRL: ++ pcinfo = &pfwinfo->rpt_ctrl.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_ctrl.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo); ++ pcinfo->req_fver = BTCRPT_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_TDMA: ++ pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_tdma.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_tdma.finfo); ++ pcinfo->req_fver = FCXTDMA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_SLOT: ++ pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_slots.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_slots.finfo); ++ pcinfo->req_fver = FCXSLOTS_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_CYSTA: ++ pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo); ++ pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo; ++ rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo); ++ pcinfo->req_fver = FCXCYSTA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_STEP: ++ pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_step.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_step.finfo.step[0]) * ++ trace_step + 8; ++ pcinfo->req_fver = FCXSTEP_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_NULLSTA: ++ pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_nullsta.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_nullsta.finfo); ++ pcinfo->req_fver = FCXNULLSTA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_MREG: ++ pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_mregval.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_mregval.finfo); ++ pcinfo->req_fver = FCXMREG_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_GPIO_DBG: ++ pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_gpio_dbg.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_gpio_dbg.finfo); ++ pcinfo->req_fver = FCXGPIODBG_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_VER: ++ pcinfo = &pfwinfo->rpt_fbtc_btver.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btver.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btver.finfo); ++ pcinfo->req_fver = FCX_BTVER_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_SCAN: ++ pcinfo = &pfwinfo->rpt_fbtc_btscan.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btscan.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btscan.finfo); ++ pcinfo->req_fver = FCX_BTSCAN_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_AFH: ++ pcinfo = &pfwinfo->rpt_fbtc_btafh.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btafh.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btafh.finfo); ++ pcinfo->req_fver = FCX_BTAFH_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_DEVICE: ++ pcinfo = &pfwinfo->rpt_fbtc_btdev.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btdev.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btdev.finfo); ++ pcinfo->req_fver = FCX_BTDEVINFO_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ default: ++ pfwinfo->err[BTFRE_UNDEF_TYPE]++; ++ return 0; ++ } ++ ++ if (rpt_len != pcinfo->req_len) { ++ if (rpt_type < BTC_RPT_TYPE_MAX) ++ pfwinfo->len_mismch |= (0x1 << rpt_type); ++ else ++ pfwinfo->len_mismch |= BIT(31); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_len:%d!=req_len:%d\n", ++ __func__, rpt_type, rpt_len, pcinfo->req_len); ++ ++ pcinfo->valid = 0; ++ return 0; ++ } else if (!pfinfo || !rpt_content || !pcinfo->req_len) { ++ pfwinfo->err[BTFRE_EXCEPTION]++; ++ pcinfo->valid = 0; ++ return 0; ++ } ++ ++ memcpy((void *)pfinfo, (void *)rpt_content, pcinfo->req_len); ++ pcinfo->valid = 1; ++ ++ if (rpt_type == BTC_RPT_TYPE_TDMA) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): check %d %ld\n", __func__, ++ BTC_DCNT_TDMA_NONSYNC, sizeof(dm->tdma_now)); ++ ++ if (memcmp(&dm->tdma_now, &pfwinfo->rpt_fbtc_tdma.finfo, ++ sizeof(dm->tdma_now)) != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d tdma_now %x %x %x %x %x %x %x %x\n", ++ __func__, BTC_DCNT_TDMA_NONSYNC, ++ dm->tdma_now.type, dm->tdma_now.rxflctrl, ++ dm->tdma_now.txpause, dm->tdma_now.wtgle_n, ++ dm->tdma_now.leak_n, dm->tdma_now.ext_ctrl, ++ dm->tdma_now.rsvd0, dm->tdma_now.rsvd1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_fbtc_tdma %x %x %x %x %x %x %x %x\n", ++ __func__, BTC_DCNT_TDMA_NONSYNC, ++ pfwinfo->rpt_fbtc_tdma.finfo.type, ++ pfwinfo->rpt_fbtc_tdma.finfo.rxflctrl, ++ pfwinfo->rpt_fbtc_tdma.finfo.txpause, ++ pfwinfo->rpt_fbtc_tdma.finfo.wtgle_n, ++ pfwinfo->rpt_fbtc_tdma.finfo.leak_n, ++ pfwinfo->rpt_fbtc_tdma.finfo.ext_ctrl, ++ pfwinfo->rpt_fbtc_tdma.finfo.rsvd0, ++ pfwinfo->rpt_fbtc_tdma.finfo.rsvd1); ++ } ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_TDMA_NONSYNC, ++ memcmp(&dm->tdma_now, ++ &pfwinfo->rpt_fbtc_tdma.finfo, ++ sizeof(dm->tdma_now))); ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_SLOT) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): check %d %ld\n", ++ __func__, BTC_DCNT_SLOT_NONSYNC, ++ sizeof(dm->slot_now)); ++ ++ if (memcmp(dm->slot_now, pfwinfo->rpt_fbtc_slots.finfo.slot, ++ sizeof(dm->slot_now)) != 0) { ++ for (i = 0; i < CXST_MAX; i++) { ++ rtp_slot = ++ &pfwinfo->rpt_fbtc_slots.finfo.slot[i]; ++ if (memcmp(&dm->slot_now[i], rtp_slot, ++ sizeof(dm->slot_now[i])) != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d slot_now[%d] dur=0x%04x tbl=%08x type=0x%04x\n", ++ __func__, ++ BTC_DCNT_SLOT_NONSYNC, i, ++ dm->slot_now[i].dur, ++ dm->slot_now[i].cxtbl, ++ dm->slot_now[i].cxtype); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_fbtc_slots[%d] dur=0x%04x tbl=%08x type=0x%04x\n", ++ __func__, ++ BTC_DCNT_SLOT_NONSYNC, i, ++ rtp_slot->dur, ++ rtp_slot->cxtbl, ++ rtp_slot->cxtype); ++ } ++ } ++ } ++ _chk_btc_err(rtwdev, BTC_DCNT_SLOT_NONSYNC, ++ memcmp(dm->slot_now, ++ pfwinfo->rpt_fbtc_slots.finfo.slot, ++ sizeof(dm->slot_now))); ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_CYSTA && ++ pcysta->cycles >= BTC_CYSTA_CHK_PERIOD) { ++ /* Check Leak-AP */ ++ if (pcysta->slot_cnt[CXST_LK] != 0 && ++ pcysta->leakrx_cnt != 0 && dm->tdma_now.rxflctrl) { ++ if (pcysta->slot_cnt[CXST_LK] < ++ BTC_LEAK_AP_TH * pcysta->leakrx_cnt) ++ dm->leak_ap = 1; ++ } ++ ++ /* Check diff time between WL slot and W1/E2G slot */ ++ if (dm->tdma_now.type == CXTDMA_OFF && ++ dm->tdma_now.ext_ctrl == CXECTL_EXT) ++ wl_slot_set = le16_to_cpu(dm->slot_now[CXST_E2G].dur); ++ else ++ wl_slot_set = le16_to_cpu(dm->slot_now[CXST_W1].dur); ++ ++ if (pcysta->tavg_cycle[CXT_WL] > wl_slot_set) { ++ diff_t = pcysta->tavg_cycle[CXT_WL] - wl_slot_set; ++ _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); ++ } ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_CTRL) { ++ prpt = &pfwinfo->rpt_ctrl.finfo; ++ btc->fwinfo.rpt_en_map = prpt->rpt_enable; ++ wl->ver_info.fw_coex = prpt->wl_fw_coex_ver; ++ wl->ver_info.fw = prpt->wl_fw_ver; ++ dm->wl_fw_cx_offload = !!(prpt->wl_fw_cx_offload); ++ } ++ ++ if (rpt_type >= BTC_RPT_TYPE_BT_VER && ++ rpt_type <= BTC_RPT_TYPE_BT_DEVICE) ++ _update_bt_report(rtwdev, rpt_type, pfinfo); ++ ++ return (rpt_len + BTC_RPT_HDR_SIZE); ++} ++ ++static void _parse_btc_report(struct rtw89_dev *rtwdev, ++ struct rtw89_btc_btf_fwinfo *pfwinfo, ++ u8 *pbuf, u32 buf_len) ++{ ++ struct rtw89_btc_prpt *btc_prpt = NULL; ++ u32 index = 0, rpt_len = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): buf_len:%d\n", ++ __func__, buf_len); ++ ++ while (pbuf) { ++ btc_prpt = (struct rtw89_btc_prpt *)&pbuf[index]; ++ if (index + 2 >= BTC_FWINFO_BUF) ++ break; ++ /* At least 3 bytes: type(1) & len(2) */ ++ rpt_len = le16_to_cpu(btc_prpt->len); ++ if ((index + rpt_len + BTC_RPT_HDR_SIZE) > buf_len) ++ break; ++ ++ rpt_len = _chk_btc_report(rtwdev, pfwinfo, pbuf, index); ++ if (!rpt_len) ++ break; ++ index += rpt_len; ++ } ++} ++ ++#define BTC_TLV_HDR_LEN 2 ++ ++static void _append_tdma(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_btf_tlv *tlv = NULL; ++ struct rtw89_btc_fbtc_tdma *v = NULL; ++ u16 len = btc->policy_len; ++ ++ if (!btc->update_policy_force && ++ !memcmp(&dm->tdma, &dm->tdma_now, sizeof(dm->tdma))) { ++ rtw89_debug(rtwdev, ++ RTW89_DBG_BTC, "[BTC], %s(): tdma no change!\n", ++ __func__); ++ return; ++ } ++ ++ tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; ++ v = (struct rtw89_btc_fbtc_tdma *)&tlv->val[0]; ++ tlv->type = CXPOLICY_TDMA; ++ tlv->len = sizeof(*v); ++ ++ memcpy(v, &dm->tdma, sizeof(*v)); ++ btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): type:%d, rxflctrl=%d, txpause=%d, wtgle_n=%d, leak_n=%d, ext_ctrl=%d\n", ++ __func__, dm->tdma.type, dm->tdma.rxflctrl, ++ dm->tdma.txpause, dm->tdma.wtgle_n, dm->tdma.leak_n, ++ dm->tdma.ext_ctrl); ++} ++ ++static void _append_slot(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_btf_tlv *tlv = NULL; ++ struct btc_fbtc_1slot *v = NULL; ++ u16 len = 0; ++ u8 i, cnt = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): A:btc->policy_len = %d\n", ++ __func__, btc->policy_len); ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (!btc->update_policy_force && ++ !memcmp(&dm->slot[i], &dm->slot_now[i], ++ sizeof(dm->slot[i]))) ++ continue; ++ ++ len = btc->policy_len; ++ ++ tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; ++ v = (struct btc_fbtc_1slot *)&tlv->val[0]; ++ tlv->type = CXPOLICY_SLOT; ++ tlv->len = sizeof(*v); ++ ++ v->fver = FCXONESLOT_VER; ++ v->sid = i; ++ v->slot = dm->slot[i]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): slot-%d: dur=%d, table=0x%08x, type=%d\n", ++ __func__, i, dm->slot[i].dur, dm->slot[i].cxtbl, ++ dm->slot[i].cxtype); ++ cnt++; ++ ++ btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); ++ } ++ ++ if (cnt > 0) ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): slot update (cnt=%d)!!\n", ++ __func__, cnt); ++} ++ ++static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev, ++ u32 rpt_map, bool rpt_state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *fwinfo = &btc->fwinfo; ++ struct rtw89_btc_btf_set_report r = {0}; ++ u32 val = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_map=%x, rpt_state=%x\n", ++ __func__, rpt_map, rpt_state); ++ ++ if (rpt_state) ++ val = fwinfo->rpt_en_map | rpt_map; ++ else ++ val = fwinfo->rpt_en_map & ~rpt_map; ++ ++ if (val == fwinfo->rpt_en_map) ++ return; ++ ++ fwinfo->rpt_en_map = val; ++ ++ r.fver = BTF_SET_REPORT_VER; ++ r.enable = cpu_to_le32(val); ++ r.para = cpu_to_le32(rpt_state); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r, sizeof(r)); ++} ++ ++static void rtw89_btc_fw_set_slots(struct rtw89_dev *rtwdev, u8 num, ++ struct rtw89_btc_fbtc_slot *s) ++{ ++ struct rtw89_btc_btf_set_slot_table *tbl = NULL; ++ u8 *ptr = NULL; ++ u16 n = 0; ++ ++ n = sizeof(*s) * num + sizeof(*tbl); ++ tbl = kmalloc(n, GFP_KERNEL); ++ if (!tbl) ++ return; ++ ++ tbl->fver = BTF_SET_SLOT_TABLE_VER; ++ tbl->tbl_num = num; ++ ptr = &tbl->buf[0]; ++ memcpy(ptr, s, num * sizeof(*s)); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_SLOT_TABLE, tbl, n); ++ ++ kfree(tbl); ++} ++ ++static void btc_fw_set_monreg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc_btf_set_mon_reg *monreg = NULL; ++ u8 n, *ptr = NULL, ulen; ++ u16 sz = 0; ++ ++ n = chip->mon_reg_num; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mon_reg_num=%d\n", __func__, n); ++ if (n > CXMREG_MAX) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mon reg count %d > %d\n", ++ __func__, n, CXMREG_MAX); ++ return; ++ } ++ ++ ulen = sizeof(struct rtw89_btc_fbtc_mreg); ++ sz = (ulen * n) + sizeof(*monreg); ++ monreg = kmalloc(sz, GFP_KERNEL); ++ if (!monreg) ++ return; ++ ++ monreg->fver = BTF_SET_MON_REG_VER; ++ monreg->reg_num = n; ++ ptr = &monreg->buf[0]; ++ memcpy((void *)ptr, chip->mon_reg, n * ulen); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): sz=%d ulen=%d n=%d\n", ++ __func__, sz, ulen, n); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_MREG_TABLE, (u8 *)monreg, sz); ++ kfree(monreg); ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_MREG, 1); ++} ++ ++static void _update_dm_step(struct rtw89_dev *rtwdev, ++ enum btc_reason_and_action reason_or_action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ /* use ring-structure to store dm step */ ++ dm->dm_step.step[dm->dm_step.step_pos] = reason_or_action; ++ dm->dm_step.step_pos++; ++ ++ if (dm->dm_step.step_pos >= ARRAY_SIZE(dm->dm_step.step)) { ++ dm->dm_step.step_pos = 0; ++ dm->dm_step.step_ov = true; ++ } ++} ++ ++static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type, ++ enum btc_reason_and_action action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ dm->run_action = action; ++ ++ _update_dm_step(rtwdev, action | BTC_ACT_EXT_BIT); ++ _update_dm_step(rtwdev, policy_type | BTC_POLICY_EXT_BIT); ++ ++ btc->policy_len = 0; ++ btc->policy_type = policy_type; ++ ++ _append_tdma(rtwdev); ++ _append_slot(rtwdev); ++ ++ if (btc->policy_len == 0 || btc->policy_len > RTW89_BTC_POLICY_MAXLEN) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): action = %d -> policy type/len: 0x%04x/%d\n", ++ __func__, action, policy_type, btc->policy_len); ++ ++ if (dm->tdma.rxflctrl == CXFLC_NULLP || ++ dm->tdma.rxflctrl == CXFLC_QOSNULL) ++ btc->lps = 1; ++ else ++ btc->lps = 0; ++ ++ if (btc->lps == 1) ++ rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_CX_POLICY, ++ btc->policy, btc->policy_len); ++ ++ memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now)); ++ memcpy(&dm->slot_now, &dm->slot, sizeof(dm->slot_now)); ++ ++ if (btc->update_policy_force) ++ btc->update_policy_force = false; ++ ++ if (btc->lps == 0) ++ rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); ++} ++ ++static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type) ++{ ++ switch (type) { ++ case CXDRVINFO_INIT: ++ rtw89_fw_h2c_cxdrv_init(rtwdev); ++ break; ++ case CXDRVINFO_ROLE: ++ rtw89_fw_h2c_cxdrv_role(rtwdev); ++ break; ++ case CXDRVINFO_CTRL: ++ rtw89_fw_h2c_cxdrv_ctrl(rtwdev); ++ break; ++ case CXDRVINFO_RFK: ++ rtw89_fw_h2c_cxdrv_rfk(rtwdev); ++ break; ++ default: ++ break; ++ } ++} ++ ++static ++void btc_fw_event(struct rtw89_dev *rtwdev, u8 evt_id, void *data, u32 len) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): evt_id:%d len:%d\n", ++ __func__, evt_id, len); ++ ++ if (!len || !data) ++ return; ++ ++ switch (evt_id) { ++ case BTF_EVNT_RPT: ++ _parse_btc_report(rtwdev, pfwinfo, data, len); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _set_gnt_wl(struct rtw89_dev *rtwdev, u8 phy_map, u8 state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_mac_ax_gnt *g = dm->gnt.band; ++ u8 i; ++ ++ if (phy_map > BTC_PHY_ALL) ++ return; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ if (!(phy_map & BIT(i))) ++ continue; ++ ++ switch (state) { ++ case BTC_GNT_HW: ++ g[i].gnt_wl_sw_en = 0; ++ g[i].gnt_wl = 0; ++ break; ++ case BTC_GNT_SW_LO: ++ g[i].gnt_wl_sw_en = 1; ++ g[i].gnt_wl = 0; ++ break; ++ case BTC_GNT_SW_HI: ++ g[i].gnt_wl_sw_en = 1; ++ g[i].gnt_wl = 1; ++ break; ++ } ++ } ++ ++ rtw89_mac_cfg_gnt(rtwdev, &dm->gnt); ++} ++ ++#define BTC_TDMA_WLROLE_MAX 2 ++ ++static void _set_bt_ignore_wlan_act(struct rtw89_dev *rtwdev, u8 enable) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): set bt %s wlan_act\n", __func__, ++ enable ? "ignore" : "do not ignore"); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_IGNORE_WLAN_ACT, &enable, 1); ++} ++ ++#define WL_TX_POWER_NO_BTC_CTRL GENMASK(31, 0) ++#define WL_TX_POWER_ALL_TIME GENMASK(15, 0) ++#define WL_TX_POWER_WITH_BT GENMASK(31, 16) ++#define WL_TX_POWER_INT_PART GENMASK(8, 2) ++#define WL_TX_POWER_FRA_PART GENMASK(1, 0) ++#define B_BTC_WL_TX_POWER_SIGN BIT(7) ++#define B_TSSI_WL_TX_POWER_SIGN BIT(8) ++ ++static void _set_wl_tx_power(struct rtw89_dev *rtwdev, u32 level) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 pwr_val; ++ ++ if (wl->rf_para.tx_pwr_freerun == level) ++ return; ++ ++ wl->rf_para.tx_pwr_freerun = level; ++ btc->dm.rf_trx_para.wl_tx_power = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ if (level == RTW89_BTC_WL_DEF_TX_PWR) { ++ pwr_val = WL_TX_POWER_NO_BTC_CTRL; ++ } else { /* only apply "force tx power" */ ++ pwr_val = FIELD_PREP(WL_TX_POWER_INT_PART, level); ++ if (pwr_val > RTW89_BTC_WL_DEF_TX_PWR) ++ pwr_val = RTW89_BTC_WL_DEF_TX_PWR; ++ ++ if (level & B_BTC_WL_TX_POWER_SIGN) ++ pwr_val |= B_TSSI_WL_TX_POWER_SIGN; ++ pwr_val |= WL_TX_POWER_WITH_BT; ++ } ++ ++ chip->ops->btc_set_wl_txpwr_ctrl(rtwdev, pwr_val); ++} ++ ++#define rtw89_btc_wl_rx_gain(rtwdev, level) do {} while (0) ++ ++static void _set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ if (wl->rf_para.rx_gain_freerun == level) ++ return; ++ ++ wl->rf_para.rx_gain_freerun = level; ++ btc->dm.rf_trx_para.wl_rx_gain = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ rtw89_btc_wl_rx_gain(rtwdev, level); ++} ++ ++static void _set_bt_tx_power(struct rtw89_dev *rtwdev, u8 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ u8 buf = 0; ++ ++ if (bt->rf_para.tx_pwr_freerun == level) ++ return; ++ ++ bt->rf_para.tx_pwr_freerun = level; ++ btc->dm.rf_trx_para.bt_tx_power = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ buf = (s8)(-level); ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_TX_PWR, &buf, 1); ++} ++ ++#define BTC_BT_RX_NORMAL_LVL 7 ++ ++static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ ++ if (bt->rf_para.rx_gain_freerun == level || ++ level > BTC_BT_RX_NORMAL_LVL) ++ return; ++ ++ bt->rf_para.rx_gain_freerun = level; ++ btc->dm.rf_trx_para.bt_rx_gain = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ if (level == BTC_BT_RX_NORMAL_LVL) ++ _write_scbd(rtwdev, BTC_WSCB_RXGAIN, false); ++ else ++ _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_LNA_CONSTRAIN, &level, 1); ++} ++ ++static void _set_rf_trx_para(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_rf_trx_para para; ++ u32 wl_stb_chg = 0; ++ u8 level_id = 0; ++ ++ if (!dm->freerun) { ++ dm->trx_para_level = 0; ++ chip->ops->btc_bt_aci_imp(rtwdev); ++ } ++ ++ level_id = (u8)dm->trx_para_level; ++ ++ if (level_id >= chip->rf_para_dlink_num || ++ level_id >= chip->rf_para_ulink_num) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): invalid level_id: %d\n", ++ __func__, level_id); ++ return; ++ } ++ ++ if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) ++ para = chip->rf_para_ulink[level_id]; ++ else ++ para = chip->rf_para_dlink[level_id]; ++ ++ if (para.wl_tx_power != RTW89_BTC_WL_DEF_TX_PWR) ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): wl_tx_power=%d\n", ++ __func__, para.wl_tx_power); ++ _set_wl_tx_power(rtwdev, para.wl_tx_power); ++ _set_wl_rx_gain(rtwdev, para.wl_rx_gain); ++ _set_bt_tx_power(rtwdev, para.bt_tx_power); ++ _set_bt_rx_gain(rtwdev, para.bt_rx_gain); ++ ++ if (bt->enable.now == 0 || wl->status.map.rf_off == 1 || ++ wl->status.map.lps == 1) ++ wl_stb_chg = 0; ++ else ++ wl_stb_chg = 1; ++ ++ if (wl_stb_chg != dm->wl_stb_chg) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): wl_stb_chg=%d\n", ++ __func__, wl_stb_chg); ++ dm->wl_stb_chg = wl_stb_chg; ++ chip->ops->btc_wl_s1_standby(rtwdev, dm->wl_stb_chg); ++ } ++} ++ ++static void _update_btc_state_map(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ ++ if (wl->status.map.connecting || wl->status.map._4way || ++ wl->status.map.roaming) { ++ cx->state_map = BTC_WLINKING; ++ } else if (wl->status.map.scan) { /* wl scan */ ++ if (bt_linfo->status.map.inq_pag) ++ cx->state_map = BTC_WSCAN_BSCAN; ++ else ++ cx->state_map = BTC_WSCAN_BNOSCAN; ++ } else if (wl->status.map.busy) { /* only busy */ ++ if (bt_linfo->status.map.inq_pag) ++ cx->state_map = BTC_WBUSY_BSCAN; ++ else ++ cx->state_map = BTC_WBUSY_BNOSCAN; ++ } else { /* wl idle */ ++ cx->state_map = BTC_WIDLE; ++ } ++} ++ ++static void _set_bt_afh_info(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ u8 en = 0, i, ch = 0, bw = 0; ++ ++ if (btc->ctrl.manual || wl->status.map.scan) ++ return; ++ ++ /* TODO if include module->ant.type == BTC_ANT_SHARED */ ++ if (wl->status.map.rf_off || bt->whql_test || ++ wl_rinfo->link_mode == BTC_WLINK_NOLINK || ++ wl_rinfo->link_mode == BTC_WLINK_5G || ++ wl_rinfo->connect_cnt > BTC_TDMA_WLROLE_MAX) { ++ en = false; ++ } else if (wl_rinfo->link_mode == BTC_WLINK_2G_MCC || ++ wl_rinfo->link_mode == BTC_WLINK_2G_SCC) { ++ en = true; ++ /* get p2p channel */ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ if (wl_rinfo->active_role[i].role == ++ RTW89_WIFI_ROLE_P2P_GO || ++ wl_rinfo->active_role[i].role == ++ RTW89_WIFI_ROLE_P2P_CLIENT) { ++ ch = wl_rinfo->active_role[i].ch; ++ bw = wl_rinfo->active_role[i].bw; ++ break; ++ } ++ } ++ } else { ++ en = true; ++ /* get 2g channel */ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ if (wl_rinfo->active_role[i].connected && ++ wl_rinfo->active_role[i].band == RTW89_BAND_2G) { ++ ch = wl_rinfo->active_role[i].ch; ++ bw = wl_rinfo->active_role[i].bw; ++ break; ++ } ++ } ++ } ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++#ifdef BTC_NON_SHARED_ANT_FREERUN ++ bw = 48; ++#else ++ bw = 20 + chip->afh_guard_ch * 2; ++#endif ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ bw = 40 + chip->afh_guard_ch * 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_5: ++ bw = 5 + chip->afh_guard_ch * 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ bw = 10 + chip->afh_guard_ch * 2; ++ break; ++ default: ++ bw = 0; ++ en = false; /* turn off AFH info if BW > 40 */ ++ break; ++ } ++ ++ if (wl->afh_info.en == en && ++ wl->afh_info.ch == ch && ++ wl->afh_info.bw == bw && ++ b->profile_cnt.last == b->profile_cnt.now) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return because no change!\n", ++ __func__); ++ return; ++ } ++ ++ wl->afh_info.en = en; ++ wl->afh_info.ch = ch; ++ wl->afh_info.bw = bw; ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_WL_CH_INFO, &wl->afh_info, 3); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): en=%d, ch=%d, bw=%d\n", ++ __func__, en, ch, bw); ++ btc->cx.cnt_wl[BTC_WCNT_CH_UPDATE]++; ++} ++ ++static bool _check_freerun(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_hid_desc *hid = &bt_linfo->hid_desc; ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ btc->dm.trx_para_level = 0; ++ return false; ++ } ++ ++ /* The below is dedicated antenna case */ ++ if (wl_rinfo->connect_cnt > BTC_TDMA_WLROLE_MAX) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (bt_linfo->profile_cnt.now == 0) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (hid->pair_cnt > BTC_TDMA_BTHID_MAX) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ /* TODO get isolation by BT psd */ ++ if (btc->mdinfo.ant.isolation >= BTC_FREERUN_ANTISO_MIN) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (!wl->status.map.busy) {/* wl idle -> freerun */ ++ btc->dm.trx_para_level = 5; ++ return true; ++ } else if (wl->rssi_level > 1) {/* WL rssi < 50% (-60dBm) */ ++ btc->dm.trx_para_level = 0; ++ return false; ++ } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { ++ if (wl->rssi_level == 0 && bt_linfo->rssi > 31) { ++ btc->dm.trx_para_level = 6; ++ return true; ++ } else if (wl->rssi_level == 1 && bt_linfo->rssi > 36) { ++ btc->dm.trx_para_level = 7; ++ return true; ++ } ++ btc->dm.trx_para_level = 0; ++ return false; ++ } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) { ++ if (bt_linfo->rssi > 28) { ++ btc->dm.trx_para_level = 6; ++ return true; ++ } ++ } ++ ++ btc->dm.trx_para_level = 0; ++ return false; ++} ++ ++#define _tdma_set_flctrl(btc, flc) ({(btc)->dm.tdma.rxflctrl = flc; }) ++#define _tdma_set_tog(btc, wtg) ({(btc)->dm.tdma.wtgle_n = wtg; }) ++#define _tdma_set_lek(btc, lek) ({(btc)->dm.tdma.leak_n = lek; }) ++ ++#define _slot_set(btc, sid, dura, tbl, type) \ ++ do { \ ++ typeof(sid) _sid = (sid); \ ++ typeof(btc) _btc = (btc); \ ++ _btc->dm.slot[_sid].dur = cpu_to_le16(dura);\ ++ _btc->dm.slot[_sid].cxtbl = cpu_to_le32(tbl); \ ++ _btc->dm.slot[_sid].cxtype = cpu_to_le16(type); \ ++ } while (0) ++ ++#define _slot_set_dur(btc, sid, dura) (btc)->dm.slot[sid].dur = cpu_to_le16(dura) ++#define _slot_set_tbl(btc, sid, tbl) (btc)->dm.slot[sid].cxtbl = cpu_to_le32(tbl) ++#define _slot_set_type(btc, sid, type) (btc)->dm.slot[sid].cxtype = cpu_to_le16(type) ++ ++struct btc_btinfo_lb2 { ++ u8 connect: 1; ++ u8 sco_busy: 1; ++ u8 inq_pag: 1; ++ u8 acl_busy: 1; ++ u8 hfp: 1; ++ u8 hid: 1; ++ u8 a2dp: 1; ++ u8 pan: 1; ++}; ++ ++struct btc_btinfo_lb3 { ++ u8 retry: 4; ++ u8 cqddr: 1; ++ u8 inq: 1; ++ u8 mesh_busy: 1; ++ u8 pag: 1; ++}; ++ ++struct btc_btinfo_hb0 { ++ s8 rssi; ++}; ++ ++struct btc_btinfo_hb1 { ++ u8 ble_connect: 1; ++ u8 reinit: 1; ++ u8 relink: 1; ++ u8 igno_wl: 1; ++ u8 voice: 1; ++ u8 ble_scan: 1; ++ u8 role_sw: 1; ++ u8 multi_link: 1; ++}; ++ ++struct btc_btinfo_hb2 { ++ u8 pan_active: 1; ++ u8 afh_update: 1; ++ u8 a2dp_active: 1; ++ u8 slave: 1; ++ u8 hid_slot: 2; ++ u8 hid_cnt: 2; ++}; ++ ++struct btc_btinfo_hb3 { ++ u8 a2dp_bitpool: 6; ++ u8 tx_3m: 1; ++ u8 a2dp_sink: 1; ++}; ++ ++union btc_btinfo { ++ u8 val; ++ struct btc_btinfo_lb2 lb2; ++ struct btc_btinfo_lb3 lb3; ++ struct btc_btinfo_hb0 hb0; ++ struct btc_btinfo_hb1 hb1; ++ struct btc_btinfo_hb2 hb2; ++ struct btc_btinfo_hb3 hb3; ++}; ++ ++static void _set_policy(struct rtw89_dev *rtwdev, u16 policy_type, ++ enum btc_reason_and_action action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_fbtc_tdma *t = &dm->tdma; ++ struct rtw89_btc_fbtc_slot *s = dm->slot; ++ u8 type; ++ u32 tbl_w1, tbl_b1, tbl_b4; ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.wl.status.map._4way) ++ tbl_w1 = cxtbl[1]; ++ else ++ tbl_w1 = cxtbl[8]; ++ tbl_b1 = cxtbl[3]; ++ tbl_b4 = cxtbl[3]; ++ } else { ++ tbl_w1 = cxtbl[16]; ++ tbl_b1 = cxtbl[17]; ++ tbl_b4 = cxtbl[17]; ++ } ++ ++ type = (u8)((policy_type & BTC_CXP_MASK) >> 8); ++ btc->bt_req_en = false; ++ ++ switch (type) { ++ case BTC_CXP_USERDEF0: ++ *t = t_def[CXTD_OFF]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); ++ btc->update_policy_force = true; ++ break; ++ case BTC_CXP_OFF: /* TDMA off */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, false); ++ *t = t_def[CXTD_OFF]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ ++ switch (policy_type) { ++ case BTC_CXP_OFF_BT: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); ++ break; ++ case BTC_CXP_OFF_WL: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[1]); ++ break; ++ case BTC_CXP_OFF_EQ0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[0]); ++ break; ++ case BTC_CXP_OFF_EQ1: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[16]); ++ break; ++ case BTC_CXP_OFF_EQ2: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[17]); ++ break; ++ case BTC_CXP_OFF_EQ3: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[18]); ++ break; ++ case BTC_CXP_OFF_BWB0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[5]); ++ break; ++ case BTC_CXP_OFF_BWB1: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); ++ break; ++ } ++ break; ++ case BTC_CXP_OFFB: /* TDMA off + beacon protect */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, false); ++ *t = t_def[CXTD_OFF_B2]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ switch (policy_type) { ++ case BTC_CXP_OFFB_BWB0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); ++ break; ++ } ++ break; ++ case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */ ++ btc->bt_req_en = true; ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_OFF_EXT]; ++ switch (policy_type) { ++ case BTC_CXP_OFFE_DEF: ++ s[CXST_E2G] = s_def[CXST_E2G]; ++ s[CXST_E5G] = s_def[CXST_E5G]; ++ s[CXST_EBT] = s_def[CXST_EBT]; ++ s[CXST_ENULL] = s_def[CXST_ENULL]; ++ break; ++ case BTC_CXP_OFFE_DEF2: ++ _slot_set(btc, CXST_E2G, 20, cxtbl[1], SLOT_ISO); ++ s[CXST_E5G] = s_def[CXST_E5G]; ++ s[CXST_EBT] = s_def[CXST_EBT]; ++ s[CXST_ENULL] = s_def[CXST_ENULL]; ++ break; ++ } ++ break; ++ case BTC_CXP_FIX: /* TDMA Fix-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_FIX]; ++ switch (policy_type) { ++ case BTC_CXP_FIX_TD3030: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2030: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD4010: ++ _slot_set(btc, CXST_W1, 40, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD4020: ++ _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_MIX); ++ _slot_set(btc, CXST_B1, 20, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD7010: ++ _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2060: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD3060: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PFIX]; ++ if (btc->cx.wl.role_info.role_map.role.ap) ++ _tdma_set_flctrl(btc, CXFLC_QOSNULL); ++ ++ switch (policy_type) { ++ case BTC_CXP_PFIX_TD3030: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2030: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2060: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_AUTO: /* TDMA Auto-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_AUTO]; ++ switch (policy_type) { ++ case BTC_CXP_AUTO_TD50200: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TD60200: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TD20200: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PAUTO]; ++ switch (policy_type) { ++ case BTC_CXP_PAUTO_TD50200: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TD60200: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TD20200: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TDW1B1: ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_AUTO2]; ++ switch (policy_type) { ++ case BTC_CXP_AUTO2_TD3050: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD6060: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], ++ tbl_b4, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PAUTO2]; ++ switch (policy_type) { ++ case BTC_CXP_PAUTO2_TD3050: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD6060: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], ++ tbl_b4, SLOT_MIX); ++ break; ++ } ++ break; ++ } ++ ++ _fw_set_policy(rtwdev, policy_type, action); ++} ++ ++static void _set_gnt_bt(struct rtw89_dev *rtwdev, u8 phy_map, u8 state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_mac_ax_gnt *g = dm->gnt.band; ++ u8 i; ++ ++ if (phy_map > BTC_PHY_ALL) ++ return; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ if (!(phy_map & BIT(i))) ++ continue; ++ ++ switch (state) { ++ case BTC_GNT_HW: ++ g[i].gnt_bt_sw_en = 0; ++ g[i].gnt_bt = 0; ++ break; ++ case BTC_GNT_SW_LO: ++ g[i].gnt_bt_sw_en = 1; ++ g[i].gnt_bt = 0; ++ break; ++ case BTC_GNT_SW_HI: ++ g[i].gnt_bt_sw_en = 1; ++ g[i].gnt_bt = 1; ++ break; ++ } ++ } ++ ++ rtw89_mac_cfg_gnt(rtwdev, &dm->gnt); ++} ++ ++static void _set_bt_plut(struct rtw89_dev *rtwdev, u8 phy_map, ++ u8 tx_val, u8 rx_val) ++{ ++ struct rtw89_mac_ax_plt plt; ++ ++ plt.band = RTW89_MAC_0; ++ plt.tx = tx_val; ++ plt.rx = rx_val; ++ ++ if (phy_map & BTC_PHY_0) ++ rtw89_mac_cfg_plt(rtwdev, &plt); ++ ++ if (!rtwdev->dbcc_en) ++ return; ++ ++ plt.band = RTW89_MAC_1; ++ if (phy_map & BTC_PHY_1) ++ rtw89_mac_cfg_plt(rtwdev, &plt); ++} ++ ++static void _set_ant(struct rtw89_dev *rtwdev, bool force_exec, ++ u8 phy_map, u8 type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ u8 gnt_wl_ctrl, gnt_bt_ctrl, plt_ctrl, i, b2g = 0; ++ u32 ant_path_type; ++ ++ ant_path_type = ((phy_map << 8) + type); ++ ++ if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF || ++ btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE || ++ btc->dm.run_reason == BTC_RSN_CMD_SET_COEX) ++ force_exec = FC_EXEC; ++ ++ if (!force_exec && ant_path_type == dm->set_ant_path) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by no change!!\n", ++ __func__); ++ return; ++ } else if (bt->rfk_info.map.run) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by bt rfk!!\n", __func__); ++ return; ++ } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK && ++ wl->rfk_info.state != BTC_WRFK_STOP) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by wl rfk!!\n", __func__); ++ return; ++ } ++ ++ dm->set_ant_path = ant_path_type; ++ ++ rtw89_debug(rtwdev, ++ RTW89_DBG_BTC, ++ "[BTC], %s(): path=0x%x, set_type=0x%x\n", ++ __func__, phy_map, dm->set_ant_path & 0xff); ++ ++ switch (type) { ++ case BTC_ANT_WPOWERON: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ break; ++ case BTC_ANT_WINIT: ++ if (bt->enable.now) { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ } else { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ } ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_BT, BTC_PLT_BT); ++ break; ++ case BTC_ANT_WONLY: ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_WOFF: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_W2G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ if (rtwdev->dbcc_en) { ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ b2g = (wl_dinfo->real_band[i] == RTW89_BAND_2G); ++ ++ gnt_wl_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; ++ _set_gnt_wl(rtwdev, BIT(i), gnt_wl_ctrl); ++ ++ gnt_bt_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; ++ /* BT should control by GNT_BT if WL_2G at S0 */ ++ if (i == 1 && ++ wl_dinfo->real_band[0] == RTW89_BAND_2G && ++ wl_dinfo->real_band[1] == RTW89_BAND_5G) ++ gnt_bt_ctrl = BTC_GNT_HW; ++ _set_gnt_bt(rtwdev, BIT(i), gnt_bt_ctrl); ++ ++ plt_ctrl = b2g ? BTC_PLT_BT : BTC_PLT_NONE; ++ _set_bt_plut(rtwdev, BIT(i), ++ plt_ctrl, plt_ctrl); ++ } ++ } else { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_HW); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, ++ BTC_PLT_BT, BTC_PLT_BT); ++ } ++ break; ++ case BTC_ANT_W5G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_W25G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_HW); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, ++ BTC_PLT_GNT_WL, BTC_PLT_GNT_WL); ++ break; ++ case BTC_ANT_FREERUN: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_WRFK: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_BRFK: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _action_wl_only(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_ONLY); ++} ++ ++static void _action_wl_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WINIT); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_INIT); ++} ++ ++static void _action_wl_off(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ if (wl->status.map.rf_off || btc->dm.bt_only) ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF); ++ ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); ++} ++ ++static void _action_freerun(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_FREERUN); ++ ++ btc->dm.freerun = true; ++} ++ ++static void _action_bt_whql(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_WHQL); ++} ++ ++static void _action_bt_off(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_OFF); ++} ++ ++static void _action_bt_idle(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *b = &btc->cx.bt.link_info; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /*wl-busy + bt idle*/ ++ if (b->profile_cnt.now > 0) ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, ++ BTC_ACT_BT_IDLE); ++ else ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ ++ if (b->profile_cnt.now > 0) ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, ++ BTC_ACT_BT_IDLE); ++ else ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD5050, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-inq or bt-idle */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD7010, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-idle */ ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_IDLE); ++ break; ++ } ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_BT_IDLE); ++ } ++} ++ ++static void _action_bt_hfp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.wl.status.map._4way) ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HFP); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB0, BTC_ACT_BT_HFP); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ2, BTC_ACT_BT_HFP); ++ } ++} ++ ++static void _action_bt_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) /* shared-antenna */ ++ if (btc->cx.wl.status.map._4way) ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HID); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB0, BTC_ACT_BT_HID); ++ else /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ3, BTC_ACT_BT_HID); ++} ++ ++static void _action_bt_a2dp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP); ++ } else { ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TD50200, BTC_ACT_BT_A2DP); ++ } ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, ++ BTC_ACT_BT_A2DP); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD50200, ++ BTC_ACT_BT_A2DP); ++ } ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD20200, BTC_ACT_BT_A2DP); ++ break; ++ } ++} ++ ++static void _action_bt_a2dpsink(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2060, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2060, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2080, BTC_ACT_BT_A2DPSINK); ++ break; ++ } ++} ++ ++static void _action_bt_pan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-pan */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN); ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+HID */ ++ case BTC_WIDLE: /* wl-idle + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP_HID); ++ } else { ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TD50200, BTC_ACT_BT_A2DP_HID); ++ } ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP_HID); ++ break; ++ ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+HID */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+HID */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, ++ BTC_ACT_BT_A2DP_HID); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD50200, ++ BTC_ACT_BT_A2DP_HID); ++ } ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_pan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD5050, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, BTC_ACT_BT_A2DP_PAN); ++ break; ++ } ++} ++ ++static void _action_bt_pan_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3030, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN_HID); ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_pan_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN+HID */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ } ++} ++ ++static void _action_wl_5g(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_5G); ++} ++ ++static void _action_wl_other(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) ++ _set_policy(rtwdev, BTC_CXP_OFFB_BWB0, BTC_ACT_WL_OTHER); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OTHER); ++} ++ ++static void _action_wl_nc(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_NC); ++} ++ ++static void _action_wl_rfk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_rfk_info rfk = btc->cx.wl.rfk_info; ++ ++ if (rfk.state != BTC_WRFK_START) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): band = %d\n", ++ __func__, rfk.band); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK); ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_WL_RFK); ++} ++ ++static void _set_btg_ctrl(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ bool is_btg = false; ++ ++ if (btc->ctrl.manual) ++ return; ++ ++ /* notify halbb ignore GNT_BT or not for WL BB Rx-AGC control */ ++ if (wl_rinfo->link_mode == BTC_WLINK_5G) /* always 0 if 5G */ ++ is_btg = false; ++ else if (wl_rinfo->link_mode == BTC_WLINK_25G_DBCC && ++ wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) ++ is_btg = false; ++ else ++ is_btg = true; ++ ++ if (btc->dm.run_reason != BTC_RSN_NTFY_INIT && ++ is_btg == btc->dm.wl_btg_rx) ++ return; ++ ++ btc->dm.wl_btg_rx = is_btg; ++ ++ if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC) ++ return; ++ ++ rtw89_ctrl_btg(rtwdev, is_btg); ++} ++ ++struct rtw89_txtime_data { ++ struct rtw89_dev *rtwdev; ++ int type; ++ u32 tx_time; ++ u8 tx_retry; ++ u16 enable; ++ bool reenable; ++}; ++ ++static void rtw89_tx_time_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_txtime_data *iter_data = ++ (struct rtw89_txtime_data *)data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_wl_link_info *plink = NULL; ++ u8 port = rtwvif->port; ++ u32 tx_time = iter_data->tx_time; ++ u8 tx_retry = iter_data->tx_retry; ++ u16 enable = iter_data->enable; ++ bool reenable = iter_data->reenable; ++ ++ plink = &wl->link_info[port]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): port = %d\n", __func__, port); ++ ++ if (!plink->connected) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): connected = %d\n", ++ __func__, plink->connected); ++ return; ++ } ++ ++ /* backup the original tx time before tx-limit on */ ++ if (reenable) { ++ rtw89_mac_get_tx_time(rtwdev, rtwsta, &plink->tx_time); ++ rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta, &plink->tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): reenable, tx_time=%d tx_retry= %d\n", ++ __func__, plink->tx_time, plink->tx_retry); ++ } ++ ++ /* restore the original tx time if no tx-limit */ ++ if (!enable) { ++ rtw89_mac_set_tx_time(rtwdev, rtwsta, true, plink->tx_time); ++ rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta, true, ++ plink->tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): restore, tx_time=%d tx_retry= %d\n", ++ __func__, plink->tx_time, plink->tx_retry); ++ ++ } else { ++ rtw89_mac_set_tx_time(rtwdev, rtwsta, false, tx_time); ++ rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta, false, tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): set, tx_time=%d tx_retry= %d\n", ++ __func__, tx_time, tx_retry); ++ } ++} ++ ++static void _set_wl_tx_limit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_txtime_data data = {.rtwdev = rtwdev}; ++ u8 mode = wl_rinfo->link_mode; ++ u8 tx_retry = 0; ++ u32 tx_time = 0; ++ u16 enable = 0; ++ bool reenable = false; ++ ++ if (btc->ctrl.manual) ++ return; ++ ++ if (btc->dm.freerun || btc->ctrl.igno_bt || b->profile_cnt.now == 0 || ++ mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) { ++ enable = 0; ++ tx_time = BTC_MAX_TX_TIME_DEF; ++ tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } else if ((hfp->exist && hid->exist) || hid->pair_cnt > 1) { ++ enable = 1; ++ tx_time = BTC_MAX_TX_TIME_L2; ++ tx_retry = BTC_MAX_TX_RETRY_L1; ++ } else if (hfp->exist || hid->exist) { ++ enable = 1; ++ tx_time = BTC_MAX_TX_TIME_L3; ++ tx_retry = BTC_MAX_TX_RETRY_L1; ++ } else { ++ enable = 0; ++ tx_time = BTC_MAX_TX_TIME_DEF; ++ tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } ++ ++ if (dm->wl_tx_limit.enable == enable && ++ dm->wl_tx_limit.tx_time == tx_time && ++ dm->wl_tx_limit.tx_retry == tx_retry) ++ return; ++ ++ if (!dm->wl_tx_limit.enable && enable) ++ reenable = true; ++ ++ dm->wl_tx_limit.enable = enable; ++ dm->wl_tx_limit.tx_time = tx_time; ++ dm->wl_tx_limit.tx_retry = tx_retry; ++ ++ data.enable = enable; ++ data.tx_time = tx_time; ++ data.tx_retry = tx_retry; ++ data.reenable = reenable; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_tx_time_iter, ++ &data); ++} ++ ++#define _set_bt_slot_req(rtwdev) do {} while (0) ++ ++static void _set_bt_rx_agc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ bool bt_hi_lna_rx = false; ++ ++ if (wl_rinfo->link_mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx) ++ bt_hi_lna_rx = true; ++ ++ if (bt_hi_lna_rx == bt->hi_lna_rx) ++ return; ++ ++ _write_scbd(rtwdev, BTC_WSCB_BT_HILNA, bt_hi_lna_rx); ++} ++ ++/* TODO add these functions */ ++static void _action_common(struct rtw89_dev *rtwdev) ++{ ++ _set_btg_ctrl(rtwdev); ++ _set_wl_tx_limit(rtwdev); ++ _set_bt_afh_info(rtwdev); ++ _set_bt_rx_agc(rtwdev); ++ _set_bt_slot_req(rtwdev); ++ _set_rf_trx_para(rtwdev); ++} ++ ++static void _action_by_bt(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; ++ u8 profile_map = 0; ++ ++ if (bt_linfo->hfp_desc.exist) ++ profile_map |= BTC_BT_HFP; ++ ++ if (bt_linfo->hid_desc.exist) ++ profile_map |= BTC_BT_HID; ++ ++ if (bt_linfo->a2dp_desc.exist) ++ profile_map |= BTC_BT_A2DP; ++ ++ if (bt_linfo->pan_desc.exist) ++ profile_map |= BTC_BT_PAN; ++ ++ switch (profile_map) { ++ case BTC_BT_NOPROFILE: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else if (a2dp.active || pan.active) ++ _action_bt_pan(rtwdev); ++ else ++ _action_bt_idle(rtwdev); ++ break; ++ case BTC_BT_HFP: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_hfp(rtwdev); ++ break; ++ case BTC_BT_HFP | BTC_BT_HID: ++ case BTC_BT_HID: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else if (a2dp.sink) ++ _action_bt_a2dpsink(rtwdev); ++ else if (bt_linfo->multi_link.now && !hid.pair_cnt) ++ _action_bt_a2dp_pan(rtwdev); ++ else ++ _action_bt_a2dp(rtwdev); ++ break; ++ case BTC_BT_PAN: ++ _action_bt_pan(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_HFP: ++ case BTC_BT_A2DP | BTC_BT_HID: ++ case BTC_BT_A2DP | BTC_BT_HFP | BTC_BT_HID: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_a2dp_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_PAN: ++ _action_bt_a2dp_pan(rtwdev); ++ break; ++ case BTC_BT_PAN | BTC_BT_HFP: ++ case BTC_BT_PAN | BTC_BT_HID: ++ case BTC_BT_PAN | BTC_BT_HFP | BTC_BT_HID: ++ _action_bt_pan_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HID: ++ case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HFP: ++ default: ++ _action_bt_a2dp_pan_hid(rtwdev); ++ break; ++ } ++} ++ ++static void _action_wl_2g_sta(struct rtw89_dev *rtwdev) ++{ ++ _action_by_bt(rtwdev); ++} ++ ++static void _action_wl_scan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ ++ if (rtwdev->dbcc_en) { ++ if (wl_dinfo->real_band[RTW89_PHY_0] != RTW89_BAND_2G && ++ wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) ++ _action_wl_5g(rtwdev); ++ else ++ _action_by_bt(rtwdev); ++ } else { ++ if (wl->scan_info.band[RTW89_PHY_0] != RTW89_BAND_2G) ++ _action_wl_5g(rtwdev); ++ else ++ _action_by_bt(rtwdev); ++ } ++} ++ ++static void _action_wl_25g_mcc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_25G_MCC); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, ++ BTC_ACT_WL_25G_MCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_25G_MCC); ++ } ++} ++ ++static void _action_wl_2g_mcc(struct rtw89_dev *rtwdev) ++{ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_2G_MCC); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, ++ BTC_ACT_WL_2G_MCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_MCC); ++ } ++} ++ ++static void _action_wl_2g_scc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_SCC); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_SCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_SCC); ++ } ++} ++ ++static void _action_wl_2g_ap(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_2G_AP); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_AP); ++ } else {/* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_AP); ++ } ++} ++ ++static void _action_wl_2g_go(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_GO); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_GO); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GO); ++ } ++} ++ ++static void _action_wl_2g_gc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ _action_by_bt(rtwdev); ++ } else {/* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GC); ++ } ++} ++ ++static void _action_wl_2g_nan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_NAN); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_NAN); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_NAN); ++ } ++} ++ ++static u32 _read_scbd(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ u32 scbd_val = 0; ++ ++ if (!chip->scbd) ++ return 0; ++ ++ scbd_val = rtw89_mac_get_sb(rtwdev); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], read scbd: 0x%08x\n", ++ scbd_val); ++ ++ btc->cx.cnt_bt[BTC_BCNT_SCBDREAD]++; ++ return scbd_val; ++} ++ ++static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 scbd_val = 0; ++ ++ if (!chip->scbd) ++ return; ++ ++ scbd_val = state ? wl->scbd | val : wl->scbd & ~val; ++ ++ if (scbd_val == wl->scbd) ++ return; ++ rtw89_mac_cfg_sb(rtwdev, scbd_val); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], write scbd: 0x%08x\n", ++ scbd_val); ++ wl->scbd = scbd_val; ++ ++ btc->cx.cnt_wl[BTC_WCNT_SCBDUPDATE]++; ++} ++ ++static u8 ++_update_rssi_state(struct rtw89_dev *rtwdev, u8 pre_state, u8 rssi, u8 thresh) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 next_state, tol = chip->rssi_tol; ++ ++ if (pre_state == BTC_RSSI_ST_LOW || ++ pre_state == BTC_RSSI_ST_STAY_LOW) { ++ if (rssi >= (thresh + tol)) ++ next_state = BTC_RSSI_ST_HIGH; ++ else ++ next_state = BTC_RSSI_ST_STAY_LOW; ++ } else { ++ if (rssi < thresh) ++ next_state = BTC_RSSI_ST_LOW; ++ else ++ next_state = BTC_RSSI_ST_STAY_HIGH; ++ } ++ ++ return next_state; ++} ++ ++static ++void _update_dbcc_band(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ btc->cx.wl.dbcc_info.real_band[phy_idx] = ++ btc->cx.wl.scan_info.phy_map & BIT(phy_idx) ? ++ btc->cx.wl.dbcc_info.scan_band[phy_idx] : ++ btc->cx.wl.dbcc_info.op_band[phy_idx]; ++} ++ ++static void _update_wl_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ u8 i, cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; ++ u8 cnt_2g = 0, cnt_5g = 0, phy; ++ u32 wl_2g_ch[2] = {0}, wl_5g_ch[2] = {0}; ++ bool b2g = false, b5g = false, client_joined = false; ++ ++ memset(wl_rinfo, 0, sizeof(*wl_rinfo)); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ /* check if role active? */ ++ if (!wl_linfo[i].active) ++ continue; ++ ++ cnt_active++; ++ wl_rinfo->active_role[cnt_active - 1].role = wl_linfo[i].role; ++ wl_rinfo->active_role[cnt_active - 1].pid = wl_linfo[i].pid; ++ wl_rinfo->active_role[cnt_active - 1].phy = wl_linfo[i].phy; ++ wl_rinfo->active_role[cnt_active - 1].band = wl_linfo[i].band; ++ wl_rinfo->active_role[cnt_active - 1].noa = (u8)wl_linfo[i].noa; ++ wl_rinfo->active_role[cnt_active - 1].connected = 0; ++ ++ wl->port_id[wl_linfo[i].role] = wl_linfo[i].pid; ++ ++ phy = wl_linfo[i].phy; ++ ++ /* check dbcc role */ ++ if (rtwdev->dbcc_en && phy < RTW89_PHY_MAX) { ++ wl_dinfo->role[phy] = wl_linfo[i].role; ++ wl_dinfo->op_band[phy] = wl_linfo[i].band; ++ _update_dbcc_band(rtwdev, phy); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ if (wl_linfo[i].connected == MLME_NO_LINK) { ++ continue; ++ } else if (wl_linfo[i].connected == MLME_LINKING) { ++ cnt_connecting++; ++ } else { ++ cnt_connect++; ++ if ((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || ++ wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && ++ wl_linfo[i].client_cnt > 1) ++ client_joined = true; ++ } ++ ++ wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); ++ wl_rinfo->active_role[cnt_active - 1].ch = wl_linfo[i].ch; ++ wl_rinfo->active_role[cnt_active - 1].bw = wl_linfo[i].bw; ++ wl_rinfo->active_role[cnt_active - 1].connected = 1; ++ ++ /* only care 2 roles + BT coex */ ++ if (wl_linfo[i].band != RTW89_BAND_2G) { ++ if (cnt_5g <= ARRAY_SIZE(wl_5g_ch) - 1) ++ wl_5g_ch[cnt_5g] = wl_linfo[i].ch; ++ cnt_5g++; ++ b5g = true; ++ } else { ++ if (cnt_2g <= ARRAY_SIZE(wl_2g_ch) - 1) ++ wl_2g_ch[cnt_2g] = wl_linfo[i].ch; ++ cnt_2g++; ++ b2g = true; ++ } ++ } ++ ++ wl_rinfo->connect_cnt = cnt_connect; ++ ++ /* Be careful to change the following sequence!! */ ++ if (cnt_connect == 0) { ++ wl_rinfo->link_mode = BTC_WLINK_NOLINK; ++ wl_rinfo->role_map.role.none = 1; ++ } else if (!b2g && b5g) { ++ wl_rinfo->link_mode = BTC_WLINK_5G; ++ } else if (wl_rinfo->role_map.role.nan) { ++ wl_rinfo->link_mode = BTC_WLINK_2G_NAN; ++ } else if (cnt_connect > BTC_TDMA_WLROLE_MAX) { ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ } else if (b2g && b5g && cnt_connect == 2) { ++ if (rtwdev->dbcc_en) { ++ switch (wl_dinfo->role[RTW89_PHY_0]) { ++ case RTW89_WIFI_ROLE_STATION: ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ break; ++ case RTW89_WIFI_ROLE_P2P_GO: ++ wl_rinfo->link_mode = BTC_WLINK_2G_GO; ++ break; ++ case RTW89_WIFI_ROLE_P2P_CLIENT: ++ wl_rinfo->link_mode = BTC_WLINK_2G_GC; ++ break; ++ case RTW89_WIFI_ROLE_AP: ++ wl_rinfo->link_mode = BTC_WLINK_2G_AP; ++ break; ++ default: ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ break; ++ } ++ } else { ++ wl_rinfo->link_mode = BTC_WLINK_25G_MCC; ++ } ++ } else if (!b5g && cnt_connect == 2) { ++ if (wl_rinfo->role_map.role.station && ++ (wl_rinfo->role_map.role.p2p_go || ++ wl_rinfo->role_map.role.p2p_gc || ++ wl_rinfo->role_map.role.ap)) { ++ if (wl_2g_ch[0] == wl_2g_ch[1]) ++ wl_rinfo->link_mode = BTC_WLINK_2G_SCC; ++ else ++ wl_rinfo->link_mode = BTC_WLINK_2G_MCC; ++ } else { ++ wl_rinfo->link_mode = BTC_WLINK_2G_MCC; ++ } ++ } else if (!b5g && cnt_connect == 1) { ++ if (wl_rinfo->role_map.role.station) ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ else if (wl_rinfo->role_map.role.ap) ++ wl_rinfo->link_mode = BTC_WLINK_2G_AP; ++ else if (wl_rinfo->role_map.role.p2p_go) ++ wl_rinfo->link_mode = BTC_WLINK_2G_GO; ++ else if (wl_rinfo->role_map.role.p2p_gc) ++ wl_rinfo->link_mode = BTC_WLINK_2G_GC; ++ else ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ } ++ ++ /* if no client_joined, don't care P2P-GO/AP role */ ++ if (wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) { ++ if (!client_joined) { ++ if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || ++ wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ wl_rinfo->connect_cnt = 1; ++ } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || ++ wl_rinfo->link_mode == BTC_WLINK_2G_AP) { ++ wl_rinfo->link_mode = BTC_WLINK_NOLINK; ++ wl_rinfo->connect_cnt = 0; ++ } ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], cnt_connect = %d, link_mode = %d\n", ++ cnt_connect, wl_rinfo->link_mode); ++ ++ _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); ++} ++ ++#define BTC_CHK_HANG_MAX 3 ++#define BTC_SCB_INV_VALUE GENMASK(31, 0) ++ ++void rtw89_coex_act1_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_act1_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ if (wl->status.map._4way) ++ wl->status.map._4way = false; ++ if (wl->status.map.connecting) ++ wl->status.map.connecting = false; ++ ++ _run_coex(rtwdev, BTC_RSN_ACT1_WORK); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_coex_bt_devinfo_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_bt_devinfo_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ a2dp->play_latency = 0; ++ _run_coex(rtwdev, BTC_RSN_BT_DEVINFO_WORK); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_coex_rfk_chk_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_rfk_chk_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ if (wl->rfk_info.state != BTC_WRFK_STOP) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): RFK timeout\n", __func__); ++ cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]++; ++ dm->error.map.wl_rfk_timeout = true; ++ wl->rfk_info.state = BTC_WRFK_STOP; ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); ++ _run_coex(rtwdev, BTC_RSN_RFK_CHK_WORK); ++ } ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ u32 val; ++ bool status_change = false; ++ ++ if (!chip->scbd) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); ++ ++ val = _read_scbd(rtwdev); ++ if (val == BTC_SCB_INV_VALUE) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by invalid scbd value\n", ++ __func__); ++ return; ++ } ++ ++ if (!(val & BTC_BSCB_ON) || ++ btc->dm.cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX) ++ bt->enable.now = 0; ++ else ++ bt->enable.now = 1; ++ ++ if (bt->enable.now != bt->enable.last) ++ status_change = true; ++ ++ /* reset bt info if bt re-enable */ ++ if (bt->enable.now && !bt->enable.last) { ++ _reset_btc_var(rtwdev, BTC_RESET_BTINFO); ++ cx->cnt_bt[BTC_BCNT_REENABLE]++; ++ bt->enable.now = 1; ++ } ++ ++ bt->enable.last = bt->enable.now; ++ bt->scbd = val; ++ bt->mbx_avl = !!(val & BTC_BSCB_ACT); ++ ++ if (bt->whql_test != !!(val & BTC_BSCB_WHQL)) ++ status_change = true; ++ ++ bt->whql_test = !!(val & BTC_BSCB_WHQL); ++ bt->btg_type = val & BTC_BSCB_BT_S1 ? BTC_BT_BTG : BTC_BT_ALONE; ++ bt->link_info.a2dp_desc.active = !!(val & BTC_BSCB_A2DP_ACT); ++ ++ /* if rfk run 1->0 */ ++ if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN)) ++ status_change = true; ++ ++ bt->rfk_info.map.run = !!(val & BTC_BSCB_RFK_RUN); ++ bt->rfk_info.map.req = !!(val & BTC_BSCB_RFK_REQ); ++ bt->hi_lna_rx = !!(val & BTC_BSCB_BT_HILNA); ++ bt->link_info.status.map.connect = !!(val & BTC_BSCB_BT_CONNECT); ++ bt->run_patch_code = !!(val & BTC_BSCB_PATCH_CODE); ++ ++ if (!only_update && status_change) ++ _run_coex(rtwdev, BTC_RSN_UPDATE_BT_SCBD); ++} ++ ++static bool _chk_wl_rfk_request(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ _update_bt_scbd(rtwdev, true); ++ ++ cx->cnt_wl[BTC_WCNT_RFK_REQ]++; ++ ++ if ((bt->rfk_info.map.run || bt->rfk_info.map.req) && ++ !bt->rfk_info.map.timeout) { ++ cx->cnt_wl[BTC_WCNT_RFK_REJECT]++; ++ } else { ++ cx->cnt_wl[BTC_WCNT_RFK_GO]++; ++ return true; ++ } ++ return false; ++} ++ ++#define _get_wl_nhm_dbm(rtwdev) do {} while (0) ++ ++static ++void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ u8 mode = wl_rinfo->link_mode; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): reason=%d, mode=%d\n", ++ __func__, reason, mode); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): wl_only=%d, bt_only=%d\n", ++ __func__, dm->wl_only, dm->bt_only); ++ ++ dm->run_reason = reason; ++ _update_dm_step(rtwdev, reason); ++ _update_btc_state_map(rtwdev); ++ _get_wl_nhm_dbm(rtwdev); ++ ++ /* Be careful to change the following function sequence!! */ ++ if (btc->ctrl.manual) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for Manual CTRL!!\n", ++ __func__); ++ return; ++ } ++ ++ if (btc->ctrl.igno_bt && ++ (reason == BTC_RSN_UPDATE_BT_INFO || ++ reason == BTC_RSN_UPDATE_BT_SCBD)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for Stop Coex DM!!\n", ++ __func__); ++ return; ++ } ++ ++ if (!wl->status.map.init_ok) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL init fail!!\n", ++ __func__); ++ return; ++ } ++ ++ if (wl->status.map.rf_off_pre == wl->status.map.rf_off && ++ wl->status.map.lps_pre == wl->status.map.lps && ++ (reason == BTC_RSN_NTFY_POWEROFF || ++ reason == BTC_RSN_NTFY_RADIO_STATE)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL rf off state no change!!\n", ++ __func__); ++ return; ++ } ++ ++ dm->cnt_dm[BTC_DCNT_RUN]++; ++ ++ if (btc->ctrl.always_freerun) { ++ _action_freerun(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ if (dm->wl_only) { ++ _action_wl_only(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { ++ _action_wl_off(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ btc->ctrl.igno_bt = false; ++ dm->freerun = false; ++ ++ if (reason == BTC_RSN_NTFY_INIT) { ++ _action_wl_init(rtwdev); ++ goto exit; ++ } ++ ++ if (!cx->bt.enable.now && !cx->other.type) { ++ _action_bt_off(rtwdev); ++ goto exit; ++ } ++ ++ if (cx->bt.whql_test) { ++ _action_bt_whql(rtwdev); ++ goto exit; ++ } ++ ++ if (wl->rfk_info.state != BTC_WRFK_STOP) { ++ _action_wl_rfk(rtwdev); ++ goto exit; ++ } ++ ++ if (cx->state_map == BTC_WLINKING) { ++ if (mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_2G_STA || ++ mode == BTC_WLINK_5G) { ++ _action_wl_scan(rtwdev); ++ goto exit; ++ } ++ } ++ ++ if (wl->status.map.scan) { ++ _action_wl_scan(rtwdev); ++ goto exit; ++ } ++ ++ switch (mode) { ++ case BTC_WLINK_NOLINK: ++ _action_wl_nc(rtwdev); ++ break; ++ case BTC_WLINK_2G_STA: ++ _action_wl_2g_sta(rtwdev); ++ break; ++ case BTC_WLINK_2G_AP: ++ _action_wl_2g_ap(rtwdev); ++ break; ++ case BTC_WLINK_2G_GO: ++ _action_wl_2g_go(rtwdev); ++ break; ++ case BTC_WLINK_2G_GC: ++ _action_wl_2g_gc(rtwdev); ++ break; ++ case BTC_WLINK_2G_SCC: ++ _action_wl_2g_scc(rtwdev); ++ break; ++ case BTC_WLINK_2G_MCC: ++ _action_wl_2g_mcc(rtwdev); ++ break; ++ case BTC_WLINK_25G_MCC: ++ _action_wl_25g_mcc(rtwdev); ++ break; ++ case BTC_WLINK_5G: ++ _action_wl_5g(rtwdev); ++ break; ++ case BTC_WLINK_2G_NAN: ++ _action_wl_2g_nan(rtwdev); ++ break; ++ default: ++ _action_wl_other(rtwdev); ++ break; ++ } ++ ++exit: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): exit\n", __func__); ++ _action_common(rtwdev); ++} ++ ++void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ btc->dm.cnt_notify[BTC_NCNT_POWER_ON]++; ++} ++ ++void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++; ++ ++ btc->cx.wl.status.map.rf_off = 1; ++ ++ _write_scbd(rtwdev, BTC_WSCB_ALL, false); ++ _run_coex(rtwdev, BTC_RSN_NTFY_POWEROFF); ++ ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, 0); ++ ++ btc->cx.wl.status.map.rf_off_pre = btc->cx.wl.status.map.rf_off; ++} ++ ++static void _set_init_info(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ dm->init_info.wl_only = (u8)dm->wl_only; ++ dm->init_info.bt_only = (u8)dm->bt_only; ++ dm->init_info.wl_init_ok = (u8)wl->status.map.init_ok; ++ dm->init_info.dbcc_en = rtwdev->dbcc_en; ++ dm->init_info.cx_other = btc->cx.other.type; ++ dm->init_info.wl_guard_ch = chip->afh_guard_ch; ++ dm->init_info.module = btc->mdinfo; ++} ++ ++void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ _reset_btc_var(rtwdev, BTC_RESET_ALL); ++ btc->dm.run_reason = BTC_RSN_NONE; ++ btc->dm.run_action = BTC_ACT_NONE; ++ btc->ctrl.igno_bt = true; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mode=%d\n", __func__, mode); ++ ++ dm->cnt_notify[BTC_NCNT_INIT_COEX]++; ++ dm->wl_only = mode == BTC_MODE_WL ? 1 : 0; ++ dm->bt_only = mode == BTC_MODE_BT ? 1 : 0; ++ wl->status.map.rf_off = mode == BTC_MODE_WLOFF ? 1 : 0; ++ ++ chip->ops->btc_set_rfe(rtwdev); ++ chip->ops->btc_init_cfg(rtwdev); ++ ++ if (!wl->status.map.init_ok) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL init fail!!\n", ++ __func__); ++ dm->error.map.init = true; ++ return; ++ } ++ ++ _write_scbd(rtwdev, ++ BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true); ++ _update_bt_scbd(rtwdev, true); ++ if (rtw89_mac_get_ctrl_path(rtwdev)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): PTA owner warning!!\n", ++ __func__); ++ dm->error.map.pta_owner = true; ++ } ++ ++ _set_init_info(rtwdev); ++ _set_wl_tx_power(rtwdev, RTW89_BTC_WL_DEF_TX_PWR); ++ rtw89_btc_fw_set_slots(rtwdev, CXST_MAX, dm->slot); ++ btc_fw_set_monreg(rtwdev); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_INIT); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_CTRL); ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_INIT); ++} ++ ++void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d, band=%d\n", ++ __func__, phy_idx, band); ++ btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++; ++ wl->status.map.scan = true; ++ wl->scan_info.band[phy_idx] = band; ++ wl->scan_info.phy_map |= BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ wl->dbcc_info.scan_band[phy_idx] = band; ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_START); ++} ++ ++void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d\n", __func__, phy_idx); ++ btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++; ++ ++ wl->status.map.scan = false; ++ wl->scan_info.phy_map &= ~BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_FINISH); ++} ++ ++void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d, band=%d\n", ++ __func__, phy_idx, band); ++ btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++; ++ ++ wl->scan_info.band[phy_idx] = band; ++ wl->scan_info.phy_map |= BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ wl->dbcc_info.scan_band[phy_idx] = band; ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ _run_coex(rtwdev, BTC_RSN_NTFY_SWBAND); ++} ++ ++void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev, ++ enum btc_pkt_type pkt_type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_link_info *b = &cx->bt.link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ u32 cnt; ++ u32 delay = RTW89_COEX_ACT1_WORK_PERIOD; ++ bool delay_work = false; ++ ++ switch (pkt_type) { ++ case PACKET_DHCP: ++ cnt = ++cx->cnt_wl[BTC_WCNT_DHCP]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): DHCP cnt=%d\n", __func__, cnt); ++ wl->status.map.connecting = true; ++ delay_work = true; ++ break; ++ case PACKET_EAPOL: ++ cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): EAPOL cnt=%d\n", __func__, cnt); ++ wl->status.map._4way = true; ++ delay_work = true; ++ if (hfp->exist || hid->exist) ++ delay /= 2; ++ break; ++ case PACKET_EAPOL_END: ++ cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): EAPOL_End cnt=%d\n", ++ __func__, cnt); ++ wl->status.map._4way = false; ++ cancel_delayed_work(&rtwdev->coex_act1_work); ++ break; ++ case PACKET_ARP: ++ cnt = ++cx->cnt_wl[BTC_WCNT_ARP]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): ARP cnt=%d\n", __func__, cnt); ++ return; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): unknown packet type %d\n", ++ __func__, pkt_type); ++ return; ++ } ++ ++ if (delay_work) { ++ cancel_delayed_work(&rtwdev->coex_act1_work); ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_act1_work, delay); ++ } ++ ++ btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++; ++ _run_coex(rtwdev, BTC_RSN_NTFY_SPECIFIC_PACKET); ++} ++ ++void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.eapol_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_EAPOL); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.arp_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_ARP); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.dhcp_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_DHCP); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &b->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc *pan = &b->pan_desc; ++ union btc_btinfo btinfo; ++ ++ if (buf[BTC_BTINFO_L1] != 6) ++ return; ++ ++ if (!memcmp(bt->raw_info, buf, BTC_BTINFO_MAX)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by bt-info duplicate!!\n", ++ __func__); ++ cx->cnt_bt[BTC_BCNT_INFOSAME]++; ++ return; ++ } ++ ++ memcpy(bt->raw_info, buf, BTC_BTINFO_MAX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): bt_info[2]=0x%02x\n", ++ __func__, bt->raw_info[2]); ++ ++ /* reset to mo-connect before update */ ++ b->status.val = BTC_BLINK_NOCONNECT; ++ b->profile_cnt.last = b->profile_cnt.now; ++ b->relink.last = b->relink.now; ++ a2dp->exist_last = a2dp->exist; ++ b->multi_link.last = b->multi_link.now; ++ bt->inq_pag.last = bt->inq_pag.now; ++ b->profile_cnt.now = 0; ++ hid->type = 0; ++ ++ /* ======= parse raw info low-Byte2 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_L2]; ++ b->status.map.connect = btinfo.lb2.connect; ++ b->status.map.sco_busy = btinfo.lb2.sco_busy; ++ b->status.map.acl_busy = btinfo.lb2.acl_busy; ++ b->status.map.inq_pag = btinfo.lb2.inq_pag; ++ bt->inq_pag.now = btinfo.lb2.inq_pag; ++ cx->cnt_bt[BTC_BCNT_INQPAG] += !!(bt->inq_pag.now && !bt->inq_pag.last); ++ ++ hfp->exist = btinfo.lb2.hfp; ++ b->profile_cnt.now += (u8)hfp->exist; ++ hid->exist = btinfo.lb2.hid; ++ b->profile_cnt.now += (u8)hid->exist; ++ a2dp->exist = btinfo.lb2.a2dp; ++ b->profile_cnt.now += (u8)a2dp->exist; ++ pan->active = btinfo.lb2.pan; ++ ++ /* ======= parse raw info low-Byte3 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_L3]; ++ if (btinfo.lb3.retry != 0) ++ cx->cnt_bt[BTC_BCNT_RETRY]++; ++ b->cqddr = btinfo.lb3.cqddr; ++ cx->cnt_bt[BTC_BCNT_INQ] += !!(btinfo.lb3.inq && !bt->inq); ++ bt->inq = btinfo.lb3.inq; ++ cx->cnt_bt[BTC_BCNT_PAGE] += !!(btinfo.lb3.pag && !bt->pag); ++ bt->pag = btinfo.lb3.pag; ++ ++ b->status.map.mesh_busy = btinfo.lb3.mesh_busy; ++ /* ======= parse raw info high-Byte0 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H0]; ++ /* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/ ++ b->rssi = chip->ops->btc_get_bt_rssi(rtwdev, btinfo.hb0.rssi); ++ ++ /* ======= parse raw info high-Byte1 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H1]; ++ b->status.map.ble_connect = btinfo.hb1.ble_connect; ++ if (btinfo.hb1.ble_connect) ++ hid->type |= (hid->exist ? BTC_HID_BLE : BTC_HID_RCU); ++ ++ cx->cnt_bt[BTC_BCNT_REINIT] += !!(btinfo.hb1.reinit && !bt->reinit); ++ bt->reinit = btinfo.hb1.reinit; ++ cx->cnt_bt[BTC_BCNT_RELINK] += !!(btinfo.hb1.relink && !b->relink.now); ++ b->relink.now = btinfo.hb1.relink; ++ cx->cnt_bt[BTC_BCNT_IGNOWL] += !!(btinfo.hb1.igno_wl && !bt->igno_wl); ++ bt->igno_wl = btinfo.hb1.igno_wl; ++ ++ if (bt->igno_wl && !cx->wl.status.map.rf_off) ++ _set_bt_ignore_wlan_act(rtwdev, false); ++ ++ hid->type |= (btinfo.hb1.voice ? BTC_HID_RCU_VOICE : 0); ++ bt->ble_scan_en = btinfo.hb1.ble_scan; ++ ++ cx->cnt_bt[BTC_BCNT_ROLESW] += !!(btinfo.hb1.role_sw && !b->role_sw); ++ b->role_sw = btinfo.hb1.role_sw; ++ ++ b->multi_link.now = btinfo.hb1.multi_link; ++ ++ /* ======= parse raw info high-Byte2 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H2]; ++ pan->exist = btinfo.hb2.pan_active; ++ b->profile_cnt.now += (u8)pan->exist; ++ ++ cx->cnt_bt[BTC_BCNT_AFH] += !!(btinfo.hb2.afh_update && !b->afh_update); ++ b->afh_update = btinfo.hb2.afh_update; ++ a2dp->active = btinfo.hb2.a2dp_active; ++ b->slave_role = btinfo.hb2.slave; ++ hid->slot_info = btinfo.hb2.hid_slot; ++ hid->pair_cnt = btinfo.hb2.hid_cnt; ++ hid->type |= (hid->slot_info == BTC_HID_218 ? ++ BTC_HID_218 : BTC_HID_418); ++ /* ======= parse raw info high-Byte3 ======= */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H3]; ++ a2dp->bitpool = btinfo.hb3.a2dp_bitpool; ++ ++ if (b->tx_3m != (u32)btinfo.hb3.tx_3m) ++ cx->cnt_bt[BTC_BCNT_RATECHG]++; ++ b->tx_3m = (u32)btinfo.hb3.tx_3m; ++ ++ a2dp->sink = btinfo.hb3.a2dp_sink; ++ ++ if (b->profile_cnt.now || b->status.map.ble_connect) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, 1); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, 0); ++ ++ if (!a2dp->exist_last && a2dp->exist) { ++ a2dp->vendor_id = 0; ++ a2dp->flush_time = 0; ++ a2dp->play_latency = 1; ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_bt_devinfo_work, ++ RTW89_COEX_BT_DEVINFO_WORK_PERIOD); ++ } ++ ++ if (a2dp->exist && (a2dp->flush_time == 0 || a2dp->vendor_id == 0 || ++ a2dp->play_latency == 1)) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, 1); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, 0); ++ ++ _run_coex(rtwdev, BTC_RSN_UPDATE_BT_INFO); ++} ++ ++enum btc_wl_mode { ++ BTC_WL_MODE_HT = 0, ++ BTC_WL_MODE_VHT = 1, ++ BTC_WL_MODE_HE = 2, ++ BTC_WL_MODE_NUM, ++}; ++ ++void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ struct rtw89_sta *rtwsta, enum btc_role_state state) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info r = {0}; ++ struct rtw89_btc_wl_link_info *wlinfo = NULL; ++ u8 mode = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], state=%d\n", state); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], role is STA=%d\n", ++ vif->type == NL80211_IFTYPE_STATION); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], port=%d\n", rtwvif->port); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], band=%d ch=%d bw=%d\n", ++ hal->current_band_type, hal->current_channel, ++ hal->current_band_width); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], associated=%d\n", ++ state == BTC_ROLE_MSTS_STA_CONN_END); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], bcn_period=%d dtim_period=%d\n", ++ vif->bss_conf.beacon_int, vif->bss_conf.dtim_period); ++ ++ if (rtwsta) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], STA mac_id=%d\n", ++ rtwsta->mac_id); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], STA support HE=%d VHT=%d HT=%d\n", ++ sta->he_cap.has_he, ++ sta->vht_cap.vht_supported, ++ sta->ht_cap.ht_supported); ++ if (sta->he_cap.has_he) ++ mode |= BIT(BTC_WL_MODE_HE); ++ if (sta->vht_cap.vht_supported) ++ mode |= BIT(BTC_WL_MODE_VHT); ++ if (sta->ht_cap.ht_supported) ++ mode |= BIT(BTC_WL_MODE_HT); ++ ++ r.mode = mode; ++ } ++ ++ if (rtwvif->wifi_role >= RTW89_WIFI_ROLE_MLME_MAX) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], wifi_role=%d\n", rtwvif->wifi_role); ++ ++ r.role = rtwvif->wifi_role; ++ r.phy = rtwvif->phy_idx; ++ r.pid = rtwvif->port; ++ r.active = true; ++ r.connected = MLME_LINKED; ++ r.bcn_period = vif->bss_conf.beacon_int; ++ r.dtim_period = vif->bss_conf.dtim_period; ++ r.band = hal->current_band_type; ++ r.ch = hal->current_channel; ++ r.bw = hal->current_band_width; ++ ether_addr_copy(r.mac_addr, rtwvif->mac_addr); ++ ++ if (rtwsta && vif->type == NL80211_IFTYPE_STATION) ++ r.mac_id = rtwsta->mac_id; ++ ++ btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++; ++ ++ wlinfo = &wl->link_info[r.pid]; ++ ++ memcpy(wlinfo, &r, sizeof(*wlinfo)); ++ _update_wl_info(rtwdev); ++ ++ if (wlinfo->role == RTW89_WIFI_ROLE_STATION && ++ wlinfo->connected == MLME_NO_LINK) ++ btc->dm.leak_ap = 0; ++ ++ if (state == BTC_ROLE_MSTS_STA_CONN_START) ++ wl->status.map.connecting = 1; ++ else ++ wl->status.map.connecting = 0; ++ ++ if (state == BTC_ROLE_MSTS_STA_DIS_CONN) ++ wl->status.map._4way = false; ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_ROLE_INFO); ++} ++ ++void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): rf_state = %d\n", ++ __func__, rf_state); ++ btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++; ++ ++ switch (rf_state) { ++ case BTC_RFCTRL_WL_OFF: ++ wl->status.map.rf_off = 1; ++ wl->status.map.lps = 0; ++ break; ++ case BTC_RFCTRL_FW_CTRL: ++ wl->status.map.rf_off = 0; ++ wl->status.map.lps = 1; ++ break; ++ case BTC_RFCTRL_WL_ON: ++ default: ++ wl->status.map.rf_off = 0; ++ wl->status.map.lps = 0; ++ break; ++ } ++ ++ if (rf_state == BTC_RFCTRL_WL_ON) { ++ rtw89_btc_fw_en_rpt(rtwdev, ++ RPT_EN_MREG | RPT_EN_BT_VER_INFO, true); ++ _write_scbd(rtwdev, BTC_WSCB_ACTIVE, true); ++ _update_bt_scbd(rtwdev, true); ++ chip->ops->btc_init_cfg(rtwdev); ++ } else { ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, false); ++ _write_scbd(rtwdev, BTC_WSCB_ACTIVE | BTC_WSCB_WLBUSY, false); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_RADIO_STATE); ++ ++ wl->status.map.rf_off_pre = wl->status.map.rf_off; ++ wl->status.map.lps_pre = wl->status.map.lps; ++} ++ ++static bool _ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_path, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ bool result = BTC_WRFK_REJECT; ++ ++ wl->rfk_info.type = type; ++ wl->rfk_info.path_map = FIELD_GET(BTC_RFK_PATH_MAP, phy_path); ++ wl->rfk_info.phy_map = FIELD_GET(BTC_RFK_PHY_MAP, phy_path); ++ wl->rfk_info.band = FIELD_GET(BTC_RFK_BAND_MAP, phy_path); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s()_start: phy=0x%x, path=0x%x, type=%d, state=%d\n", ++ __func__, wl->rfk_info.phy_map, wl->rfk_info.path_map, ++ type, state); ++ ++ switch (state) { ++ case BTC_WRFK_START: ++ result = _chk_wl_rfk_request(rtwdev); ++ wl->rfk_info.state = result ? BTC_WRFK_START : BTC_WRFK_STOP; ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, result); ++ ++ btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++; ++ break; ++ case BTC_WRFK_ONESHOT_START: ++ case BTC_WRFK_ONESHOT_STOP: ++ if (wl->rfk_info.state == BTC_WRFK_STOP) { ++ result = BTC_WRFK_REJECT; ++ } else { ++ result = BTC_WRFK_ALLOW; ++ wl->rfk_info.state = state; ++ } ++ break; ++ case BTC_WRFK_STOP: ++ result = BTC_WRFK_ALLOW; ++ wl->rfk_info.state = BTC_WRFK_STOP; ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); ++ cancel_delayed_work(&rtwdev->coex_rfk_chk_work); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s() warning state=%d\n", __func__, state); ++ break; ++ } ++ ++ if (result == BTC_WRFK_ALLOW) { ++ if (wl->rfk_info.state == BTC_WRFK_START || ++ wl->rfk_info.state == BTC_WRFK_STOP) ++ _run_coex(rtwdev, BTC_RSN_NTFY_WL_RFK); ++ ++ if (wl->rfk_info.state == BTC_WRFK_START) ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_rfk_chk_work, ++ RTW89_COEX_RFK_CHK_WORK_PERIOD); ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s()_finish: rfk_cnt=%d, result=%d\n", ++ __func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result); ++ ++ return result == BTC_WRFK_ALLOW; ++} ++ ++void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state) ++{ ++ u8 band; ++ bool allow; ++ int ret; ++ ++ band = FIELD_GET(BTC_RFK_BAND_MAP, phy_map); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RFK] RFK notify (%s / PHY%u / K_type = %u / path_idx = %lu / process = %s)\n", ++ band == RTW89_BAND_2G ? "2G" : ++ band == RTW89_BAND_5G ? "5G" : "6G", ++ !!(FIELD_GET(BTC_RFK_PHY_MAP, phy_map) & BIT(RTW89_PHY_1)), ++ type, ++ FIELD_GET(BTC_RFK_PATH_MAP, phy_map), ++ state == BTC_WRFK_STOP ? "RFK_STOP" : ++ state == BTC_WRFK_START ? "RFK_START" : ++ state == BTC_WRFK_ONESHOT_START ? "ONE-SHOT_START" : ++ "ONE-SHOT_STOP"); ++ ++ if (state != BTC_WRFK_START || rtwdev->is_bt_iqk_timeout) { ++ _ntfy_wl_rfk(rtwdev, phy_map, type, state); ++ return; ++ } ++ ++ ret = read_poll_timeout(_ntfy_wl_rfk, allow, allow, 40, 100000, false, ++ rtwdev, phy_map, type, state); ++ if (ret) { ++ rtw89_warn(rtwdev, "RFK notify timeout\n"); ++ rtwdev->is_bt_iqk_timeout = true; ++ } ++} ++ ++struct rtw89_btc_wl_sta_iter_data { ++ struct rtw89_dev *rtwdev; ++ u8 busy_all; ++ u8 dir_all; ++ u8 rssi_map_all; ++ bool is_sta_change; ++ bool is_traffic_change; ++}; ++ ++static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_btc_wl_sta_iter_data *iter_data = ++ (struct rtw89_btc_wl_sta_iter_data *)data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info *link_info = NULL; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_traffic_stats *link_info_t = NULL; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_traffic_stats *stats = &rtwvif->stats; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u32 last_tx_rate, last_rx_rate; ++ u16 last_tx_lvl, last_rx_lvl; ++ u8 port = rtwvif->port; ++ u8 rssi; ++ u8 busy = 0; ++ u8 dir = 0; ++ u8 rssi_map = 0; ++ u8 i = 0; ++ bool is_sta_change = false, is_traffic_change = false; ++ ++ rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], rssi=%d\n", rssi); ++ ++ link_info = &wl->link_info[port]; ++ link_info->stat.traffic = rtwvif->stats; ++ link_info_t = &link_info->stat.traffic; ++ ++ if (link_info->connected == MLME_NO_LINK) { ++ link_info->rx_rate_drop_cnt = 0; ++ return; ++ } ++ ++ link_info->stat.rssi = rssi; ++ for (i = 0; i < BTC_WL_RSSI_THMAX; i++) { ++ link_info->rssi_state[i] = ++ _update_rssi_state(rtwdev, ++ link_info->rssi_state[i], ++ link_info->stat.rssi, ++ chip->wl_rssi_thres[i]); ++ if (BTC_RSSI_LOW(link_info->rssi_state[i])) ++ rssi_map |= BIT(i); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED && ++ BTC_RSSI_CHANGE(link_info->rssi_state[i])) ++ is_sta_change = true; ++ } ++ iter_data->rssi_map_all |= rssi_map; ++ ++ last_tx_rate = link_info_t->tx_rate; ++ last_rx_rate = link_info_t->rx_rate; ++ last_tx_lvl = (u16)link_info_t->tx_tfc_lv; ++ last_rx_lvl = (u16)link_info_t->rx_tfc_lv; ++ ++ if (stats->tx_tfc_lv != RTW89_TFC_IDLE || ++ stats->rx_tfc_lv != RTW89_TFC_IDLE) ++ busy = 1; ++ ++ if (stats->tx_tfc_lv > stats->rx_tfc_lv) ++ dir = RTW89_TFC_UL; ++ else ++ dir = RTW89_TFC_DL; ++ ++ link_info = &wl->link_info[port]; ++ if (link_info->busy != busy || link_info->dir != dir) { ++ is_sta_change = true; ++ link_info->busy = busy; ++ link_info->dir = dir; ++ } ++ ++ iter_data->busy_all |= busy; ++ iter_data->dir_all |= BIT(dir); ++ ++ if (rtwsta->rx_hw_rate <= RTW89_HW_RATE_CCK2 && ++ last_rx_rate > RTW89_HW_RATE_CCK2 && ++ link_info_t->rx_tfc_lv > RTW89_TFC_IDLE) ++ link_info->rx_rate_drop_cnt++; ++ ++ if (last_tx_rate != rtwsta->ra_report.hw_rate || ++ last_rx_rate != rtwsta->rx_hw_rate || ++ last_tx_lvl != link_info_t->tx_tfc_lv || ++ last_rx_lvl != link_info_t->rx_tfc_lv) ++ is_traffic_change = true; ++ ++ link_info_t->tx_rate = rtwsta->ra_report.hw_rate; ++ link_info_t->rx_rate = rtwsta->rx_hw_rate; ++ ++ wl->role_info.active_role[port].tx_lvl = (u16)stats->tx_tfc_lv; ++ wl->role_info.active_role[port].rx_lvl = (u16)stats->rx_tfc_lv; ++ wl->role_info.active_role[port].tx_rate = rtwsta->ra_report.hw_rate; ++ wl->role_info.active_role[port].rx_rate = rtwsta->rx_hw_rate; ++ ++ if (is_sta_change) ++ iter_data->is_sta_change = true; ++ ++ if (is_traffic_change) ++ iter_data->is_traffic_change = true; ++} ++ ++#define BTC_NHM_CHK_INTVL 20 ++ ++static void _ntfy_wl_sta(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_sta_iter_data data = {.rtwdev = rtwdev}; ++ u8 i; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_btc_ntfy_wl_sta_iter, ++ &data); ++ ++ wl->rssi_level = 0; ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]++; ++ for (i = BTC_WL_RSSI_THMAX; i > 0; i--) { ++ /* set RSSI level 4 ~ 0 if rssi bit map match */ ++ if (data.rssi_map_all & BIT(i - 1)) { ++ wl->rssi_level = i; ++ break; ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): busy=%d\n", ++ __func__, !!wl->status.map.busy); ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLBUSY, (!!wl->status.map.busy)); ++ ++ if (data.is_traffic_change) ++ _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); ++ if (data.is_sta_change) { ++ wl->status.map.busy = data.busy_all; ++ wl->status.map.traffic_dir = data.dir_all; ++ _run_coex(rtwdev, BTC_RSN_NTFY_WL_STA); ++ } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >= ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + BTC_NHM_CHK_INTVL) { ++ _get_wl_nhm_dbm(rtwdev); ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]; ++ } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] < ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) { ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]; ++ } ++} ++ ++void rtw89_btc_ntfy_wl_sta_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.wl_sta_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ _ntfy_wl_sta(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++#define _update_bt_psd(rtwdev, buf, len) do {} while (0) ++#define _update_offload_runinfo(rtwdev, buf, len) do {} while (0) ++ ++void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ /* The below is just sample code. Don't use magic number in your release ++ * version. ++ */ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ ++ /* note: 'len' includes header, so 'buf' length is 'len - 8' */ ++ u8 *buf = &skb->data[8]; /* size of C2H header is 8 */ ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): C2H BT len:%d class:%d fun:%d\n", ++ __func__, len, class, func); ++ ++ if (class != 0x12) ++ return; ++ ++ switch (func) { ++ case BTF_EVNT_RPT: ++ case BTF_EVNT_BUF_OVERFLOW: ++ pfwinfo->event[func]++; ++ /* Don't need rtw89_leave_ps_mode() */ ++ btc_fw_event(rtwdev, func, buf, len); ++ break; ++ case BTF_EVNT_BT_INFO: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], handle C2H BT INFO with data %8ph\n", buf); ++ btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++; ++ rtw89_leave_ps_mode(rtwdev); ++ _update_bt_info(rtwdev, buf, len); ++ break; ++ case BTF_EVNT_BT_SCBD: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], handle C2H BT SCBD with data %8ph\n", buf); ++ btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++; ++ rtw89_leave_ps_mode(rtwdev); ++ _update_bt_scbd(rtwdev, false); ++ break; ++ case BTF_EVNT_BT_PSD: ++ _update_bt_psd(rtwdev, buf, len); ++ break; ++ case BTF_EVNT_BT_REG: ++ btc->dbg.rb_done = true; ++ btc->dbg.rb_val = ((buf[3] << 24) | (buf[2] << 16) | ++ (buf[1] << 8) | (buf[0])); ++ break; ++ case BTF_EVNT_C2H_LOOPBACK: ++ btc->dbg.rb_done = true; ++ btc->dbg.rb_val = buf[0]; ++ break; ++ case BTF_EVNT_CX_RUNINFO: ++ btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++; ++ _update_offload_runinfo(rtwdev, buf, len); ++ break; } ++} ++ ++#define BTC_CX_FW_OFFLOAD 0 ++ ++static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_CX)) ++ return; ++ ++ dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++; ++ ++ seq_printf(m, "========== [BTC COEX INFO (%d)] ==========\n", ++ chip->chip_id); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), chip->para_ver); ++ ver_sub = FIELD_GET(GENMASK(23, 16), chip->para_ver); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->para_ver); ++ id_branch = FIELD_GET(GENMASK(7, 0), chip->para_ver); ++ seq_printf(m, " %-15s : Coex:%d.%d.%d(branch:%d), ", ++ "[coex_version]", ver_main, ver_sub, ver_hotfix, id_branch); ++ ++ if (dm->wl_fw_cx_offload != BTC_CX_FW_OFFLOAD) ++ dm->error.map.offload_mismatch = true; ++ else ++ dm->error.map.offload_mismatch = false; ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw_coex); ++ ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw_coex); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw_coex); ++ id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw_coex); ++ seq_printf(m, "WL_FW_coex:%d.%d.%d(branch:%d)", ++ ver_main, ver_sub, ver_hotfix, id_branch); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), chip->wlcx_desired); ++ ver_sub = FIELD_GET(GENMASK(23, 16), chip->wlcx_desired); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->wlcx_desired); ++ seq_printf(m, "(%s, desired:%d.%d.%d), ", ++ (wl->ver_info.fw_coex >= chip->wlcx_desired ? ++ "Match" : "Mis-Match"), ver_main, ver_sub, ver_hotfix); ++ ++ seq_printf(m, "BT_FW_coex:%d(%s, desired:%d)\n", ++ bt->ver_info.fw_coex, ++ (bt->ver_info.fw_coex >= chip->btcx_desired ? ++ "Match" : "Mis-Match"), chip->btcx_desired); ++ ++ if (bt->enable.now && bt->ver_info.fw == 0) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, true); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, false); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw); ++ ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw); ++ id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw); ++ seq_printf(m, " %-15s : WL_FW:%d.%d.%d.%d, BT_FW:0x%x(%s)\n", ++ "[sub_module]", ++ ver_main, ver_sub, ver_hotfix, id_branch, ++ bt->ver_info.fw, bt->run_patch_code ? "patch" : "ROM"); ++ ++ seq_printf(m, " %-15s : cv:%x, rfe_type:0x%x, ant_iso:%d, ant_pg:%d, %s", ++ "[hw_info]", btc->mdinfo.cv, btc->mdinfo.rfe_type, ++ btc->mdinfo.ant.isolation, btc->mdinfo.ant.num, ++ (btc->mdinfo.ant.num > 1 ? "" : (btc->mdinfo.ant.single_pos ? ++ "1Ant_Pos:S1, " : "1Ant_Pos:S0, "))); ++ ++ seq_printf(m, "3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d\n", ++ btc->cx.other.type, rtwdev->dbcc_en, hal->tx_nss, ++ hal->rx_nss); ++} ++ ++static void _show_wl_role_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_link_info *plink = NULL; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ struct rtw89_traffic_stats *t; ++ u8 i; ++ ++ if (rtwdev->dbcc_en) { ++ seq_printf(m, ++ " %-15s : PHY0_band(op:%d/scan:%d/real:%d), ", ++ "[dbcc_info]", wl_dinfo->op_band[RTW89_PHY_0], ++ wl_dinfo->scan_band[RTW89_PHY_0], ++ wl_dinfo->real_band[RTW89_PHY_0]); ++ seq_printf(m, ++ "PHY1_band(op:%d/scan:%d/real:%d)\n", ++ wl_dinfo->op_band[RTW89_PHY_1], ++ wl_dinfo->scan_band[RTW89_PHY_1], ++ wl_dinfo->real_band[RTW89_PHY_1]); ++ } ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ plink = &btc->cx.wl.link_info[i]; ++ ++ if (!plink->active) ++ continue; ++ ++ seq_printf(m, ++ " [port_%d] : role=%d(phy-%d), connect=%d(client_cnt=%d), mode=%d, center_ch=%d, bw=%d", ++ plink->pid, (u32)plink->role, plink->phy, ++ (u32)plink->connected, plink->client_cnt - 1, ++ (u32)plink->mode, plink->ch, (u32)plink->bw); ++ ++ if (plink->connected == MLME_NO_LINK) ++ continue; ++ ++ seq_printf(m, ++ ", mac_id=%d, max_tx_time=%dus, max_tx_retry=%d\n", ++ plink->mac_id, plink->tx_time, plink->tx_retry); ++ ++ seq_printf(m, ++ " [port_%d] : rssi=-%ddBm(%d), busy=%d, dir=%s, ", ++ plink->pid, 110 - plink->stat.rssi, ++ plink->stat.rssi, plink->busy, ++ plink->dir == RTW89_TFC_UL ? "UL" : "DL"); ++ ++ t = &plink->stat.traffic; ++ ++ seq_printf(m, ++ "tx[rate:%d/busy_level:%d], ", ++ (u32)t->tx_rate, t->tx_tfc_lv); ++ ++ seq_printf(m, "rx[rate:%d/busy_level:%d/drop:%d]\n", ++ (u32)t->rx_rate, ++ t->rx_tfc_lv, plink->rx_rate_drop_cnt); ++ } ++} ++ ++static void _show_wl_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL)) ++ return; ++ ++ seq_puts(m, "========== [WL Status] ==========\n"); ++ ++ seq_printf(m, " %-15s : link_mode:%d, ", ++ "[status]", (u32)wl_rinfo->link_mode); ++ ++ seq_printf(m, ++ "rf_off:%s, power_save:%s, scan:%s(band:%d/phy_map:0x%x), ", ++ wl->status.map.rf_off ? "Y" : "N", ++ wl->status.map.lps ? "Y" : "N", ++ wl->status.map.scan ? "Y" : "N", ++ wl->scan_info.band[RTW89_PHY_0], wl->scan_info.phy_map); ++ ++ seq_printf(m, ++ "connecting:%s, roam:%s, 4way:%s, init_ok:%s\n", ++ wl->status.map.connecting ? "Y" : "N", ++ wl->status.map.roaming ? "Y" : "N", ++ wl->status.map._4way ? "Y" : "N", ++ wl->status.map.init_ok ? "Y" : "N"); ++ ++ _show_wl_role_info(rtwdev, m); ++} ++ ++#define _get_bt_polt_cnt(rtwdev, phy, polt_cnt) do {} while (0) ++ ++enum btc_bt_a2dp_type { ++ BTC_A2DP_LEGACY = 0, ++ BTC_A2DP_TWS_SNIFF = 1, ++ BTC_A2DP_TWS_RELAY = 2, ++}; ++ ++static void _show_bt_profile_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_hfp_desc hfp = bt_linfo->hfp_desc; ++ struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; ++ ++ if (hfp.exist) { ++ seq_printf(m, " %-15s : type:%s, sut_pwr:%d, golden-rx:%d", ++ "[HFP]", (hfp.type == 0 ? "SCO" : "eSCO"), ++ bt_linfo->sut_pwr_level[0], ++ bt_linfo->golden_rx_shift[0]); ++ } ++ ++ if (hid.exist) { ++ seq_printf(m, ++ "\n\r %-15s : type:%s%s%s%s%s pair-cnt:%d, sut_pwr:%d, golden-rx:%d\n", ++ "[HID]", ++ hid.type & BTC_HID_218 ? "2/18," : "", ++ hid.type & BTC_HID_418 ? "4/18," : "", ++ hid.type & BTC_HID_BLE ? "BLE," : "", ++ hid.type & BTC_HID_RCU ? "RCU," : "", ++ hid.type & BTC_HID_RCU_VOICE ? "RCU-Voice," : "", ++ hid.pair_cnt, bt_linfo->sut_pwr_level[1], ++ bt_linfo->golden_rx_shift[1]); ++ } ++ ++ if (a2dp.exist) { ++ seq_printf(m, ++ " %-15s : type:%s, bit-pool:%d, flush-time:%d, ", ++ "[A2DP]", ++ a2dp.type == BTC_A2DP_LEGACY ? "Legacy" : "TWS", ++ a2dp.bitpool, a2dp.flush_time); ++ ++ seq_printf(m, ++ "vid:0x%x, Dev-name:0x%x, sut_pwr:%d, golden-rx:%d\n", ++ a2dp.vendor_id, a2dp.device_name, ++ bt_linfo->sut_pwr_level[2], ++ bt_linfo->golden_rx_shift[2]); ++ } ++ ++ if (pan.exist) { ++ seq_printf(m, " %-15s : sut_pwr:%d, golden-rx:%d\n", ++ "[PAN]", ++ bt_linfo->sut_pwr_level[3], ++ bt_linfo->golden_rx_shift[3]); ++ } ++} ++ ++static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ u8 *afh = bt_linfo->afh_map; ++ u16 polt_cnt = 0; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) ++ return; ++ ++ seq_puts(m, "========== [BT Status] ==========\n"); ++ ++ seq_printf(m, " %-15s : enable:%s, btg:%s%s, connect:%s, ", ++ "[status]", bt->enable.now ? "Y" : "N", ++ bt->btg_type ? "Y" : "N", ++ (bt->enable.now && (bt->btg_type != module->bt_pos) ? ++ "(efuse-mismatch!!)" : ""), ++ (bt_linfo->status.map.connect ? "Y" : "N")); ++ ++ seq_printf(m, "igno_wl:%s, mailbox_avl:%s, rfk_state:0x%x\n", ++ bt->igno_wl ? "Y" : "N", ++ bt->mbx_avl ? "Y" : "N", bt->rfk_info.val); ++ ++ seq_printf(m, " %-15s : profile:%s%s%s%s%s ", ++ "[profile]", ++ (bt_linfo->profile_cnt.now == 0) ? "None," : "", ++ bt_linfo->hfp_desc.exist ? "HFP," : "", ++ bt_linfo->hid_desc.exist ? "HID," : "", ++ bt_linfo->a2dp_desc.exist ? ++ (bt_linfo->a2dp_desc.sink ? "A2DP_sink," : "A2DP,") : "", ++ bt_linfo->pan_desc.exist ? "PAN," : ""); ++ ++ seq_printf(m, ++ "multi-link:%s, role:%s, ble-connect:%s, CQDDR:%s, A2DP_active:%s, PAN_active:%s\n", ++ bt_linfo->multi_link.now ? "Y" : "N", ++ bt_linfo->slave_role ? "Slave" : "Master", ++ bt_linfo->status.map.ble_connect ? "Y" : "N", ++ bt_linfo->cqddr ? "Y" : "N", ++ bt_linfo->a2dp_desc.active ? "Y" : "N", ++ bt_linfo->pan_desc.active ? "Y" : "N"); ++ ++ seq_printf(m, ++ " %-15s : rssi:%ddBm, tx_rate:%dM, %s%s%s", ++ "[link]", bt_linfo->rssi - 100, ++ bt_linfo->tx_3m ? 3 : 2, ++ bt_linfo->status.map.inq_pag ? " inq-page!!" : "", ++ bt_linfo->status.map.acl_busy ? " acl_busy!!" : "", ++ bt_linfo->status.map.mesh_busy ? " mesh_busy!!" : ""); ++ ++ seq_printf(m, ++ "%s afh_map[%02x%02x_%02x%02x_%02x%02x_%02x%02x_%02x%02x], ", ++ bt_linfo->relink.now ? " ReLink!!" : "", ++ afh[0], afh[1], afh[2], afh[3], afh[4], ++ afh[5], afh[6], afh[7], afh[8], afh[9]); ++ ++ seq_printf(m, "wl_ch_map[en:%d/ch:%d/bw:%d]\n", ++ wl->afh_info.en, wl->afh_info.ch, wl->afh_info.bw); ++ ++ seq_printf(m, ++ " %-15s : retry:%d, relink:%d, rate_chg:%d, reinit:%d, reenable:%d, ", ++ "[stat_cnt]", cx->cnt_bt[BTC_BCNT_RETRY], ++ cx->cnt_bt[BTC_BCNT_RELINK], cx->cnt_bt[BTC_BCNT_RATECHG], ++ cx->cnt_bt[BTC_BCNT_REINIT], cx->cnt_bt[BTC_BCNT_REENABLE]); ++ ++ seq_printf(m, ++ "role-switch:%d, afh:%d, inq_page:%d(inq:%d/page:%d), igno_wl:%d\n", ++ cx->cnt_bt[BTC_BCNT_ROLESW], cx->cnt_bt[BTC_BCNT_AFH], ++ cx->cnt_bt[BTC_BCNT_INQPAG], cx->cnt_bt[BTC_BCNT_INQ], ++ cx->cnt_bt[BTC_BCNT_PAGE], cx->cnt_bt[BTC_BCNT_IGNOWL]); ++ ++ _show_bt_profile_info(rtwdev, m); ++ ++ seq_printf(m, ++ " %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)\n", ++ "[bt_info]", bt->raw_info[2], bt->raw_info[3], ++ bt->raw_info[4], bt->raw_info[5], bt->raw_info[6], ++ bt->raw_info[7], ++ bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", ++ cx->cnt_bt[BTC_BCNT_INFOUPDATE], ++ cx->cnt_bt[BTC_BCNT_INFOSAME]); ++ ++ if (wl->status.map.lps || wl->status.map.rf_off) ++ return; ++ ++ chip->ops->btc_update_bt_cnt(rtwdev); ++ _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_FREEZE, 0); ++ _get_bt_polt_cnt(rtwdev, RTW89_PHY_0, &polt_cnt); ++ ++ seq_printf(m, ++ " %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)\n", ++ "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX], cx->cnt_bt[BTC_BCNT_LOPRI_RX], ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX], polt_cnt); ++} ++ ++#define CASE_BTC_RSN_STR(e) case BTC_RSN_ ## e: return #e ++#define CASE_BTC_ACT_STR(e) case BTC_ACT_ ## e | BTC_ACT_EXT_BIT: return #e ++#define CASE_BTC_POLICY_STR(e) \ ++ case BTC_CXP_ ## e | BTC_POLICY_EXT_BIT: return #e ++ ++static const char *steps_to_str(u16 step) ++{ ++ switch (step) { ++ CASE_BTC_RSN_STR(NONE); ++ CASE_BTC_RSN_STR(NTFY_INIT); ++ CASE_BTC_RSN_STR(NTFY_SWBAND); ++ CASE_BTC_RSN_STR(NTFY_WL_STA); ++ CASE_BTC_RSN_STR(NTFY_RADIO_STATE); ++ CASE_BTC_RSN_STR(UPDATE_BT_SCBD); ++ CASE_BTC_RSN_STR(NTFY_WL_RFK); ++ CASE_BTC_RSN_STR(UPDATE_BT_INFO); ++ CASE_BTC_RSN_STR(NTFY_SCAN_START); ++ CASE_BTC_RSN_STR(NTFY_SCAN_FINISH); ++ CASE_BTC_RSN_STR(NTFY_SPECIFIC_PACKET); ++ CASE_BTC_RSN_STR(NTFY_POWEROFF); ++ CASE_BTC_RSN_STR(NTFY_ROLE_INFO); ++ CASE_BTC_RSN_STR(CMD_SET_COEX); ++ CASE_BTC_RSN_STR(ACT1_WORK); ++ CASE_BTC_RSN_STR(BT_DEVINFO_WORK); ++ CASE_BTC_RSN_STR(RFK_CHK_WORK); ++ ++ CASE_BTC_ACT_STR(NONE); ++ CASE_BTC_ACT_STR(WL_ONLY); ++ CASE_BTC_ACT_STR(WL_5G); ++ CASE_BTC_ACT_STR(WL_OTHER); ++ CASE_BTC_ACT_STR(WL_IDLE); ++ CASE_BTC_ACT_STR(WL_NC); ++ CASE_BTC_ACT_STR(WL_RFK); ++ CASE_BTC_ACT_STR(WL_INIT); ++ CASE_BTC_ACT_STR(WL_OFF); ++ CASE_BTC_ACT_STR(FREERUN); ++ CASE_BTC_ACT_STR(BT_WHQL); ++ CASE_BTC_ACT_STR(BT_RFK); ++ CASE_BTC_ACT_STR(BT_OFF); ++ CASE_BTC_ACT_STR(BT_IDLE); ++ CASE_BTC_ACT_STR(BT_HFP); ++ CASE_BTC_ACT_STR(BT_HID); ++ CASE_BTC_ACT_STR(BT_A2DP); ++ CASE_BTC_ACT_STR(BT_A2DPSINK); ++ CASE_BTC_ACT_STR(BT_PAN); ++ CASE_BTC_ACT_STR(BT_A2DP_HID); ++ CASE_BTC_ACT_STR(BT_A2DP_PAN); ++ CASE_BTC_ACT_STR(BT_PAN_HID); ++ CASE_BTC_ACT_STR(BT_A2DP_PAN_HID); ++ CASE_BTC_ACT_STR(WL_25G_MCC); ++ CASE_BTC_ACT_STR(WL_2G_MCC); ++ CASE_BTC_ACT_STR(WL_2G_SCC); ++ CASE_BTC_ACT_STR(WL_2G_AP); ++ CASE_BTC_ACT_STR(WL_2G_GO); ++ CASE_BTC_ACT_STR(WL_2G_GC); ++ CASE_BTC_ACT_STR(WL_2G_NAN); ++ ++ CASE_BTC_POLICY_STR(OFF_BT); ++ CASE_BTC_POLICY_STR(OFF_WL); ++ CASE_BTC_POLICY_STR(OFF_EQ0); ++ CASE_BTC_POLICY_STR(OFF_EQ1); ++ CASE_BTC_POLICY_STR(OFF_EQ2); ++ CASE_BTC_POLICY_STR(OFF_EQ3); ++ CASE_BTC_POLICY_STR(OFF_BWB0); ++ CASE_BTC_POLICY_STR(OFF_BWB1); ++ CASE_BTC_POLICY_STR(OFFB_BWB0); ++ CASE_BTC_POLICY_STR(OFFE_DEF); ++ CASE_BTC_POLICY_STR(OFFE_DEF2); ++ CASE_BTC_POLICY_STR(FIX_TD3030); ++ CASE_BTC_POLICY_STR(FIX_TD5050); ++ CASE_BTC_POLICY_STR(FIX_TD2030); ++ CASE_BTC_POLICY_STR(FIX_TD4010); ++ CASE_BTC_POLICY_STR(FIX_TD7010); ++ CASE_BTC_POLICY_STR(FIX_TD2060); ++ CASE_BTC_POLICY_STR(FIX_TD3060); ++ CASE_BTC_POLICY_STR(FIX_TD2080); ++ CASE_BTC_POLICY_STR(FIX_TDW1B1); ++ CASE_BTC_POLICY_STR(FIX_TD4020); ++ CASE_BTC_POLICY_STR(PFIX_TD3030); ++ CASE_BTC_POLICY_STR(PFIX_TD5050); ++ CASE_BTC_POLICY_STR(PFIX_TD2030); ++ CASE_BTC_POLICY_STR(PFIX_TD2060); ++ CASE_BTC_POLICY_STR(PFIX_TD3070); ++ CASE_BTC_POLICY_STR(PFIX_TD2080); ++ CASE_BTC_POLICY_STR(PFIX_TDW1B1); ++ CASE_BTC_POLICY_STR(AUTO_TD50200); ++ CASE_BTC_POLICY_STR(AUTO_TD60200); ++ CASE_BTC_POLICY_STR(AUTO_TD20200); ++ CASE_BTC_POLICY_STR(AUTO_TDW1B1); ++ CASE_BTC_POLICY_STR(PAUTO_TD50200); ++ CASE_BTC_POLICY_STR(PAUTO_TD60200); ++ CASE_BTC_POLICY_STR(PAUTO_TD20200); ++ CASE_BTC_POLICY_STR(PAUTO_TDW1B1); ++ CASE_BTC_POLICY_STR(AUTO2_TD3050); ++ CASE_BTC_POLICY_STR(AUTO2_TD3070); ++ CASE_BTC_POLICY_STR(AUTO2_TD5050); ++ CASE_BTC_POLICY_STR(AUTO2_TD6060); ++ CASE_BTC_POLICY_STR(AUTO2_TD2080); ++ CASE_BTC_POLICY_STR(AUTO2_TDW1B4); ++ CASE_BTC_POLICY_STR(PAUTO2_TD3050); ++ CASE_BTC_POLICY_STR(PAUTO2_TD3070); ++ CASE_BTC_POLICY_STR(PAUTO2_TD5050); ++ CASE_BTC_POLICY_STR(PAUTO2_TD6060); ++ CASE_BTC_POLICY_STR(PAUTO2_TD2080); ++ CASE_BTC_POLICY_STR(PAUTO2_TDW1B4); ++ default: ++ return "unknown step"; ++ } ++} ++ ++static ++void seq_print_segment(struct seq_file *m, const char *prefix, u16 *data, ++ u8 len, u8 seg_len, u8 start_idx, u8 ring_len) ++{ ++ u8 i; ++ u8 cur_index; ++ ++ for (i = 0; i < len ; i++) { ++ if ((i % seg_len) == 0) ++ seq_printf(m, " %-15s : ", prefix); ++ cur_index = (start_idx + i) % ring_len; ++ if (i % 3 == 0) ++ seq_printf(m, "-> %-20s", ++ steps_to_str(*(data + cur_index))); ++ else if (i % 3 == 1) ++ seq_printf(m, "-> %-15s", ++ steps_to_str(*(data + cur_index))); ++ else ++ seq_printf(m, "-> %-13s", ++ steps_to_str(*(data + cur_index))); ++ if (i == (len - 1) || (i % seg_len) == (seg_len - 1)) ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_dm_step(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ u8 start_idx; ++ u8 len; ++ ++ len = dm->dm_step.step_ov ? RTW89_BTC_DM_MAXSTEP : dm->dm_step.step_pos; ++ start_idx = dm->dm_step.step_ov ? dm->dm_step.step_pos : 0; ++ ++ seq_print_segment(m, "[dm_steps]", dm->dm_step.step, len, 6, start_idx, ++ ARRAY_SIZE(dm->dm_step.step)); ++} ++ ++static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_DM)) ++ return; ++ ++ seq_printf(m, "========== [Mechanism Status %s] ==========\n", ++ (btc->ctrl.manual ? "(Manual)" : "(Auto)")); ++ ++ seq_printf(m, ++ " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%ld, run_cnt:%d\n", ++ "[status]", ++ module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated", ++ steps_to_str(dm->run_reason), ++ steps_to_str(dm->run_action | BTC_ACT_EXT_BIT), ++ FIELD_GET(GENMASK(7, 0), dm->set_ant_path), ++ dm->cnt_dm[BTC_DCNT_RUN]); ++ ++ _show_dm_step(rtwdev, m); ++ ++ seq_printf(m, " %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, wl_mimo_ps:%d, ", ++ "[dm_flag]", dm->wl_only, dm->bt_only, btc->ctrl.igno_bt, ++ dm->freerun, btc->lps, dm->wl_mimo_ps); ++ ++ seq_printf(m, "leak_ap:%d, fw_offload:%s%s\n", dm->leak_ap, ++ (BTC_CX_FW_OFFLOAD ? "Y" : "N"), ++ (dm->wl_fw_cx_offload == BTC_CX_FW_OFFLOAD ? ++ "" : "(Mis-Match!!)")); ++ ++ if (dm->rf_trx_para.wl_tx_power == 0xff) ++ seq_printf(m, ++ " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:orig, ", ++ "[trx_ctrl]", wl->rssi_level, dm->trx_para_level); ++ ++ else ++ seq_printf(m, ++ " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:%d, ", ++ "[trx_ctrl]", wl->rssi_level, dm->trx_para_level, ++ dm->rf_trx_para.wl_tx_power); ++ ++ seq_printf(m, ++ "wl_rx_lvl:%d, bt_tx_pwr_dec:%d, bt_rx_lna:%d(%s-tbl), wl_btg_rx:%d\n", ++ dm->rf_trx_para.wl_rx_gain, dm->rf_trx_para.bt_tx_power, ++ dm->rf_trx_para.bt_rx_gain, ++ (bt->hi_lna_rx ? "Hi" : "Ori"), dm->wl_btg_rx); ++ ++ seq_printf(m, ++ " %-15s : wl_tx_limit[en:%d/max_t:%dus/max_retry:%d], bt_slot_reg:%d-TU\n", ++ "[dm_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time, ++ dm->wl_tx_limit.tx_retry, btc->bt_req_len); ++} ++ ++static void _show_error(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_fbtc_cysta *pcysta = NULL; ++ ++ pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; ++ ++ if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW] == 0 && ++ pcysta->except_cnt == 0 && ++ !pfwinfo->len_mismch && !pfwinfo->fver_mismch) ++ return; ++ ++ seq_printf(m, " %-15s : ", "[error]"); ++ ++ if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]) { ++ seq_printf(m, ++ "overflow-cnt: %d, ", ++ pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]); ++ } ++ ++ if (pfwinfo->len_mismch) { ++ seq_printf(m, ++ "len-mismatch: 0x%x, ", ++ pfwinfo->len_mismch); ++ } ++ ++ if (pfwinfo->fver_mismch) { ++ seq_printf(m, ++ "fver-mismatch: 0x%x, ", ++ pfwinfo->fver_mismch); ++ } ++ ++ /* cycle statistics exceptions */ ++ if (pcysta->exception || pcysta->except_cnt) { ++ seq_printf(m, ++ "exception-type: 0x%x, exception-cnt = %d", ++ pcysta->exception, pcysta->except_cnt); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_tdma(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_tdma *t = NULL; ++ struct rtw89_btc_fbtc_slot *s = NULL; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ u8 i, cnt = 0; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ t = &pfwinfo->rpt_fbtc_tdma.finfo; ++ ++ seq_printf(m, ++ " %-15s : ", "[tdma_policy]"); ++ seq_printf(m, ++ "type:%d, rx_flow_ctrl:%d, tx_pause:%d, ", ++ (u32)t->type, ++ t->rxflctrl, t->txpause); ++ ++ seq_printf(m, ++ "wl_toggle_n:%d, leak_n:%d, ext_ctrl:%d, ", ++ t->wtgle_n, t->leak_n, t->ext_ctrl); ++ ++ seq_printf(m, ++ "policy_type:%d", ++ (u32)btc->policy_type); ++ ++ s = pfwinfo->rpt_fbtc_slots.finfo.slot; ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (dm->update_slot_map == BIT(CXST_MAX) - 1) ++ break; ++ ++ if (!(dm->update_slot_map & BIT(i))) ++ continue; ++ ++ if (cnt % 6 == 0) ++ seq_printf(m, ++ " %-15s : %d[%d/0x%x/%d]", ++ "[slot_policy]", ++ (u32)i, ++ s[i].dur, s[i].cxtbl, s[i].cxtype); ++ else ++ seq_printf(m, ++ ", %d[%d/0x%x/%d]", ++ (u32)i, ++ s[i].dur, s[i].cxtbl, s[i].cxtype); ++ if (cnt % 6 == 5) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_slots(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_slots *pslots = NULL; ++ struct rtw89_btc_fbtc_slot s; ++ u8 i = 0; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pslots = &pfwinfo->rpt_fbtc_slots.finfo; ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ s = pslots->slot[i]; ++ if (i % 6 == 0) ++ seq_printf(m, ++ " %-15s : %02d[%03d/0x%x/%d]", ++ "[slot_list]", ++ (u32)i, ++ s.dur, s.cxtbl, s.cxtype); ++ else ++ seq_printf(m, ++ ", %02d[%03d/0x%x/%d]", ++ (u32)i, ++ s.dur, s.cxtbl, s.cxtype); ++ if (i % 6 == 5) ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_fbtc_cysta(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_cysta *pcysta_le32 = NULL; ++ struct rtw89_btc_fbtc_cysta_cpu pcysta[1]; ++ union rtw89_btc_fbtc_rxflct r; ++ u8 i, cnt = 0, slot_pair; ++ u16 cycle, c_begin, c_end, store_index; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo; ++ rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta); ++ seq_printf(m, ++ " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", ++ "[cycle_cnt]", pcysta->cycles, pcysta->bcn_cnt[CXBCN_ALL], ++ pcysta->bcn_cnt[CXBCN_ALL_OK], ++ pcysta->bcn_cnt[CXBCN_BT_SLOT], ++ pcysta->bcn_cnt[CXBCN_BT_OK]); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles); ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (!pcysta->slot_cnt[i]) ++ continue; ++ seq_printf(m, ++ ", %d:%d", (u32)i, pcysta->slot_cnt[i]); ++ } ++ ++ if (dm->tdma_now.rxflctrl) { ++ seq_printf(m, ++ ", leak_rx:%d", pcysta->leakrx_cnt); ++ } ++ ++ if (pcysta->collision_cnt) { ++ seq_printf(m, ++ ", collision:%d", pcysta->collision_cnt); ++ } ++ ++ if (pcysta->skip_cnt) { ++ seq_printf(m, ++ ", skip:%d", pcysta->skip_cnt); ++ } ++ seq_puts(m, "\n"); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); ++ _chk_btc_err(rtwdev, BTC_DCNT_B1_FREEZE, pcysta->slot_cnt[CXST_B1]); ++ ++ seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", ++ "[cycle_time]", ++ pcysta->tavg_cycle[CXT_WL], ++ pcysta->tavg_cycle[CXT_BT], ++ pcysta->tavg_lk / 1000, pcysta->tavg_lk % 1000); ++ seq_printf(m, ++ ", max_t[wl:%d/bt:%d/lk:%d.%03d]", ++ pcysta->tmax_cycle[CXT_WL], ++ pcysta->tmax_cycle[CXT_BT], ++ pcysta->tmax_lk / 1000, pcysta->tmax_lk % 1000); ++ seq_printf(m, ++ ", maxdiff_t[wl:%d/bt:%d]\n", ++ pcysta->tmaxdiff_cycle[CXT_WL], ++ pcysta->tmaxdiff_cycle[CXT_BT]); ++ ++ if (pcysta->cycles == 0) ++ return; ++ ++ /* 1 cycle record 1 wl-slot and 1 bt-slot */ ++ slot_pair = BTC_CYCLE_SLOT_MAX / 2; ++ ++ if (pcysta->cycles <= slot_pair) ++ c_begin = 1; ++ else ++ c_begin = pcysta->cycles - slot_pair + 1; ++ ++ c_end = pcysta->cycles; ++ ++ for (cycle = c_begin; cycle <= c_end; cycle++) { ++ cnt++; ++ store_index = ((cycle - 1) % slot_pair) * 2; ++ ++ if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 1) ++ seq_printf(m, ++ " %-15s : ->b%02d->w%02d", "[cycle_step]", ++ pcysta->tslot_cycle[store_index], ++ pcysta->tslot_cycle[store_index + 1]); ++ else ++ seq_printf(m, ++ "->b%02d->w%02d", ++ pcysta->tslot_cycle[store_index], ++ pcysta->tslot_cycle[store_index + 1]); ++ if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 0 || cnt == c_end) ++ seq_puts(m, "\n"); ++ } ++ ++ if (a2dp->exist) { ++ seq_printf(m, ++ " %-15s : a2dp_ept:%d, a2dp_late:%d", ++ "[a2dp_t_sta]", ++ pcysta->a2dpept, pcysta->a2dpeptto); ++ ++ seq_printf(m, ++ ", avg_t:%d, max_t:%d", ++ pcysta->tavg_a2dpept, pcysta->tmax_a2dpept); ++ r.val = dm->tdma_now.rxflctrl; ++ ++ if (r.type && r.tgln_n) { ++ seq_printf(m, ++ ", cycle[PSTDMA:%d/TDMA:%d], ", ++ pcysta->cycles_a2dp[CXT_FLCTRL_ON], ++ pcysta->cycles_a2dp[CXT_FLCTRL_OFF]); ++ ++ seq_printf(m, ++ "avg_t[PSTDMA:%d/TDMA:%d], ", ++ pcysta->tavg_a2dp[CXT_FLCTRL_ON], ++ pcysta->tavg_a2dp[CXT_FLCTRL_OFF]); ++ ++ seq_printf(m, ++ "max_t[PSTDMA:%d/TDMA:%d]", ++ pcysta->tmax_a2dp[CXT_FLCTRL_ON], ++ pcysta->tmax_a2dp[CXT_FLCTRL_OFF]); ++ } ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_fbtc_nullsta(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_cynullsta *ns = NULL; ++ u8 i = 0; ++ ++ if (!btc->dm.tdma_now.rxflctrl) ++ return; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ ns = &pfwinfo->rpt_fbtc_nullsta.finfo; ++ ++ seq_printf(m, " %-15s : ", "[null_sta]"); ++ ++ for (i = 0; i < 2; i++) { ++ if (i != 0) ++ seq_printf(m, ", null-%d", i); ++ else ++ seq_printf(m, "null-%d", i); ++ seq_printf(m, "[ok:%d/", le32_to_cpu(ns->result[i][1])); ++ seq_printf(m, "fail:%d/", le32_to_cpu(ns->result[i][0])); ++ seq_printf(m, "on_time:%d/", le32_to_cpu(ns->result[i][2])); ++ seq_printf(m, "retry:%d/", le32_to_cpu(ns->result[i][3])); ++ seq_printf(m, "avg_t:%d.%03d/", ++ le32_to_cpu(ns->avg_t[i]) / 1000, ++ le32_to_cpu(ns->avg_t[i]) % 1000); ++ seq_printf(m, "max_t:%d.%03d]", ++ le32_to_cpu(ns->max_t[i]) / 1000, ++ le32_to_cpu(ns->max_t[i]) % 1000); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_step(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_steps *pstep = NULL; ++ u8 type, val, cnt = 0, state = 0; ++ bool outloop = false; ++ u16 i, diff_t, n_start = 0, n_stop = 0; ++ u16 pos_old, pos_new; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pstep = &pfwinfo->rpt_fbtc_step.finfo; ++ pos_old = le16_to_cpu(pstep->pos_old); ++ pos_new = le16_to_cpu(pstep->pos_new); ++ ++ if (pcinfo->req_fver != pstep->fver) ++ return; ++ ++ /* store step info by using ring instead of FIFO*/ ++ do { ++ switch (state) { ++ case 0: ++ n_start = pos_old; ++ if (pos_new >= pos_old) ++ n_stop = pos_new; ++ else ++ n_stop = btc->ctrl.trace_step - 1; ++ ++ state = 1; ++ break; ++ case 1: ++ for (i = n_start; i <= n_stop; i++) { ++ type = pstep->step[i].type; ++ val = pstep->step[i].val; ++ diff_t = le16_to_cpu(pstep->step[i].difft); ++ ++ if (type == CXSTEP_NONE || type >= CXSTEP_MAX) ++ continue; ++ ++ if (cnt % 10 == 0) ++ seq_printf(m, " %-15s : ", "[steps]"); ++ ++ seq_printf(m, "-> %s(%02d)(%02d)", ++ (type == CXSTEP_SLOT ? "SLT" : ++ "EVT"), (u32)val, diff_t); ++ if (cnt % 10 == 9) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ ++ state = 2; ++ break; ++ case 2: ++ if (pos_new < pos_old && n_start != 0) { ++ n_start = 0; ++ n_stop = pos_new; ++ state = 1; ++ } else { ++ outloop = true; ++ } ++ break; ++ } ++ } while (!outloop); ++} ++ ++static void _show_fw_dm_msg(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM)) ++ return; ++ ++ _show_error(rtwdev, m); ++ _show_fbtc_tdma(rtwdev, m); ++ _show_fbtc_slots(rtwdev, m); ++ _show_fbtc_cysta(rtwdev, m); ++ _show_fbtc_nullsta(rtwdev, m); ++ _show_fbtc_step(rtwdev, m); ++} ++ ++static void _show_mreg(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_mreg_val *pmreg = NULL; ++ struct rtw89_btc_fbtc_gpio_dbg *gdbg = NULL; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_mac_ax_gnt gnt[2] = {0}; ++ u8 i = 0, type = 0, cnt = 0; ++ u32 val, offset; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG)) ++ return; ++ ++ seq_puts(m, "========== [HW Status] ==========\n"); ++ ++ seq_printf(m, ++ " %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)\n", ++ "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], ++ bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], ++ cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); ++ ++ /* To avoid I/O if WL LPS or power-off */ ++ if (!wl->status.map.lps && !wl->status.map.rf_off) { ++ rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); ++ if (val & (B_AX_GNT_BT_RFC_S0_SW_VAL | ++ B_AX_GNT_BT_BB_S0_SW_VAL)) ++ gnt[0].gnt_bt = true; ++ if (val & (B_AX_GNT_BT_RFC_S0_SW_CTRL | ++ B_AX_GNT_BT_BB_S0_SW_CTRL)) ++ gnt[0].gnt_bt_sw_en = true; ++ if (val & (B_AX_GNT_WL_RFC_S0_SW_VAL | ++ B_AX_GNT_WL_BB_S0_SW_VAL)) ++ gnt[0].gnt_wl = true; ++ if (val & (B_AX_GNT_WL_RFC_S0_SW_CTRL | ++ B_AX_GNT_WL_BB_S0_SW_CTRL)) ++ gnt[0].gnt_wl_sw_en = true; ++ ++ if (val & (B_AX_GNT_BT_RFC_S1_SW_VAL | ++ B_AX_GNT_BT_BB_S1_SW_VAL)) ++ gnt[1].gnt_bt = true; ++ if (val & (B_AX_GNT_BT_RFC_S1_SW_CTRL | ++ B_AX_GNT_BT_BB_S1_SW_CTRL)) ++ gnt[1].gnt_bt_sw_en = true; ++ if (val & (B_AX_GNT_WL_RFC_S1_SW_VAL | ++ B_AX_GNT_WL_BB_S1_SW_VAL)) ++ gnt[1].gnt_wl = true; ++ if (val & (B_AX_GNT_WL_RFC_S1_SW_CTRL | ++ B_AX_GNT_WL_BB_S1_SW_CTRL)) ++ gnt[1].gnt_wl_sw_en = true; ++ ++ seq_printf(m, ++ " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", ++ "[gnt_status]", ++ (rtw89_mac_get_ctrl_path(rtwdev) ? "WL" : "BT"), ++ (gnt[0].gnt_wl_sw_en ? "SW" : "HW"), gnt[0].gnt_wl, ++ (gnt[0].gnt_bt_sw_en ? "SW" : "HW"), gnt[0].gnt_bt); ++ ++ seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", ++ (gnt[1].gnt_wl_sw_en ? "SW" : "HW"), gnt[1].gnt_wl, ++ (gnt[1].gnt_bt_sw_en ? "SW" : "HW"), gnt[1].gnt_bt); ++ } ++ ++ pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; ++ if (!pcinfo->valid) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): stop due rpt_fbtc_mregval.cinfo\n", ++ __func__); ++ return; ++ } ++ ++ pmreg = &pfwinfo->rpt_fbtc_mregval.finfo; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_fbtc_mregval reg_num = %d\n", ++ __func__, pmreg->reg_num); ++ ++ for (i = 0; i < pmreg->reg_num; i++) { ++ type = (u8)le16_to_cpu(chip->mon_reg[i].type); ++ offset = le32_to_cpu(chip->mon_reg[i].offset); ++ val = le32_to_cpu(pmreg->mreg_val[i]); ++ ++ if (cnt % 6 == 0) ++ seq_printf(m, " %-15s : %d_0x%04x=0x%08x", ++ "[reg]", (u32)type, offset, val); ++ else ++ seq_printf(m, ", %d_0x%04x=0x%08x", (u32)type, ++ offset, val); ++ if (cnt % 6 == 5) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ ++ pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; ++ if (!pcinfo->valid) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): stop due rpt_fbtc_gpio_dbg.cinfo\n", ++ __func__); ++ return; ++ } ++ ++ gdbg = &pfwinfo->rpt_fbtc_gpio_dbg.finfo; ++ if (!gdbg->en_map) ++ return; ++ ++ seq_printf(m, " %-15s : enable_map:0x%08x", ++ "[gpio_dbg]", gdbg->en_map); ++ ++ for (i = 0; i < BTC_DBG_MAX1; i++) { ++ if (!(gdbg->en_map & BIT(i))) ++ continue; ++ seq_printf(m, ", %d->GPIO%d", (u32)i, gdbg->gpio_map[i]); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_summary(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_rpt_ctrl *prptctrl = NULL; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; ++ u8 i; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) ++ return; ++ ++ seq_puts(m, "========== [Statistics] ==========\n"); ++ ++ pcinfo = &pfwinfo->rpt_ctrl.cinfo; ++ if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { ++ prptctrl = &pfwinfo->rpt_ctrl.finfo; ++ ++ seq_printf(m, ++ " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d), ", ++ "[summary]", pfwinfo->cnt_h2c, ++ pfwinfo->cnt_h2c_fail, prptctrl->h2c_cnt, ++ pfwinfo->cnt_c2h, prptctrl->c2h_cnt); ++ ++ seq_printf(m, ++ "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x, dm_error_map:0x%x", ++ pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_cnt, ++ prptctrl->rpt_enable, dm->error.val); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_RPT_FREEZE, ++ pfwinfo->event[BTF_EVNT_RPT]); ++ ++ if (dm->error.map.wl_fw_hang) ++ seq_puts(m, " (WL FW Hang!!)"); ++ seq_puts(m, "\n"); ++ seq_printf(m, ++ " %-15s : send_ok:%d, send_fail:%d, recv:%d", ++ "[mailbox]", prptctrl->mb_send_ok_cnt, ++ prptctrl->mb_send_fail_cnt, prptctrl->mb_recv_cnt); ++ ++ seq_printf(m, ++ "(A2DP_empty:%d, A2DP_flowstop:%d, A2DP_full:%d)\n", ++ prptctrl->mb_a2dp_empty_cnt, ++ prptctrl->mb_a2dp_flct_cnt, ++ prptctrl->mb_a2dp_full_cnt); ++ ++ seq_printf(m, ++ " %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]", ++ "[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ], ++ cx->cnt_wl[BTC_WCNT_RFK_GO], ++ cx->cnt_wl[BTC_WCNT_RFK_REJECT], ++ cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); ++ ++ seq_printf(m, ++ ", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]\n", ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REQ], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_GO], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REJECT], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_FAIL]); ++ ++ if (prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT] > 0) ++ bt->rfk_info.map.timeout = 1; ++ else ++ bt->rfk_info.map.timeout = 0; ++ ++ dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout; ++ } else { ++ seq_printf(m, ++ " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d, rpt_cnt=%d, rpt_map=0x%x", ++ "[summary]", pfwinfo->cnt_h2c, ++ pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h, ++ pfwinfo->event[BTF_EVNT_RPT], ++ btc->fwinfo.rpt_en_map); ++ seq_puts(m, " (WL FW report invalid!!)\n"); ++ } ++ ++ for (i = 0; i < BTC_NCNT_NUM; i++) ++ cnt_sum += dm->cnt_notify[i]; ++ ++ seq_printf(m, ++ " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", ++ "[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], ++ cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); ++ ++ seq_printf(m, ++ "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d\n", ++ cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], ++ cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], ++ cnt[BTC_NCNT_WL_STA]); ++ ++ seq_printf(m, ++ " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", ++ "[notify_cnt]", cnt[BTC_NCNT_SCAN_START], ++ cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND], ++ cnt[BTC_NCNT_SPECIAL_PACKET]); ++ ++ seq_printf(m, ++ "timer=%d, control=%d, customerize=%d\n", ++ cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], ++ cnt[BTC_NCNT_CUSTOMERIZE]); ++} ++ ++void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_fw_suit *fw_suit = &rtwdev->fw.normal; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ seq_puts(m, "=========================================\n"); ++ seq_printf(m, "WL FW / BT FW %d.%d.%d.%d / NA\n", ++ fw_suit->major_ver, fw_suit->minor_ver, ++ fw_suit->sub_ver, fw_suit->sub_idex); ++ seq_printf(m, "manual %d\n", btc->ctrl.manual); ++ ++ seq_puts(m, "=========================================\n"); ++ ++ seq_printf(m, "\n\r %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)", ++ "[bt_info]", ++ bt->raw_info[2], bt->raw_info[3], ++ bt->raw_info[4], bt->raw_info[5], ++ bt->raw_info[6], bt->raw_info[7], ++ bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", ++ cx->cnt_bt[BTC_BCNT_INFOUPDATE], ++ cx->cnt_bt[BTC_BCNT_INFOSAME]); ++ ++ seq_puts(m, "\n=========================================\n"); ++ ++ _show_cx_info(rtwdev, m); ++ _show_wl_info(rtwdev, m); ++ _show_bt_info(rtwdev, m); ++ _show_dm_info(rtwdev, m); ++ _show_fw_dm_msg(rtwdev, m); ++ _show_mreg(rtwdev, m); ++ _show_summary(rtwdev, m); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/coex.h b/drivers/net/wireless/realtek/rtw89/coex.h +new file mode 100644 +index 000000000000..f180db24af77 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/coex.h +@@ -0,0 +1,179 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_COEX_H__ ++#define __RTW89_COEX_H__ ++ ++#include "core.h" ++ ++enum btc_mode { ++ BTC_MODE_NORMAL, ++ BTC_MODE_WL, ++ BTC_MODE_BT, ++ BTC_MODE_WLOFF, ++ BTC_MODE_MAX ++}; ++ ++enum btc_wl_rfk_type { ++ BTC_WRFKT_IQK = 0, ++ BTC_WRFKT_LCK = 1, ++ BTC_WRFKT_DPK = 2, ++ BTC_WRFKT_TXGAPK = 3, ++ BTC_WRFKT_DACK = 4, ++ BTC_WRFKT_RXDCK = 5, ++ BTC_WRFKT_TSSI = 6, ++}; ++ ++#define NM_EXEC false ++#define FC_EXEC true ++ ++#define RTW89_COEX_ACT1_WORK_PERIOD round_jiffies_relative(HZ * 4) ++#define RTW89_COEX_BT_DEVINFO_WORK_PERIOD round_jiffies_relative(HZ * 16) ++#define RTW89_COEX_RFK_CHK_WORK_PERIOD round_jiffies_relative(HZ * 0.3) ++#define BTC_RFK_PATH_MAP GENMASK(3, 0) ++#define BTC_RFK_PHY_MAP GENMASK(5, 4) ++#define BTC_RFK_BAND_MAP GENMASK(7, 6) ++ ++enum btc_wl_rfk_state { ++ BTC_WRFK_STOP = 0, ++ BTC_WRFK_START = 1, ++ BTC_WRFK_ONESHOT_START = 2, ++ BTC_WRFK_ONESHOT_STOP = 3, ++}; ++ ++enum btc_pri { ++ BTC_PRI_MASK_RX_RESP = 0, ++ BTC_PRI_MASK_TX_RESP, ++ BTC_PRI_MASK_BEACON, ++ BTC_PRI_MASK_RX_CCK, ++ BTC_PRI_MASK_TX_MNGQ, ++ BTC_PRI_MASK_MAX, ++}; ++ ++enum btc_bt_trs { ++ BTC_BT_SS_GROUP = 0x0, ++ BTC_BT_TX_GROUP = 0x2, ++ BTC_BT_RX_GROUP = 0x3, ++ BTC_BT_MAX_GROUP, ++}; ++ ++enum btc_rssi_st { ++ BTC_RSSI_ST_LOW = 0x0, ++ BTC_RSSI_ST_HIGH, ++ BTC_RSSI_ST_STAY_LOW, ++ BTC_RSSI_ST_STAY_HIGH, ++ BTC_RSSI_ST_MAX ++}; ++ ++#define BTC_RSSI_HIGH(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_HIGH || \ ++ __rssi == BTC_RSSI_ST_STAY_HIGH) ? 1 : 0); }) ++ ++#define BTC_RSSI_LOW(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_LOW || \ ++ __rssi == BTC_RSSI_ST_STAY_LOW) ? 1 : 0); }) ++ ++#define BTC_RSSI_CHANGE(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_LOW || \ ++ __rssi == BTC_RSSI_ST_HIGH) ? 1 : 0); }) ++ ++enum btc_ant { ++ BTC_ANT_SHARED = 0, ++ BTC_ANT_DEDICATED, ++ BTC_ANTTYPE_MAX ++}; ++ ++enum btc_bt_btg { ++ BTC_BT_ALONE = 0, ++ BTC_BT_BTG ++}; ++ ++enum btc_switch { ++ BTC_SWITCH_INTERNAL = 0, ++ BTC_SWITCH_EXTERNAL ++}; ++ ++enum btc_pkt_type { ++ PACKET_DHCP, ++ PACKET_ARP, ++ PACKET_EAPOL, ++ PACKET_EAPOL_END, ++ PACKET_MAX ++}; ++ ++enum btc_bt_mailbox_id { ++ BTC_BTINFO_REPLY = 0x23, ++ BTC_BTINFO_AUTO = 0x27 ++}; ++ ++enum btc_role_state { ++ BTC_ROLE_START, ++ BTC_ROLE_STOP, ++ BTC_ROLE_CHG_TYPE, ++ BTC_ROLE_MSTS_STA_CONN_START, ++ BTC_ROLE_MSTS_STA_CONN_END, ++ BTC_ROLE_MSTS_STA_DIS_CONN, ++ BTC_ROLE_MSTS_AP_START, ++ BTC_ROLE_MSTS_AP_STOP, ++ BTC_ROLE_STATE_UNKNOWN ++}; ++ ++enum btc_rfctrl { ++ BTC_RFCTRL_WL_OFF, ++ BTC_RFCTRL_WL_ON, ++ BTC_RFCTRL_FW_CTRL, ++ BTC_RFCTRL_MAX ++}; ++ ++void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev); ++void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev); ++void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode); ++void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band); ++void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx); ++void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band); ++void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev, ++ enum btc_pkt_type pkt_type); ++void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ struct rtw89_sta *rtwsta, enum btc_role_state state); ++void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state); ++void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state); ++void rtw89_btc_ntfy_wl_sta_work(struct work_struct *work); ++void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m); ++void rtw89_coex_act1_work(struct work_struct *work); ++void rtw89_coex_bt_devinfo_work(struct work_struct *work); ++void rtw89_coex_rfk_chk_work(struct work_struct *work); ++void rtw89_coex_power_on(struct rtw89_dev *rtwdev); ++ ++static inline u8 rtw89_btc_phymap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ enum rtw89_rf_path_bit paths) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 phy_map; ++ ++ phy_map = FIELD_PREP(BTC_RFK_PATH_MAP, paths) | ++ FIELD_PREP(BTC_RFK_PHY_MAP, BIT(phy_idx)) | ++ FIELD_PREP(BTC_RFK_BAND_MAP, hal->current_band_type); ++ ++ return phy_map; ++} ++ ++static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ enum rtw89_rf_path path) ++{ ++ return rtw89_btc_phymap(rtwdev, phy_idx, BIT(path)); ++} ++ ++#endif + +From patchwork Fri Aug 20 04:35:17 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448365 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 4F44DC432BE + for ; + Fri, 20 Aug 2021 04:36:48 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 1C76860EB5 + for ; + Fri, 20 Aug 2021 04:36:48 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S232732AbhHTEhY (ORCPT + ); + Fri, 20 Aug 2021 00:37:24 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39215 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233148AbhHTEhX (ORCPT + ); + Fri, 20 Aug 2021 00:37:23 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4aeIS3003756, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4aeIS3003756 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:41 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:40 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:39 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 03/24] rtw89: add core and trx files +Date: Fri, 20 Aug 2021 12:35:17 +0800 +Message-ID: <20210820043538.12424-4-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_all_Bitcoin, bb} +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Implement main flows that contains register/unregister mac80211 hw with +hardware capability, power on/off sequence, STA state actions, and +TX/RX path. + +The chip info is read from efuse while probing PCI, and then it can be +used to induce supported channel, band, bitrate, ht/vht/he capability, +and etc. Then, we register hardware with these capabilities. + +When network interface is up, driver does power-on sequence to enable MAC, +BB and RF function blocks. Oppositely, do power-off sequence when +interface is going to down. + +To maintain STA state, five callbacks are implemented -- add, assoc, +disassoc, disconnect and remove. In which state, driver tells firmware STA +info via H2C. + +TX flow: +When a SKB is going to be transmitted, we must know its type first. If +the type is mgmt or fwcmd made by driver, SKB is queued into corresponding +DMA channel and PCI ring. The other type is data frame that is more +complex, because it needs to establish BA session to have better throughput +with AMPDU and AMSDU. +In order to have better PCI DMA efficiency, we don't kick off DMA every +SKB. With wake TX queue, kick off DMA after a bunch of SKBs are written. +To achieve this, we have two HCI ops -- tx_write and tx_kick_off. + +BA establishment work: +For data frames, we start to establish BA session if the STA is associated +with APMDU capability and the TID session isn't established, and then the +BA work is used to ask mac80211 to start AMPDU actions. Driver implements +AMPDU action callbacks to know the session is established, so that we can +set AGG_EN bit in TX descriptor to enable AMPDU. + +RX flow: +When a RX SKB is delivered from PCI, rtw89_core_rx() process it depneds on +its type -- WIFI, C2H or PPDU. If type is C2H, it's queued into a C2H +queue, and wake a work to handle the C2H packet. If type is WIFI, it's a +normal RX packet. When mgmt or data frame is received, it is queued +into pending RX SKB queue to wait for corresponding PPDU packet (another +RX packet with PPDU type) to fill its rx_status, like RSSI. And, then +indicate this packet to mac80211. When control frame is received, indicate +it to mac80211 immediately. + +Track work: +Use track work to monitor PHY status to know the changes of environment, +and then update RA status or do RFK accordingly. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/core.c | 2428 +++++++++++++++ + drivers/net/wireless/realtek/rtw89/core.h | 3360 +++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/txrx.h | 393 +++ + drivers/net/wireless/realtek/rtw89/util.h | 17 + + 4 files changed, 6198 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/core.c + create mode 100644 drivers/net/wireless/realtek/rtw89/core.h + create mode 100644 drivers/net/wireless/realtek/rtw89/txrx.h + create mode 100644 drivers/net/wireless/realtek/rtw89/util.h + +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +new file mode 100644 +index 000000000000..654af9f893c5 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -0,0 +1,2428 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "core.h" ++#include "efuse.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++#include "ser.h" ++#include "txrx.h" ++#include "util.h" ++ ++static bool rtw89_disable_ps_mode; ++module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); ++MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); ++ ++static struct ieee80211_channel rtw89_channels_2ghz[] = { ++ { .center_freq = 2412, .hw_value = 1, }, ++ { .center_freq = 2417, .hw_value = 2, }, ++ { .center_freq = 2422, .hw_value = 3, }, ++ { .center_freq = 2427, .hw_value = 4, }, ++ { .center_freq = 2432, .hw_value = 5, }, ++ { .center_freq = 2437, .hw_value = 6, }, ++ { .center_freq = 2442, .hw_value = 7, }, ++ { .center_freq = 2447, .hw_value = 8, }, ++ { .center_freq = 2452, .hw_value = 9, }, ++ { .center_freq = 2457, .hw_value = 10, }, ++ { .center_freq = 2462, .hw_value = 11, }, ++ { .center_freq = 2467, .hw_value = 12, }, ++ { .center_freq = 2472, .hw_value = 13, }, ++ { .center_freq = 2484, .hw_value = 14, }, ++}; ++ ++static struct ieee80211_channel rtw89_channels_5ghz[] = { ++ {.center_freq = 5180, .hw_value = 36,}, ++ {.center_freq = 5200, .hw_value = 40,}, ++ {.center_freq = 5220, .hw_value = 44,}, ++ {.center_freq = 5240, .hw_value = 48,}, ++ {.center_freq = 5260, .hw_value = 52,}, ++ {.center_freq = 5280, .hw_value = 56,}, ++ {.center_freq = 5300, .hw_value = 60,}, ++ {.center_freq = 5320, .hw_value = 64,}, ++ {.center_freq = 5500, .hw_value = 100,}, ++ {.center_freq = 5520, .hw_value = 104,}, ++ {.center_freq = 5540, .hw_value = 108,}, ++ {.center_freq = 5560, .hw_value = 112,}, ++ {.center_freq = 5580, .hw_value = 116,}, ++ {.center_freq = 5600, .hw_value = 120,}, ++ {.center_freq = 5620, .hw_value = 124,}, ++ {.center_freq = 5640, .hw_value = 128,}, ++ {.center_freq = 5660, .hw_value = 132,}, ++ {.center_freq = 5680, .hw_value = 136,}, ++ {.center_freq = 5700, .hw_value = 140,}, ++ {.center_freq = 5720, .hw_value = 144,}, ++ {.center_freq = 5745, .hw_value = 149,}, ++ {.center_freq = 5765, .hw_value = 153,}, ++ {.center_freq = 5785, .hw_value = 157,}, ++ {.center_freq = 5805, .hw_value = 161,}, ++ {.center_freq = 5825, .hw_value = 165, ++ .flags = IEEE80211_CHAN_NO_HT40MINUS}, ++}; ++ ++static struct ieee80211_rate rtw89_bitrates[] = { ++ { .bitrate = 10, .hw_value = 0x00, }, ++ { .bitrate = 20, .hw_value = 0x01, }, ++ { .bitrate = 55, .hw_value = 0x02, }, ++ { .bitrate = 110, .hw_value = 0x03, }, ++ { .bitrate = 60, .hw_value = 0x04, }, ++ { .bitrate = 90, .hw_value = 0x05, }, ++ { .bitrate = 120, .hw_value = 0x06, }, ++ { .bitrate = 180, .hw_value = 0x07, }, ++ { .bitrate = 240, .hw_value = 0x08, }, ++ { .bitrate = 360, .hw_value = 0x09, }, ++ { .bitrate = 480, .hw_value = 0x0a, }, ++ { .bitrate = 540, .hw_value = 0x0b, }, ++}; ++ ++u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate) ++{ ++ struct ieee80211_rate rate; ++ ++ if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { ++ rtw89_info(rtwdev, "invalid rpt rate %d\n", rpt_rate); ++ return 0; ++ } ++ ++ rate = rtw89_bitrates[rpt_rate]; ++ ++ return rate.bitrate; ++} ++ ++static struct ieee80211_supported_band rtw89_sband_2ghz = { ++ .band = NL80211_BAND_2GHZ, ++ .channels = rtw89_channels_2ghz, ++ .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), ++ .bitrates = rtw89_bitrates, ++ .n_bitrates = ARRAY_SIZE(rtw89_bitrates), ++ .ht_cap = {0}, ++ .vht_cap = {0}, ++}; ++ ++static struct ieee80211_supported_band rtw89_sband_5ghz = { ++ .band = NL80211_BAND_5GHZ, ++ .channels = rtw89_channels_5ghz, ++ .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), ++ ++ /* 5G has no CCK rates, 1M/2M/5.5M/11M */ ++ .bitrates = rtw89_bitrates + 4, ++ .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, ++ .ht_cap = {0}, ++ .vht_cap = {0}, ++}; ++ ++static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats, ++ struct sk_buff *skb, bool tx) ++{ ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ++ ++ if (!ieee80211_is_data(hdr->frame_control)) ++ return; ++ ++ if (is_broadcast_ether_addr(hdr->addr1) || ++ is_multicast_ether_addr(hdr->addr1)) ++ return; ++ ++ if (tx) { ++ stats->tx_cnt++; ++ stats->tx_unicast += skb->len; ++ } else { ++ stats->rx_cnt++; ++ stats->rx_unicast += skb->len; ++ } ++} ++ ++static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, ++ struct rtw89_channel_params *chan_param) ++{ ++ struct ieee80211_channel *channel = chandef->chan; ++ enum nl80211_chan_width width = chandef->width; ++ u8 *cch_by_bw = chan_param->cch_by_bw; ++ u32 primary_freq, center_freq; ++ u8 center_chan; ++ u8 bandwidth = RTW89_CHANNEL_WIDTH_20; ++ u8 primary_chan_idx = 0; ++ u8 i; ++ ++ center_chan = channel->hw_value; ++ primary_freq = channel->center_freq; ++ center_freq = chandef->center_freq1; ++ ++ /* assign the center channel used while 20M bw is selected */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_20] = channel->hw_value; ++ ++ switch (width) { ++ case NL80211_CHAN_WIDTH_20_NOHT: ++ case NL80211_CHAN_WIDTH_20: ++ bandwidth = RTW89_CHANNEL_WIDTH_20; ++ primary_chan_idx = RTW89_SC_DONT_CARE; ++ break; ++ case NL80211_CHAN_WIDTH_40: ++ bandwidth = RTW89_CHANNEL_WIDTH_40; ++ if (primary_freq > center_freq) { ++ primary_chan_idx = RTW89_SC_20_UPPER; ++ center_chan -= 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_LOWER; ++ center_chan += 2; ++ } ++ break; ++ case NL80211_CHAN_WIDTH_80: ++ bandwidth = RTW89_CHANNEL_WIDTH_80; ++ if (primary_freq > center_freq) { ++ if (primary_freq - center_freq == 10) { ++ primary_chan_idx = RTW89_SC_20_UPPER; ++ center_chan -= 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_UPMOST; ++ center_chan -= 6; ++ } ++ /* assign the center channel used ++ * while 40M bw is selected ++ */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan + 4; ++ } else { ++ if (center_freq - primary_freq == 10) { ++ primary_chan_idx = RTW89_SC_20_LOWER; ++ center_chan += 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_LOWEST; ++ center_chan += 6; ++ } ++ /* assign the center channel used ++ * while 40M bw is selected ++ */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan - 4; ++ } ++ break; ++ default: ++ center_chan = 0; ++ break; ++ } ++ ++ chan_param->center_chan = center_chan; ++ chan_param->primary_chan = channel->hw_value; ++ chan_param->bandwidth = bandwidth; ++ chan_param->pri_ch_idx = primary_chan_idx; ++ ++ /* assign the center channel used while current bw is selected */ ++ cch_by_bw[bandwidth] = center_chan; ++ ++ for (i = bandwidth + 1; i <= RTW89_MAX_CHANNEL_WIDTH; i++) ++ cch_by_bw[i] = 0; ++} ++ ++void rtw89_set_channel(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_channel_params ch_param; ++ struct rtw89_channel_help_params bak; ++ u8 center_chan, bandwidth; ++ u8 band_type; ++ bool band_changed; ++ u8 i; ++ ++ rtw89_get_channel_params(&hw->conf.chandef, &ch_param); ++ if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) ++ return; ++ ++ center_chan = ch_param.center_chan; ++ bandwidth = ch_param.bandwidth; ++ band_type = center_chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; ++ band_changed = hal->current_band_type != band_type || ++ hal->current_channel == 0; ++ ++ hal->current_band_width = bandwidth; ++ hal->current_channel = center_chan; ++ hal->current_primary_channel = ch_param.primary_chan; ++ hal->current_band_type = band_type; ++ ++ switch (center_chan) { ++ case 1 ... 14: ++ hal->current_subband = RTW89_CH_2G; ++ break; ++ case 36 ... 64: ++ hal->current_subband = RTW89_CH_5G_BAND_1; ++ break; ++ case 100 ... 144: ++ hal->current_subband = RTW89_CH_5G_BAND_3; ++ break; ++ case 149 ... 177: ++ hal->current_subband = RTW89_CH_5G_BAND_4; ++ break; ++ } ++ ++ for (i = RTW89_CHANNEL_WIDTH_20; i <= RTW89_MAX_CHANNEL_WIDTH; i++) ++ hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; ++ ++ rtw89_chip_set_channel_prepare(rtwdev, &bak); ++ ++ chip->ops->set_channel(rtwdev, &ch_param); ++ ++ rtw89_chip_set_txpwr(rtwdev); ++ ++ rtw89_chip_set_channel_done(rtwdev, &bak); ++ ++ if (band_changed) { ++ rtw89_btc_ntfy_switch_band(rtwdev, RTW89_PHY_0, hal->current_band_type); ++ rtw89_chip_rfk_band_changed(rtwdev); ++ } ++} ++ ++static enum rtw89_core_tx_type ++rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ ++ if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) ++ return RTW89_CORE_TX_TYPE_MGMT; ++ ++ return RTW89_CORE_TX_TYPE_DATA; ++} ++ ++static void ++rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, u8 tid) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_sta *rtwsta; ++ u8 ampdu_num; ++ ++ if (!sta) { ++ rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); ++ return; ++ } ++ ++ rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? ++ rtwsta->ampdu_params[tid].agg_num : ++ 4 << sta->ht_cap.ampdu_factor) - 1); ++ ++ desc_info->agg_en = true; ++ desc_info->ampdu_density = sta->ht_cap.ampdu_density; ++ desc_info->ampdu_num = ampdu_num; ++} ++ ++static void ++rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct ieee80211_vif *vif = tx_req->vif; ++ struct ieee80211_tx_info *info; ++ struct ieee80211_key_conf *key; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ struct rtw89_sec_cam_entry *sec_cam; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; ++ ++ if (!vif) { ++ rtw89_warn(rtwdev, "cannot set sec key without vif\n"); ++ return; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ ++ info = IEEE80211_SKB_CB(skb); ++ key = info->control.hw_key; ++ sec_cam = addr_cam->sec_entries[key->hw_key_idx]; ++ if (!sec_cam) { ++ rtw89_warn(rtwdev, "sec cam entry is empty\n"); ++ return; ++ } ++ ++ switch (key->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ sec_type = RTW89_SEC_KEY_TYPE_WEP40; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ sec_type = RTW89_SEC_KEY_TYPE_WEP104; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ sec_type = RTW89_SEC_KEY_TYPE_TKIP; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ sec_type = RTW89_SEC_KEY_TYPE_CCMP128; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP_256: ++ sec_type = RTW89_SEC_KEY_TYPE_CCMP256; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP: ++ sec_type = RTW89_SEC_KEY_TYPE_GCMP128; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP_256: ++ sec_type = RTW89_SEC_KEY_TYPE_GCMP256; ++ break; ++ default: ++ rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); ++ return; ++ } ++ ++ desc_info->sec_en = true; ++ desc_info->sec_type = sec_type; ++ desc_info->sec_cam_idx = sec_cam->sec_cam_idx; ++} ++ ++static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_vif *vif = tx_info->control.vif; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u16 lowest_rate = hal->current_band_type == RTW89_BAND_2G ? ++ RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6; ++ ++ if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) ++ return lowest_rate; ++ ++ return __ffs(vif->bss_conf.basic_rates) + lowest_rate; ++} ++ ++static void ++rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ u8 qsel, ch_dma; ++ ++ qsel = RTW89_TX_QSEL_B0_MGMT; ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ desc_info->qsel = RTW89_TX_QSEL_B0_MGMT; ++ desc_info->ch_dma = ch_dma; ++ ++ /* fixed data rate for mgmt frames */ ++ desc_info->en_wd_info = true; ++ desc_info->use_rate = true; ++ desc_info->dis_data_fb = true; ++ desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "tx mgmt frame with rate 0x%x on channel %d (bw %d)\n", ++ desc_info->data_rate, rtwdev->hal.current_channel, ++ rtwdev->hal.current_band_width); ++} ++ ++static void ++rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ ++ desc_info->is_bmc = false; ++ desc_info->wd_page = false; ++ desc_info->ch_dma = RTW89_DMA_H2C; ++} ++ ++static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) ++{ ++ static const u8 rtw89_bandwidth_to_om[] = { ++ [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, ++ [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, ++ [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, ++ [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, ++ [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, ++ }; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 om_bandwidth; ++ ++ if (!chip->dis_2g_40m_ul_ofdma || ++ hal->current_band_type != RTW89_BAND_2G || ++ hal->current_band_width != RTW89_CHANNEL_WIDTH_40) ++ return; ++ ++ om_bandwidth = hal->current_band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? ++ rtw89_bandwidth_to_om[hal->current_band_width] : 0; ++ *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | ++ le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | ++ le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | ++ le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | ++ le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | ++ le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); ++} ++ ++static bool ++__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, ++ enum btc_pkt_type pkt_type) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ ++ /* AP IOT issue with EAPoL, ARP and DHCP */ ++ if (pkt_type < PACKET_MAX) ++ return false; ++ ++ if (!sta || !sta->he_cap.has_he) ++ return false; ++ ++ if (!ieee80211_is_data_qos(fc)) ++ return false; ++ ++ if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) ++ return false; ++ ++ return true; ++} ++ ++static void ++__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ void *data; ++ __le32 *htc; ++ u8 *qc; ++ int hdr_len; ++ ++ hdr_len = ieee80211_has_a4(fc) ? 32 : 26; ++ data = skb_push(skb, IEEE80211_HT_CTL_LEN); ++ memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); ++ ++ hdr = data; ++ htc = data + hdr_len; ++ hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); ++ *htc = rtwsta->htc_template ? rtwsta->htc_template : ++ le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | ++ le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); ++ ++ qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; ++ qc[0] |= IEEE80211_QOS_CTL_EOSP; ++} ++ ++static void ++rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, ++ enum btc_pkt_type pkt_type) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct ieee80211_vif *vif = tx_req->vif; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) ++ goto desc_bk; ++ ++ __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); ++ ++ desc_info->pkt_size += IEEE80211_HT_CTL_LEN; ++ desc_info->a_ctrl_bsr = true; ++ ++desc_bk: ++ if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) ++ return; ++ ++ rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; ++ desc_info->bk = true; ++} ++ ++static void ++rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ u8 tid, tid_indicate; ++ u8 qsel, ch_dma; ++ ++ tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); ++ qsel = rtw89_core_get_qsel(rtwdev, tid); ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ desc_info->ch_dma = ch_dma; ++ desc_info->tid_indicate = tid_indicate; ++ desc_info->qsel = qsel; ++ ++ /* enable wd_info for AMPDU */ ++ desc_info->en_wd_info = true; ++ ++ if (IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU) ++ rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, tid); ++ if (IEEE80211_SKB_CB(skb)->control.hw_key) ++ rtw89_core_tx_update_sec_key(rtwdev, tx_req); ++} ++ ++static enum btc_pkt_type ++rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct sk_buff *skb = tx_req->skb; ++ struct udphdr *udphdr; ++ ++ if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); ++ return PACKET_EAPOL; ++ } ++ ++ if (skb->protocol == htons(ETH_P_ARP)) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); ++ return PACKET_ARP; ++ } ++ ++ if (skb->protocol == htons(ETH_P_IP) && ++ ip_hdr(skb)->protocol == IPPROTO_UDP) { ++ udphdr = udp_hdr(skb); ++ if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || ++ (udphdr->source == htons(68) && udphdr->dest == htons(67))) && ++ skb->len > 282) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); ++ return PACKET_DHCP; ++ } ++ } ++ ++ return PACKET_MAX; ++} ++ ++static void ++rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ enum rtw89_core_tx_type tx_type; ++ enum btc_pkt_type pkt_type; ++ bool is_bmc; ++ u16 seq; ++ ++ seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; ++ if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { ++ tx_type = rtw89_core_get_tx_type(rtwdev, skb); ++ tx_req->tx_type = tx_type; ++ } ++ is_bmc = (is_broadcast_ether_addr(hdr->addr1) || ++ is_multicast_ether_addr(hdr->addr1)); ++ ++ desc_info->seq = seq; ++ desc_info->pkt_size = skb->len; ++ desc_info->is_bmc = is_bmc; ++ desc_info->wd_page = true; ++ ++ switch (tx_req->tx_type) { ++ case RTW89_CORE_TX_TYPE_MGMT: ++ rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); ++ break; ++ case RTW89_CORE_TX_TYPE_DATA: ++ rtw89_core_tx_update_data_info(rtwdev, tx_req); ++ pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); ++ rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); ++ break; ++ case RTW89_CORE_TX_TYPE_FWCMD: ++ rtw89_core_tx_update_h2c_info(rtwdev, tx_req); ++ break; ++ } ++} ++ ++void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) ++{ ++ u8 ch_dma; ++ ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ rtw89_hci_tx_kick_off(rtwdev, ch_dma); ++} ++ ++int rtw89_h2c_tx(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, bool fwdl) ++{ ++ struct rtw89_core_tx_request tx_req = {0}; ++ u32 cnt; ++ int ret; ++ ++ tx_req.skb = skb; ++ tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; ++ if (fwdl) ++ tx_req.desc_info.fw_dl = true; ++ ++ rtw89_core_tx_update_desc_info(rtwdev, &tx_req); ++ ++ if (!fwdl) ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); ++ ++ cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); ++ if (cnt == 0) { ++ rtw89_err(rtwdev, "no tx fwcmd resource\n"); ++ return -ENOSPC; ++ } ++ ++ ret = rtw89_hci_tx_write(rtwdev, &tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); ++ return ret; ++ } ++ rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); ++ ++ return 0; ++} ++ ++int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) ++{ ++ struct rtw89_core_tx_request tx_req = {0}; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret; ++ ++ tx_req.skb = skb; ++ tx_req.sta = sta; ++ tx_req.vif = vif; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); ++ rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); ++ rtw89_core_tx_update_desc_info(rtwdev, &tx_req); ++ ret = rtw89_hci_tx_write(rtwdev, &tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); ++ return ret; ++ } ++ ++ if (qsel) ++ *qsel = tx_req.desc_info.qsel; ++ ++ return 0; ++} ++ ++void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_tx_desc_info *desc_info, ++ void *txdesc) ++{ ++ RTW89_SET_TXWD_BODY_WP_OFFSET(txdesc, desc_info->wp_offset); ++ RTW89_SET_TXWD_BODY_WD_INFO_EN(txdesc, desc_info->en_wd_info); ++ RTW89_SET_TXWD_BODY_CHANNEL_DMA(txdesc, desc_info->ch_dma); ++ RTW89_SET_TXWD_BODY_HDR_LLC_LEN(txdesc, desc_info->hdr_llc_len); ++ RTW89_SET_TXWD_BODY_WD_PAGE(txdesc, desc_info->wd_page); ++ RTW89_SET_TXWD_BODY_FW_DL(txdesc, desc_info->fw_dl); ++ RTW89_SET_TXWD_BODY_SW_SEQ(txdesc, desc_info->seq); ++ ++ RTW89_SET_TXWD_BODY_TID_INDICATE(txdesc, desc_info->tid_indicate); ++ RTW89_SET_TXWD_BODY_QSEL(txdesc, desc_info->qsel); ++ RTW89_SET_TXWD_BODY_TXPKT_SIZE(txdesc, desc_info->pkt_size); ++ RTW89_SET_TXWD_BODY_AGG_EN(txdesc, desc_info->agg_en); ++ RTW89_SET_TXWD_BODY_BK(txdesc, desc_info->bk); ++ ++ if (!desc_info->en_wd_info) ++ return; ++ ++ RTW89_SET_TXWD_INFO_USE_RATE(txdesc, desc_info->use_rate); ++ RTW89_SET_TXWD_INFO_DATA_RATE(txdesc, desc_info->data_rate); ++ RTW89_SET_TXWD_INFO_DISDATAFB(txdesc, desc_info->dis_data_fb); ++ RTW89_SET_TXWD_INFO_MAX_AGGNUM(txdesc, desc_info->ampdu_num); ++ RTW89_SET_TXWD_INFO_AMPDU_DENSITY(txdesc, desc_info->ampdu_density); ++ RTW89_SET_TXWD_INFO_SEC_TYPE(txdesc, desc_info->sec_type); ++ RTW89_SET_TXWD_INFO_SEC_HW_ENC(txdesc, desc_info->sec_en); ++ RTW89_SET_TXWD_INFO_SEC_CAM_IDX(txdesc, desc_info->sec_cam_idx); ++ RTW89_SET_TXWD_INFO_RTS_EN(txdesc, 1); ++ RTW89_SET_TXWD_INFO_HW_RTS_EN(txdesc, 1); ++ RTW89_SET_TXWD_INFO_A_CTRL_BSR(txdesc, desc_info->a_ctrl_bsr); ++} ++EXPORT_SYMBOL(rtw89_core_fill_txdesc); ++ ++static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ bool rx_cnt_valid = false; ++ u8 plcp_size = 0; ++ u8 usr_num = 0; ++ u8 *phy_sts; ++ ++ rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); ++ plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; ++ usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); ++ if (usr_num > RTW89_PPDU_MAX_USR) { ++ rtw89_warn(rtwdev, "Invalid user number in mac info\n"); ++ return -EINVAL; ++ } ++ ++ phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; ++ phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; ++ /* 8-byte alignment */ ++ if (usr_num & BIT(0)) ++ phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; ++ if (rx_cnt_valid) ++ phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; ++ phy_sts += plcp_size; ++ ++ phy_ppdu->buf = phy_sts; ++ phy_ppdu->len = skb->data + skb->len - phy_sts; ++ ++ return 0; ++} ++ ++static void rtw89_core_rx_process_phy_ppdu_iter(void *data, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; ++ ++ if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) ++ ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); ++} ++ ++#define VAR_LEN 0xff ++#define VAR_LEN_UNIT 8 ++static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) ++{ ++ static const u8 physts_ie_len_tab[32] = { ++ 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, ++ VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, ++ VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 ++ }; ++ u16 ie_len; ++ u8 ie; ++ ++ ie = RTW89_GET_PHY_STS_IE_TYPE(addr); ++ if (physts_ie_len_tab[ie] != VAR_LEN) ++ ie_len = physts_ie_len_tab[ie]; ++ else ++ ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; ++ ++ return ie_len; ++} ++ ++static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ s16 cfo; ++ ++ /* sign conversion for S(12,2) */ ++ cfo = sign_extend32(RTW89_GET_PHY_STS_IE0_CFO(addr), 11); ++ rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); ++} ++ ++static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ u8 ie; ++ ++ ie = RTW89_GET_PHY_STS_IE_TYPE(addr); ++ switch (ie) { ++ case RTW89_PHYSTS_IE01_CMN_OFDM: ++ rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ s8 *rssi = phy_ppdu->rssi; ++ u8 *buf = phy_ppdu->buf; ++ ++ phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); ++ rssi[RF_PATH_A] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_A(buf)); ++ rssi[RF_PATH_B] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_B(buf)); ++ rssi[RF_PATH_C] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_C(buf)); ++ rssi[RF_PATH_D] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_D(buf)); ++} ++ ++static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { ++ rtw89_warn(rtwdev, "phy ppdu len mismatch\n"); ++ return -EINVAL; ++ } ++ rtw89_core_update_phy_ppdu(phy_ppdu); ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_core_rx_process_phy_ppdu_iter, ++ phy_ppdu); ++ ++ return 0; ++} ++ ++static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ u16 ie_len; ++ u8 *pos, *end; ++ ++ if (!phy_ppdu->to_self) ++ return 0; ++ ++ pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; ++ end = (u8 *)phy_ppdu->buf + phy_ppdu->len; ++ while (pos < end) { ++ ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); ++ rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); ++ pos += ie_len; ++ if (pos > end || ie_len == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "phy status parse failed\n"); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ int ret; ++ ++ ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); ++ else ++ phy_ppdu->valid = true; ++} ++ ++static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, ++ const struct rtw89_rx_desc_info *desc_info, ++ bool rx_status) ++{ ++ switch (desc_info->gi_ltf) { ++ case RTW89_GILTF_SGI_4XHE08: ++ case RTW89_GILTF_2XHE08: ++ case RTW89_GILTF_1XHE08: ++ return NL80211_RATE_INFO_HE_GI_0_8; ++ case RTW89_GILTF_2XHE16: ++ case RTW89_GILTF_1XHE16: ++ return NL80211_RATE_INFO_HE_GI_1_6; ++ case RTW89_GILTF_LGI_4XHE32: ++ return NL80211_RATE_INFO_HE_GI_3_2; ++ default: ++ rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); ++ return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; ++ } ++} ++ ++static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *status) ++{ ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; ++ u16 data_rate; ++ bool ret; ++ ++ data_rate = desc_info->data_rate; ++ data_rate_mode = GET_DATA_RATE_MODE(data_rate); ++ if (data_rate_mode == DATA_RATE_MODE_NON_HT) { ++ rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); ++ /* No 4 CCK rates for 5G */ ++ if (status->band == NL80211_BAND_5GHZ) ++ rate_idx -= 4; ++ } else if (data_rate_mode == DATA_RATE_MODE_HT) { ++ rate_idx = GET_DATA_RATE_HT_IDX(data_rate); ++ } else if (data_rate_mode == DATA_RATE_MODE_VHT) { ++ rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ } else if (data_rate_mode == DATA_RATE_MODE_HE) { ++ rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ } else { ++ rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); ++ } ++ ++ if (desc_info->bw == RTW89_CHANNEL_WIDTH_80) ++ bw = RATE_INFO_BW_80; ++ else if (desc_info->bw == RTW89_CHANNEL_WIDTH_40) ++ bw = RATE_INFO_BW_40; ++ else ++ bw = RATE_INFO_BW_20; ++ ++ gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); ++ ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && ++ status->rate_idx == rate_idx && ++ status->he_gi == gi_ltf && ++ status->bw == bw; ++ ++ return ret; ++} ++ ++struct rtw89_vif_rx_stats_iter_data { ++ struct rtw89_dev *rtwdev; ++ struct rtw89_rx_phy_ppdu *phy_ppdu; ++ struct rtw89_rx_desc_info *desc_info; ++ struct sk_buff *skb; ++ const u8 *bssid; ++}; ++ ++static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_vif_rx_stats_iter_data *iter_data = data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; ++ struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; ++ struct sk_buff *skb = iter_data->skb; ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ++ const u8 *bssid = iter_data->bssid; ++ ++ if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) ++ return; ++ ++ if (ieee80211_is_beacon(hdr->frame_control)) ++ pkt_stat->beacon_nr++; ++ ++ if (!ether_addr_equal(vif->addr, hdr->addr1)) ++ return; ++ ++ if (desc_info->data_rate < RTW89_HW_RATE_NR) ++ pkt_stat->rx_rate_cnt[desc_info->data_rate]++; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); ++} ++ ++static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct rtw89_vif_rx_stats_iter_data iter_data; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); ++ ++ iter_data.rtwdev = rtwdev; ++ iter_data.phy_ppdu = phy_ppdu; ++ iter_data.desc_info = desc_info; ++ iter_data.skb = skb; ++ iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); ++ rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); ++} ++ ++static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; ++ struct sk_buff *skb_ppdu = NULL, *tmp; ++ struct ieee80211_rx_status *rx_status; ++ ++ if (curr > RTW89_MAX_PPDU_CNT) ++ return; ++ ++ skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { ++ skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); ++ rx_status = IEEE80211_SKB_RXCB(skb_ppdu); ++ if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) ++ rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); ++ rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++ ++static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, ++ .len = skb->len, ++ .to_self = desc_info->addr1_match, ++ .mac_id = desc_info->mac_id}; ++ int ret; ++ ++ if (desc_info->mac_info_valid) ++ rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); ++ ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); ++ ++ rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); ++ rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); ++ dev_kfree_skb_any(skb); ++} ++ ++static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ switch (desc_info->pkt_type) { ++ case RTW89_CORE_RX_TYPE_C2H: ++ rtw89_fw_c2h_irqsafe(rtwdev, skb); ++ break; ++ case RTW89_CORE_RX_TYPE_PPDU_STAT: ++ rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", ++ desc_info->pkt_type); ++ dev_kfree_skb_any(skb); ++ break; ++ } ++} ++ ++void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ u8 *data, u32 data_offset) ++{ ++ struct rtw89_rxdesc_short *rxd_s; ++ struct rtw89_rxdesc_long *rxd_l; ++ u8 shift_len, drv_info_len; ++ ++ rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); ++ desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); ++ desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); ++ desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); ++ desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); ++ desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); ++ desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); ++ desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); ++ desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); ++ desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); ++ desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); ++ desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); ++ desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); ++ desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); ++ desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); ++ desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); ++ desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); ++ desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); ++ desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); ++ ++ shift_len = desc_info->shift << 1; /* 2-byte unit */ ++ drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ ++ desc_info->offset = data_offset + shift_len + drv_info_len; ++ desc_info->ready = true; ++ ++ if (!desc_info->long_rxdesc) ++ return; ++ ++ rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); ++ desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); ++ desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); ++ desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); ++ desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); ++ desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); ++ desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); ++} ++EXPORT_SYMBOL(rtw89_core_query_rxdesc); ++ ++struct rtw89_core_iter_rx_status { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_rx_status *rx_status; ++ struct rtw89_rx_desc_info *desc_info; ++ u8 mac_id; ++}; ++ ++static ++void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_core_iter_rx_status *iter_data = ++ (struct rtw89_core_iter_rx_status *)data; ++ struct ieee80211_rx_status *rx_status = iter_data->rx_status; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; ++ u8 mac_id = iter_data->mac_id; ++ ++ if (mac_id != rtwsta->mac_id) ++ return; ++ ++ rtwsta->rx_status = *rx_status; ++ rtwsta->rx_hw_rate = desc_info->data_rate; ++} ++ ++static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *rx_status) ++{ ++ struct rtw89_core_iter_rx_status iter_data; ++ ++ if (!desc_info->addr1_match || !desc_info->long_rxdesc) ++ return; ++ ++ if (desc_info->frame_type != RTW89_RX_TYPE_DATA) ++ return; ++ ++ iter_data.rtwdev = rtwdev; ++ iter_data.rx_status = rx_status; ++ iter_data.desc_info = desc_info; ++ iter_data.mac_id = desc_info->mac_id; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_core_stats_sta_rx_status_iter, ++ &iter_data); ++} ++ ++static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *rx_status) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ u16 data_rate; ++ u8 data_rate_mode; ++ ++ /* currently using single PHY */ ++ rx_status->freq = hw->conf.chandef.chan->center_freq; ++ rx_status->band = hw->conf.chandef.chan->band; ++ ++ if (desc_info->icv_err || desc_info->crc32_err) ++ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; ++ ++ if (desc_info->hw_dec && ++ !(desc_info->sw_dec || desc_info->icv_err)) ++ rx_status->flag |= RX_FLAG_DECRYPTED; ++ ++ if (desc_info->bw == RTW89_CHANNEL_WIDTH_80) ++ rx_status->bw = RATE_INFO_BW_80; ++ else if (desc_info->bw == RTW89_CHANNEL_WIDTH_40) ++ rx_status->bw = RATE_INFO_BW_40; ++ else ++ rx_status->bw = RATE_INFO_BW_20; ++ ++ data_rate = desc_info->data_rate; ++ data_rate_mode = GET_DATA_RATE_MODE(data_rate); ++ if (data_rate_mode == DATA_RATE_MODE_NON_HT) { ++ rx_status->encoding = RX_ENC_LEGACY; ++ rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); ++ /* No 4 CCK rates for 5G */ ++ if (rx_status->band == NL80211_BAND_5GHZ) ++ rx_status->rate_idx -= 4; ++ if (rtwdev->scanning) ++ rx_status->rate_idx = min_t(u8, rx_status->rate_idx, ++ ARRAY_SIZE(rtw89_bitrates) - 5); ++ } else if (data_rate_mode == DATA_RATE_MODE_HT) { ++ rx_status->encoding = RX_ENC_HT; ++ rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); ++ if (desc_info->gi_ltf) ++ rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; ++ } else if (data_rate_mode == DATA_RATE_MODE_VHT) { ++ rx_status->encoding = RX_ENC_VHT; ++ rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; ++ if (desc_info->gi_ltf) ++ rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; ++ } else if (data_rate_mode == DATA_RATE_MODE_HE) { ++ rx_status->encoding = RX_ENC_HE; ++ rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; ++ } else { ++ rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); ++ } ++ ++ /* he_gi is used to match ppdu, so we always fill it. */ ++ rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); ++ rx_status->flag |= RX_FLAG_MACTIME_START; ++ rx_status->mactime = desc_info->free_run_cnt; ++ ++ rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); ++} ++ ++static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (rtw89_disable_ps_mode || !chip->ps_mode_supported) ++ return RTW89_PS_MODE_NONE; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) ++ return RTW89_PS_MODE_PWR_GATED; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) ++ return RTW89_PS_MODE_CLK_GATED; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) ++ return RTW89_PS_MODE_RFOFF; ++ ++ return RTW89_PS_MODE_NONE; ++} ++ ++static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info) ++{ ++ struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ struct sk_buff *skb_ppdu, *tmp; ++ ++ skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { ++ skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); ++ rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb_ppdu); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++ ++void rtw89_core_rx(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_rx_status *rx_status; ++ struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; ++ u8 ppdu_cnt = desc_info->ppdu_cnt; ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ ++ if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { ++ rtw89_core_rx_process_report(rtwdev, desc_info, skb); ++ return; ++ } ++ ++ if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { ++ rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); ++ ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; ++ } ++ ++ rx_status = IEEE80211_SKB_RXCB(skb); ++ memset(rx_status, 0, sizeof(*rx_status)); ++ rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); ++ if (desc_info->long_rxdesc && ++ BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) { ++ skb_queue_tail(&ppdu_sts->rx_queue[band], skb); ++ } else { ++ rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++EXPORT_SYMBOL(rtw89_core_rx); ++ ++void rtw89_core_napi_start(struct rtw89_dev *rtwdev) ++{ ++ if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) ++ return; ++ ++ napi_enable(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_start); ++ ++void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) ++{ ++ if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) ++ return; ++ ++ napi_synchronize(&rtwdev->napi); ++ napi_disable(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_stop); ++ ++void rtw89_core_napi_init(struct rtw89_dev *rtwdev) ++{ ++ init_dummy_netdev(&rtwdev->netdev); ++ netif_napi_add(&rtwdev->netdev, &rtwdev->napi, ++ rtwdev->hci.ops->napi_poll, NAPI_POLL_WEIGHT); ++} ++EXPORT_SYMBOL(rtw89_core_napi_init); ++ ++void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) ++{ ++ rtw89_core_napi_stop(rtwdev); ++ netif_napi_del(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_deinit); ++ ++static void rtw89_core_ba_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = ++ container_of(work, struct rtw89_dev, ba_work); ++ struct rtw89_txq *rtwtxq, *tmp; ++ int ret; ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ u8 tid = txq->tid; ++ ++ if (!sta) { ++ rtw89_warn(rtwdev, "cannot start BA without sta\n"); ++ goto skip_ba_work; ++ } ++ ++ if (rtwsta->disassoc) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "cannot start BA with disassoc sta\n"); ++ goto skip_ba_work; ++ } ++ ++ ret = ieee80211_start_tx_ba_session(sta, tid, 0); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "failed to setup BA session for %pM:%2d: %d\n", ++ sta->addr, tid, ret); ++ if (ret == -EINVAL) ++ set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); ++ } ++skip_ba_work: ++ list_del_init(&rtwtxq->list); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_txq *rtwtxq, *tmp; ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ ++ if (sta == txq->sta) ++ list_del_init(&rtwtxq->list); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, ++ struct rtw89_txq *rtwtxq, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (unlikely(skb_get_queue_mapping(skb) == IEEE80211_AC_VO)) ++ return; ++ ++ if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) ++ return; ++ ++ if (unlikely(!sta)) ++ return; ++ ++ if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) ++ return; ++ ++ if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { ++ IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; ++ return; ++ } ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { ++ list_add_tail(&rtwtxq->list, &rtwdev->ba_list); ++ ieee80211_queue_work(hw, &rtwdev->ba_work); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, ++ struct rtw89_txq *rtwtxq, ++ unsigned long frame_cnt, ++ unsigned long byte_cnt) ++{ ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_vif *vif = txq->vif; ++ struct ieee80211_sta *sta = txq->sta; ++ struct sk_buff *skb; ++ unsigned long i; ++ int ret; ++ ++ for (i = 0; i < frame_cnt; i++) { ++ skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); ++ if (!skb) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); ++ return; ++ } ++ rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); ++ ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to push txq: %d\n", ret); ++ ieee80211_free_txskb(rtwdev->hw, skb); ++ break; ++ } ++ } ++} ++ ++static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ u8 qsel, ch_dma; ++ ++ qsel = rtw89_core_get_qsel(rtwdev, tid); ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); ++} ++ ++static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, ++ struct ieee80211_txq *txq, ++ unsigned long *frame_cnt, ++ bool *sched_txq, bool *reinvoke) ++{ ++ struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (!sta || rtwsta->max_agg_wait <= 0) ++ return false; ++ ++ if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) ++ return false; ++ ++ if (*frame_cnt > 1) { ++ *frame_cnt -= 1; ++ *sched_txq = true; ++ *reinvoke = true; ++ rtwtxq->wait_cnt = 1; ++ return false; ++ } ++ ++ if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { ++ *reinvoke = true; ++ rtwtxq->wait_cnt++; ++ return true; ++ } ++ ++ rtwtxq->wait_cnt = 0; ++ return false; ++} ++ ++static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_txq *txq; ++ struct rtw89_txq *rtwtxq; ++ unsigned long frame_cnt; ++ unsigned long byte_cnt; ++ u32 tx_resource; ++ bool sched_txq; ++ ++ ieee80211_txq_schedule_start(hw, ac); ++ while ((txq = ieee80211_next_txq(hw, ac))) { ++ rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); ++ sched_txq = false; ++ ++ ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); ++ if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { ++ ieee80211_return_txq(hw, txq, true); ++ continue; ++ } ++ frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); ++ rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); ++ ieee80211_return_txq(hw, txq, sched_txq); ++ if (frame_cnt != 0) ++ rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); ++ } ++ ieee80211_txq_schedule_end(hw, ac); ++} ++ ++static void rtw89_core_txq_work(struct work_struct *w) ++{ ++ struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); ++ bool reinvoke = false; ++ u8 ac; ++ ++ for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) ++ rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); ++ ++ if (reinvoke) { ++ /* reinvoke to process the last frame */ ++ mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); ++ } ++} ++ ++static void rtw89_core_txq_reinvoke_work(struct work_struct *w) ++{ ++ struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, ++ txq_reinvoke_work.work); ++ ++ queue_work(rtwdev->txq_wq, &rtwdev->txq_work); ++} ++ ++static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, ++ u32 throughput, u64 cnt) ++{ ++ if (cnt < 100) ++ return RTW89_TFC_IDLE; ++ if (throughput > 50) ++ return RTW89_TFC_HIGH; ++ if (throughput > 10) ++ return RTW89_TFC_MID; ++ if (throughput > 2) ++ return RTW89_TFC_LOW; ++ return RTW89_TFC_ULTRA_LOW; ++} ++ ++static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats) ++{ ++ enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; ++ ++ stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); ++ stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); ++ ++ ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); ++ ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); ++ ++ stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); ++ stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); ++ stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, ++ stats->tx_cnt); ++ stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, ++ stats->rx_cnt); ++ stats->tx_avg_len = stats->tx_cnt ? ++ DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; ++ stats->rx_avg_len = stats->rx_cnt ? ++ DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; ++ ++ stats->tx_unicast = 0; ++ stats->rx_unicast = 0; ++ stats->tx_cnt = 0; ++ stats->rx_cnt = 0; ++ ++ if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.wl_sta_notify_work); ++ return true; ++ } ++ ++ return false; ++} ++ ++static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ bool tfc_changed; ++ ++ tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); ++ ++ return tfc_changed; ++} ++ ++static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) ++ return; ++ ++ if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && ++ rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) ++ rtw89_enter_lps(rtwdev, rtwvif->mac_id); ++} ++ ++static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_vif_enter_lps(rtwdev, rtwvif); ++} ++ ++void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats) ++{ ++ stats->tx_unicast = 0; ++ stats->rx_unicast = 0; ++ stats->tx_cnt = 0; ++ stats->rx_cnt = 0; ++ ewma_tp_init(&stats->tx_ewma_tp); ++ ewma_tp_init(&stats->rx_ewma_tp); ++} ++ ++static void rtw89_track_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ track_work.work); ++ bool tfc_changed; ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ goto out; ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, ++ RTW89_TRACK_WORK_PERIOD); ++ ++ tfc_changed = rtw89_traffic_stats_track(rtwdev); ++ if (rtwdev->scanning) ++ goto out; ++ ++ rtw89_leave_lps(rtwdev); ++ ++ if (tfc_changed) ++ rtw89_hci_recalc_int_mit(rtwdev); ++ rtw89_mac_bf_monitor_track(rtwdev); ++ rtw89_phy_stat_track(rtwdev); ++ rtw89_phy_env_monitor_track(rtwdev); ++ rtw89_phy_dig(rtwdev); ++ rtw89_chip_rfk_track(rtwdev); ++ rtw89_phy_ra_update(rtwdev); ++ rtw89_phy_cfo_track(rtwdev); ++ ++ if (rtwdev->lps_enabled && !rtwdev->btc.lps) ++ rtw89_enter_lps_track(rtwdev); ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) ++{ ++ unsigned long bit; ++ ++ bit = find_first_zero_bit(addr, size); ++ if (bit < size) ++ set_bit(bit, addr); ++ ++ return bit; ++} ++ ++void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) ++{ ++ clear_bit(bit, addr); ++} ++ ++void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) ++{ ++ bitmap_zero(addr, nbits); ++} ++ ++#define RTW89_TYPE_MAPPING(_type) \ ++ case NL80211_IFTYPE_ ## _type: \ ++ rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ ++ break ++void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ switch (vif->type) { ++ RTW89_TYPE_MAPPING(ADHOC); ++ RTW89_TYPE_MAPPING(STATION); ++ RTW89_TYPE_MAPPING(AP); ++ RTW89_TYPE_MAPPING(MONITOR); ++ RTW89_TYPE_MAPPING(MESH_POINT); ++ default: ++ WARN_ON(1); ++ break; ++ } ++ ++ switch (vif->type) { ++ case NL80211_IFTYPE_AP: ++ case NL80211_IFTYPE_MESH_POINT: ++ rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; ++ rtwvif->self_role = RTW89_SELF_ROLE_AP; ++ break; ++ case NL80211_IFTYPE_ADHOC: ++ rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; ++ rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; ++ break; ++ case NL80211_IFTYPE_STATION: ++ if (assoc) { ++ rtwvif->net_type = RTW89_NET_TYPE_INFRA; ++ rtwvif->trigger = vif->bss_conf.he_support; ++ } else { ++ rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; ++ rtwvif->trigger = false; ++ } ++ rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; ++ rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; ++ break; ++ default: ++ WARN_ON(1); ++ break; ++ } ++} ++ ++int rtw89_core_sta_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ int i; ++ ++ rtwsta->rtwvif = rtwvif; ++ rtwsta->prev_rssi = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(sta->txq); i++) ++ rtw89_core_txq_init(rtwdev, sta->txq[i]); ++ ++ ewma_rssi_init(&rtwsta->avg_rssi); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ rtwvif->mgd.ap = sta; ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_CONN_START); ++ rtw89_chip_rfk_channel(rtwdev); ++ } ++ ++ return 0; ++} ++ ++int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ rtwdev->total_sta_assoc--; ++ rtwsta->disassoc = true; ++ ++ return 0; ++} ++ ++int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret; ++ ++ rtw89_mac_bf_monitor_calc(rtwdev, sta, true); ++ rtw89_mac_bf_disassoc(rtwdev, vif, sta); ++ rtw89_core_free_sta_pending_ba(rtwdev, sta); ++ ++ rtw89_vif_type_mapping(vif, false); ++ ++ ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, 1); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c join info\n"); ++ return ret; ++ } ++ ++ /* update cam aid mac_id net_type */ ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cam\n"); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ int ret; ++ ++ rtw89_vif_type_mapping(vif, true); ++ ++ ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); ++ return ret; ++ } ++ ++ /* for station mode, assign the mac_id from itself */ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ rtwsta->mac_id = rtwvif->mac_id; ++ ++ ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, 0); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c join info\n"); ++ return ret; ++ } ++ ++ /* update cam aid mac_id net_type */ ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cam\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c general packet\n"); ++ return ret; ++ } ++ ++ rtwdev->total_sta_assoc++; ++ rtw89_phy_ra_assoc(rtwdev, sta); ++ rtw89_mac_bf_assoc(rtwdev, vif, sta); ++ rtw89_mac_bf_monitor_calc(rtwdev, sta, false); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_CONN_END); ++ rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); ++ } ++ ++ return ret; ++} ++ ++int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_DIS_CONN); ++ ++ return 0; ++} ++ ++static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta_ht_cap *ht_cap) ++{ ++ static const __le16 highest[RF_PATH_MAX] = { ++ cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), ++ }; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 nss = hal->rx_nss; ++ int i; ++ ++ ht_cap->ht_supported = true; ++ ht_cap->cap = 0; ++ ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_MAX_AMSDU | ++ IEEE80211_HT_CAP_TX_STBC | ++ (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); ++ ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; ++ ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | ++ IEEE80211_HT_CAP_DSSSCCK40 | ++ IEEE80211_HT_CAP_SGI_40; ++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; ++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; ++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; ++ for (i = 0; i < nss; i++) ++ ht_cap->mcs.rx_mask[i] = 0xFF; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ht_cap->mcs.rx_highest = highest[nss - 1]; ++} ++ ++static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta_vht_cap *vht_cap) ++{ ++ static const __le16 highest[RF_PATH_MAX] = { ++ cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), ++ }; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u16 tx_mcs_map = 0, rx_mcs_map = 0; ++ u8 sts_cap = 3; ++ int i; ++ ++ for (i = 0; i < 8; i++) { ++ if (i < hal->tx_nss) ++ tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); ++ else ++ tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); ++ if (i < hal->rx_nss) ++ rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); ++ else ++ rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); ++ } ++ ++ vht_cap->vht_supported = true; ++ vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | ++ IEEE80211_VHT_CAP_SHORT_GI_80 | ++ IEEE80211_VHT_CAP_RXSTBC_1 | ++ IEEE80211_VHT_CAP_HTC_VHT | ++ IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | ++ 0; ++ vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; ++ vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; ++ vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | ++ IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; ++ vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; ++ vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); ++ vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); ++ vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; ++ vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; ++} ++ ++#define RTW89_SBAND_IFTYPES_NR 2 ++ ++static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, ++ enum nl80211_band band, ++ struct ieee80211_supported_band *sband) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_sband_iftype_data *iftype_data; ++ bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || ++ (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); ++ u16 mcs_map = 0; ++ int i; ++ int nss = hal->rx_nss; ++ int idx = 0; ++ ++ iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); ++ if (!iftype_data) ++ return; ++ ++ for (i = 0; i < 8; i++) { ++ if (i < nss) ++ mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ } ++ ++ for (i = 0; i < NUM_NL80211_IFTYPES; i++) { ++ struct ieee80211_sta_he_cap *he_cap; ++ u8 *mac_cap_info; ++ u8 *phy_cap_info; ++ ++ switch (i) { ++ case NL80211_IFTYPE_STATION: ++ case NL80211_IFTYPE_AP: ++ break; ++ default: ++ continue; ++ } ++ ++ if (idx >= RTW89_SBAND_IFTYPES_NR) { ++ rtw89_warn(rtwdev, "run out of iftype_data\n"); ++ break; ++ } ++ ++ iftype_data[idx].types_mask = BIT(i); ++ he_cap = &iftype_data[idx].he_cap; ++ mac_cap_info = he_cap->he_cap_elem.mac_cap_info; ++ phy_cap_info = he_cap->he_cap_elem.phy_cap_info; ++ ++ he_cap->has_he = true; ++ if (i == NL80211_IFTYPE_AP) ++ mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; ++ if (i == NL80211_IFTYPE_STATION) ++ mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; ++ mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | ++ IEEE80211_HE_MAC_CAP2_BSR; ++ mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; ++ if (i == NL80211_IFTYPE_AP) ++ mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; ++ mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | ++ IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; ++ if (i == NL80211_IFTYPE_STATION) ++ mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; ++ phy_cap_info[0] = IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; ++ phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | ++ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | ++ IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; ++ phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | ++ IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | ++ IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | ++ IEEE80211_HE_PHY_CAP2_DOPPLER_TX; ++ phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; ++ if (i == NL80211_IFTYPE_STATION) ++ phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | ++ IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; ++ if (i == NL80211_IFTYPE_AP) ++ phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; ++ phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | ++ IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; ++ phy_cap_info[5] = no_ng16 ? 0 : ++ IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | ++ IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; ++ phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | ++ IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | ++ IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | ++ IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; ++ phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | ++ IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP7_MAX_NC_1; ++ phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; ++ phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | ++ IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | ++ IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | ++ IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | ++ IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US; ++ if (i == NL80211_IFTYPE_STATION) ++ phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; ++ he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); ++ he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); ++ ++ idx++; ++ } ++ ++ sband->iftype_data = iftype_data; ++ sband->n_iftype_data = idx; ++} ++ ++static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; ++ u32 size = sizeof(struct ieee80211_supported_band); ++ ++ sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); ++ if (!sband_2ghz) ++ goto err; ++ rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); ++ rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; ++ ++ sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); ++ if (!sband_5ghz) ++ goto err; ++ rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); ++ rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); ++ rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; ++ ++ return 0; ++ ++err: ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; ++ if (sband_2ghz) ++ kfree(sband_2ghz->iftype_data); ++ if (sband_5ghz) ++ kfree(sband_5ghz->iftype_data); ++ kfree(sband_2ghz); ++ kfree(sband_5ghz); ++ return -ENOMEM; ++} ++ ++static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ ++ kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); ++ kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); ++ kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); ++ kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; ++} ++ ++static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) ++{ ++ int i; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) ++ skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); ++ for (i = 0; i < RTW89_PHY_MAX; i++) ++ rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; ++} ++ ++int rtw89_core_start(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ rtwdev->mac.qta_mode = RTW89_QTA_SCC; ++ ret = rtw89_mac_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); ++ return ret; ++ } ++ ++ rtw89_btc_ntfy_poweron(rtwdev); ++ ++ /* efuse process */ ++ ++ /* pre-config BB/RF, BB reset/RFC reset */ ++ rtw89_mac_disable_bb_rf(rtwdev); ++ rtw89_mac_enable_bb_rf(rtwdev); ++ rtw89_phy_init_bb_reg(rtwdev); ++ rtw89_phy_init_rf_reg(rtwdev); ++ ++ rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); ++ ++ rtw89_phy_dm_init(rtwdev); ++ ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); ++ rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); ++ ++ ret = rtw89_hci_start(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to start hci\n"); ++ return ret; ++ } ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, ++ RTW89_TRACK_WORK_PERIOD); ++ ++ set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); ++ rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); ++ ++ return 0; ++} ++ ++void rtw89_core_stop(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ /* Prvent to stop twice; enter_ips and ops_stop */ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ return; ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); ++ ++ clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ ++ mutex_unlock(&rtwdev->mutex); ++ ++ cancel_work_sync(&rtwdev->c2h_work); ++ cancel_work_sync(&btc->eapol_notify_work); ++ cancel_work_sync(&btc->arp_notify_work); ++ cancel_work_sync(&btc->dhcp_notify_work); ++ cancel_work_sync(&btc->wl_sta_notify_work); ++ cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); ++ cancel_delayed_work_sync(&rtwdev->track_work); ++ cancel_delayed_work_sync(&rtwdev->coex_act1_work); ++ cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); ++ cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); ++ cancel_delayed_work_sync(&rtwdev->cfo_track_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ rtw89_btc_ntfy_poweroff(rtwdev); ++ rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); ++ rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); ++ rtw89_hci_stop(rtwdev); ++ rtw89_hci_deinit(rtwdev); ++ rtw89_mac_pwr_off(rtwdev); ++ rtw89_hci_reset(rtwdev); ++} ++ ++int rtw89_core_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ int ret; ++ ++ INIT_LIST_HEAD(&rtwdev->ba_list); ++ INIT_LIST_HEAD(&rtwdev->rtwvifs_list); ++ INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); ++ INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); ++ INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); ++ INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); ++ INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); ++ rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); ++ spin_lock_init(&rtwdev->ba_lock); ++ mutex_init(&rtwdev->mutex); ++ mutex_init(&rtwdev->rf_mutex); ++ rtwdev->total_sta_assoc = 0; ++ ++ INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); ++ skb_queue_head_init(&rtwdev->c2h_queue); ++ rtw89_core_ppdu_sts_init(rtwdev); ++ rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); ++ ++ rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); ++ rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; ++ ++ INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); ++ INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); ++ INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); ++ INIT_WORK(&btc->wl_sta_notify_work, rtw89_btc_ntfy_wl_sta_work); ++ ++ ret = rtw89_load_firmware(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "no firmware loaded\n"); ++ return ret; ++ } ++ rtw89_ser_init(rtwdev); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_core_init); ++ ++void rtw89_core_deinit(struct rtw89_dev *rtwdev) ++{ ++ rtw89_ser_deinit(rtwdev); ++ rtw89_unload_firmware(rtwdev); ++ ++ destroy_workqueue(rtwdev->txq_wq); ++ mutex_destroy(&rtwdev->rf_mutex); ++ mutex_destroy(&rtwdev->mutex); ++} ++EXPORT_SYMBOL(rtw89_core_deinit); ++ ++static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) ++{ ++ u8 cv; ++ ++ cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); ++ if (cv <= CHIP_CBV) { ++ if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) ++ cv = CHIP_CAV; ++ else ++ cv = CHIP_CBV; ++ } ++ ++ rtwdev->hal.cv = cv; ++} ++ ++static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_partial_init(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_parse_efuse_map(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_parse_phycap_map(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_setup_phycap(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_pwr_off(rtwdev); ++ ++ return 0; ++} ++ ++static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) ++{ ++ rtw89_chip_fem_setup(rtwdev); ++ ++ return 0; ++} ++ ++int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ rtw89_read_chip_ver(rtwdev); ++ ++ ret = rtw89_wait_firmware_completion(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to wait firmware completion\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_recognize(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to recognize firmware\n"); ++ return ret; ++ } ++ ++ ret = rtw89_chip_efuse_info_setup(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_chip_board_info_setup(rtwdev); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_chip_info_setup); ++ ++static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ int ret; ++ int tx_headroom = IEEE80211_HT_CTL_LEN; ++ ++ hw->vif_data_size = sizeof(struct rtw89_vif); ++ hw->sta_data_size = sizeof(struct rtw89_sta); ++ hw->txq_data_size = sizeof(struct rtw89_txq); ++ ++ SET_IEEE80211_PERM_ADDR(hw, efuse->addr); ++ ++ hw->extra_tx_headroom = tx_headroom; ++ hw->queues = IEEE80211_NUM_ACS; ++ hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; ++ hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; ++ ++ ieee80211_hw_set(hw, SIGNAL_DBM); ++ ieee80211_hw_set(hw, HAS_RATE_CONTROL); ++ ieee80211_hw_set(hw, MFP_CAPABLE); ++ ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); ++ ieee80211_hw_set(hw, AMPDU_AGGREGATION); ++ ieee80211_hw_set(hw, RX_INCLUDES_FCS); ++ ieee80211_hw_set(hw, TX_AMSDU); ++ ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); ++ ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); ++ ieee80211_hw_set(hw, SUPPORTS_PS); ++ ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); ++ ++ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); ++ hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; ++ hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; ++ ++ hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; ++ ++ wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); ++ ++ ret = rtw89_core_set_supported_band(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set supported band\n"); ++ return ret; ++ } ++ ++ hw->wiphy->reg_notifier = rtw89_regd_notifier; ++ hw->wiphy->sar_capa = &rtw89_sar_capa; ++ ++ ret = ieee80211_register_hw(hw); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register hw\n"); ++ goto err; ++ } ++ ++ ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init regd\n"); ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ ++ ieee80211_unregister_hw(hw); ++ rtw89_core_clr_supported_band(rtwdev); ++} ++ ++int rtw89_core_register(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_core_register_hw(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register core hw\n"); ++ return ret; ++ } ++ ++ rtw89_debugfs_init(rtwdev); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_core_register); ++ ++void rtw89_core_unregister(struct rtw89_dev *rtwdev) ++{ ++ rtw89_core_unregister_hw(rtwdev); ++} ++EXPORT_SYMBOL(rtw89_core_unregister); ++ ++MODULE_AUTHOR("Realtek Corporation"); ++MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +new file mode 100644 +index 000000000000..ce46251edee6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -0,0 +1,3360 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_CORE_H__ ++#define __RTW89_CORE_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rtw89_dev; ++ ++extern const struct ieee80211_ops rtw89_ops; ++extern const struct rtw89_chip_info rtw8852a_chip_info; ++ ++#define MASKBYTE0 0xff ++#define MASKBYTE1 0xff00 ++#define MASKBYTE2 0xff0000 ++#define MASKBYTE3 0xff000000 ++#define MASKBYTE4 0xff00000000ULL ++#define MASKHWORD 0xffff0000 ++#define MASKLWORD 0x0000ffff ++#define MASKDWORD 0xffffffff ++#define RFREG_MASK 0xfffff ++#define INV_RF_DATA 0xffffffff ++ ++#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) ++#define CFO_TRACK_MAX_USER 64 ++#define MAX_RSSI 110 ++#define RSSI_FACTOR 1 ++#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) ++#define RTW89_MAX_HW_PORT_NUM 5 ++ ++#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) ++#define RTW89_HTC_VARIANT_HE 3 ++#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) ++#define RTW89_HTC_VARIANT_HE_CID_OM 1 ++#define RTW89_HTC_VARIANT_HE_CID_CAS 6 ++#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) ++ ++#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) ++enum htc_om_channel_width { ++ HTC_OM_CHANNEL_WIDTH_20 = 0, ++ HTC_OM_CHANNEL_WIDTH_40 = 1, ++ HTC_OM_CHANNEL_WIDTH_80 = 2, ++ HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, ++}; ++#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) ++#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) ++#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) ++#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) ++#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) ++#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) ++ ++enum rtw89_subband { ++ RTW89_CH_2G = 0, ++ RTW89_CH_5G_BAND_1 = 1, ++ /* RTW89_CH_5G_BAND_2 = 2, unused */ ++ RTW89_CH_5G_BAND_3 = 3, ++ RTW89_CH_5G_BAND_4 = 4, ++ ++ RTW89_SUBBAND_NR, ++}; ++ ++enum rtw89_hci_type { ++ RTW89_HCI_TYPE_PCIE, ++ RTW89_HCI_TYPE_USB, ++ RTW89_HCI_TYPE_SDIO, ++}; ++ ++enum rtw89_core_chip_id { ++ RTL8852A, ++ RTL8852B, ++ RTL8852C, ++}; ++ ++enum rtw89_cv { ++ CHIP_CAV, ++ CHIP_CBV, ++ CHIP_CCV, ++ CHIP_CDV, ++ CHIP_CEV, ++ CHIP_CFV, ++ CHIP_CV_MAX, ++ CHIP_CV_INVALID = CHIP_CV_MAX, ++}; ++ ++enum rtw89_core_tx_type { ++ RTW89_CORE_TX_TYPE_DATA, ++ RTW89_CORE_TX_TYPE_MGMT, ++ RTW89_CORE_TX_TYPE_FWCMD, ++}; ++ ++enum rtw89_core_rx_type { ++ RTW89_CORE_RX_TYPE_WIFI = 0, ++ RTW89_CORE_RX_TYPE_PPDU_STAT = 1, ++ RTW89_CORE_RX_TYPE_CHAN_INFO = 2, ++ RTW89_CORE_RX_TYPE_BB_SCOPE = 3, ++ RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, ++ RTW89_CORE_RX_TYPE_SS2FW = 5, ++ RTW89_CORE_RX_TYPE_TX_REPORT = 6, ++ RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, ++ RTW89_CORE_RX_TYPE_DFS_REPORT = 8, ++ RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, ++ RTW89_CORE_RX_TYPE_C2H = 10, ++ RTW89_CORE_RX_TYPE_CSI = 11, ++ RTW89_CORE_RX_TYPE_CQI = 12, ++}; ++ ++enum rtw89_txq_flags { ++ RTW89_TXQ_F_AMPDU = 0, ++ RTW89_TXQ_F_BLOCK_BA = 1, ++}; ++ ++enum rtw89_net_type { ++ RTW89_NET_TYPE_NO_LINK = 0, ++ RTW89_NET_TYPE_AD_HOC = 1, ++ RTW89_NET_TYPE_INFRA = 2, ++ RTW89_NET_TYPE_AP_MODE = 3, ++}; ++ ++enum rtw89_wifi_role { ++ RTW89_WIFI_ROLE_NONE, ++ RTW89_WIFI_ROLE_STATION, ++ RTW89_WIFI_ROLE_AP, ++ RTW89_WIFI_ROLE_AP_VLAN, ++ RTW89_WIFI_ROLE_ADHOC, ++ RTW89_WIFI_ROLE_ADHOC_MASTER, ++ RTW89_WIFI_ROLE_MESH_POINT, ++ RTW89_WIFI_ROLE_MONITOR, ++ RTW89_WIFI_ROLE_P2P_DEVICE, ++ RTW89_WIFI_ROLE_P2P_CLIENT, ++ RTW89_WIFI_ROLE_P2P_GO, ++ RTW89_WIFI_ROLE_NAN, ++ RTW89_WIFI_ROLE_MLME_MAX ++}; ++ ++enum rtw89_upd_mode { ++ RTW89_VIF_CREATE, ++ RTW89_VIF_REMOVE, ++ RTW89_VIF_TYPE_CHANGE, ++ RTW89_VIF_INFO_CHANGE, ++ RTW89_VIF_CON_DISCONN ++}; ++ ++enum rtw89_self_role { ++ RTW89_SELF_ROLE_CLIENT, ++ RTW89_SELF_ROLE_AP, ++ RTW89_SELF_ROLE_AP_CLIENT ++}; ++ ++enum rtw89_msk_sO_el { ++ RTW89_NO_MSK, ++ RTW89_SMA, ++ RTW89_TMA, ++ RTW89_BSSID ++}; ++ ++enum rtw89_sch_tx_sel { ++ RTW89_SCH_TX_SEL_ALL, ++ RTW89_SCH_TX_SEL_HIQ, ++ RTW89_SCH_TX_SEL_MG0, ++ RTW89_SCH_TX_SEL_MACID, ++}; ++ ++/* RTW89_ADDR_CAM_SEC_NONE : not enabled ++ * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast ++ * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP ++ * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP ++ */ ++enum rtw89_add_cam_sec_mode { ++ RTW89_ADDR_CAM_SEC_NONE = 0, ++ RTW89_ADDR_CAM_SEC_ALL_UNI = 1, ++ RTW89_ADDR_CAM_SEC_NORMAL = 2, ++ RTW89_ADDR_CAM_SEC_4GROUP = 3, ++}; ++ ++enum rtw89_sec_key_type { ++ RTW89_SEC_KEY_TYPE_NONE = 0, ++ RTW89_SEC_KEY_TYPE_WEP40 = 1, ++ RTW89_SEC_KEY_TYPE_WEP104 = 2, ++ RTW89_SEC_KEY_TYPE_TKIP = 3, ++ RTW89_SEC_KEY_TYPE_WAPI = 4, ++ RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, ++ RTW89_SEC_KEY_TYPE_CCMP128 = 6, ++ RTW89_SEC_KEY_TYPE_CCMP256 = 7, ++ RTW89_SEC_KEY_TYPE_GCMP128 = 8, ++ RTW89_SEC_KEY_TYPE_GCMP256 = 9, ++ RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, ++}; ++ ++enum rtw89_port { ++ RTW89_PORT_0 = 0, ++ RTW89_PORT_1 = 1, ++ RTW89_PORT_2 = 2, ++ RTW89_PORT_3 = 3, ++ RTW89_PORT_4 = 4, ++ RTW89_PORT_NUM ++}; ++ ++enum rtw89_band { ++ RTW89_BAND_2G = 0, ++ RTW89_BAND_5G = 1, ++ RTW89_BAND_MAX, ++}; ++ ++enum rtw89_hw_rate { ++ RTW89_HW_RATE_CCK1 = 0x0, ++ RTW89_HW_RATE_CCK2 = 0x1, ++ RTW89_HW_RATE_CCK5_5 = 0x2, ++ RTW89_HW_RATE_CCK11 = 0x3, ++ RTW89_HW_RATE_OFDM6 = 0x4, ++ RTW89_HW_RATE_OFDM9 = 0x5, ++ RTW89_HW_RATE_OFDM12 = 0x6, ++ RTW89_HW_RATE_OFDM18 = 0x7, ++ RTW89_HW_RATE_OFDM24 = 0x8, ++ RTW89_HW_RATE_OFDM36 = 0x9, ++ RTW89_HW_RATE_OFDM48 = 0xA, ++ RTW89_HW_RATE_OFDM54 = 0xB, ++ RTW89_HW_RATE_MCS0 = 0x80, ++ RTW89_HW_RATE_MCS1 = 0x81, ++ RTW89_HW_RATE_MCS2 = 0x82, ++ RTW89_HW_RATE_MCS3 = 0x83, ++ RTW89_HW_RATE_MCS4 = 0x84, ++ RTW89_HW_RATE_MCS5 = 0x85, ++ RTW89_HW_RATE_MCS6 = 0x86, ++ RTW89_HW_RATE_MCS7 = 0x87, ++ RTW89_HW_RATE_MCS8 = 0x88, ++ RTW89_HW_RATE_MCS9 = 0x89, ++ RTW89_HW_RATE_MCS10 = 0x8A, ++ RTW89_HW_RATE_MCS11 = 0x8B, ++ RTW89_HW_RATE_MCS12 = 0x8C, ++ RTW89_HW_RATE_MCS13 = 0x8D, ++ RTW89_HW_RATE_MCS14 = 0x8E, ++ RTW89_HW_RATE_MCS15 = 0x8F, ++ RTW89_HW_RATE_MCS16 = 0x90, ++ RTW89_HW_RATE_MCS17 = 0x91, ++ RTW89_HW_RATE_MCS18 = 0x92, ++ RTW89_HW_RATE_MCS19 = 0x93, ++ RTW89_HW_RATE_MCS20 = 0x94, ++ RTW89_HW_RATE_MCS21 = 0x95, ++ RTW89_HW_RATE_MCS22 = 0x96, ++ RTW89_HW_RATE_MCS23 = 0x97, ++ RTW89_HW_RATE_MCS24 = 0x98, ++ RTW89_HW_RATE_MCS25 = 0x99, ++ RTW89_HW_RATE_MCS26 = 0x9A, ++ RTW89_HW_RATE_MCS27 = 0x9B, ++ RTW89_HW_RATE_MCS28 = 0x9C, ++ RTW89_HW_RATE_MCS29 = 0x9D, ++ RTW89_HW_RATE_MCS30 = 0x9E, ++ RTW89_HW_RATE_MCS31 = 0x9F, ++ RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, ++ RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, ++ RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, ++ RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, ++ RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, ++ RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, ++ RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, ++ RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, ++ RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, ++ RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, ++ RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, ++ RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, ++ RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, ++ RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, ++ RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, ++ RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, ++ RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, ++ RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, ++ RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, ++ RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, ++ RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, ++ RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, ++ RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, ++ RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, ++ RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, ++ RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, ++ RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, ++ RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, ++ RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, ++ RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, ++ RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, ++ RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, ++ RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, ++ RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, ++ RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, ++ RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, ++ RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, ++ RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, ++ RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, ++ RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, ++ RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, ++ RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, ++ RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, ++ RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, ++ RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, ++ RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, ++ RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, ++ RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, ++ RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, ++ RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, ++ RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, ++ RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, ++ RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, ++ RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, ++ RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, ++ RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, ++ RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, ++ RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, ++ RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, ++ RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, ++ RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, ++ RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, ++ RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, ++ RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, ++ RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, ++ RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, ++ RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, ++ RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, ++ RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, ++ RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, ++ RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, ++ RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, ++ RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, ++ RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, ++ RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, ++ RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, ++ RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, ++ RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, ++ RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, ++ RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, ++ RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, ++ RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, ++ RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, ++ RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, ++ RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, ++ RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, ++ RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, ++ RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, ++ RTW89_HW_RATE_NR, ++ ++ RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), ++ RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), ++}; ++ ++/* 2G channels, ++ * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 ++ */ ++#define RTW89_2G_CH_NUM 14 ++ ++/* 5G channels, ++ * 36, 38, 40, 42, 44, 46, 48, 50, ++ * 52, 54, 56, 58, 60, 62, 64, ++ * 100, 102, 104, 106, 108, 110, 112, 114, ++ * 116, 118, 120, 122, 124, 126, 128, 130, ++ * 132, 134, 136, 138, 140, 142, 144, ++ * 149, 151, 153, 155, 157, 159, 161, 163, ++ * 165, 167, 169, 171, 173, 175, 177 ++ */ ++#define RTW89_5G_CH_NUM 53 ++ ++enum rtw89_rate_section { ++ RTW89_RS_CCK, ++ RTW89_RS_OFDM, ++ RTW89_RS_MCS, /* for HT/VHT/HE */ ++ RTW89_RS_HEDCM, ++ RTW89_RS_OFFSET, ++ RTW89_RS_MAX, ++ RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, ++}; ++ ++enum rtw89_rate_max { ++ RTW89_RATE_CCK_MAX = 4, ++ RTW89_RATE_OFDM_MAX = 8, ++ RTW89_RATE_MCS_MAX = 12, ++ RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ ++ RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ ++}; ++ ++enum rtw89_nss { ++ RTW89_NSS_1 = 0, ++ RTW89_NSS_2 = 1, ++ /* HE DCM only support 1ss and 2ss */ ++ RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, ++ RTW89_NSS_3 = 2, ++ RTW89_NSS_4 = 3, ++ RTW89_NSS_MAX, ++}; ++ ++enum rtw89_ntx { ++ RTW89_1TX = 0, ++ RTW89_2TX = 1, ++ RTW89_NTX_NUM, ++}; ++ ++enum rtw89_beamforming_type { ++ RTW89_NONBF = 0, ++ RTW89_BF = 1, ++ RTW89_BF_NUM, ++}; ++ ++enum rtw89_regulation_type { ++ RTW89_WW = 0, ++ RTW89_ETSI = 1, ++ RTW89_FCC = 2, ++ RTW89_MKK = 3, ++ RTW89_NA = 4, ++ RTW89_IC = 5, ++ RTW89_KCC = 6, ++ RTW89_NCC = 7, ++ RTW89_CHILE = 8, ++ RTW89_ACMA = 9, ++ RTW89_MEXICO = 10, ++ RTW89_UKRAINE = 11, ++ RTW89_CN = 12, ++ RTW89_REGD_NUM, ++}; ++ ++extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX]; ++extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX]; ++ ++struct rtw89_txpwr_byrate { ++ s8 cck[RTW89_RATE_CCK_MAX]; ++ s8 ofdm[RTW89_RATE_OFDM_MAX]; ++ s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; ++ s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; ++ s8 offset[RTW89_RATE_OFFSET_MAX]; ++}; ++ ++enum rtw89_bandwidth_section_num { ++ RTW89_BW20_SEC_NUM = 8, ++ RTW89_BW40_SEC_NUM = 4, ++ RTW89_BW80_SEC_NUM = 2, ++}; ++ ++struct rtw89_txpwr_limit { ++ s8 cck_20m[RTW89_BF_NUM]; ++ s8 cck_40m[RTW89_BF_NUM]; ++ s8 ofdm[RTW89_BF_NUM]; ++ s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_160m[RTW89_BF_NUM]; ++ s8 mcs_40m_0p5[RTW89_BF_NUM]; ++ s8 mcs_40m_2p5[RTW89_BF_NUM]; ++}; ++ ++#define RTW89_RU_SEC_NUM 8 ++ ++struct rtw89_txpwr_limit_ru { ++ s8 ru26[RTW89_RU_SEC_NUM]; ++ s8 ru52[RTW89_RU_SEC_NUM]; ++ s8 ru106[RTW89_RU_SEC_NUM]; ++}; ++ ++struct rtw89_rate_desc { ++ enum rtw89_nss nss; ++ enum rtw89_rate_section rs; ++ u8 idx; ++}; ++ ++#define PHY_STS_HDR_LEN 8 ++#define RF_PATH_MAX 4 ++#define RTW89_MAX_PPDU_CNT 8 ++struct rtw89_rx_phy_ppdu { ++ u8 *buf; ++ u32 len; ++ u8 rssi_avg; ++ s8 rssi[RF_PATH_MAX]; ++ u8 mac_id; ++ bool to_self; ++ bool valid; ++}; ++ ++enum rtw89_mac_idx { ++ RTW89_MAC_0 = 0, ++ RTW89_MAC_1 = 1, ++}; ++ ++enum rtw89_phy_idx { ++ RTW89_PHY_0 = 0, ++ RTW89_PHY_1 = 1, ++ RTW89_PHY_MAX ++}; ++ ++enum rtw89_rf_path { ++ RF_PATH_A = 0, ++ RF_PATH_B = 1, ++ RF_PATH_C = 2, ++ RF_PATH_D = 3, ++ RF_PATH_AB, ++ RF_PATH_AC, ++ RF_PATH_AD, ++ RF_PATH_BC, ++ RF_PATH_BD, ++ RF_PATH_CD, ++ RF_PATH_ABC, ++ RF_PATH_ABD, ++ RF_PATH_ACD, ++ RF_PATH_BCD, ++ RF_PATH_ABCD, ++}; ++ ++enum rtw89_rf_path_bit { ++ RF_A = BIT(0), ++ RF_B = BIT(1), ++ RF_C = BIT(2), ++ RF_D = BIT(3), ++ ++ RF_AB = (RF_A | RF_B), ++ RF_AC = (RF_A | RF_C), ++ RF_AD = (RF_A | RF_D), ++ RF_BC = (RF_B | RF_C), ++ RF_BD = (RF_B | RF_D), ++ RF_CD = (RF_C | RF_D), ++ ++ RF_ABC = (RF_A | RF_B | RF_C), ++ RF_ABD = (RF_A | RF_B | RF_D), ++ RF_ACD = (RF_A | RF_C | RF_D), ++ RF_BCD = (RF_B | RF_C | RF_D), ++ ++ RF_ABCD = (RF_A | RF_B | RF_C | RF_D), ++}; ++ ++enum rtw89_bandwidth { ++ RTW89_CHANNEL_WIDTH_20 = 0, ++ RTW89_CHANNEL_WIDTH_40 = 1, ++ RTW89_CHANNEL_WIDTH_80 = 2, ++ RTW89_CHANNEL_WIDTH_160 = 3, ++ RTW89_CHANNEL_WIDTH_80_80 = 4, ++ RTW89_CHANNEL_WIDTH_5 = 5, ++ RTW89_CHANNEL_WIDTH_10 = 6, ++}; ++ ++enum rtw89_ps_mode { ++ RTW89_PS_MODE_NONE = 0, ++ RTW89_PS_MODE_RFOFF = 1, ++ RTW89_PS_MODE_CLK_GATED = 2, ++ RTW89_PS_MODE_PWR_GATED = 3, ++}; ++ ++#define RTW89_MAX_CHANNEL_WIDTH RTW89_CHANNEL_WIDTH_80 ++#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) ++#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) ++#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) ++ ++enum rtw89_ru_bandwidth { ++ RTW89_RU26 = 0, ++ RTW89_RU52 = 1, ++ RTW89_RU106 = 2, ++ RTW89_RU_NUM, ++}; ++ ++enum rtw89_sc_offset { ++ RTW89_SC_DONT_CARE = 0, ++ RTW89_SC_20_UPPER = 1, ++ RTW89_SC_20_LOWER = 2, ++ RTW89_SC_20_UPMOST = 3, ++ RTW89_SC_20_LOWEST = 4, ++ RTW89_SC_40_UPPER = 9, ++ RTW89_SC_40_LOWER = 10, ++}; ++ ++struct rtw89_channel_params { ++ u8 center_chan; ++ u8 primary_chan; ++ u8 bandwidth; ++ u8 pri_ch_idx; ++ u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; ++}; ++ ++struct rtw89_channel_help_params { ++ u16 tx_en; ++}; ++ ++struct rtw89_port_reg { ++ u32 port_cfg; ++ u32 tbtt_prohib; ++ u32 bcn_area; ++ u32 bcn_early; ++ u32 tbtt_early; ++ u32 tbtt_agg; ++ u32 bcn_space; ++ u32 bcn_forcetx; ++ u32 bcn_err_cnt; ++ u32 bcn_err_flag; ++ u32 dtim_ctrl; ++ u32 tbtt_shift; ++ u32 bcn_cnt_tmr; ++ u32 tsftr_l; ++ u32 tsftr_h; ++}; ++ ++struct rtw89_txwd_body { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++} __packed; ++ ++struct rtw89_txwd_info { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++} __packed; ++ ++struct rtw89_rx_desc_info { ++ u16 pkt_size; ++ u8 pkt_type; ++ u8 drv_info_size; ++ u8 shift; ++ u8 wl_hd_iv_len; ++ bool long_rxdesc; ++ bool bb_sel; ++ bool mac_info_valid; ++ u16 data_rate; ++ u8 gi_ltf; ++ u8 bw; ++ u32 free_run_cnt; ++ u8 user_id; ++ bool sr_en; ++ u8 ppdu_cnt; ++ u8 ppdu_type; ++ bool icv_err; ++ bool crc32_err; ++ bool hw_dec; ++ bool sw_dec; ++ bool addr1_match; ++ u8 frag; ++ u16 seq; ++ u8 frame_type; ++ u8 rx_pl_id; ++ bool addr_cam_valid; ++ u8 addr_cam_id; ++ u8 sec_cam_id; ++ u8 mac_id; ++ u16 offset; ++ bool ready; ++}; ++ ++struct rtw89_rxdesc_short { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++} __packed; ++ ++struct rtw89_rxdesc_long { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++ __le32 dword6; ++ __le32 dword7; ++} __packed; ++ ++struct rtw89_tx_desc_info { ++ u16 pkt_size; ++ u8 wp_offset; ++ u8 qsel; ++ u8 ch_dma; ++ u8 hdr_llc_len; ++ bool is_bmc; ++ bool en_wd_info; ++ bool wd_page; ++ bool use_rate; ++ bool dis_data_fb; ++ bool tid_indicate; ++ bool agg_en; ++ bool bk; ++ u8 ampdu_density; ++ u8 ampdu_num; ++ bool sec_en; ++ u8 sec_type; ++ u8 sec_cam_idx; ++ u16 data_rate; ++ bool fw_dl; ++ u16 seq; ++ bool a_ctrl_bsr; ++}; ++ ++struct rtw89_core_tx_request { ++ enum rtw89_core_tx_type tx_type; ++ ++ struct sk_buff *skb; ++ struct ieee80211_vif *vif; ++ struct ieee80211_sta *sta; ++ struct rtw89_tx_desc_info desc_info; ++}; ++ ++struct rtw89_txq { ++ struct list_head list; ++ unsigned long flags; ++ int wait_cnt; ++}; ++ ++struct rtw89_mac_ax_gnt { ++ u8 gnt_bt_sw_en; ++ u8 gnt_bt; ++ u8 gnt_wl_sw_en; ++ u8 gnt_wl; ++}; ++ ++#define RTW89_MAC_AX_COEX_GNT_NR 2 ++struct rtw89_mac_ax_coex_gnt { ++ struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; ++}; ++ ++enum rtw89_btc_ncnt { ++ BTC_NCNT_POWER_ON = 0x0, ++ BTC_NCNT_POWER_OFF, ++ BTC_NCNT_INIT_COEX, ++ BTC_NCNT_SCAN_START, ++ BTC_NCNT_SCAN_FINISH, ++ BTC_NCNT_SPECIAL_PACKET, ++ BTC_NCNT_SWITCH_BAND, ++ BTC_NCNT_RFK_TIMEOUT, ++ BTC_NCNT_SHOW_COEX_INFO, ++ BTC_NCNT_ROLE_INFO, ++ BTC_NCNT_CONTROL, ++ BTC_NCNT_RADIO_STATE, ++ BTC_NCNT_CUSTOMERIZE, ++ BTC_NCNT_WL_RFK, ++ BTC_NCNT_WL_STA, ++ BTC_NCNT_FWINFO, ++ BTC_NCNT_TIMER, ++ BTC_NCNT_NUM ++}; ++ ++enum rtw89_btc_btinfo { ++ BTC_BTINFO_L0 = 0, ++ BTC_BTINFO_L1, ++ BTC_BTINFO_L2, ++ BTC_BTINFO_L3, ++ BTC_BTINFO_H0, ++ BTC_BTINFO_H1, ++ BTC_BTINFO_H2, ++ BTC_BTINFO_H3, ++ BTC_BTINFO_MAX ++}; ++ ++enum rtw89_btc_dcnt { ++ BTC_DCNT_RUN = 0x0, ++ BTC_DCNT_CX_RUNINFO, ++ BTC_DCNT_RPT, ++ BTC_DCNT_RPT_FREEZE, ++ BTC_DCNT_CYCLE, ++ BTC_DCNT_CYCLE_FREEZE, ++ BTC_DCNT_W1, ++ BTC_DCNT_W1_FREEZE, ++ BTC_DCNT_B1, ++ BTC_DCNT_B1_FREEZE, ++ BTC_DCNT_TDMA_NONSYNC, ++ BTC_DCNT_SLOT_NONSYNC, ++ BTC_DCNT_BTCNT_FREEZE, ++ BTC_DCNT_WL_SLOT_DRIFT, ++ BTC_DCNT_WL_STA_LAST, ++ BTC_DCNT_NUM, ++}; ++ ++enum rtw89_btc_wl_state_cnt { ++ BTC_WCNT_SCANAP = 0x0, ++ BTC_WCNT_DHCP, ++ BTC_WCNT_EAPOL, ++ BTC_WCNT_ARP, ++ BTC_WCNT_SCBDUPDATE, ++ BTC_WCNT_RFK_REQ, ++ BTC_WCNT_RFK_GO, ++ BTC_WCNT_RFK_REJECT, ++ BTC_WCNT_RFK_TIMEOUT, ++ BTC_WCNT_CH_UPDATE, ++ BTC_WCNT_NUM ++}; ++ ++enum rtw89_btc_bt_state_cnt { ++ BTC_BCNT_RETRY = 0x0, ++ BTC_BCNT_REINIT, ++ BTC_BCNT_REENABLE, ++ BTC_BCNT_SCBDREAD, ++ BTC_BCNT_RELINK, ++ BTC_BCNT_IGNOWL, ++ BTC_BCNT_INQPAG, ++ BTC_BCNT_INQ, ++ BTC_BCNT_PAGE, ++ BTC_BCNT_ROLESW, ++ BTC_BCNT_AFH, ++ BTC_BCNT_INFOUPDATE, ++ BTC_BCNT_INFOSAME, ++ BTC_BCNT_SCBDUPDATE, ++ BTC_BCNT_HIPRI_TX, ++ BTC_BCNT_HIPRI_RX, ++ BTC_BCNT_LOPRI_TX, ++ BTC_BCNT_LOPRI_RX, ++ BTC_BCNT_RATECHG, ++ BTC_BCNT_NUM ++}; ++ ++enum rtw89_btc_bt_profile { ++ BTC_BT_NOPROFILE = 0, ++ BTC_BT_HFP = BIT(0), ++ BTC_BT_HID = BIT(1), ++ BTC_BT_A2DP = BIT(2), ++ BTC_BT_PAN = BIT(3), ++ BTC_PROFILE_MAX = 4, ++}; ++ ++struct rtw89_btc_ant_info { ++ u8 type; /* shared, dedicated */ ++ u8 num; ++ u8 isolation; ++ ++ u8 single_pos: 1;/* Single antenna at S0 or S1 */ ++ u8 diversity: 1; ++}; ++ ++enum rtw89_tfc_dir { ++ RTW89_TFC_UL, ++ RTW89_TFC_DL, ++}; ++ ++struct rtw89_btc_wl_smap { ++ u32 busy: 1; ++ u32 scan: 1; ++ u32 connecting: 1; ++ u32 roaming: 1; ++ u32 _4way: 1; ++ u32 rf_off: 1; ++ u32 lps: 1; ++ u32 ips: 1; ++ u32 init_ok: 1; ++ u32 traffic_dir : 2; ++ u32 rf_off_pre: 1; ++ u32 lps_pre: 1; ++}; ++ ++enum rtw89_tfc_lv { ++ RTW89_TFC_IDLE, ++ RTW89_TFC_ULTRA_LOW, ++ RTW89_TFC_LOW, ++ RTW89_TFC_MID, ++ RTW89_TFC_HIGH, ++}; ++ ++#define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ ++DECLARE_EWMA(tp, 10, 2); ++ ++struct rtw89_traffic_stats { ++ /* units in bytes */ ++ u64 tx_unicast; ++ u64 rx_unicast; ++ u32 tx_avg_len; ++ u32 rx_avg_len; ++ ++ /* count for packets */ ++ u64 tx_cnt; ++ u64 rx_cnt; ++ ++ /* units in Mbps */ ++ u32 tx_throughput; ++ u32 rx_throughput; ++ u32 tx_throughput_raw; ++ u32 rx_throughput_raw; ++ enum rtw89_tfc_lv tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv; ++ struct ewma_tp tx_ewma_tp; ++ struct ewma_tp rx_ewma_tp; ++ ++ u16 tx_rate; ++ u16 rx_rate; ++}; ++ ++struct rtw89_btc_statistic { ++ u8 rssi; /* 0%~110% (dBm = rssi -110) */ ++ struct rtw89_traffic_stats traffic; ++}; ++ ++#define BTC_WL_RSSI_THMAX 4 ++ ++struct rtw89_btc_wl_link_info { ++ struct rtw89_btc_statistic stat; ++ enum rtw89_tfc_dir dir; ++ u8 rssi_state[BTC_WL_RSSI_THMAX]; ++ u8 mac_addr[ETH_ALEN]; ++ u8 busy; ++ u8 ch; ++ u8 bw; ++ u8 band; ++ u8 role; ++ u8 pid; ++ u8 phy; ++ u8 dtim_period; ++ u8 mode; ++ ++ u8 mac_id; ++ u8 tx_retry; ++ ++ u32 bcn_period; ++ u32 busy_t; ++ u32 tx_time; ++ u32 client_cnt; ++ u32 rx_rate_drop_cnt; ++ ++ u32 active: 1; ++ u32 noa: 1; ++ u32 client_ps: 1; ++ u32 connected: 2; ++}; ++ ++union rtw89_btc_wl_state_map { ++ u32 val; ++ struct rtw89_btc_wl_smap map; ++}; ++ ++struct rtw89_btc_bt_hfp_desc { ++ u32 exist: 1; ++ u32 type: 2; ++ u32 rsvd: 29; ++}; ++ ++struct rtw89_btc_bt_hid_desc { ++ u32 exist: 1; ++ u32 slot_info: 2; ++ u32 pair_cnt: 2; ++ u32 type: 8; ++ u32 rsvd: 19; ++}; ++ ++struct rtw89_btc_bt_a2dp_desc { ++ u8 exist: 1; ++ u8 exist_last: 1; ++ u8 play_latency: 1; ++ u8 type: 3; ++ u8 active: 1; ++ u8 sink: 1; ++ ++ u8 bitpool; ++ u16 vendor_id; ++ u32 device_name; ++ u32 flush_time; ++}; ++ ++struct rtw89_btc_bt_pan_desc { ++ u32 exist: 1; ++ u32 type: 1; ++ u32 active: 1; ++ u32 rsvd: 29; ++}; ++ ++struct rtw89_btc_bt_rfk_info { ++ u32 run: 1; ++ u32 req: 1; ++ u32 timeout: 1; ++ u32 rsvd: 29; ++}; ++ ++union rtw89_btc_bt_rfk_info_map { ++ u32 val; ++ struct rtw89_btc_bt_rfk_info map; ++}; ++ ++struct rtw89_btc_bt_ver_info { ++ u32 fw_coex; /* match with which coex_ver */ ++ u32 fw; ++}; ++ ++struct rtw89_btc_bool_sta_chg { ++ u32 now: 1; ++ u32 last: 1; ++ u32 remain: 1; ++ u32 srvd: 29; ++}; ++ ++struct rtw89_btc_u8_sta_chg { ++ u8 now; ++ u8 last; ++ u8 remain; ++ u8 rsvd; ++}; ++ ++struct rtw89_btc_wl_scan_info { ++ u8 band[RTW89_PHY_MAX]; ++ u8 phy_map; ++ u8 rsvd; ++}; ++ ++struct rtw89_btc_wl_dbcc_info { ++ u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ ++ u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ ++ u8 real_band[RTW89_PHY_MAX]; ++ u8 role[RTW89_PHY_MAX]; /* role in each phy */ ++}; ++ ++struct rtw89_btc_wl_active_role { ++ u8 connected: 1; ++ u8 pid: 3; ++ u8 phy: 1; ++ u8 noa: 1; ++ u8 band: 2; ++ ++ u8 client_ps: 1; ++ u8 bw: 7; ++ ++ u8 role; ++ u8 ch; ++ ++ u16 tx_lvl; ++ u16 rx_lvl; ++ u16 tx_rate; ++ u16 rx_rate; ++}; ++ ++struct rtw89_btc_wl_role_info_bpos { ++ u16 none: 1; ++ u16 station: 1; ++ u16 ap: 1; ++ u16 vap: 1; ++ u16 adhoc: 1; ++ u16 adhoc_master: 1; ++ u16 mesh: 1; ++ u16 moniter: 1; ++ u16 p2p_device: 1; ++ u16 p2p_gc: 1; ++ u16 p2p_go: 1; ++ u16 nan: 1; ++}; ++ ++union rtw89_btc_wl_role_info_map { ++ u16 val; ++ struct rtw89_btc_wl_role_info_bpos role; ++}; ++ ++struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ ++ u8 connect_cnt; ++ u8 link_mode; ++ union rtw89_btc_wl_role_info_map role_map; ++ struct rtw89_btc_wl_active_role active_role[RTW89_MAX_HW_PORT_NUM]; ++}; ++ ++struct rtw89_btc_wl_ver_info { ++ u32 fw_coex; /* match with which coex_ver */ ++ u32 fw; ++ u32 mac; ++ u32 bb; ++ u32 rf; ++}; ++ ++struct rtw89_btc_wl_afh_info { ++ u8 en; ++ u8 ch; ++ u8 bw; ++ u8 rsvd; ++} __packed; ++ ++struct rtw89_btc_wl_rfk_info { ++ u32 state: 2; ++ u32 path_map: 4; ++ u32 phy_map: 2; ++ u32 band: 2; ++ u32 type: 8; ++ u32 rsvd: 14; ++}; ++ ++struct rtw89_btc_bt_smap { ++ u32 connect: 1; ++ u32 ble_connect: 1; ++ u32 acl_busy: 1; ++ u32 sco_busy: 1; ++ u32 mesh_busy: 1; ++ u32 inq_pag: 1; ++}; ++ ++union rtw89_btc_bt_state_map { ++ u32 val; ++ struct rtw89_btc_bt_smap map; ++}; ++ ++#define BTC_BT_RSSI_THMAX 4 ++#define BTC_BT_AFH_GROUP 12 ++ ++struct rtw89_btc_bt_link_info { ++ struct rtw89_btc_u8_sta_chg profile_cnt; ++ struct rtw89_btc_bool_sta_chg multi_link; ++ struct rtw89_btc_bool_sta_chg relink; ++ struct rtw89_btc_bt_hfp_desc hfp_desc; ++ struct rtw89_btc_bt_hid_desc hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan_desc; ++ union rtw89_btc_bt_state_map status; ++ ++ u8 sut_pwr_level[BTC_PROFILE_MAX]; ++ u8 golden_rx_shift[BTC_PROFILE_MAX]; ++ u8 rssi_state[BTC_BT_RSSI_THMAX]; ++ u8 afh_map[BTC_BT_AFH_GROUP]; ++ ++ u32 role_sw: 1; ++ u32 slave_role: 1; ++ u32 afh_update: 1; ++ u32 cqddr: 1; ++ u32 rssi: 8; ++ u32 tx_3m: 1; ++ u32 rsvd: 19; ++}; ++ ++struct rtw89_btc_3rdcx_info { ++ u8 type; /* 0: none, 1:zigbee, 2:LTE */ ++ u8 hw_coex; ++ u16 rsvd; ++}; ++ ++struct rtw89_btc_dm_emap { ++ u32 init: 1; ++ u32 pta_owner: 1; ++ u32 wl_rfk_timeout: 1; ++ u32 bt_rfk_timeout: 1; ++ ++ u32 wl_fw_hang: 1; ++ u32 offload_mismatch: 1; ++ u32 cycle_hang: 1; ++ u32 w1_hang: 1; ++ ++ u32 b1_hang: 1; ++ u32 tdma_no_sync: 1; ++ u32 wl_slot_drift: 1; ++}; ++ ++union rtw89_btc_dm_error_map { ++ u32 val; ++ struct rtw89_btc_dm_emap map; ++}; ++ ++struct rtw89_btc_rf_para { ++ u32 tx_pwr_freerun; ++ u32 rx_gain_freerun; ++ u32 tx_pwr_perpkt; ++ u32 rx_gain_perpkt; ++}; ++ ++struct rtw89_btc_wl_info { ++ struct rtw89_btc_wl_link_info link_info[RTW89_MAX_HW_PORT_NUM]; ++ struct rtw89_btc_wl_rfk_info rfk_info; ++ struct rtw89_btc_wl_ver_info ver_info; ++ struct rtw89_btc_wl_afh_info afh_info; ++ struct rtw89_btc_wl_role_info role_info; ++ struct rtw89_btc_wl_scan_info scan_info; ++ struct rtw89_btc_wl_dbcc_info dbcc_info; ++ struct rtw89_btc_rf_para rf_para; ++ union rtw89_btc_wl_state_map status; ++ ++ u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; ++ u8 rssi_level; ++ ++ u32 scbd; ++}; ++ ++struct rtw89_btc_module { ++ struct rtw89_btc_ant_info ant; ++ u8 rfe_type; ++ u8 cv; ++ ++ u8 bt_solo: 1; ++ u8 bt_pos: 1; ++ u8 switch_type: 1; ++ ++ u8 rsvd; ++}; ++ ++#define RTW89_BTC_DM_MAXSTEP 30 ++#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) ++ ++struct rtw89_btc_dm_step { ++ u16 step[RTW89_BTC_DM_MAXSTEP]; ++ u8 step_pos; ++ bool step_ov; ++}; ++ ++struct rtw89_btc_init_info { ++ struct rtw89_btc_module module; ++ u8 wl_guard_ch; ++ ++ u8 wl_only: 1; ++ u8 wl_init_ok: 1; ++ u8 dbcc_en: 1; ++ u8 cx_other: 1; ++ u8 bt_only: 1; ++ ++ u16 rsvd; ++}; ++ ++struct rtw89_btc_wl_tx_limit_para { ++ u16 enable; ++ u32 tx_time; /* unit: us */ ++ u16 tx_retry; ++}; ++ ++struct rtw89_btc_bt_scan_info { ++ u16 win; ++ u16 intvl; ++ u32 enable: 1; ++ u32 interlace: 1; ++ u32 rsvd: 30; ++}; ++ ++enum rtw89_btc_bt_scan_type { ++ BTC_SCAN_INQ = 0, ++ BTC_SCAN_PAGE, ++ BTC_SCAN_BLE, ++ BTC_SCAN_INIT, ++ BTC_SCAN_TV, ++ BTC_SCAN_ADV, ++ BTC_SCAN_MAX1, ++}; ++ ++struct rtw89_btc_bt_info { ++ struct rtw89_btc_bt_link_info link_info; ++ struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; ++ struct rtw89_btc_bt_ver_info ver_info; ++ struct rtw89_btc_bool_sta_chg enable; ++ struct rtw89_btc_bool_sta_chg inq_pag; ++ struct rtw89_btc_rf_para rf_para; ++ union rtw89_btc_bt_rfk_info_map rfk_info; ++ ++ u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ ++ ++ u32 scbd; ++ u32 feature; ++ ++ u32 mbx_avl: 1; ++ u32 whql_test: 1; ++ u32 igno_wl: 1; ++ u32 reinit: 1; ++ u32 ble_scan_en: 1; ++ u32 btg_type: 1; ++ u32 inq: 1; ++ u32 pag: 1; ++ u32 run_patch_code: 1; ++ u32 hi_lna_rx: 1; ++ u32 rsvd: 22; ++}; ++ ++struct rtw89_btc_cx { ++ struct rtw89_btc_wl_info wl; ++ struct rtw89_btc_bt_info bt; ++ struct rtw89_btc_3rdcx_info other; ++ u32 state_map; ++ u32 cnt_bt[BTC_BCNT_NUM]; ++ u32 cnt_wl[BTC_WCNT_NUM]; ++}; ++ ++struct rtw89_btc_fbtc_tdma { ++ u8 type; ++ u8 rxflctrl; ++ u8 txpause; ++ u8 wtgle_n; ++ u8 leak_n; ++ u8 ext_ctrl; ++ u8 rsvd0; ++ u8 rsvd1; ++} __packed; ++ ++#define CXMREG_MAX 30 ++#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ ++#define BTCRPT_VER 1 ++#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ ++ ++enum rtw89_btc_bt_rfk_counter { ++ BTC_BCNT_RFK_REQ = 0, ++ BTC_BCNT_RFK_GO = 1, ++ BTC_BCNT_RFK_REJECT = 2, ++ BTC_BCNT_RFK_FAIL = 3, ++ BTC_BCNT_RFK_TIMEOUT = 4, ++ BTC_BCNT_RFK_MAX ++}; ++ ++struct rtw89_btc_fbtc_rpt_ctrl { ++ u16 fver; ++ u16 rpt_cnt; /* tmr counters */ ++ u32 wl_fw_coex_ver; /* match which driver's coex version */ ++ u32 wl_fw_cx_offload; ++ u32 wl_fw_ver; ++ u32 rpt_enable; ++ u32 rpt_para; /* ms */ ++ u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ ++ u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ ++ u32 mb_recv_cnt; /* fw recv mailbox counter */ ++ u32 mb_a2dp_empty_cnt; /* a2dp empty count */ ++ u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ ++ u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ ++ u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; ++ u32 c2h_cnt; /* fw send c2h counter */ ++ u32 h2c_cnt; /* fw recv h2c counter */ ++} __packed; ++ ++enum rtw89_fbtc_ext_ctrl_type { ++ CXECTL_OFF = 0x0, /* tdma off */ ++ CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ ++ CXECTL_EXT = 0x2, ++ CXECTL_MAX ++}; ++ ++union rtw89_btc_fbtc_rxflct { ++ u8 val; ++ u8 type: 3; ++ u8 tgln_n: 5; ++}; ++ ++enum rtw89_btc_cxst_state { ++ CXST_OFF = 0x0, ++ CXST_B2W = 0x1, ++ CXST_W1 = 0x2, ++ CXST_W2 = 0x3, ++ CXST_W2B = 0x4, ++ CXST_B1 = 0x5, ++ CXST_B2 = 0x6, ++ CXST_B3 = 0x7, ++ CXST_B4 = 0x8, ++ CXST_LK = 0x9, ++ CXST_BLK = 0xa, ++ CXST_E2G = 0xb, ++ CXST_E5G = 0xc, ++ CXST_EBT = 0xd, ++ CXST_ENULL = 0xe, ++ CXST_WLK = 0xf, ++ CXST_W1FDD = 0x10, ++ CXST_B1FDD = 0x11, ++ CXST_MAX = 0x12, ++}; ++ ++enum { ++ CXBCN_ALL = 0x0, ++ CXBCN_ALL_OK, ++ CXBCN_BT_SLOT, ++ CXBCN_BT_OK, ++ CXBCN_MAX ++}; ++ ++enum btc_slot_type { ++ SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ ++ SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ ++ CXSTYPE_NUM, ++}; ++ ++enum { /* TIME */ ++ CXT_BT = 0x0, ++ CXT_WL = 0x1, ++ CXT_MAX ++}; ++ ++enum { /* TIME-A2DP */ ++ CXT_FLCTRL_OFF = 0x0, ++ CXT_FLCTRL_ON = 0x1, ++ CXT_FLCTRL_MAX ++}; ++ ++enum { /* STEP TYPE */ ++ CXSTEP_NONE = 0x0, ++ CXSTEP_EVNT = 0x1, ++ CXSTEP_SLOT = 0x2, ++ CXSTEP_MAX, ++}; ++ ++#define FCXGPIODBG_VER 1 ++#define BTC_DBG_MAX1 32 ++struct rtw89_btc_fbtc_gpio_dbg { ++ u8 fver; ++ u8 rsvd; ++ u16 rsvd2; ++ u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ ++ u32 pre_state; /* the debug signal is 1 or 0 */ ++ u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ ++} __packed; ++ ++#define FCXMREG_VER 1 ++struct rtw89_btc_fbtc_mreg_val { ++ u8 fver; ++ u8 reg_num; ++ __le16 rsvd; ++ __le32 mreg_val[CXMREG_MAX]; ++} __packed; ++ ++#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ ++ { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ ++ .offset = cpu_to_le32(__offset), } ++ ++struct rtw89_btc_fbtc_mreg { ++ __le16 type; ++ __le16 bytes; ++ __le32 offset; ++} __packed; ++ ++struct rtw89_btc_fbtc_slot { ++ __le16 dur; ++ __le32 cxtbl; ++ __le16 cxtype; ++} __packed; ++ ++#define FCXSLOTS_VER 1 ++struct rtw89_btc_fbtc_slots { ++ u8 fver; ++ u8 tbl_num; ++ __le16 rsvd; ++ __le32 update_map; ++ struct rtw89_btc_fbtc_slot slot[CXST_MAX]; ++} __packed; ++ ++#define FCXSTEP_VER 2 ++struct rtw89_btc_fbtc_step { ++ u8 type; ++ u8 val; ++ __le16 difft; ++} __packed; ++ ++struct rtw89_btc_fbtc_steps { ++ u8 fver; ++ u8 rsvd; ++ __le16 cnt; ++ __le16 pos_old; ++ __le16 pos_new; ++ struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; ++} __packed; ++ ++#define FCXCYSTA_VER 2 ++struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ ++ u8 fver; ++ u8 rsvd; ++ __le16 cycles; /* total cycle number */ ++ __le16 cycles_a2dp[CXT_FLCTRL_MAX]; ++ __le16 a2dpept; /* a2dp empty cnt */ ++ __le16 a2dpeptto; /* a2dp empty timeout cnt*/ ++ __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ ++ __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ ++ __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ ++ __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ ++ __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ ++ __le16 tavg_a2dpept; /* avg a2dp empty time */ ++ __le16 tmax_a2dpept; /* max a2dp empty time */ ++ __le16 tavg_lk; /* avg leak-slot time */ ++ __le16 tmax_lk; /* max leak-slot time */ ++ __le32 slot_cnt[CXST_MAX]; /* slot count */ ++ __le32 bcn_cnt[CXBCN_MAX]; ++ __le32 leakrx_cnt; /* the rximr occur at leak slot */ ++ __le32 collision_cnt; /* counter for event/timer occur at same time */ ++ __le32 skip_cnt; ++ __le32 exception; ++ __le32 except_cnt; ++#if (FCXCYSTA_VER > 1) ++ __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; ++#endif ++} __packed; ++ ++#define FCXNULLSTA_VER 1 ++struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ ++ __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ ++ __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ ++} __packed; ++ ++#define FCX_BTVER_VER 1 ++struct rtw89_btc_fbtc_btver { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ ++ __le32 fw_ver; ++ __le32 feature; ++} __packed; ++ ++#define FCX_BTSCAN_VER 1 ++struct rtw89_btc_fbtc_btscan { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ u8 scan[6]; ++} __packed; ++ ++#define FCX_BTAFH_VER 1 ++struct rtw89_btc_fbtc_btafh { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ ++ u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ ++ u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ ++} __packed; ++ ++#define FCX_BTDEVINFO_VER 1 ++struct rtw89_btc_fbtc_btdevinfo { ++ u8 fver; ++ u8 rsvd; ++ __le16 vendor_id; ++ __le32 dev_name; /* only 24 bits valid */ ++ __le32 flush_time; ++} __packed; ++ ++#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) ++struct rtw89_btc_rf_trx_para { ++ u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ ++ u32 wl_rx_gain; /* rx gain table index (TBD.) */ ++ u8 bt_tx_power; /* decrease Tx power (dB) */ ++ u8 bt_rx_gain; /* LNA constrain level */ ++}; ++ ++struct rtw89_btc_dm { ++ struct rtw89_btc_fbtc_slot slot[CXST_MAX]; ++ struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; ++ struct rtw89_btc_fbtc_tdma tdma; ++ struct rtw89_btc_fbtc_tdma tdma_now; ++ struct rtw89_mac_ax_coex_gnt gnt; ++ struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ ++ struct rtw89_btc_rf_trx_para rf_trx_para; ++ struct rtw89_btc_wl_tx_limit_para wl_tx_limit; ++ struct rtw89_btc_dm_step dm_step; ++ union rtw89_btc_dm_error_map error; ++ u32 cnt_dm[BTC_DCNT_NUM]; ++ u32 cnt_notify[BTC_NCNT_NUM]; ++ ++ u32 update_slot_map; ++ u32 set_ant_path; ++ ++ u32 wl_only: 1; ++ u32 wl_fw_cx_offload: 1; ++ u32 freerun: 1; ++ u32 wl_ps_ctrl: 2; ++ u32 wl_mimo_ps: 1; ++ u32 leak_ap: 1; ++ u32 noisy_level: 3; ++ u32 coex_info_map: 8; ++ u32 bt_only: 1; ++ u32 wl_btg_rx: 1; ++ u32 trx_para_level: 8; ++ u32 wl_stb_chg: 1; ++ u32 rsvd: 3; ++ ++ u16 slot_dur[CXST_MAX]; ++ ++ u8 run_reason; ++ u8 run_action; ++}; ++ ++struct rtw89_btc_ctrl { ++ u32 manual: 1; ++ u32 igno_bt: 1; ++ u32 always_freerun: 1; ++ u32 trace_step: 16; ++ u32 rsvd: 12; ++}; ++ ++struct rtw89_btc_dbg { ++ /* cmd "rb" */ ++ bool rb_done; ++ u32 rb_val; ++}; ++ ++#define FCXTDMA_VER 1 ++ ++enum rtw89_btc_btf_fw_event { ++ BTF_EVNT_RPT = 0, ++ BTF_EVNT_BT_INFO = 1, ++ BTF_EVNT_BT_SCBD = 2, ++ BTF_EVNT_BT_REG = 3, ++ BTF_EVNT_CX_RUNINFO = 4, ++ BTF_EVNT_BT_PSD = 5, ++ BTF_EVNT_BUF_OVERFLOW, ++ BTF_EVNT_C2H_LOOPBACK, ++ BTF_EVNT_MAX, ++}; ++ ++enum btf_fw_event_report { ++ BTC_RPT_TYPE_CTRL = 0x0, ++ BTC_RPT_TYPE_TDMA, ++ BTC_RPT_TYPE_SLOT, ++ BTC_RPT_TYPE_CYSTA, ++ BTC_RPT_TYPE_STEP, ++ BTC_RPT_TYPE_NULLSTA, ++ BTC_RPT_TYPE_MREG, ++ BTC_RPT_TYPE_GPIO_DBG, ++ BTC_RPT_TYPE_BT_VER, ++ BTC_RPT_TYPE_BT_SCAN, ++ BTC_RPT_TYPE_BT_AFH, ++ BTC_RPT_TYPE_BT_DEVICE, ++ BTC_RPT_TYPE_TEST, ++ BTC_RPT_TYPE_MAX = 31 ++}; ++ ++enum rtw_btc_btf_reg_type { ++ REG_MAC = 0x0, ++ REG_BB = 0x1, ++ REG_RF = 0x2, ++ REG_BT_RF = 0x3, ++ REG_BT_MODEM = 0x4, ++ REG_BT_BLUEWIZE = 0x5, ++ REG_BT_VENDOR = 0x6, ++ REG_BT_LE = 0x7, ++ REG_MAX_TYPE, ++}; ++ ++struct rtw89_btc_rpt_cmn_info { ++ u32 rx_cnt; ++ u32 rx_len; ++ u32 req_len; /* expected rsp len */ ++ u8 req_fver; /* expected rsp fver */ ++ u8 rsp_fver; /* fver from fw */ ++ u8 valid; ++} __packed; ++ ++struct rtw89_btc_report_ctrl_state { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_tdma { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_slots { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_slots finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_cysta { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_step { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_steps finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_nullsta { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_mreg { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_gpio_dbg { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btver { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btver finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btscan { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btafh { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btdev { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ ++}; ++ ++enum rtw89_btc_btfre_type { ++ BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ ++ BTFRE_UNDEF_TYPE, ++ BTFRE_EXCEPTION, ++ BTFRE_MAX, ++}; ++ ++struct rtw89_btc_btf_fwinfo { ++ u32 cnt_c2h; ++ u32 cnt_h2c; ++ u32 cnt_h2c_fail; ++ u32 event[BTF_EVNT_MAX]; ++ ++ u32 err[BTFRE_MAX]; ++ u32 len_mismch; ++ u32 fver_mismch; ++ u32 rpt_en_map; ++ ++ struct rtw89_btc_report_ctrl_state rpt_ctrl; ++ struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; ++ struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; ++ struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; ++ struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; ++ struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; ++ struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; ++ struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; ++ struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; ++ struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; ++ struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; ++ struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; ++}; ++ ++#define RTW89_BTC_POLICY_MAXLEN 512 ++ ++struct rtw89_btc { ++ struct rtw89_btc_cx cx; ++ struct rtw89_btc_dm dm; ++ struct rtw89_btc_ctrl ctrl; ++ struct rtw89_btc_module mdinfo; ++ struct rtw89_btc_btf_fwinfo fwinfo; ++ struct rtw89_btc_dbg dbg; ++ ++ struct work_struct eapol_notify_work; ++ struct work_struct arp_notify_work; ++ struct work_struct dhcp_notify_work; ++ struct work_struct wl_sta_notify_work; ++ ++ u32 bt_req_len; ++ ++ u8 policy[RTW89_BTC_POLICY_MAXLEN]; ++ u16 policy_len; ++ u16 policy_type; ++ bool bt_req_en; ++ bool update_policy_force; ++ bool lps; ++}; ++ ++enum rtw89_ra_mode { ++ RTW89_RA_MODE_CCK = BIT(0), ++ RTW89_RA_MODE_OFDM = BIT(1), ++ RTW89_RA_MODE_HT = BIT(2), ++ RTW89_RA_MODE_VHT = BIT(3), ++ RTW89_RA_MODE_HE = BIT(4), ++}; ++ ++enum rtw89_ra_report_mode { ++ RTW89_RA_RPT_MODE_LEGACY, ++ RTW89_RA_RPT_MODE_HT, ++ RTW89_RA_RPT_MODE_VHT, ++ RTW89_RA_RPT_MODE_HE, ++}; ++ ++enum rtw89_dig_noisy_level { ++ RTW89_DIG_NOISY_LEVEL0 = -1, ++ RTW89_DIG_NOISY_LEVEL1 = 0, ++ RTW89_DIG_NOISY_LEVEL2 = 1, ++ RTW89_DIG_NOISY_LEVEL3 = 2, ++ RTW89_DIG_NOISY_LEVEL_MAX = 3, ++}; ++ ++enum rtw89_gi_ltf { ++ RTW89_GILTF_LGI_4XHE32 = 0, ++ RTW89_GILTF_SGI_4XHE08 = 1, ++ RTW89_GILTF_2XHE16 = 2, ++ RTW89_GILTF_2XHE08 = 3, ++ RTW89_GILTF_1XHE16 = 4, ++ RTW89_GILTF_1XHE08 = 5, ++ RTW89_GILTF_MAX ++}; ++ ++enum rtw89_rx_frame_type { ++ RTW89_RX_TYPE_MGNT = 0, ++ RTW89_RX_TYPE_CTRL = 1, ++ RTW89_RX_TYPE_DATA = 2, ++ RTW89_RX_TYPE_RSVD = 3, ++}; ++ ++struct rtw89_ra_info { ++ u8 is_dis_ra:1; ++ /* Bit0 : CCK ++ * Bit1 : OFDM ++ * Bit2 : HT ++ * Bit3 : VHT ++ * Bit4 : HE ++ */ ++ u8 mode_ctrl:5; ++ u8 bw_cap:2; ++ u8 macid; ++ u8 dcm_cap:1; ++ u8 er_cap:1; ++ u8 init_rate_lv:2; ++ u8 upd_all:1; ++ u8 en_sgi:1; ++ u8 ldpc_cap:1; ++ u8 stbc_cap:1; ++ u8 ss_num:3; ++ u8 giltf:3; ++ u8 upd_bw_nss_mask:1; ++ u8 upd_mask:1; ++ u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ ++ /* BFee CSI */ ++ u8 band_num; ++ u8 ra_csi_rate_en:1; ++ u8 fixed_csi_rate_en:1; ++ u8 cr_tbl_sel:1; ++ u8 rsvd2:5; ++ u8 csi_mcs_ss_idx; ++ u8 csi_mode:2; ++ u8 csi_gi_ltf:3; ++ u8 csi_bw:3; ++}; ++ ++#define RTW89_PPDU_MAX_USR 4 ++#define RTW89_PPDU_MAC_INFO_USR_SIZE 4 ++#define RTW89_PPDU_MAC_INFO_SIZE 8 ++#define RTW89_PPDU_MAC_RX_CNT_SIZE 96 ++ ++#define RTW89_MAX_RX_AGG_NUM 64 ++#define RTW89_MAX_TX_AGG_NUM 128 ++ ++struct rtw89_ampdu_params { ++ u16 agg_num; ++ bool amsdu; ++}; ++ ++struct rtw89_ra_report { ++ struct rate_info txrate; ++ u32 bit_rate; ++ u16 hw_rate; ++}; ++ ++DECLARE_EWMA(rssi, 10, 16); ++ ++struct rtw89_sta { ++ u8 mac_id; ++ bool disassoc; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_ra_info ra; ++ struct rtw89_ra_report ra_report; ++ int max_agg_wait; ++ u8 prev_rssi; ++ struct ewma_rssi avg_rssi; ++ struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; ++ struct ieee80211_rx_status rx_status; ++ u16 rx_hw_rate; ++ __le32 htc_template; ++ ++ bool use_cfg_mask; ++ struct cfg80211_bitrate_mask mask; ++ ++ bool cctl_tx_time; ++ u32 ampdu_max_time:4; ++ bool cctl_tx_retry_limit; ++ u32 data_tx_cnt_lmt:6; ++}; ++ ++#define RTW89_MAX_ADDR_CAM_NUM 128 ++#define RTW89_MAX_BSSID_CAM_NUM 20 ++#define RTW89_MAX_SEC_CAM_NUM 128 ++#define RTW89_SEC_CAM_IN_ADDR_CAM 7 ++ ++struct rtw89_addr_cam_entry { ++ u8 addr_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 valid : 1; ++ u8 addr_mask : 6; ++ u8 wapi : 1; ++ u8 mask_sel : 2; ++ u8 bssid_cam_idx: 6; ++ u8 tma[ETH_ALEN]; ++ u8 sma[ETH_ALEN]; ++ ++ u8 sec_ent_mode; ++ DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); ++ u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; ++ u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; ++ struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; ++}; ++ ++struct rtw89_bssid_cam_entry { ++ u8 bssid[ETH_ALEN]; ++ u8 phy_idx; ++ u8 bssid_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 valid : 1; ++ u8 num; ++}; ++ ++struct rtw89_sec_cam_entry { ++ u8 sec_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 type : 4; ++ u8 ext_key : 1; ++ u8 spp_mode : 1; ++ /* 256 bits */ ++ u8 key[32]; ++}; ++ ++struct rtw89_efuse { ++ bool valid; ++ u8 xtal_cap; ++ u8 addr[ETH_ALEN]; ++ u8 rfe_type; ++ char country_code[2]; ++}; ++ ++struct rtw89_vif { ++ struct list_head list; ++ u8 mac_id; ++ u8 port; ++ u8 mac_addr[ETH_ALEN]; ++ u8 bssid[ETH_ALEN]; ++ u8 phy_idx; ++ u8 mac_idx; ++ u8 net_type; ++ u8 wifi_role; ++ u8 self_role; ++ u8 wmm; ++ u8 bcn_hit_cond; ++ u8 hit_rule; ++ bool trigger; ++ bool lsig_txop; ++ u8 tgt_ind; ++ u8 frm_tgt_ind; ++ bool wowlan_pattern; ++ bool wowlan_uc; ++ bool wowlan_magic; ++ bool is_hesta; ++ bool last_a_ctrl; ++ union { ++ struct { ++ struct ieee80211_sta *ap; ++ } mgd; ++ struct { ++ struct list_head sta_list; ++ } ap; ++ }; ++ struct rtw89_addr_cam_entry addr_cam; ++ struct rtw89_bssid_cam_entry bssid_cam; ++ struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; ++ struct rtw89_traffic_stats stats; ++}; ++ ++enum rtw89_lv1_rcvy_step { ++ RTW89_LV1_RCVY_STEP_1, ++ RTW89_LV1_RCVY_STEP_2, ++}; ++ ++struct rtw89_hci_ops { ++ int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); ++ void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); ++ void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); ++ void (*reset)(struct rtw89_dev *rtwdev); ++ int (*start)(struct rtw89_dev *rtwdev); ++ void (*stop)(struct rtw89_dev *rtwdev); ++ void (*link_ps)(struct rtw89_dev *rtwdev, bool enter); ++ void (*recalc_int_mit)(struct rtw89_dev *rtwdev); ++ ++ u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); ++ u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); ++ u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); ++ void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); ++ void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); ++ void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); ++ ++ int (*mac_pre_init)(struct rtw89_dev *rtwdev); ++ int (*mac_post_init)(struct rtw89_dev *rtwdev); ++ int (*deinit)(struct rtw89_dev *rtwdev); ++ ++ u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); ++ int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); ++ void (*dump_err_status)(struct rtw89_dev *rtwdev); ++ int (*napi_poll)(struct napi_struct *napi, int budget); ++}; ++ ++struct rtw89_hci_info { ++ const struct rtw89_hci_ops *ops; ++ enum rtw89_hci_type type; ++ u32 rpwm_addr; ++ u32 cpwm_addr; ++}; ++ ++struct rtw89_chip_ops { ++ void (*bb_reset)(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx); ++ void (*bb_sethw)(struct rtw89_dev *rtwdev); ++ u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask); ++ bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data); ++ void (*set_channel)(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param); ++ void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, ++ struct rtw89_channel_help_params *p); ++ int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); ++ int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); ++ void (*fem_setup)(struct rtw89_dev *rtwdev); ++ void (*rfk_init)(struct rtw89_dev *rtwdev); ++ void (*rfk_channel)(struct rtw89_dev *rtwdev); ++ void (*rfk_band_changed)(struct rtw89_dev *rtwdev); ++ void (*rfk_track)(struct rtw89_dev *rtwdev); ++ void (*power_trim)(struct rtw89_dev *rtwdev); ++ void (*set_txpwr)(struct rtw89_dev *rtwdev); ++ void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); ++ int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); ++ u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); ++ void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); ++ void (*query_ppdu)(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status); ++ void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); ++ void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, ++ s16 pw_ofst, enum rtw89_mac_idx mac_idx); ++ ++ void (*btc_set_rfe)(struct rtw89_dev *rtwdev); ++ void (*btc_init_cfg)(struct rtw89_dev *rtwdev); ++ void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); ++ void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); ++ s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); ++ void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); ++ void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); ++ void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); ++}; ++ ++enum rtw89_dma_ch { ++ RTW89_DMA_ACH0 = 0, ++ RTW89_DMA_ACH1 = 1, ++ RTW89_DMA_ACH2 = 2, ++ RTW89_DMA_ACH3 = 3, ++ RTW89_DMA_ACH4 = 4, ++ RTW89_DMA_ACH5 = 5, ++ RTW89_DMA_ACH6 = 6, ++ RTW89_DMA_ACH7 = 7, ++ RTW89_DMA_B0MG = 8, ++ RTW89_DMA_B0HI = 9, ++ RTW89_DMA_B1MG = 10, ++ RTW89_DMA_B1HI = 11, ++ RTW89_DMA_H2C = 12, ++ RTW89_DMA_CH_NUM = 13 ++}; ++ ++enum rtw89_qta_mode { ++ RTW89_QTA_SCC, ++ RTW89_QTA_DLFW, ++ ++ /* keep last */ ++ RTW89_QTA_INVALID, ++}; ++ ++struct rtw89_hfc_ch_cfg { ++ u16 min; ++ u16 max; ++#define grp_0 0 ++#define grp_1 1 ++#define grp_num 2 ++ u8 grp; ++}; ++ ++struct rtw89_hfc_ch_info { ++ u16 aval; ++ u16 used; ++}; ++ ++struct rtw89_hfc_pub_cfg { ++ u16 grp0; ++ u16 grp1; ++ u16 pub_max; ++ u16 wp_thrd; ++}; ++ ++struct rtw89_hfc_pub_info { ++ u16 g0_used; ++ u16 g1_used; ++ u16 g0_aval; ++ u16 g1_aval; ++ u16 pub_aval; ++ u16 wp_aval; ++}; ++ ++struct rtw89_hfc_prec_cfg { ++ u16 ch011_prec; ++ u16 h2c_prec; ++ u16 wp_ch07_prec; ++ u16 wp_ch811_prec; ++ u8 ch011_full_cond; ++ u8 h2c_full_cond; ++ u8 wp_ch07_full_cond; ++ u8 wp_ch811_full_cond; ++}; ++ ++struct rtw89_hfc_param { ++ bool en; ++ bool h2c_en; ++ u8 mode; ++ struct rtw89_hfc_ch_cfg *ch_cfg; ++ struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; ++ struct rtw89_hfc_pub_cfg *pub_cfg; ++ struct rtw89_hfc_pub_info pub_info; ++ struct rtw89_hfc_prec_cfg *prec_cfg; ++}; ++ ++struct rtw89_hfc_param_ini { ++ struct rtw89_hfc_ch_cfg *ch_cfg; ++ struct rtw89_hfc_pub_cfg *pub_cfg; ++ struct rtw89_hfc_prec_cfg *prec_cfg; ++ u8 mode; ++}; ++ ++struct rtw89_dle_size { ++ u16 pge_size; ++ u16 lnk_pge_num; ++ u16 unlnk_pge_num; ++}; ++ ++struct rtw89_wde_quota { ++ u16 hif; ++ u16 wcpu; ++ u16 pkt_in; ++ u16 cpu_io; ++}; ++ ++struct rtw89_ple_quota { ++ u16 cma0_tx; ++ u16 cma1_tx; ++ u16 c2h; ++ u16 h2c; ++ u16 wcpu; ++ u16 mpdu_proc; ++ u16 cma0_dma; ++ u16 cma1_dma; ++ u16 bb_rpt; ++ u16 wd_rel; ++ u16 cpu_io; ++}; ++ ++struct rtw89_dle_mem { ++ enum rtw89_qta_mode mode; ++ struct rtw89_dle_size *wde_size; ++ struct rtw89_dle_size *ple_size; ++ struct rtw89_wde_quota *wde_min_qt; ++ struct rtw89_wde_quota *wde_max_qt; ++ struct rtw89_ple_quota *ple_min_qt; ++ struct rtw89_ple_quota *ple_max_qt; ++}; ++ ++struct rtw89_reg_def { ++ u32 addr; ++ u32 mask; ++}; ++ ++struct rtw89_reg2_def { ++ u32 addr; ++ u32 data; ++}; ++ ++struct rtw89_reg3_def { ++ u32 addr; ++ u32 mask; ++ u32 data; ++}; ++ ++struct rtw89_reg5_def { ++ u8 flag; /* recognized by parsers */ ++ u8 path; ++ u32 addr; ++ u32 mask; ++ u32 data; ++}; ++ ++struct rtw89_phy_table { ++ const struct rtw89_reg2_def *regs; ++ u32 n_regs; ++ enum rtw89_rf_path rf_path; ++}; ++ ++struct rtw89_txpwr_table { ++ const void *data; ++ u32 size; ++ void (*load)(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl); ++}; ++ ++struct rtw89_chip_info { ++ enum rtw89_core_chip_id chip_id; ++ const struct rtw89_chip_ops *ops; ++ const char *fw_name; ++ u32 fifo_size; ++ u16 max_amsdu_limit; ++ bool dis_2g_40m_ul_ofdma; ++ struct rtw89_hfc_param_ini *hfc_param_ini; ++ struct rtw89_dle_mem *dle_mem; ++ u32 rf_base_addr[2]; ++ u8 rf_path_num; ++ u8 tx_nss; ++ u8 rx_nss; ++ u8 acam_num; ++ u8 bcam_num; ++ u8 scam_num; ++ ++ u8 sec_ctrl_efuse_size; ++ u32 physical_efuse_size; ++ u32 logical_efuse_size; ++ u32 limit_efuse_size; ++ u32 phycap_addr; ++ u32 phycap_size; ++ ++ const struct rtw89_pwr_cfg * const *pwr_on_seq; ++ const struct rtw89_pwr_cfg * const *pwr_off_seq; ++ const struct rtw89_phy_table *bb_table; ++ const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; ++ const struct rtw89_phy_table *nctl_table; ++ const struct rtw89_txpwr_table *byr_table; ++ const struct rtw89_phy_dig_gain_table *dig_table; ++ const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++ const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++ const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ ++ u8 txpwr_factor_rf; ++ u8 txpwr_factor_mac; ++ ++ u32 para_ver; ++ u32 wlcx_desired; ++ u8 btcx_desired; ++ u8 scbd; ++ u8 mailbox; ++ ++ u8 afh_guard_ch; ++ const u8 *wl_rssi_thres; ++ const u8 *bt_rssi_thres; ++ u8 rssi_tol; ++ ++ u8 mon_reg_num; ++ const struct rtw89_btc_fbtc_mreg *mon_reg; ++ u8 rf_para_ulink_num; ++ const struct rtw89_btc_rf_trx_para *rf_para_ulink; ++ u8 rf_para_dlink_num; ++ const struct rtw89_btc_rf_trx_para *rf_para_dlink; ++ u8 ps_mode_supported; ++}; ++ ++enum rtw89_hcifc_mode { ++ RTW89_HCIFC_POH = 0, ++ RTW89_HCIFC_STF = 1, ++ RTW89_HCIFC_SDIO = 2, ++ ++ /* keep last */ ++ RTW89_HCIFC_MODE_INVALID, ++}; ++ ++struct rtw89_dle_info { ++ enum rtw89_qta_mode qta_mode; ++ u16 wde_pg_size; ++ u16 ple_pg_size; ++ u16 c0_rx_qta; ++ u16 c1_rx_qta; ++}; ++ ++enum rtw89_host_rpr_mode { ++ RTW89_RPR_MODE_POH = 0, ++ RTW89_RPR_MODE_STF ++}; ++ ++struct rtw89_mac_info { ++ struct rtw89_dle_info dle_info; ++ struct rtw89_hfc_param hfc_param; ++ enum rtw89_qta_mode qta_mode; ++ u8 rpwm_seq_num; ++ u8 cpwm_seq_num; ++}; ++ ++enum rtw89_fw_type { ++ RTW89_FW_NORMAL = 1, ++ RTW89_FW_WOWLAN = 3, ++}; ++ ++struct rtw89_fw_suit { ++ const u8 *data; ++ u32 size; ++ u8 major_ver; ++ u8 minor_ver; ++ u8 sub_ver; ++ u8 sub_idex; ++ u16 build_year; ++ u16 build_mon; ++ u16 build_date; ++ u16 build_hour; ++ u16 build_min; ++ u8 cmd_ver; ++}; ++ ++struct rtw89_fw_info { ++ const struct firmware *firmware; ++ struct rtw89_dev *rtwdev; ++ struct completion completion; ++ u8 h2c_seq; ++ u8 rec_seq; ++ struct rtw89_fw_suit normal; ++ struct rtw89_fw_suit wowlan; ++ bool fw_log_enable; ++}; ++ ++struct rtw89_cam_info { ++ DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); ++ DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); ++ DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); ++}; ++ ++enum rtw89_sar_sources { ++ RTW89_SAR_SOURCE_NONE, ++ RTW89_SAR_SOURCE_COMMON, ++ ++ RTW89_SAR_SOURCE_NR, ++}; ++ ++struct rtw89_sar_cfg_common { ++ bool set[RTW89_SUBBAND_NR]; ++ s32 cfg[RTW89_SUBBAND_NR]; ++}; ++ ++struct rtw89_sar_info { ++ /* used to decide how to acces SAR cfg union */ ++ enum rtw89_sar_sources src; ++ ++ /* reserved for different knids of SAR cfg struct. ++ * supposed that a single cfg struct cannot handle various SAR sources. ++ */ ++ union { ++ struct rtw89_sar_cfg_common cfg_common; ++ }; ++}; ++ ++struct rtw89_hal { ++ u32 rx_fltr; ++ u8 cv; ++ u8 current_channel; ++ u8 current_primary_channel; ++ enum rtw89_subband current_subband; ++ u8 current_band_width; ++ u8 current_band_type; ++ /* center channel for different available bandwidth, ++ * val of (bw > current_band_width) is invalid ++ */ ++ u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; ++ u32 sw_amsdu_max_size; ++ u32 antenna_tx; ++ u32 antenna_rx; ++ u8 tx_nss; ++ u8 rx_nss; ++}; ++ ++#define RTW89_MAX_MAC_ID_NUM 128 ++ ++enum rtw89_flags { ++ RTW89_FLAG_POWERON, ++ RTW89_FLAG_FW_RDY, ++ RTW89_FLAG_RUNNING, ++ RTW89_FLAG_BFEE_MON, ++ RTW89_FLAG_BFEE_EN, ++ RTW89_FLAG_NAPI_RUNNING, ++ RTW89_FLAG_LEISURE_PS, ++ RTW89_FLAG_LOW_POWER_MODE, ++ RTW89_FLAG_INACTIVE_PS, ++ ++ NUM_OF_RTW89_FLAGS, ++}; ++ ++struct rtw89_pkt_stat { ++ u16 beacon_nr; ++ u32 rx_rate_cnt[RTW89_HW_RATE_NR]; ++}; ++ ++DECLARE_EWMA(thermal, 4, 4); ++ ++struct rtw89_phy_stat { ++ struct ewma_thermal avg_thermal[RF_PATH_MAX]; ++ struct rtw89_pkt_stat cur_pkt_stat; ++ struct rtw89_pkt_stat last_pkt_stat; ++}; ++ ++#define RTW89_DACK_PATH_NR 2 ++#define RTW89_DACK_IDX_NR 2 ++#define RTW89_DACK_MSBK_NR 16 ++struct rtw89_dack_info { ++ bool dack_done; ++ u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; ++ u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u32 dack_cnt; ++ bool addck_timeout[RTW89_DACK_PATH_NR]; ++ bool dadck_timeout[RTW89_DACK_PATH_NR]; ++ bool msbk_timeout[RTW89_DACK_PATH_NR]; ++}; ++ ++#define RTW89_IQK_CHS_NR 2 ++#define RTW89_IQK_PATH_NR 4 ++struct rtw89_iqk_info { ++ bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ u32 iqk_fail_cnt; ++ bool is_iqk_init; ++ u32 iqk_channel[RTW89_IQK_CHS_NR]; ++ u8 iqk_band[RTW89_IQK_PATH_NR]; ++ u8 iqk_ch[RTW89_IQK_PATH_NR]; ++ u8 iqk_bw[RTW89_IQK_PATH_NR]; ++ u8 kcount; ++ u8 iqk_times; ++ u8 version; ++ u32 nb_txcfir[RTW89_IQK_PATH_NR]; ++ u32 nb_rxcfir[RTW89_IQK_PATH_NR]; ++ u32 bp_txkresult[RTW89_IQK_PATH_NR]; ++ u32 bp_rxkresult[RTW89_IQK_PATH_NR]; ++ u32 bp_iqkenable[RTW89_IQK_PATH_NR]; ++ bool is_wb_txiqk[RTW89_IQK_PATH_NR]; ++ bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; ++ bool is_nbiqk; ++ bool iqk_fft_en; ++ bool iqk_xym_en; ++ bool iqk_sram_en; ++ bool iqk_cfir_en; ++ u8 thermal[RTW89_IQK_PATH_NR]; ++ bool thermal_rek_en; ++ u32 syn1to2; ++ u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ u8 iqk_table_idx[RTW89_IQK_PATH_NR]; ++}; ++ ++#define RTW89_DPK_RF_PATH 2 ++#define RTW89_DPK_AVG_THERMAL_NUM 8 ++#define RTW89_DPK_BKUP_NUM 2 ++struct rtw89_dpk_bkup_para { ++ enum rtw89_band band; ++ enum rtw89_bandwidth bw; ++ u8 ch; ++ bool path_ok; ++ u8 txagc_dpk; ++ u8 ther_dpk; ++ u8 gs; ++ u16 pwsf; ++}; ++ ++struct rtw89_dpk_info { ++ bool is_dpk_enable; ++ bool is_dpk_reload_en; ++ u16 dc_i[RTW89_DPK_RF_PATH]; ++ u16 dc_q[RTW89_DPK_RF_PATH]; ++ u8 corr_val[RTW89_DPK_RF_PATH]; ++ u8 corr_idx[RTW89_DPK_RF_PATH]; ++ u8 cur_idx[RTW89_DPK_RF_PATH]; ++ struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; ++}; ++ ++struct rtw89_fem_info { ++ bool elna_2g; ++ bool elna_5g; ++ bool epa_2g; ++ bool epa_5g; ++}; ++ ++struct rtw89_phy_ch_info { ++ u8 rssi_min; ++ u16 rssi_min_macid; ++ u8 pre_rssi_min; ++ u8 rssi_max; ++ u16 rssi_max_macid; ++ u8 rxsc_160; ++ u8 rxsc_80; ++ u8 rxsc_40; ++ u8 rxsc_20; ++ u8 rxsc_l; ++ u8 is_noisy; ++}; ++ ++struct rtw89_agc_gaincode_set { ++ u8 lna_idx; ++ u8 tia_idx; ++ u8 rxb_idx; ++}; ++ ++#define IGI_RSSI_TH_NUM 5 ++#define FA_TH_NUM 4 ++#define LNA_GAIN_NUM 7 ++#define TIA_GAIN_NUM 2 ++struct rtw89_dig_info { ++ struct rtw89_agc_gaincode_set cur_gaincode; ++ bool force_gaincode_idx_en; ++ struct rtw89_agc_gaincode_set force_gaincode; ++ u8 igi_rssi_th[IGI_RSSI_TH_NUM]; ++ u16 fa_th[FA_TH_NUM]; ++ u8 igi_rssi; ++ u8 igi_fa_rssi; ++ u8 fa_rssi_ofst; ++ u8 dyn_igi_max; ++ u8 dyn_igi_min; ++ bool dyn_pd_th_en; ++ u8 dyn_pd_th_max; ++ u8 pd_low_th_ofst; ++ u8 ib_pbk; ++ s8 ib_pkpwr; ++ s8 lna_gain_a[LNA_GAIN_NUM]; ++ s8 lna_gain_g[LNA_GAIN_NUM]; ++ s8 *lna_gain; ++ s8 tia_gain_a[TIA_GAIN_NUM]; ++ s8 tia_gain_g[TIA_GAIN_NUM]; ++ s8 *tia_gain; ++ bool is_linked_pre; ++ bool bypass_dig; ++}; ++ ++enum rtw89_multi_cfo_mode { ++ RTW89_PKT_BASED_AVG_MODE = 0, ++ RTW89_ENTRY_BASED_AVG_MODE = 1, ++ RTW89_TP_BASED_AVG_MODE = 2, ++}; ++ ++enum rtw89_phy_cfo_status { ++ RTW89_PHY_DCFO_STATE_NORMAL = 0, ++ RTW89_PHY_DCFO_STATE_ENHANCE = 1, ++ RTW89_PHY_DCFO_STATE_MAX ++}; ++ ++struct rtw89_cfo_tracking_info { ++ u16 cfo_timer_ms; ++ bool cfo_trig_by_timer_en; ++ enum rtw89_phy_cfo_status phy_cfo_status; ++ u8 phy_cfo_trk_cnt; ++ bool is_adjust; ++ enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; ++ bool apply_compensation; ++ u8 crystal_cap; ++ u8 crystal_cap_default; ++ u8 def_x_cap; ++ s8 x_cap_ofst; ++ u32 sta_cfo_tolerance; ++ s32 cfo_tail[CFO_TRACK_MAX_USER]; ++ u16 cfo_cnt[CFO_TRACK_MAX_USER]; ++ s32 cfo_avg_pre; ++ s32 cfo_avg[CFO_TRACK_MAX_USER]; ++ s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; ++ u32 packet_count; ++ u32 packet_count_pre; ++ s32 residual_cfo_acc; ++ u8 phy_cfotrk_state; ++ u8 phy_cfotrk_cnt; ++}; ++ ++/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ ++#define TSSI_TRIM_CH_GROUP_NUM 8 ++ ++#define TSSI_CCK_CH_GROUP_NUM 6 ++#define TSSI_MCS_2G_CH_GROUP_NUM 5 ++#define TSSI_MCS_5G_CH_GROUP_NUM 14 ++#define TSSI_MCS_CH_GROUP_NUM \ ++ (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) ++ ++struct rtw89_tssi_info { ++ u8 thermal[RF_PATH_MAX]; ++ s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; ++ s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; ++ s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; ++ s8 extra_ofst[RF_PATH_MAX]; ++ bool tssi_tracking_check[RF_PATH_MAX]; ++ u8 default_txagc_offset[RF_PATH_MAX]; ++ u32 base_thermal[RF_PATH_MAX]; ++}; ++ ++struct rtw89_power_trim_info { ++ bool pg_thermal_trim; ++ bool pg_pa_bias_trim; ++ u8 thermal_trim[RF_PATH_MAX]; ++ u8 pa_bias_trim[RF_PATH_MAX]; ++}; ++ ++struct rtw89_regulatory { ++ char alpha2[3]; ++ u8 txpwr_regd[RTW89_BAND_MAX]; ++}; ++ ++enum rtw89_ifs_clm_application { ++ RTW89_IFS_CLM_INIT = 0, ++ RTW89_IFS_CLM_BACKGROUND = 1, ++ RTW89_IFS_CLM_ACS = 2, ++ RTW89_IFS_CLM_DIG = 3, ++ RTW89_IFS_CLM_TDMA_DIG = 4, ++ RTW89_IFS_CLM_DBG = 5, ++ RTW89_IFS_CLM_DBG_MANUAL = 6 ++}; ++ ++enum rtw89_env_racing_lv { ++ RTW89_RAC_RELEASE = 0, ++ RTW89_RAC_LV_1 = 1, ++ RTW89_RAC_LV_2 = 2, ++ RTW89_RAC_LV_3 = 3, ++ RTW89_RAC_LV_4 = 4, ++ RTW89_RAC_MAX_NUM = 5 ++}; ++ ++struct rtw89_ccx_para_info { ++ enum rtw89_env_racing_lv rac_lv; ++ u16 mntr_time; ++ u8 nhm_manual_th_ofst; ++ u8 nhm_manual_th0; ++ enum rtw89_ifs_clm_application ifs_clm_app; ++ u32 ifs_clm_manual_th_times; ++ u32 ifs_clm_manual_th0; ++ u8 fahm_manual_th_ofst; ++ u8 fahm_manual_th0; ++ u8 fahm_numer_opt; ++ u8 fahm_denom_opt; ++}; ++ ++enum rtw89_ccx_edcca_opt_sc_idx { ++ RTW89_CCX_EDCCA_SEG0_P0 = 0, ++ RTW89_CCX_EDCCA_SEG0_S1 = 1, ++ RTW89_CCX_EDCCA_SEG0_S2 = 2, ++ RTW89_CCX_EDCCA_SEG0_S3 = 3, ++ RTW89_CCX_EDCCA_SEG1_P0 = 4, ++ RTW89_CCX_EDCCA_SEG1_S1 = 5, ++ RTW89_CCX_EDCCA_SEG1_S2 = 6, ++ RTW89_CCX_EDCCA_SEG1_S3 = 7 ++}; ++ ++enum rtw89_ccx_edcca_opt_bw_idx { ++ RTW89_CCX_EDCCA_BW20_0 = 0, ++ RTW89_CCX_EDCCA_BW20_1 = 1, ++ RTW89_CCX_EDCCA_BW20_2 = 2, ++ RTW89_CCX_EDCCA_BW20_3 = 3, ++ RTW89_CCX_EDCCA_BW20_4 = 4, ++ RTW89_CCX_EDCCA_BW20_5 = 5, ++ RTW89_CCX_EDCCA_BW20_6 = 6, ++ RTW89_CCX_EDCCA_BW20_7 = 7 ++}; ++ ++#define RTW89_NHM_TH_NUM 11 ++#define RTW89_FAHM_TH_NUM 11 ++#define RTW89_NHM_RPT_NUM 12 ++#define RTW89_FAHM_RPT_NUM 12 ++#define RTW89_IFS_CLM_NUM 4 ++struct rtw89_env_monitor_info { ++ u32 ccx_trigger_time; ++ u64 start_time; ++ u8 ccx_rpt_stamp; ++ u8 ccx_watchdog_result; ++ bool ccx_ongoing; ++ u8 ccx_rac_lv; ++ bool ccx_manual_ctrl; ++ u8 ccx_pre_rssi; ++ u16 clm_mntr_time; ++ u16 nhm_mntr_time; ++ u16 ifs_clm_mntr_time; ++ enum rtw89_ifs_clm_application ifs_clm_app; ++ u16 fahm_mntr_time; ++ u16 edcca_clm_mntr_time; ++ u16 ccx_period; ++ u8 ccx_unit_idx; ++ enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; ++ u8 nhm_th[RTW89_NHM_TH_NUM]; ++ u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; ++ u8 fahm_numer_opt; ++ u8 fahm_denom_opt; ++ u8 fahm_th[RTW89_FAHM_TH_NUM]; ++ u16 clm_result; ++ u16 nhm_result[RTW89_NHM_RPT_NUM]; ++ u8 nhm_wgt[RTW89_NHM_RPT_NUM]; ++ u16 nhm_tx_cnt; ++ u16 nhm_cca_cnt; ++ u16 nhm_idle_cnt; ++ u16 ifs_clm_tx; ++ u16 ifs_clm_edcca_excl_cca; ++ u16 ifs_clm_ofdmfa; ++ u16 ifs_clm_ofdmcca_excl_fa; ++ u16 ifs_clm_cckfa; ++ u16 ifs_clm_cckcca_excl_fa; ++ u16 ifs_clm_total_ifs; ++ u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; ++ u16 fahm_result[RTW89_FAHM_RPT_NUM]; ++ u16 fahm_denom_result; ++ u16 edcca_clm_result; ++ u8 clm_ratio; ++ u8 nhm_rpt[RTW89_NHM_RPT_NUM]; ++ u8 nhm_tx_ratio; ++ u8 nhm_cca_ratio; ++ u8 nhm_idle_ratio; ++ u8 nhm_ratio; ++ u16 nhm_result_sum; ++ u8 nhm_pwr; ++ u8 ifs_clm_tx_ratio; ++ u8 ifs_clm_edcca_excl_cca_ratio; ++ u8 ifs_clm_cck_fa_ratio; ++ u8 ifs_clm_ofdm_fa_ratio; ++ u8 ifs_clm_cck_cca_excl_fa_ratio; ++ u8 ifs_clm_ofdm_cca_excl_fa_ratio; ++ u16 ifs_clm_cck_fa_permil; ++ u16 ifs_clm_ofdm_fa_permil; ++ u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; ++ u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; ++ u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; ++ u16 fahm_result_sum; ++ u8 fahm_ratio; ++ u8 fahm_denom_ratio; ++ u8 fahm_pwr; ++ u8 edcca_clm_ratio; ++}; ++ ++enum rtw89_ser_rcvy_step { ++ RTW89_SER_DRV_STOP_TX, ++ RTW89_SER_DRV_STOP_RX, ++ RTW89_SER_DRV_STOP_RUN, ++ RTW89_SER_HAL_STOP_DMA, ++ RTW89_NUM_OF_SER_FLAGS ++}; ++ ++struct rtw89_ser { ++ u8 state; ++ u8 alarm_event; ++ ++ struct work_struct ser_hdl_work; ++ struct delayed_work ser_alarm_work; ++ struct state_ent *st_tbl; ++ struct event_ent *ev_tbl; ++ struct list_head msg_q; ++ spinlock_t msg_q_lock; /* lock when read/write ser msg */ ++ DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); ++}; ++ ++enum rtw89_mac_ax_ps_mode { ++ RTW89_MAC_AX_PS_MODE_ACTIVE = 0, ++ RTW89_MAC_AX_PS_MODE_LEGACY = 1, ++ RTW89_MAC_AX_PS_MODE_WMMPS = 2, ++ RTW89_MAC_AX_PS_MODE_MAX = 3, ++}; ++ ++enum rtw89_last_rpwm_mode { ++ RTW89_LAST_RPWM_PS = 0x0, ++ RTW89_LAST_RPWM_ACTIVE = 0x6, ++}; ++ ++struct rtw89_lps_parm { ++ u8 macid; ++ u8 psmode; /* enum rtw89_mac_ax_ps_mode */ ++ u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ ++}; ++ ++struct rtw89_ppdu_sts_info { ++ struct sk_buff_head rx_queue[RTW89_PHY_MAX]; ++ u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; ++}; ++ ++struct rtw89_dev { ++ struct ieee80211_hw *hw; ++ struct device *dev; ++ ++ bool dbcc_en; ++ const struct rtw89_chip_info *chip; ++ struct rtw89_hal hal; ++ struct rtw89_mac_info mac; ++ struct rtw89_fw_info fw; ++ struct rtw89_hci_info hci; ++ struct rtw89_efuse efuse; ++ struct rtw89_traffic_stats stats; ++ ++ /* ensures exclusive access from mac80211 callbacks */ ++ struct mutex mutex; ++ struct list_head rtwvifs_list; ++ /* used to protect rf read write */ ++ struct mutex rf_mutex; ++ struct workqueue_struct *txq_wq; ++ struct work_struct txq_work; ++ struct delayed_work txq_reinvoke_work; ++ /* used to protect ba_list */ ++ spinlock_t ba_lock; ++ /* txqs to setup ba session */ ++ struct list_head ba_list; ++ struct work_struct ba_work; ++ ++ struct rtw89_cam_info cam_info; ++ ++ struct sk_buff_head c2h_queue; ++ struct work_struct c2h_work; ++ ++ struct rtw89_ser ser; ++ ++ DECLARE_BITMAP(hw_port, RTW89_MAX_HW_PORT_NUM); ++ DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); ++ DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); ++ ++ struct rtw89_phy_stat phystat; ++ struct rtw89_dack_info dack; ++ struct rtw89_iqk_info iqk; ++ struct rtw89_dpk_info dpk; ++ bool is_tssi_mode[RF_PATH_MAX]; ++ bool is_bt_iqk_timeout; ++ ++ struct rtw89_fem_info fem; ++ struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; ++ struct rtw89_tssi_info tssi; ++ struct rtw89_power_trim_info pwr_trim; ++ ++ struct rtw89_cfo_tracking_info cfo_tracking; ++ struct rtw89_env_monitor_info env_monitor; ++ struct rtw89_dig_info dig; ++ struct rtw89_phy_ch_info ch_info; ++ struct delayed_work track_work; ++ struct delayed_work coex_act1_work; ++ struct delayed_work coex_bt_devinfo_work; ++ struct delayed_work coex_rfk_chk_work; ++ struct delayed_work cfo_track_work; ++ struct rtw89_ppdu_sts_info ppdu_sts; ++ u8 total_sta_assoc; ++ bool scanning; ++ ++ const struct rtw89_regulatory *regd; ++ struct rtw89_sar_info sar; ++ ++ struct rtw89_btc btc; ++ enum rtw89_ps_mode ps_mode; ++ bool lps_enabled; ++ ++ /* napi structure */ ++ struct net_device netdev; ++ struct napi_struct napi; ++ int napi_budget_countdown; ++ ++ /* HCI related data, keep last */ ++ u8 priv[0] __aligned(sizeof(void *)); ++}; ++ ++static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ return rtwdev->hci.ops->tx_write(rtwdev, tx_req); ++} ++ ++static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->reset(rtwdev); ++} ++ ++static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) ++{ ++ return rtwdev->hci.ops->start(rtwdev); ++} ++ ++static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->stop(rtwdev); ++} ++ ++static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) ++{ ++ return rtwdev->hci.ops->deinit(rtwdev); ++} ++ ++static inline void rtw89_hci_link_ps(struct rtw89_dev *rtwdev, bool enter) ++{ ++ rtwdev->hci.ops->link_ps(rtwdev, enter); ++} ++ ++static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->recalc_int_mit(rtwdev); ++} ++ ++static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); ++} ++ ++static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); ++} ++ ++static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, ++ bool drop) ++{ ++ if (rtwdev->hci.ops->flush_queues) ++ return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); ++} ++ ++static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read8(rtwdev, addr); ++} ++ ++static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read16(rtwdev, addr); ++} ++ ++static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read32(rtwdev, addr); ++} ++ ++static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) ++{ ++ rtwdev->hci.ops->write8(rtwdev, addr, data); ++} ++ ++static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) ++{ ++ rtwdev->hci.ops->write16(rtwdev, addr, data); ++} ++ ++static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) ++{ ++ rtwdev->hci.ops->write32(rtwdev, addr, data); ++} ++ ++static inline void ++rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) ++{ ++ u8 val; ++ ++ val = rtw89_read8(rtwdev, addr); ++ rtw89_write8(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) ++{ ++ u16 val; ++ ++ val = rtw89_read16(rtwdev, addr); ++ rtw89_write16(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, addr); ++ rtw89_write32(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) ++{ ++ u8 val; ++ ++ val = rtw89_read8(rtwdev, addr); ++ rtw89_write8(rtwdev, addr, val & ~bit); ++} ++ ++static inline void ++rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) ++{ ++ u16 val; ++ ++ val = rtw89_read16(rtwdev, addr); ++ rtw89_write16(rtwdev, addr, val & ~bit); ++} ++ ++static inline void ++rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, addr); ++ rtw89_write32(rtwdev, addr, val & ~bit); ++} ++ ++static inline u32 ++rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read32(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline u16 ++rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read16(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline u8 ++rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read8(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline void ++rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 set; ++ ++ WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); ++ ++ orig = rtw89_read32(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write32(rtwdev, addr, set); ++} ++ ++static inline void ++rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) ++{ ++ u32 shift; ++ u16 orig, set; ++ ++ mask &= 0xffff; ++ shift = __ffs(mask); ++ ++ orig = rtw89_read16(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write16(rtwdev, addr, set); ++} ++ ++static inline void ++rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) ++{ ++ u32 shift; ++ u8 orig, set; ++ ++ mask &= 0xff; ++ shift = __ffs(mask); ++ ++ orig = rtw89_read8(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write8(rtwdev, addr, set); ++} ++ ++static inline u32 ++rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask) ++{ ++ u32 val; ++ ++ mutex_lock(&rtwdev->rf_mutex); ++ val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); ++ mutex_unlock(&rtwdev->rf_mutex); ++ ++ return val; ++} ++ ++static inline void ++rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data) ++{ ++ mutex_lock(&rtwdev->rf_mutex); ++ rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); ++ mutex_unlock(&rtwdev->rf_mutex); ++} ++ ++static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) ++{ ++ void *p = rtwtxq; ++ ++ return container_of(p, struct ieee80211_txq, drv_priv); ++} ++ ++static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, ++ struct ieee80211_txq *txq) ++{ ++ struct rtw89_txq *rtwtxq; ++ ++ if (!txq) ++ return; ++ ++ rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ INIT_LIST_HEAD(&rtwtxq->list); ++} ++ ++static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) ++{ ++ void *p = rtwvif; ++ ++ return container_of(p, struct ieee80211_vif, drv_priv); ++} ++ ++static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) ++{ ++ void *p = rtwsta; ++ ++ return container_of(p, struct ieee80211_sta, drv_priv); ++} ++ ++static inline ++void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_help_params *p) ++{ ++ rtwdev->chip->ops->set_channel_help(rtwdev, true, p); ++} ++ ++static inline ++void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_help_params *p) ++{ ++ rtwdev->chip->ops->set_channel_help(rtwdev, false, p); ++} ++ ++static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->fem_setup) ++ chip->ops->fem_setup(rtwdev); ++} ++ ++static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->bb_sethw) ++ chip->ops->bb_sethw(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_init) ++ chip->ops->rfk_init(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_channel) ++ chip->ops->rfk_channel(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_band_changed) ++ chip->ops->rfk_band_changed(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_track) ++ chip->ops->rfk_track(rtwdev); ++} ++ ++static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->set_txpwr_ctrl) ++ chip->ops->set_txpwr_ctrl(rtwdev); ++} ++ ++static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch = rtwdev->hal.current_channel; ++ ++ if (!ch) ++ return; ++ ++ if (chip->ops->set_txpwr) ++ chip->ops->set_txpwr(rtwdev); ++} ++ ++static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->power_trim) ++ chip->ops->power_trim(rtwdev); ++} ++ ++static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->init_txpwr_unit) ++ chip->ops->init_txpwr_unit(rtwdev, phy_idx); ++} ++ ++static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path rf_path) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (!chip->ops->get_thermal) ++ return 0x10; ++ ++ return chip->ops->get_thermal(rtwdev, rf_path); ++} ++ ++static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->query_ppdu) ++ chip->ops->query_ppdu(rtwdev, phy_ppdu, status); ++} ++ ++static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, ++ bool bt_en) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->bb_ctrl_btc_preagc) ++ chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); ++} ++ ++static inline ++void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) ++ return; ++ ++ if (chip->ops->set_txpwr_ul_tb_offset) ++ chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); ++} ++ ++static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl) ++{ ++ tbl->load(rtwdev, tbl); ++} ++ ++static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) ++{ ++ return rtwdev->regd->txpwr_regd[band]; ++} ++ ++static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->ctrl_btg) ++ chip->ops->ctrl_btg(rtwdev, btg); ++} ++ ++static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) ++{ ++ __le16 fc = hdr->frame_control; ++ ++ if (ieee80211_has_tods(fc)) ++ return hdr->addr1; ++ else if (ieee80211_has_fromds(fc)) ++ return hdr->addr2; ++ else ++ return hdr->addr3; ++} ++ ++static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) ++{ ++ if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || ++ (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || ++ (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) ++ return true; ++ return false; ++} ++ ++static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, ++ enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ ++ if (type == RTW89_FW_WOWLAN) ++ return &fw_info->wowlan; ++ return &fw_info->normal; ++} ++ ++int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); ++int rtw89_h2c_tx(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, bool fwdl); ++void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); ++void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_tx_desc_info *desc_info, ++ void *txdesc); ++void rtw89_core_rx(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb); ++void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ u8 *data, u32 data_offset); ++void rtw89_core_napi_start(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_init(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); ++int rtw89_core_sta_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_init(struct rtw89_dev *rtwdev); ++void rtw89_core_deinit(struct rtw89_dev *rtwdev); ++int rtw89_core_register(struct rtw89_dev *rtwdev); ++void rtw89_core_unregister(struct rtw89_dev *rtwdev); ++void rtw89_set_channel(struct rtw89_dev *rtwdev); ++u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); ++void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); ++void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); ++void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); ++int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); ++u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate); ++int rtw89_regd_init(struct rtw89_dev *rtwdev, ++ void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); ++void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); ++void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats); ++int rtw89_core_start(struct rtw89_dev *rtwdev); ++void rtw89_core_stop(struct rtw89_dev *rtwdev); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/txrx.h b/drivers/net/wireless/realtek/rtw89/txrx.h +new file mode 100644 +index 000000000000..0dc99cbc6761 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/txrx.h +@@ -0,0 +1,393 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_TXRX_H__ ++#define __RTW89_TXRX_H__ ++ ++#include "debug.h" ++ ++#define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) ++#define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) ++#define DATA_RATE_MODE_NON_HT 0x0 ++#define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) ++#define DATA_RATE_MODE_HT 0x1 ++#define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) ++#define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) ++#define DATA_RATE_MODE_VHT 0x2 ++#define DATA_RATE_MODE_HE 0x3 ++#define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) ++#define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) ++#define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) ++#define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) ++#define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) ++ ++/* TX WD BODY DWORD 0 */ ++#define RTW89_SET_TXWD_BODY_WP_OFFSET(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, GENMASK(31, 24)) ++#define RTW89_SET_TXWD_BODY_MORE_DATA(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(23)) ++#define RTW89_SET_TXWD_BODY_WD_INFO_EN(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(22)) ++#define RTW89_SET_TXWD_BODY_FW_DL(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(20)) ++#define RTW89_SET_TXWD_BODY_CHANNEL_DMA(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, GENMASK(19, 16)) ++#define RTW89_SET_TXWD_BODY_HDR_LLC_LEN(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, GENMASK(15, 11)) ++#define RTW89_SET_TXWD_BODY_WD_PAGE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(7)) ++#define RTW89_SET_TXWD_BODY_HW_AMSDU(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(5)) ++ ++/* TX WD BODY DWORD 1 */ ++#define RTW89_SET_TXWD_BODY_PAYLOAD_ID(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x01, GENMASK(31, 16)) ++ ++/* TX WD BODY DWORD 2 */ ++#define RTW89_SET_TXWD_BODY_MACID(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x02, GENMASK(30, 24)) ++#define RTW89_SET_TXWD_BODY_TID_INDICATE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x02, BIT(23)) ++#define RTW89_SET_TXWD_BODY_QSEL(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x02, GENMASK(22, 17)) ++#define RTW89_SET_TXWD_BODY_TXPKT_SIZE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x02, GENMASK(13, 0)) ++ ++/* TX WD BODY DWORD 3 */ ++#define RTW89_SET_TXWD_BODY_BK(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x03, BIT(13)) ++#define RTW89_SET_TXWD_BODY_AGG_EN(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x03, BIT(12)) ++#define RTW89_SET_TXWD_BODY_SW_SEQ(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x03, GENMASK(11, 0)) ++ ++/* TX WD BODY DWORD 4 */ ++ ++/* TX WD BODY DWORD 5 */ ++ ++/* TX WD INFO DWORD 0 */ ++#define RTW89_SET_TXWD_INFO_USE_RATE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x6, BIT(30)) ++#define RTW89_SET_TXWD_INFO_DATA_BW(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x6, GENMASK(29, 28)) ++#define RTW89_SET_TXWD_INFO_GI_LTF(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x6, GENMASK(27, 25)) ++#define RTW89_SET_TXWD_INFO_DATA_RATE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x6, GENMASK(24, 16)) ++#define RTW89_SET_TXWD_INFO_DISDATAFB(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x6, BIT(10)) ++ ++/* TX WD INFO DWORD 1 */ ++#define RTW89_SET_TXWD_INFO_A_CTRL_BSR(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x7, BIT(14)) ++#define RTW89_SET_TXWD_INFO_MAX_AGGNUM(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x7, GENMASK(7, 0)) ++ ++/* TX WD INFO DWORD 2 */ ++#define RTW89_SET_TXWD_INFO_AMPDU_DENSITY(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x8, GENMASK(20, 18)) ++#define RTW89_SET_TXWD_INFO_SEC_TYPE(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x8, GENMASK(12, 9)) ++#define RTW89_SET_TXWD_INFO_SEC_HW_ENC(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x8, BIT(8)) ++#define RTW89_SET_TXWD_INFO_SEC_CAM_IDX(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0x8, GENMASK(7, 0)) ++ ++/* TX WD INFO DWORD 3 */ ++ ++/* TX WD INFO DWORD 4 */ ++#define RTW89_SET_TXWD_INFO_RTS_EN(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0xA, BIT(27)) ++#define RTW89_SET_TXWD_INFO_HW_RTS_EN(txdesc, val) \ ++ RTW89_SET_TXWD(txdesc, val, 0xA, BIT(31)) ++ ++/* TX WD INFO DWORD 5 */ ++ ++/* RX DESC helpers */ ++/* Short Descriptor */ ++#define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(31)) ++#define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) ++#define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) ++#define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(23)) ++#define RTW89_GET_RXWD_BB_SEL(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(22)) ++#define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) ++#define RTW89_GET_RXWD_SHIFT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) ++#define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) ++#define RTW89_GET_RXWD_BW(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) ++#define RTW89_GET_RXWD_GI_LTF(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) ++#define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) ++#define RTW89_GET_RXWD_USER_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) ++#define RTW89_GET_RXWD_SR_EN(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, BIT(7)) ++#define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) ++#define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) ++#define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) ++#define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(10)) ++#define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(9)) ++#define RTW89_GET_RXWD_HW_DEC(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(2)) ++#define RTW89_GET_RXWD_SW_DEC(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(1)) ++#define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(0)) ++ ++/* Long Descriptor */ ++#define RTW89_GET_RXWD_FRAG(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) ++#define RTW89_GET_RXWD_SEQ(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) ++#define RTW89_GET_RXWD_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) ++#define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, BIT(28)) ++#define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) ++#define RTW89_GET_RXWD_MAC_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) ++#define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) ++#define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) ++ ++#define RTW89_GET_RXINFO_USR_NUM(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(3, 0)) ++#define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(15, 8)) ++#define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(27, 16)) ++#define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), BIT(28)) ++#define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), BIT(29)) ++#define RTW89_GET_RXINFO_LONG_RXD(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(31, 30)) ++#define RTW89_GET_RXINFO_SERVICE(rpt) \ ++ le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(15, 0)) ++#define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ ++ le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(23, 16)) ++#define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(0)) ++#define RTW89_GET_RXINFO_DATA(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(1)) ++#define RTW89_GET_RXINFO_CTRL(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(2)) ++#define RTW89_GET_RXINFO_MGMT(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(3)) ++#define RTW89_GET_RXINFO_BCM(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(4)) ++#define RTW89_GET_RXINFO_MACID(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) ++ ++#define RTW89_GET_PHY_STS_RSSI_A(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(7, 0)) ++#define RTW89_GET_PHY_STS_RSSI_B(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(15, 8)) ++#define RTW89_GET_PHY_STS_RSSI_C(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(23, 16)) ++#define RTW89_GET_PHY_STS_RSSI_D(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(31, 24)) ++#define RTW89_GET_PHY_STS_LEN(sts) \ ++ le32_get_bits(*((__le32 *)sts), GENMASK(15, 8)) ++#define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ ++ le32_get_bits(*((__le32 *)sts), GENMASK(31, 24)) ++#define RTW89_GET_PHY_STS_IE_TYPE(ie) \ ++ le32_get_bits(*((__le32 *)ie), GENMASK(4, 0)) ++#define RTW89_GET_PHY_STS_IE_LEN(ie) \ ++ le32_get_bits(*((__le32 *)ie), GENMASK(11, 5)) ++#define RTW89_GET_PHY_STS_IE0_CFO(ie) \ ++ le32_get_bits(*((__le32 *)(ie) + 1), GENMASK(31, 20)) ++ ++enum rtw89_tx_channel { ++ RTW89_TXCH_ACH0 = 0, ++ RTW89_TXCH_ACH1 = 1, ++ RTW89_TXCH_ACH2 = 2, ++ RTW89_TXCH_ACH3 = 3, ++ RTW89_TXCH_ACH4 = 4, ++ RTW89_TXCH_ACH5 = 5, ++ RTW89_TXCH_ACH6 = 6, ++ RTW89_TXCH_ACH7 = 7, ++ RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ ++ RTW89_TXCH_CH9 = 9, /* HI Band 0 */ ++ RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ ++ RTW89_TXCH_CH11 = 11, /* HI Band 1 */ ++ RTW89_TXCH_CH12 = 12, /* FW CMD */ ++ ++ /* keep last */ ++ RTW89_TXCH_NUM, ++ RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 ++}; ++ ++enum rtw89_rx_channel { ++ RTW89_RXCH_RXQ = 0, ++ RTW89_RXCH_RPQ = 1, ++ ++ /* keep last */ ++ RTW89_RXCH_NUM, ++ RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 ++}; ++ ++enum rtw89_tx_qsel { ++ RTW89_TX_QSEL_BE_0 = 0x00, ++ RTW89_TX_QSEL_BK_0 = 0x01, ++ RTW89_TX_QSEL_VI_0 = 0x02, ++ RTW89_TX_QSEL_VO_0 = 0x03, ++ RTW89_TX_QSEL_BE_1 = 0x04, ++ RTW89_TX_QSEL_BK_1 = 0x05, ++ RTW89_TX_QSEL_VI_1 = 0x06, ++ RTW89_TX_QSEL_VO_1 = 0x07, ++ RTW89_TX_QSEL_BE_2 = 0x08, ++ RTW89_TX_QSEL_BK_2 = 0x09, ++ RTW89_TX_QSEL_VI_2 = 0x0a, ++ RTW89_TX_QSEL_VO_2 = 0x0b, ++ RTW89_TX_QSEL_BE_3 = 0x0c, ++ RTW89_TX_QSEL_BK_3 = 0x0d, ++ RTW89_TX_QSEL_VI_3 = 0x0e, ++ RTW89_TX_QSEL_VO_3 = 0x0f, ++ RTW89_TX_QSEL_B0_BCN = 0x10, ++ RTW89_TX_QSEL_B0_HI = 0x11, ++ RTW89_TX_QSEL_B0_MGMT = 0x12, ++ RTW89_TX_QSEL_B0_NOPS = 0x13, ++ RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, ++ /* reserved */ ++ /* reserved */ ++ /* reserved */ ++ RTW89_TX_QSEL_B1_BCN = 0x18, ++ RTW89_TX_QSEL_B1_HI = 0x19, ++ RTW89_TX_QSEL_B1_MGMT = 0x1a, ++ RTW89_TX_QSEL_B1_NOPS = 0x1b, ++ RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, ++ /* reserved */ ++ /* reserved */ ++ /* reserved */ ++}; ++ ++enum rtw89_phy_status_ie_type { ++ RTW89_PHYSTS_IE00_CMN_CCK = 0, ++ RTW89_PHYSTS_IE01_CMN_OFDM = 1, ++ RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, ++ RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, ++ RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, ++ RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, ++ RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, ++ RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, ++ RTW89_PHYSTS_IE08_FTR_CH = 8, ++ RTW89_PHYSTS_IE09_FTR_PLCP_0 = 9, ++ RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, ++ RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, ++ RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, ++ RTW89_PHYSTS_IE13_DL_MU_DEF = 13, ++ RTW89_PHYSTS_IE14_TB_UL_CQI = 14, ++ RTW89_PHYSTS_IE15_TB_UL_DEF = 15, ++ RTW89_PHYSTS_IE16_RSVD16 = 16, ++ RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, ++ RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, ++ RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, ++ RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, ++ RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, ++ RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, ++ RTW89_PHYSTS_IE23_RSVD23 = 23, ++ RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A = 24, ++ RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B = 25, ++ RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C = 26, ++ RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D = 27, ++ RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, ++ RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, ++ RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, ++ RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, ++ ++ /* keep last */ ++ RTW89_PHYSTS_IE_NUM, ++ RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 ++}; ++ ++static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ switch (tid) { ++ default: ++ rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); ++ fallthrough; ++ case 0: ++ case 3: ++ return RTW89_TX_QSEL_BE_0; ++ case 1: ++ case 2: ++ return RTW89_TX_QSEL_BK_0; ++ case 4: ++ case 5: ++ return RTW89_TX_QSEL_VI_0; ++ case 6: ++ case 7: ++ return RTW89_TX_QSEL_VO_0; ++ } ++} ++ ++static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) ++{ ++ switch (qsel) { ++ default: ++ rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); ++ fallthrough; ++ case RTW89_TX_QSEL_BE_0: ++ return RTW89_TXCH_ACH0; ++ case RTW89_TX_QSEL_BK_0: ++ return RTW89_TXCH_ACH1; ++ case RTW89_TX_QSEL_VI_0: ++ return RTW89_TXCH_ACH2; ++ case RTW89_TX_QSEL_VO_0: ++ return RTW89_TXCH_ACH3; ++ case RTW89_TX_QSEL_B0_MGMT: ++ return RTW89_TXCH_CH8; ++ case RTW89_TX_QSEL_B0_HI: ++ return RTW89_TXCH_CH9; ++ case RTW89_TX_QSEL_B1_MGMT: ++ return RTW89_TXCH_CH10; ++ case RTW89_TX_QSEL_B1_HI: ++ return RTW89_TXCH_CH11; ++ } ++} ++ ++static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ switch (tid) { ++ case 3: ++ case 2: ++ case 5: ++ case 7: ++ return 1; ++ default: ++ rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); ++ fallthrough; ++ case 0: ++ case 1: ++ case 4: ++ case 6: ++ return 0; ++ } ++} ++ ++static __always_inline void RTW89_SET_TXWD(u8 *txdesc, u32 val, u8 offset, u32 mask) ++{ ++ u32 *txd32 = (u32 *)txdesc; ++ ++ le32p_replace_bits((__le32 *)(txd32 + offset), val, mask); ++} ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/util.h b/drivers/net/wireless/realtek/rtw89/util.h +new file mode 100644 +index 000000000000..229e81009de6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/util.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ * Copyright(c) 2019-2020 Realtek Corporation ++ */ ++#ifndef __RTW89_UTIL_H__ ++#define __RTW89_UTIL_H__ ++ ++#include "core.h" ++ ++#define rtw89_iterate_vifs_bh(rtwdev, iterator, data) \ ++ ieee80211_iterate_active_interfaces_atomic((rtwdev)->hw, \ ++ IEEE80211_IFACE_ITER_NORMAL, iterator, data) ++ ++/* call this function with rtwdev->mutex is held */ ++#define rtw89_for_each_rtwvif(rtwdev, rtwvif) \ ++ list_for_each_entry(rtwvif, &(rtwdev)->rtwvifs_list, list) ++ ++#endif + +From patchwork Fri Aug 20 04:35:18 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448369 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 4D914C4320E + for ; + Fri, 20 Aug 2021 04:36:50 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 20C7D60F8F + for ; + Fri, 20 Aug 2021 04:36:50 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233395AbhHTEh0 (ORCPT + ); + Fri, 20 Aug 2021 00:37:26 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39223 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233148AbhHTEhZ (ORCPT + ); + Fri, 20 Aug 2021 00:37:25 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4aiWjB003764, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4aiWjB003764 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:44 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:43 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:42 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 04/24] rtw89: add debug files +Date: Fri, 20 Aug 2021 12:35:18 +0800 +Message-ID: <20210820043538.12424-5-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +To recognize issues happened in field, two debug methods, debug message and +debugfs, are added. + +The debug messages are written to kernel log, and four levels can be chosen +according to the cases -- debug, info, warn and err. + +Debugfs is used to read and write registers and driver status. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/debug.c | 2404 ++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/debug.h | 77 + + 2 files changed, 2481 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/debug.c + create mode 100644 drivers/net/wireless/realtek/rtw89/debug.h + +diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c +new file mode 100644 +index 000000000000..5b3b1b2d1c43 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/debug.c +@@ -0,0 +1,2404 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++unsigned int rtw89_debug_mask; ++EXPORT_SYMBOL(rtw89_debug_mask); ++module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); ++MODULE_PARM_DESC(debug_mask, "Debugging mask"); ++#endif ++ ++#ifdef CONFIG_RTW89_DEBUGFS ++struct rtw89_debugfs_priv { ++ struct rtw89_dev *rtwdev; ++ int (*cb_read)(struct seq_file *m, void *v); ++ ssize_t (*cb_write)(struct file *filp, const char __user *buffer, ++ size_t count, loff_t *loff); ++ union { ++ u32 cb_data; ++ struct { ++ u32 addr; ++ u8 len; ++ } read_reg; ++ struct { ++ u32 addr; ++ u32 mask; ++ u8 path; ++ } read_rf; ++ struct { ++ u8 ss_dbg:1; ++ u8 dle_dbg:1; ++ u8 dmac_dbg:1; ++ u8 cmac_dbg:1; ++ u8 dbg_port:1; ++ } dbgpkg_en; ++ struct { ++ u32 start; ++ u32 len; ++ u8 sel; ++ } mac_mem; ++ }; ++}; ++ ++static int rtw89_debugfs_single_show(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ ++ return debugfs_priv->cb_read(m, v); ++} ++ ++static ssize_t rtw89_debugfs_single_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ ++ return debugfs_priv->cb_write(filp, buffer, count, loff); ++} ++ ++static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *seqpriv = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; ++ ++ return debugfs_priv->cb_write(filp, buffer, count, loff); ++} ++ ++static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) ++{ ++ return single_open(filp, rtw89_debugfs_single_show, inode->i_private); ++} ++ ++static int rtw89_debugfs_close(struct inode *inode, struct file *filp) ++{ ++ return 0; ++} ++ ++static const struct file_operations file_ops_single_r = { ++ .owner = THIS_MODULE, ++ .open = rtw89_debugfs_single_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct file_operations file_ops_common_rw = { ++ .owner = THIS_MODULE, ++ .open = rtw89_debugfs_single_open, ++ .release = single_release, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = rtw89_debugfs_seq_file_write, ++}; ++ ++static const struct file_operations file_ops_single_w = { ++ .owner = THIS_MODULE, ++ .write = rtw89_debugfs_single_write, ++ .open = simple_open, ++ .release = rtw89_debugfs_close, ++}; ++ ++static ssize_t ++rtw89_debug_priv_read_reg_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x", &addr, &len); ++ if (num != 2) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->read_reg.addr = addr; ++ debugfs_priv->read_reg.len = len; ++ ++ rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ u32 addr, data; ++ u8 len; ++ ++ len = debugfs_priv->read_reg.len; ++ addr = debugfs_priv->read_reg.addr; ++ ++ switch (len) { ++ case 1: ++ data = rtw89_read8(rtwdev, addr); ++ break; ++ case 2: ++ data = rtw89_read16(rtwdev, addr); ++ break; ++ case 4: ++ data = rtw89_read32(rtwdev, addr); ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid read reg len %d\n", len); ++ return -EINVAL; ++ } ++ ++ seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, val, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x %x", &addr, &val, &len); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ switch (len) { ++ case 1: ++ rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); ++ rtw89_write8(rtwdev, addr, (u8)val); ++ break; ++ case 2: ++ rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); ++ rtw89_write16(rtwdev, addr, (u16)val); ++ break; ++ case 4: ++ rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); ++ rtw89_write32(rtwdev, addr, (u32)val); ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid read write len %d\n", len); ++ break; ++ } ++ ++ return count; ++} ++ ++static ssize_t ++rtw89_debug_priv_read_rf_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, mask; ++ u8 path; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ if (path >= rtwdev->chip->rf_path_num) { ++ rtw89_info(rtwdev, "wrong rf path\n"); ++ return -EINVAL; ++ } ++ debugfs_priv->read_rf.addr = addr; ++ debugfs_priv->read_rf.mask = mask; ++ debugfs_priv->read_rf.path = path; ++ ++ rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ u32 addr, data, mask; ++ u8 path; ++ ++ addr = debugfs_priv->read_rf.addr; ++ mask = debugfs_priv->read_rf.mask; ++ path = debugfs_priv->read_rf.path; ++ ++ data = rtw89_read_rf(rtwdev, path, addr, mask); ++ ++ seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, val, mask; ++ u8 path; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); ++ if (num != 4) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ if (path >= rtwdev->chip->rf_path_num) { ++ rtw89_info(rtwdev, "wrong rf path\n"); ++ return -EINVAL; ++ } ++ ++ rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", ++ path, addr, val, mask); ++ rtw89_write_rf(rtwdev, path, addr, mask, val); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u32 addr, offset, data; ++ u8 path; ++ ++ for (path = 0; path < chip->rf_path_num; path++) { ++ seq_printf(m, "RF path %d:\n\n", path); ++ for (addr = 0; addr < 0x100; addr += 4) { ++ seq_printf(m, "0x%08x: ", addr); ++ for (offset = 0; offset < 4; offset++) { ++ data = rtw89_read_rf(rtwdev, path, ++ addr + offset, RFREG_MASK); ++ seq_printf(m, "0x%05x ", data); ++ } ++ seq_puts(m, "\n"); ++ } ++ seq_puts(m, "\n"); ++ } ++ ++ return 0; ++} ++ ++struct txpwr_ent { ++ const char *txt; ++ u8 len; ++}; ++ ++struct txpwr_map { ++ const struct txpwr_ent *ent; ++ u8 size; ++ u32 addr_from; ++ u32 addr_to; ++}; ++ ++#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ ++ { .len = 2, .txt = _t "\t- " _e0 " " _e1 } ++ ++#define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ ++ { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } ++ ++#define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ ++ { .len = 8, .txt = _t "\t- " \ ++ _e0 " " _e1 " " _e2 " " _e3 " " \ ++ _e4 " " _e5 " " _e6 " " _e7 } ++ ++static const struct txpwr_ent __txpwr_ent_byr[] = { ++ __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), ++ __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), ++ __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), ++ /* 1NSS */ ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), ++ __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), ++ /* 2NSS */ ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), ++ __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == ++ (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); ++ ++static const struct txpwr_map __txpwr_map_byr = { ++ .ent = __txpwr_ent_byr, ++ .size = ARRAY_SIZE(__txpwr_ent_byr), ++ .addr_from = R_AX_PWR_BY_RATE, ++ .addr_to = R_AX_PWR_BY_RATE_MAX, ++}; ++ ++static const struct txpwr_ent __txpwr_ent_lmt[] = { ++ /* 1TX */ ++ __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), ++ /* 2TX */ ++ __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == ++ (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); ++ ++static const struct txpwr_map __txpwr_map_lmt = { ++ .ent = __txpwr_ent_lmt, ++ .size = ARRAY_SIZE(__txpwr_ent_lmt), ++ .addr_from = R_AX_PWR_LMT, ++ .addr_to = R_AX_PWR_LMT_MAX, ++}; ++ ++static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { ++ /* 1TX */ ++ __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", ++ "RU26__4", "RU26__5", "RU26__6", "RU26__7"), ++ __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", ++ "RU52__4", "RU52__5", "RU52__6", "RU52__7"), ++ __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", ++ "RU106_4", "RU106_5", "RU106_6", "RU106_7"), ++ /* 2TX */ ++ __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", ++ "RU26__4", "RU26__5", "RU26__6", "RU26__7"), ++ __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", ++ "RU52__4", "RU52__5", "RU52__6", "RU52__7"), ++ __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", ++ "RU106_4", "RU106_5", "RU106_6", "RU106_7"), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == ++ (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); ++ ++static const struct txpwr_map __txpwr_map_lmt_ru = { ++ .ent = __txpwr_ent_lmt_ru, ++ .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), ++ .addr_from = R_AX_PWR_RU_LMT, ++ .addr_to = R_AX_PWR_RU_LMT_MAX, ++}; ++ ++static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, ++ const u8 *buf, const u8 cur) ++{ ++ char *fmt; ++ ++ switch (ent->len) { ++ case 2: ++ fmt = "%s\t| %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); ++ return 2; ++ case 4: ++ fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], ++ buf[cur + 2], buf[cur + 3]); ++ return 4; ++ case 8: ++ fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], ++ buf[cur + 2], buf[cur + 3], buf[cur + 4], ++ buf[cur + 5], buf[cur + 6], buf[cur + 7]); ++ return 8; ++ default: ++ return 0; ++ } ++} ++ ++static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, ++ const struct txpwr_map *map) ++{ ++ u8 fct = rtwdev->chip->txpwr_factor_mac; ++ u8 *buf, cur, i; ++ u32 val, addr; ++ int ret; ++ ++ buf = vzalloc(map->addr_to - map->addr_from + 4); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { ++ ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); ++ if (ret) ++ val = MASKDWORD; ++ ++ cur = addr - map->addr_from; ++ for (i = 0; i < 4; i++, val >>= 8) ++ buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; ++ } ++ ++ for (cur = 0, i = 0; i < map->size; i++) ++ cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); ++ ++ vfree(buf); ++ return 0; ++} ++ ++#define case_REGD(_regd) \ ++ case RTW89_ ## _regd: \ ++ seq_puts(m, #_regd "\n"); \ ++ break ++ ++static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) ++{ ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ ++ switch (regd) { ++ default: ++ seq_printf(m, "UNKNOWN: %d\n", regd); ++ break; ++ case_REGD(WW); ++ case_REGD(ETSI); ++ case_REGD(FCC); ++ case_REGD(MKK); ++ case_REGD(NA); ++ case_REGD(IC); ++ case_REGD(KCC); ++ case_REGD(NCC); ++ case_REGD(CHILE); ++ case_REGD(ACMA); ++ case_REGD(MEXICO); ++ case_REGD(UKRAINE); ++ case_REGD(CN); ++ } ++} ++ ++#undef case_REGD ++ ++static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ seq_puts(m, "[Regulatory] "); ++ __print_regd(m, rtwdev); ++ ++ seq_puts(m, "[SAR]\n"); ++ rtw89_print_sar(m, rtwdev); ++ ++ seq_puts(m, "\n[TX power byrate]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); ++ if (ret) ++ goto err; ++ ++ seq_puts(m, "\n[TX power limit]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); ++ if (ret) ++ goto err; ++ ++ seq_puts(m, "\n[TX power limit_ru]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); ++ if (ret) ++ goto err; ++ ++err: ++ mutex_unlock(&rtwdev->mutex); ++ return ret; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_reg_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ int sel; ++ int ret; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ ret = kstrtoint(buf, 0, &sel); ++ if (ret) ++ return ret; ++ ++ if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { ++ rtw89_info(rtwdev, "invalid args: %d\n", sel); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->cb_data = sel; ++ rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); ++ ++ return count; ++} ++ ++#define RTW89_MAC_PAGE_SIZE 0x100 ++ ++static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; ++ u32 start, end; ++ u32 i, j, k, page; ++ u32 val; ++ ++ switch (reg_sel) { ++ case RTW89_DBG_SEL_MAC_00: ++ seq_puts(m, "Debug selected MAC page 0x00\n"); ++ start = 0x000; ++ end = 0x014; ++ break; ++ case RTW89_DBG_SEL_MAC_40: ++ seq_puts(m, "Debug selected MAC page 0x40\n"); ++ start = 0x040; ++ end = 0x07f; ++ break; ++ case RTW89_DBG_SEL_MAC_80: ++ seq_puts(m, "Debug selected MAC page 0x80\n"); ++ start = 0x080; ++ end = 0x09f; ++ break; ++ case RTW89_DBG_SEL_MAC_C0: ++ seq_puts(m, "Debug selected MAC page 0xc0\n"); ++ start = 0x0c0; ++ end = 0x0df; ++ break; ++ case RTW89_DBG_SEL_MAC_E0: ++ seq_puts(m, "Debug selected MAC page 0xe0\n"); ++ start = 0x0e0; ++ end = 0x0ff; ++ break; ++ case RTW89_DBG_SEL_BB: ++ seq_puts(m, "Debug selected BB register\n"); ++ start = 0x100; ++ end = 0x17f; ++ break; ++ case RTW89_DBG_SEL_IQK: ++ seq_puts(m, "Debug selected IQK register\n"); ++ start = 0x180; ++ end = 0x1bf; ++ break; ++ case RTW89_DBG_SEL_RFC: ++ seq_puts(m, "Debug selected RFC register\n"); ++ start = 0x1c0; ++ end = 0x1ff; ++ break; ++ default: ++ seq_puts(m, "Selected invalid register page\n"); ++ return -EINVAL; ++ } ++ ++ for (i = start; i <= end; i++) { ++ page = i << 8; ++ for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { ++ seq_printf(m, "%08xh : ", 0x18600000 + j); ++ for (k = 0; k < 4; k++) { ++ val = rtw89_read32(rtwdev, j + (k << 2)); ++ seq_printf(m, "%08x ", val); ++ } ++ seq_puts(m, "\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_mem_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 sel, start_addr, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->mac_mem.sel = sel; ++ debugfs_priv->mac_mem.start = start_addr; ++ debugfs_priv->mac_mem.len = len; ++ ++ rtw89_info(rtwdev, "select mem %d start %d len %d\n", ++ sel, start_addr, len); ++ ++ return count; ++} ++ ++static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { ++ [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, ++ [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, ++ [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, ++ [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, ++ [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, ++ [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, ++ [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, ++}; ++ ++static void rtw89_debug_dump_mac_mem(struct seq_file *m, ++ struct rtw89_dev *rtwdev, ++ u8 sel, u32 start_addr, u32 len) ++{ ++ u32 base_addr, start_page, residue; ++ u32 i, j, p, pages; ++ u32 dump_len, remain; ++ u32 val; ++ ++ remain = len; ++ pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; ++ start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; ++ residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; ++ base_addr = mac_mem_base_addr_table[sel]; ++ base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; ++ ++ for (p = 0; p < pages; p++) { ++ dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); ++ for (i = R_AX_INDIR_ACCESS_ENTRY + residue; ++ i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { ++ seq_printf(m, "%08xh:", i); ++ for (j = 0; ++ j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; ++ j++, i += 4) { ++ val = rtw89_read32(rtwdev, i); ++ seq_printf(m, " %08x", val); ++ remain -= 4; ++ } ++ seq_puts(m, "\n"); ++ } ++ base_addr += MAC_MEM_DUMP_PAGE_SIZE; ++ } ++} ++ ++static int ++rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_debug_dump_mac_mem(m, rtwdev, ++ debugfs_priv->mac_mem.sel, ++ debugfs_priv->mac_mem.start, ++ debugfs_priv->mac_mem.len); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ int sel, set; ++ int num; ++ bool enable; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%d %d", &sel, &set); ++ if (num != 2) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ enable = set == 0 ? false : true; ++ switch (sel) { ++ case 0: ++ debugfs_priv->dbgpkg_en.ss_dbg = enable; ++ break; ++ case 1: ++ debugfs_priv->dbgpkg_en.dle_dbg = enable; ++ break; ++ case 2: ++ debugfs_priv->dbgpkg_en.dmac_dbg = enable; ++ break; ++ case 3: ++ debugfs_priv->dbgpkg_en.cmac_dbg = enable; ++ break; ++ case 4: ++ debugfs_priv->dbgpkg_en.dbg_port = enable; ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); ++ return -EINVAL; ++ } ++ ++ rtw89_info(rtwdev, "%s debug port dump %d\n", ++ enable ? "Enable" : "Disable", sel); ++ ++ return count; ++} ++ ++static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++#define DLE_DFI_DUMP(__type, __target, __sel) \ ++({ \ ++ u32 __ctrl; \ ++ u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ ++ u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ ++ u32 __data, __val32; \ ++ int __ret; \ ++ \ ++ __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ ++ DLE_DFI_TYPE_##__target) | \ ++ FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ ++ B_AX_WDE_DFI_ACTIVE; \ ++ rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ ++ __ret = read_poll_timeout(rtw89_read32, __val32, \ ++ !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ ++ 1000, 50000, false, \ ++ rtwdev, __reg_ctrl); \ ++ if (__ret) { \ ++ rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ ++ #__type, #__target, __sel); \ ++ return __ret; \ ++ } \ ++ \ ++ __data = rtw89_read32(rtwdev, __reg_data); \ ++ __data; \ ++}) ++ ++#define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ ++({ \ ++ u32 __freepg, __pubpg; \ ++ u32 __freepg_head, __freepg_tail, __pubpg_num; \ ++ \ ++ __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ ++ __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ ++ __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ ++ __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ ++ __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ ++ seq_printf(__m, "[%s] freepg head: %d\n", \ ++ #__type, __freepg_head); \ ++ seq_printf(__m, "[%s] freepg tail: %d\n", \ ++ #__type, __freepg_tail); \ ++ seq_printf(__m, "[%s] pubpg num : %d\n", \ ++ #__type, __pubpg_num); \ ++}) ++ ++#define case_QUOTA(__m, __type, __id) \ ++ case __type##_QTAID_##__id: \ ++ val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ ++ rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ ++ use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ ++ seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ ++ #__type, #__id, rsv_pgnum); \ ++ seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ ++ #__type, #__id, use_pgnum); \ ++ break ++ u32 quota_id; ++ u32 val32; ++ u16 rsv_pgnum, use_pgnum; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[DLE] : DMAC not enabled\n"); ++ return ret; ++ } ++ ++ DLE_DFI_FREE_PAGE_DUMP(m, WDE); ++ DLE_DFI_FREE_PAGE_DUMP(m, PLE); ++ for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { ++ switch (quota_id) { ++ case_QUOTA(m, WDE, HOST_IF); ++ case_QUOTA(m, WDE, WLAN_CPU); ++ case_QUOTA(m, WDE, DATA_CPU); ++ case_QUOTA(m, WDE, PKTIN); ++ case_QUOTA(m, WDE, CPUIO); ++ } ++ } ++ for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { ++ switch (quota_id) { ++ case_QUOTA(m, PLE, B0_TXPL); ++ case_QUOTA(m, PLE, B1_TXPL); ++ case_QUOTA(m, PLE, C2H); ++ case_QUOTA(m, PLE, H2C); ++ case_QUOTA(m, PLE, WLAN_CPU); ++ case_QUOTA(m, PLE, MPDU); ++ case_QUOTA(m, PLE, CMAC0_RX); ++ case_QUOTA(m, PLE, CMAC1_RX); ++ case_QUOTA(m, PLE, CMAC1_BBRPT); ++ case_QUOTA(m, PLE, WDRLS); ++ case_QUOTA(m, PLE, CPUIO); ++ } ++ } ++ ++ return 0; ++ ++#undef case_QUOTA ++#undef DLE_DFI_DUMP ++#undef DLE_DFI_FREE_PAGE_DUMP ++} ++ ++static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[DMAC] : DMAC not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); ++ seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); ++ seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); ++ seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); ++ seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); ++ seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); ++ seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); ++ seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); ++ seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); ++ seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); ++ seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); ++ seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); ++ seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); ++ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); ++ seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); ++ seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); ++ seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL)); ++ seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); ++ seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); ++ seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); ++ seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); ++ seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); ++ seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); ++ seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); ++ seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); ++ seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); ++ seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); ++ seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); ++ ++ return 0; ++} ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { ++ .sel_addr = R_AX_PTCL_DBG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_PTCL_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x3F, ++ .rd_addr = R_AX_PTCL_DBG_INFO, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PTCL_DBG_INFO_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { ++ .sel_addr = R_AX_PTCL_DBG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_PTCL_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x3F, ++ .rd_addr = R_AX_PTCL_DBG_INFO_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PTCL_DBG_INFO_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { ++ .sel_addr = R_AX_SCH_DBG_SEL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_SCH_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x2F, ++ .rd_addr = R_AX_SCH_DBG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_SCHEDULER_DBG_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { ++ .sel_addr = R_AX_SCH_DBG_SEL_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_SCH_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x2F, ++ .rd_addr = R_AX_SCH_DBG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_SCHEDULER_DBG_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { ++ .sel_addr = R_AX_MACTX_DBG_SEL_CNT, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_MACTX_MASK, ++ .srt = 0x00, ++ .end = 0x19, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { ++ .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_MACTX_MASK, ++ .srt = 0x00, ++ .end = 0x19, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { ++ .sel_addr = R_AX_RX_DEBUG_SELECT, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x58, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { ++ .sel_addr = R_AX_RX_DEBUG_SELECT_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x58, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { ++ .sel_addr = R_AX_RX_STATE_MONITOR, ++ .sel_byte = 1, ++ .sel_msk = B_AX_STATE_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x17, ++ .rd_addr = R_AX_RX_STATE_MONITOR, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RX_STATE_MONITOR_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { ++ .sel_addr = R_AX_RX_STATE_MONITOR_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_STATE_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x17, ++ .rd_addr = R_AX_RX_STATE_MONITOR_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RX_STATE_MONITOR_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { ++ .sel_addr = R_AX_RMAC_PLCP_MON, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PCLP_MON_SEL_MASK, ++ .srt = 0x0, ++ .end = 0xF, ++ .rd_addr = R_AX_RMAC_PLCP_MON, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RMAC_PLCP_MON_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { ++ .sel_addr = R_AX_RMAC_PLCP_MON_C1, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PCLP_MON_SEL_MASK, ++ .srt = 0x0, ++ .end = 0xF, ++ .rd_addr = R_AX_RMAC_PLCP_MON_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RMAC_PLCP_MON_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { ++ .sel_addr = R_AX_DBGSEL_TRXPTCL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, ++ .srt = 0x08, ++ .end = 0x10, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { ++ .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, ++ .srt = 0x08, ++ .end = 0x10, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_2, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x80000001, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80010000, ++ .end = 0x80010004, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80020000, ++ .end = 0x80020FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80030000, ++ .end = 0x80030FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80040000, ++ .end = 0x80040FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80050000, ++ .end = 0x80050FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80060000, ++ .end = 0x80060453, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80070000, ++ .end = 0x80070011, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x80000001, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80010000, ++ .end = 0x8001000A, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80020000, ++ .end = 0x80020DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80030000, ++ .end = 0x80030DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80040000, ++ .end = 0x80040DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80050000, ++ .end = 0x80050DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80060000, ++ .end = 0x80060041, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80070000, ++ .end = 0x80070001, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { ++ .sel_addr = R_AX_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x8000017f, ++ .rd_addr = R_AX_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x03, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x01, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x05, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x05, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x06, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { ++ .sel_addr = R_AX_DBG_CTRL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBG_SEL0, ++ .srt = 0x34, ++ .end = 0x3C, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info * ++rtw89_debug_mac_dbg_port_sel(struct seq_file *m, ++ struct rtw89_dev *rtwdev, u32 sel) ++{ ++ const struct rtw89_mac_dbg_port_info *info; ++ u32 val32; ++ u16 val16; ++ u8 val8; ++ ++ switch (sel) { ++ case RTW89_DBG_PORT_SEL_PTCL_C0: ++ info = &dbg_port_ptcl_c0; ++ val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); ++ val16 |= B_AX_PTCL_DBG_EN; ++ rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); ++ seq_puts(m, "Enable PTCL C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PTCL_C1: ++ info = &dbg_port_ptcl_c1; ++ val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); ++ val16 |= B_AX_PTCL_DBG_EN; ++ rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); ++ seq_puts(m, "Enable PTCL C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_SCH_C0: ++ info = &dbg_port_sch_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); ++ val32 |= B_AX_SCH_DBG_EN; ++ rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); ++ seq_puts(m, "Enable SCH C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_SCH_C1: ++ info = &dbg_port_sch_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); ++ val32 |= B_AX_SCH_DBG_EN; ++ rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); ++ seq_puts(m, "Enable SCH C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TMAC_C0: ++ info = &dbg_port_tmac_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TMAC C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TMAC_C1: ++ info = &dbg_port_tmac_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TMAC C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_C0: ++ info = &dbg_port_rmac_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ ++ val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); ++ seq_puts(m, "Enable RMAC C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_C1: ++ info = &dbg_port_rmac_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ ++ val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); ++ seq_puts(m, "Enable RMAC C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMACST_C0: ++ info = &dbg_port_rmacst_c0; ++ seq_puts(m, "Enable RMAC state C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMACST_C1: ++ info = &dbg_port_rmacst_c1; ++ seq_puts(m, "Enable RMAC state C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: ++ info = &dbg_port_rmac_plcp_c0; ++ seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: ++ info = &dbg_port_rmac_plcp_c1; ++ seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TRXPTCL_C0: ++ info = &dbg_port_trxptcl_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TRXPTCL_C1: ++ info = &dbg_port_trxptcl_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOL_C0: ++ info = &dbg_port_tx_infol_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOH_C0: ++ info = &dbg_port_tx_infoh_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOL_C1: ++ info = &dbg_port_tx_infol_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOH_C1: ++ info = &dbg_port_tx_infoh_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: ++ info = &dbg_port_txtf_infol_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx tf infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: ++ info = &dbg_port_txtf_infoh_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx tf infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: ++ info = &dbg_port_txtf_infol_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx tf infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: ++ info = &dbg_port_txtf_infoh_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx tf infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: ++ info = &dbg_port_wde_bufmgn_freepg; ++ seq_puts(m, "Enable wde bufmgn freepg dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: ++ info = &dbg_port_wde_bufmgn_quota; ++ seq_puts(m, "Enable wde bufmgn quota dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: ++ info = &dbg_port_wde_bufmgn_pagellt; ++ seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: ++ info = &dbg_port_wde_bufmgn_pktinfo; ++ seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: ++ info = &dbg_port_wde_quemgn_prepkt; ++ seq_puts(m, "Enable wde quemgn prepkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: ++ info = &dbg_port_wde_quemgn_nxtpkt; ++ seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: ++ info = &dbg_port_wde_quemgn_qlnktbl; ++ seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: ++ info = &dbg_port_wde_quemgn_qempty; ++ seq_puts(m, "Enable wde quemgn qempty dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: ++ info = &dbg_port_ple_bufmgn_freepg; ++ seq_puts(m, "Enable ple bufmgn freepg dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: ++ info = &dbg_port_ple_bufmgn_quota; ++ seq_puts(m, "Enable ple bufmgn quota dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: ++ info = &dbg_port_ple_bufmgn_pagellt; ++ seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: ++ info = &dbg_port_ple_bufmgn_pktinfo; ++ seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: ++ info = &dbg_port_ple_quemgn_prepkt; ++ seq_puts(m, "Enable ple quemgn prepkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: ++ info = &dbg_port_ple_quemgn_nxtpkt; ++ seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: ++ info = &dbg_port_ple_quemgn_qlnktbl; ++ seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: ++ info = &dbg_port_ple_quemgn_qempty; ++ seq_puts(m, "Enable ple quemgn qempty dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PKTINFO: ++ info = &dbg_port_pktinfo; ++ seq_puts(m, "Enable pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_TXDMA: ++ info = &dbg_port_pcie_txdma; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie txdma dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_RXDMA: ++ info = &dbg_port_pcie_rxdma; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie rxdma dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_CVT: ++ info = &dbg_port_pcie_cvt; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie cvt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_CXPL: ++ info = &dbg_port_pcie_cxpl; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie cxpl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_IO: ++ info = &dbg_port_pcie_io; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie io dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_MISC: ++ info = &dbg_port_pcie_misc; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie misc dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_MISC2: ++ info = &dbg_port_pcie_misc2; ++ val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); ++ val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, ++ B_AX_DBG_SEL_MASK); ++ rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); ++ seq_puts(m, "Enable pcie misc2 dump.\n"); ++ break; ++ default: ++ seq_puts(m, "Dbg port select err\n"); ++ return NULL; ++ } ++ ++ return info; ++} ++ ++static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) ++{ ++ if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && ++ sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && ++ sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) ++ return false; ++ if (rtwdev->chip->chip_id == RTL8852B && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && ++ sel <= RTW89_DBG_PORT_SEL_PKTINFO) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) ++ return false; ++ ++ return true; ++} ++ ++static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, ++ struct seq_file *m, u32 sel) ++{ ++ const struct rtw89_mac_dbg_port_info *info; ++ u8 val8; ++ u16 val16; ++ u32 val32; ++ u32 i; ++ ++ info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); ++ if (!info) { ++ rtw89_err(rtwdev, "failed to select debug port %d\n", sel); ++ return -EINVAL; ++ } ++ ++#define case_DBG_SEL(__sel) \ ++ case RTW89_DBG_PORT_SEL_##__sel: \ ++ seq_puts(m, "Dump debug port " #__sel ":\n"); \ ++ break ++ ++ switch (sel) { ++ case_DBG_SEL(PTCL_C0); ++ case_DBG_SEL(PTCL_C1); ++ case_DBG_SEL(SCH_C0); ++ case_DBG_SEL(SCH_C1); ++ case_DBG_SEL(TMAC_C0); ++ case_DBG_SEL(TMAC_C1); ++ case_DBG_SEL(RMAC_C0); ++ case_DBG_SEL(RMAC_C1); ++ case_DBG_SEL(RMACST_C0); ++ case_DBG_SEL(RMACST_C1); ++ case_DBG_SEL(TRXPTCL_C0); ++ case_DBG_SEL(TRXPTCL_C1); ++ case_DBG_SEL(TX_INFOL_C0); ++ case_DBG_SEL(TX_INFOH_C0); ++ case_DBG_SEL(TX_INFOL_C1); ++ case_DBG_SEL(TX_INFOH_C1); ++ case_DBG_SEL(TXTF_INFOL_C0); ++ case_DBG_SEL(TXTF_INFOH_C0); ++ case_DBG_SEL(TXTF_INFOL_C1); ++ case_DBG_SEL(TXTF_INFOH_C1); ++ case_DBG_SEL(WDE_BUFMGN_FREEPG); ++ case_DBG_SEL(WDE_BUFMGN_QUOTA); ++ case_DBG_SEL(WDE_BUFMGN_PAGELLT); ++ case_DBG_SEL(WDE_BUFMGN_PKTINFO); ++ case_DBG_SEL(WDE_QUEMGN_PREPKT); ++ case_DBG_SEL(WDE_QUEMGN_NXTPKT); ++ case_DBG_SEL(WDE_QUEMGN_QLNKTBL); ++ case_DBG_SEL(WDE_QUEMGN_QEMPTY); ++ case_DBG_SEL(PLE_BUFMGN_FREEPG); ++ case_DBG_SEL(PLE_BUFMGN_QUOTA); ++ case_DBG_SEL(PLE_BUFMGN_PAGELLT); ++ case_DBG_SEL(PLE_BUFMGN_PKTINFO); ++ case_DBG_SEL(PLE_QUEMGN_PREPKT); ++ case_DBG_SEL(PLE_QUEMGN_NXTPKT); ++ case_DBG_SEL(PLE_QUEMGN_QLNKTBL); ++ case_DBG_SEL(PLE_QUEMGN_QEMPTY); ++ case_DBG_SEL(PKTINFO); ++ case_DBG_SEL(PCIE_TXDMA); ++ case_DBG_SEL(PCIE_RXDMA); ++ case_DBG_SEL(PCIE_CVT); ++ case_DBG_SEL(PCIE_CXPL); ++ case_DBG_SEL(PCIE_IO); ++ case_DBG_SEL(PCIE_MISC); ++ case_DBG_SEL(PCIE_MISC2); ++ } ++ ++#undef case_DBG_SEL ++ ++ seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); ++ seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); ++ ++ for (i = info->srt; i <= info->end; i++) { ++ switch (info->sel_byte) { ++ case 1: ++ default: ++ rtw89_write8_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%02X: ", i); ++ break; ++ case 2: ++ rtw89_write16_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%04X: ", i); ++ break; ++ case 4: ++ rtw89_write32_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%04X: ", i); ++ break; ++ } ++ ++ udelay(10); ++ ++ switch (info->rd_byte) { ++ case 1: ++ default: ++ val8 = rtw89_read8_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%02X\n", val8); ++ break; ++ case 2: ++ val16 = rtw89_read16_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%04X\n", val16); ++ break; ++ case 4: ++ val32 = rtw89_read32_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%08X\n", val32); ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ u32 sel; ++ int ret = 0; ++ ++ for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; ++ sel < RTW89_DBG_PORT_SEL_LAST; sel++) { ++ if (!is_dbg_port_valid(rtwdev, sel)) ++ continue; ++ ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); ++ if (ret) { ++ rtw89_err(rtwdev, ++ "failed to dump debug port %d\n", sel); ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int ++rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ if (debugfs_priv->dbgpkg_en.ss_dbg) ++ rtw89_debug_mac_dump_ss_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dle_dbg) ++ rtw89_debug_mac_dump_dle_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dmac_dbg) ++ rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.cmac_dbg) ++ rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dbg_port) ++ rtw89_debug_mac_dump_dbg_port(rtwdev, m); ++ ++ return 0; ++}; ++ ++static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[256]; ++ size_t buf_size; ++ u8 h2c[128]; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ num = buf_size / 2; ++ if (hex2bin(h2c, buf, num)) { ++ rtw89_info(rtwdev, "invalid format: H1H2H3...\n"); ++ return -EINVAL; ++ } ++ ++ rtw89_fw_h2c_raw(rtwdev, h2c, num); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ rtw89_btc_dump_info(rtwdev, m); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ bool btc_manual; ++ ++ if (kstrtobool_from_user(user_buf, count, &btc_manual)) ++ goto out; ++ ++ btc->ctrl.manual = btc_manual; ++out: ++ return count; ++} ++ ++static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ bool fw_log_manual; ++ ++ if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) ++ goto out; ++ ++ mutex_lock(&rtwdev->mutex); ++ fw_info->fw_log_enable = fw_log_manual; ++ rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); ++ mutex_unlock(&rtwdev->mutex); ++out: ++ return count; ++} ++ ++static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) ++{ ++ static const char * const he_gi_str[] = { ++ [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", ++ [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", ++ [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", ++ }; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rate_info *rate = &rtwsta->ra_report.txrate; ++ struct ieee80211_rx_status *status = &rtwsta->rx_status; ++ struct seq_file *m = (struct seq_file *)data; ++ u8 rssi; ++ ++ seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); ++ ++ if (rate->flags & RATE_INFO_FLAGS_MCS) ++ seq_printf(m, "HT MCS-%d%s", rate->mcs, ++ rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); ++ else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) ++ seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, ++ rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); ++ else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) ++ seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, ++ rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? ++ he_gi_str[rate->he_gi] : "N/A"); ++ else ++ seq_printf(m, "Legacy %d", rate->legacy); ++ seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); ++ seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, ++ sta->max_rc_amsdu_len); ++ ++ seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); ++ ++ switch (status->encoding) { ++ case RX_ENC_LEGACY: ++ seq_printf(m, "Legacy %d", status->rate_idx + ++ (status->band == NL80211_BAND_5GHZ ? 4 : 0)); ++ break; ++ case RX_ENC_HT: ++ seq_printf(m, "HT MCS-%d%s", status->rate_idx, ++ status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); ++ break; ++ case RX_ENC_VHT: ++ seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, ++ status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); ++ break; ++ case RX_ENC_HE: ++ seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, ++ status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? ++ he_gi_str[rate->he_gi] : "N/A"); ++ break; ++ } ++ seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); ++ ++ rssi = ewma_rssi_read(&rtwsta->avg_rssi); ++ seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", ++ RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); ++} ++ ++static void ++rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, ++ enum rtw89_hw_rate first_rate, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) ++ seq_printf(m, "%s%u", i == 0 ? "" : ", ", ++ pkt_stat->rx_rate_cnt[first_rate + i]); ++} ++ ++static const struct rtw89_rx_rate_cnt_info { ++ enum rtw89_hw_rate first_rate; ++ int len; ++ const char *rate_mode; ++} rtw89_rx_rate_cnt_infos[] = { ++ {RTW89_HW_RATE_CCK1, 4, "Legacy:"}, ++ {RTW89_HW_RATE_OFDM6, 8, "OFDM:"}, ++ {RTW89_HW_RATE_MCS0, 8, "HT 0:"}, ++ {RTW89_HW_RATE_MCS8, 8, "HT 1:"}, ++ {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, "VHT 1SS:"}, ++ {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, "VHT 2SS:"}, ++ {RTW89_HW_RATE_HE_NSS1_MCS0, 12, "HE 1SS:"}, ++ {RTW89_HW_RATE_HE_NSS2_MCS0, 12, "HE 2ss:"}, ++}; ++ ++static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; ++ const struct rtw89_rx_rate_cnt_info *info; ++ int i; ++ ++ seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", ++ stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, ++ stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); ++ seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); ++ seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, ++ stats->rx_avg_len); ++ ++ seq_puts(m, "RX count:\n"); ++ for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { ++ info = &rtw89_rx_rate_cnt_infos[i]; ++ seq_printf(m, "%10s [", info->rate_mode); ++ rtw89_debug_append_rx_rate(m, pkt_stat, ++ info->first_rate, info->len); ++ seq_puts(m, "]\n"); ++ } ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); ++ ++ return 0; ++} ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { ++ .cb_read = rtw89_debug_priv_read_reg_get, ++ .cb_write = rtw89_debug_priv_read_reg_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { ++ .cb_write = rtw89_debug_priv_write_reg_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { ++ .cb_read = rtw89_debug_priv_read_rf_get, ++ .cb_write = rtw89_debug_priv_read_rf_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { ++ .cb_write = rtw89_debug_priv_write_rf_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { ++ .cb_read = rtw89_debug_priv_rf_reg_dump_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { ++ .cb_read = rtw89_debug_priv_txpwr_table_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { ++ .cb_read = rtw89_debug_priv_mac_reg_dump_get, ++ .cb_write = rtw89_debug_priv_mac_reg_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { ++ .cb_read = rtw89_debug_priv_mac_mem_dump_get, ++ .cb_write = rtw89_debug_priv_mac_mem_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { ++ .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, ++ .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { ++ .cb_write = rtw89_debug_priv_send_h2c_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { ++ .cb_read = rtw89_debug_priv_btc_info_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { ++ .cb_write = rtw89_debug_priv_btc_manual_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { ++ .cb_write = rtw89_debug_fw_log_btc_manual_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { ++ .cb_read = rtw89_debug_priv_phy_info_get, ++}; ++ ++#define rtw89_debugfs_add(name, mode, fopname, parent) \ ++ do { \ ++ rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ ++ if (!debugfs_create_file(#name, mode, \ ++ parent, &rtw89_debug_priv_ ##name, \ ++ &file_ops_ ##fopname)) \ ++ pr_debug("Unable to initialize debugfs:%s\n", #name); \ ++ } while (0) ++ ++#define rtw89_debugfs_add_w(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) ++#define rtw89_debugfs_add_rw(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) ++#define rtw89_debugfs_add_r(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) ++ ++void rtw89_debugfs_init(struct rtw89_dev *rtwdev) ++{ ++ struct dentry *debugfs_topdir; ++ ++ debugfs_topdir = debugfs_create_dir("rtw89", ++ rtwdev->hw->wiphy->debugfsdir); ++ ++ rtw89_debugfs_add_rw(read_reg); ++ rtw89_debugfs_add_w(write_reg); ++ rtw89_debugfs_add_rw(read_rf); ++ rtw89_debugfs_add_w(write_rf); ++ rtw89_debugfs_add_r(rf_reg_dump); ++ rtw89_debugfs_add_r(txpwr_table); ++ rtw89_debugfs_add_rw(mac_reg_dump); ++ rtw89_debugfs_add_rw(mac_mem_dump); ++ rtw89_debugfs_add_rw(mac_dbg_port_dump); ++ rtw89_debugfs_add_w(send_h2c); ++ rtw89_debugfs_add_r(btc_info); ++ rtw89_debugfs_add_w(btc_manual); ++ rtw89_debugfs_add_w(fw_log_manual); ++ rtw89_debugfs_add_r(phy_info); ++} ++#endif ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++void __rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...) ++{ ++ struct va_format vaf = { ++ .fmt = fmt, ++ }; ++ ++ va_list args; ++ ++ va_start(args, fmt); ++ vaf.va = &args; ++ ++ if (rtw89_debug_mask & mask) ++ dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); ++ ++ va_end(args); ++} ++EXPORT_SYMBOL(__rtw89_debug); ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/debug.h b/drivers/net/wireless/realtek/rtw89/debug.h +new file mode 100644 +index 000000000000..f14b726c1a9f +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/debug.h +@@ -0,0 +1,77 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_DEBUG_H__ ++#define __RTW89_DEBUG_H__ ++ ++#include "core.h" ++ ++enum rtw89_debug_mask { ++ RTW89_DBG_TXRX = BIT(0), ++ RTW89_DBG_RFK = BIT(1), ++ RTW89_DBG_RFK_TRACK = BIT(2), ++ RTW89_DBG_CFO = BIT(3), ++ RTW89_DBG_TSSI = BIT(4), ++ RTW89_DBG_TXPWR = BIT(5), ++ RTW89_DBG_HCI = BIT(6), ++ RTW89_DBG_RA = BIT(7), ++ RTW89_DBG_REGD = BIT(8), ++ RTW89_DBG_PHY_TRACK = BIT(9), ++ RTW89_DBG_DIG = BIT(10), ++ RTW89_DBG_SER = BIT(11), ++ RTW89_DBG_FW = BIT(12), ++ RTW89_DBG_BTC = BIT(13), ++ RTW89_DBG_BF = BIT(14), ++}; ++ ++enum rtw89_debug_mac_reg_sel { ++ RTW89_DBG_SEL_MAC_00, ++ RTW89_DBG_SEL_MAC_40, ++ RTW89_DBG_SEL_MAC_80, ++ RTW89_DBG_SEL_MAC_C0, ++ RTW89_DBG_SEL_MAC_E0, ++ RTW89_DBG_SEL_BB, ++ RTW89_DBG_SEL_IQK, ++ RTW89_DBG_SEL_RFC, ++}; ++ ++#ifdef CONFIG_RTW89_DEBUGFS ++void rtw89_debugfs_init(struct rtw89_dev *rtwdev); ++#else ++static inline void rtw89_debugfs_init(struct rtw89_dev *rtwdev) {} ++#endif ++ ++#define rtw89_info(rtwdev, a...) dev_info((rtwdev)->dev, ##a) ++#define rtw89_warn(rtwdev, a...) dev_warn((rtwdev)->dev, ##a) ++#define rtw89_err(rtwdev, a...) dev_err((rtwdev)->dev, ##a) ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++extern unsigned int rtw89_debug_mask; ++#define rtw89_debug(rtwdev, a...) __rtw89_debug(rtwdev, ##a) ++ ++__printf(3, 4) ++void __rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...); ++static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *prefix_str, ++ const void *buf, size_t len) ++{ ++ if (!(rtw89_debug_mask & mask)) ++ return; ++ ++ print_hex_dump_bytes(prefix_str, DUMP_PREFIX_OFFSET, buf, len); ++} ++#else ++static inline void rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...) {} ++static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *prefix_str, ++ const void *buf, size_t len) {} ++#endif ++ ++#endif + +From patchwork Fri Aug 20 04:35:19 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448367 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id CC194C43214 + for ; + Fri, 20 Aug 2021 04:36:53 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id A9D7660F8F + for ; + Fri, 20 Aug 2021 04:36:53 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233505AbhHTEh3 (ORCPT + ); + Fri, 20 Aug 2021 00:37:29 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39234 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232776AbhHTEh2 (ORCPT + ); + Fri, 20 Aug 2021 00:37:28 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4albpF003889, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4albpF003889 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:47 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:47 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:46 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 05/24] rtw89: add efuse files +Date: Fri, 20 Aug 2021 12:35:19 +0800 +Message-ID: <20210820043538.12424-6-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Efuse is divided into several parts, in which physical map and PHY cap +parts are read and parsed by driver. + +Storing main data, physical map is translated into logic map, and then use +chip specific map to explain the logic map. Then, we can have MAC address, +country code, thermal tracking calibration values, and so on. + +PHY cap part is used to store PHY data. We don't need to translate it, +because it's a direct map, like logic map. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/efuse.c | 188 +++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/efuse.h | 13 ++ + 2 files changed, 201 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/efuse.c + create mode 100644 drivers/net/wireless/realtek/rtw89/efuse.h + +diff --git a/drivers/net/wireless/realtek/rtw89/efuse.c b/drivers/net/wireless/realtek/rtw89/efuse.c +new file mode 100644 +index 000000000000..c0b80f3da56c +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/efuse.c +@@ -0,0 +1,188 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "efuse.h" ++#include "reg.h" ++ ++enum rtw89_efuse_bank { ++ RTW89_EFUSE_BANK_WIFI, ++ RTW89_EFUSE_BANK_BT, ++}; ++ ++static int rtw89_switch_efuse_bank(struct rtw89_dev *rtwdev, ++ enum rtw89_efuse_bank bank) ++{ ++ u8 val; ++ ++ val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1, ++ B_AX_EF_CELL_SEL_MASK); ++ if (bank == val) ++ return 0; ++ ++ rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK, ++ bank); ++ ++ val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1, ++ B_AX_EF_CELL_SEL_MASK); ++ if (bank == val) ++ return 0; ++ ++ return -EBUSY; ++} ++ ++static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map, ++ u32 dump_addr, u32 dump_size) ++{ ++ u32 efuse_ctl; ++ u32 addr; ++ int ret; ++ ++ rtw89_switch_efuse_bank(rtwdev, RTW89_EFUSE_BANK_WIFI); ++ ++ for (addr = dump_addr; addr < dump_addr + dump_size; addr++) { ++ efuse_ctl = u32_encode_bits(addr, B_AX_EF_ADDR_MASK); ++ rtw89_write32(rtwdev, R_AX_EFUSE_CTRL, efuse_ctl & ~B_AX_EF_RDY); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, efuse_ctl, ++ efuse_ctl & B_AX_EF_RDY, 1, 1000000, ++ true, rtwdev, R_AX_EFUSE_CTRL); ++ if (ret) ++ return -EBUSY; ++ ++ *map++ = (u8)(efuse_ctl & 0xff); ++ } ++ ++ return 0; ++} ++ ++#define invalid_efuse_header(hdr1, hdr2) \ ++ ((hdr1) == 0xff || (hdr2) == 0xff) ++#define invalid_efuse_content(word_en, i) \ ++ (((word_en) & BIT(i)) != 0x0) ++#define get_efuse_blk_idx(hdr1, hdr2) \ ++ ((((hdr2) & 0xf0) >> 4) | (((hdr1) & 0x0f) << 4)) ++#define block_idx_to_logical_idx(blk_idx, i) \ ++ (((blk_idx) << 3) + ((i) << 1)) ++static int rtw89_dump_logical_efuse_map(struct rtw89_dev *rtwdev, u8 *phy_map, ++ u8 *log_map) ++{ ++ u32 physical_size = rtwdev->chip->physical_efuse_size; ++ u32 logical_size = rtwdev->chip->logical_efuse_size; ++ u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size; ++ u32 phy_idx = sec_ctrl_size; ++ u32 log_idx; ++ u8 hdr1, hdr2; ++ u8 blk_idx; ++ u8 word_en; ++ int i; ++ ++ while (phy_idx < physical_size - sec_ctrl_size) { ++ hdr1 = phy_map[phy_idx]; ++ hdr2 = phy_map[phy_idx + 1]; ++ if (invalid_efuse_header(hdr1, hdr2)) ++ break; ++ ++ blk_idx = get_efuse_blk_idx(hdr1, hdr2); ++ word_en = hdr2 & 0xf; ++ phy_idx += 2; ++ ++ for (i = 0; i < 4; i++) { ++ if (invalid_efuse_content(word_en, i)) ++ continue; ++ ++ log_idx = block_idx_to_logical_idx(blk_idx, i); ++ if (phy_idx + 1 > physical_size - sec_ctrl_size - 1 || ++ log_idx + 1 > logical_size) ++ return -EINVAL; ++ ++ log_map[log_idx] = phy_map[phy_idx]; ++ log_map[log_idx + 1] = phy_map[phy_idx + 1]; ++ phy_idx += 2; ++ } ++ } ++ return 0; ++} ++ ++int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev) ++{ ++ u32 phy_size = rtwdev->chip->physical_efuse_size; ++ u32 log_size = rtwdev->chip->logical_efuse_size; ++ u8 *phy_map = NULL; ++ u8 *log_map = NULL; ++ int ret; ++ ++ if (rtw89_read16(rtwdev, R_AX_SYS_WL_EFUSE_CTRL) & B_AX_AUTOLOAD_SUS) ++ rtwdev->efuse.valid = true; ++ else ++ rtw89_warn(rtwdev, "failed to check efuse autoload\n"); ++ ++ phy_map = kmalloc(phy_size, GFP_KERNEL); ++ log_map = kmalloc(log_size, GFP_KERNEL); ++ ++ if (!phy_map || !log_map) { ++ ret = -ENOMEM; ++ goto out_free; ++ } ++ ++ ret = rtw89_dump_physical_efuse_map(rtwdev, phy_map, 0, phy_size); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump efuse physical map\n"); ++ goto out_free; ++ } ++ ++ memset(log_map, 0xff, log_size); ++ ret = rtw89_dump_logical_efuse_map(rtwdev, phy_map, log_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump efuse logical map\n"); ++ goto out_free; ++ } ++ ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "log_map: ", log_map, log_size); ++ ++ ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to read efuse map\n"); ++ goto out_free; ++ } ++ ++out_free: ++ kfree(log_map); ++ kfree(phy_map); ++ ++ return ret; ++} ++ ++int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev) ++{ ++ u32 phycap_addr = rtwdev->chip->phycap_addr; ++ u32 phycap_size = rtwdev->chip->phycap_size; ++ u8 *phycap_map = NULL; ++ int ret = 0; ++ ++ if (!phycap_size) ++ return 0; ++ ++ phycap_map = kmalloc(phycap_size, GFP_KERNEL); ++ if (!phycap_map) ++ return -ENOMEM; ++ ++ ret = rtw89_dump_physical_efuse_map(rtwdev, phycap_map, ++ phycap_addr, phycap_size); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump phycap map\n"); ++ goto out_free; ++ } ++ ++ ret = rtwdev->chip->ops->read_phycap(rtwdev, phycap_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to read phycap map\n"); ++ goto out_free; ++ } ++ ++out_free: ++ kfree(phycap_map); ++ ++ return ret; ++} +diff --git a/drivers/net/wireless/realtek/rtw89/efuse.h b/drivers/net/wireless/realtek/rtw89/efuse.h +new file mode 100644 +index 000000000000..622ff95e7476 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/efuse.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_EFUSE_H__ ++#define __RTW89_EFUSE_H__ ++ ++#include "core.h" ++ ++int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev); ++int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev); ++ ++#endif + +From patchwork Fri Aug 20 04:35:20 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448371 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 203EFC4338F + for ; + Fri, 20 Aug 2021 04:36:58 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id EBF7760F91 + for ; + Fri, 20 Aug 2021 04:36:57 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S232649AbhHTEhe (ORCPT + ); + Fri, 20 Aug 2021 00:37:34 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39238 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232776AbhHTEhd (ORCPT + ); + Fri, 20 Aug 2021 00:37:33 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4apkY7003958, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4apkY7003958 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:51 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:51 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:50 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 06/24] rtw89: add files to download and communicate with + firmware +Date: Fri, 20 Aug 2021 12:35:20 +0800 +Message-ID: <20210820043538.12424-7-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +The firmware must be downloaded right after HCI basic initialization, and +then we can obtain hardware capabilities that are used to do mac80211 +register hw. + +To download firmware, we need to parse the header to know how many sections +the firmware has, and then download each section to proper location. + +We introduce H2C and C2H to do bi-direction communication with firmware, +and both support packet-based and register-based methods. +Normally, we use packet-based H2C/C2H, because it has no number and size +limits. In contrast, register-based H2C/C2H has only one message and +fix-four-dword in size. + +Header size of packet-based H2C/C2H is eight bytes (two dwords), which uses +a hierarchical IDs, containing type, category, class and function, to +classify a H2C or C2H command. + +When a C2H is received in interrupt context, we don't process it right +there, but queue the skb and wake up a ieee80211 work to handle the skb. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/fw.c | 1600 +++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/fw.h | 1394 ++++++++++++++++++++ + 2 files changed, 2994 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/fw.c + create mode 100644 drivers/net/wireless/realtek/rtw89/fw.h + +diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c +new file mode 100644 +index 000000000000..5d64a047e125 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/fw.c +@@ -0,0 +1,1600 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++ ++static struct sk_buff *rtw89_fw_h2c_alloc_skb(u32 len, bool header) ++{ ++ struct sk_buff *skb; ++ u32 header_len = 0; ++ ++ if (header) ++ header_len = H2C_HEADER_LEN; ++ ++ skb = dev_alloc_skb(len + header_len + 24); ++ if (!skb) ++ return NULL; ++ skb_reserve(skb, header_len + 24); ++ memset(skb->data, 0, len); ++ ++ return skb; ++} ++ ++struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len) ++{ ++ return rtw89_fw_h2c_alloc_skb(len, true); ++} ++ ++struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len) ++{ ++ return rtw89_fw_h2c_alloc_skb(len, false); ++} ++ ++static u8 _fw_get_rdy(struct rtw89_dev *rtwdev) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); ++ ++ return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); ++} ++ ++#define FWDL_WAIT_CNT 400000 ++int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev) ++{ ++ u8 val; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(_fw_get_rdy, val, ++ val == RTW89_FWDL_WCPU_FW_INIT_RDY, ++ 1, FWDL_WAIT_CNT, false, rtwdev); ++ if (ret) { ++ switch (val) { ++ case RTW89_FWDL_CHECKSUM_FAIL: ++ rtw89_err(rtwdev, "fw checksum fail\n"); ++ return -EINVAL; ++ ++ case RTW89_FWDL_SECURITY_FAIL: ++ rtw89_err(rtwdev, "fw security fail\n"); ++ return -EINVAL; ++ ++ case RTW89_FWDL_CV_NOT_MATCH: ++ rtw89_err(rtwdev, "fw cv not match\n"); ++ return -EINVAL; ++ ++ default: ++ return -EBUSY; ++ } ++ } ++ ++ set_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ ++ return 0; ++} ++ ++static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len, ++ struct rtw89_fw_bin_info *info) ++{ ++ struct rtw89_fw_hdr_section_info *section_info; ++ const u8 *fw_end = fw + len; ++ const u8 *bin; ++ u32 i; ++ ++ if (!info) ++ return -EINVAL; ++ ++ info->section_num = GET_FW_HDR_SEC_NUM(fw); ++ info->hdr_len = RTW89_FW_HDR_SIZE + ++ info->section_num * RTW89_FW_SECTION_HDR_SIZE; ++ SET_FW_HDR_PART_SIZE(fw, FWDL_SECTION_PER_PKT_LEN); ++ ++ bin = fw + info->hdr_len; ++ ++ /* jump to section header */ ++ fw += RTW89_FW_HDR_SIZE; ++ section_info = info->section_info; ++ for (i = 0; i < info->section_num; i++) { ++ section_info->len = GET_FWSECTION_HDR_SEC_SIZE(fw); ++ if (GET_FWSECTION_HDR_CHECKSUM(fw)) ++ section_info->len += FWDL_SECTION_CHKSUM_LEN; ++ section_info->redl = GET_FWSECTION_HDR_REDL(fw); ++ section_info->dladdr = ++ GET_FWSECTION_HDR_DL_ADDR(fw) & 0x1fffffff; ++ section_info->addr = bin; ++ bin += section_info->len; ++ fw += RTW89_FW_SECTION_HDR_SIZE; ++ section_info++; ++ } ++ ++ if (fw_end != bin) { ++ rtw89_err(rtwdev, "[ERR]fw bin size\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static ++int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type, ++ struct rtw89_fw_suit *fw_suit) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ const u8 *mfw = fw_info->firmware->data; ++ u32 mfw_len = fw_info->firmware->size; ++ const struct rtw89_mfw_hdr *mfw_hdr = (const struct rtw89_mfw_hdr *)mfw; ++ const struct rtw89_mfw_info *mfw_info; ++ int i; ++ ++ if (mfw_hdr->sig != RTW89_MFW_SIG) { ++ rtw89_debug(rtwdev, RTW89_DBG_FW, "use legacy firmware\n"); ++ /* legacy firmware support normal type only */ ++ if (type != RTW89_FW_NORMAL) ++ return -EINVAL; ++ fw_suit->data = mfw; ++ fw_suit->size = mfw_len; ++ return 0; ++ } ++ ++ for (i = 0; i < mfw_hdr->fw_nr; i++) { ++ mfw_info = &mfw_hdr->info[i]; ++ if (mfw_info->cv != rtwdev->hal.cv || ++ mfw_info->type != type || ++ mfw_info->mp) ++ continue; ++ ++ fw_suit->data = mfw + le32_to_cpu(mfw_info->shift); ++ fw_suit->size = le32_to_cpu(mfw_info->size); ++ return 0; ++ } ++ ++ rtw89_err(rtwdev, "no suitable firmware found\n"); ++ return -ENOENT; ++} ++ ++static void rtw89_fw_update_ver(struct rtw89_dev *rtwdev, ++ enum rtw89_fw_type type, ++ struct rtw89_fw_suit *fw_suit) ++{ ++ const u8 *hdr = fw_suit->data; ++ ++ fw_suit->major_ver = GET_FW_HDR_MAJOR_VERSION(hdr); ++ fw_suit->minor_ver = GET_FW_HDR_MINOR_VERSION(hdr); ++ fw_suit->sub_ver = GET_FW_HDR_SUBVERSION(hdr); ++ fw_suit->sub_idex = GET_FW_HDR_SUBINDEX(hdr); ++ fw_suit->build_year = GET_FW_HDR_YEAR(hdr); ++ fw_suit->build_mon = GET_FW_HDR_MONTH(hdr); ++ fw_suit->build_date = GET_FW_HDR_DATE(hdr); ++ fw_suit->build_hour = GET_FW_HDR_HOUR(hdr); ++ fw_suit->build_min = GET_FW_HDR_MIN(hdr); ++ fw_suit->cmd_ver = GET_FW_HDR_CMD_VERSERION(hdr); ++ ++ rtw89_info(rtwdev, ++ "Firmware version %u.%u.%u.%u, cmd version %u, type %u\n", ++ fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver, ++ fw_suit->sub_idex, fw_suit->cmd_ver, type); ++} ++ ++static ++int __rtw89_fw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type); ++ int ret; ++ ++ ret = rtw89_mfw_recognize(rtwdev, type, fw_suit); ++ if (ret) ++ return ret; ++ ++ rtw89_fw_update_ver(rtwdev, type, fw_suit); ++ ++ return 0; ++} ++ ++int rtw89_fw_recognize(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL); ++ if (ret) ++ return ret; ++ ++ /* It still works if wowlan firmware isn't existing. */ ++ __rtw89_fw_recognize(rtwdev, RTW89_FW_WOWLAN); ++ ++ return 0; ++} ++ ++void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ bool rack, bool dack, u32 len) ++{ ++ struct fwcmd_hdr *hdr; ++ ++ hdr = (struct fwcmd_hdr *)skb_push(skb, 8); ++ ++ if (!(rtwdev->fw.h2c_seq % 4)) ++ rack = true; ++ hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) | ++ FIELD_PREP(H2C_HDR_CAT, cat) | ++ FIELD_PREP(H2C_HDR_CLASS, class) | ++ FIELD_PREP(H2C_HDR_FUNC, func) | ++ FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq)); ++ ++ hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN, ++ len + H2C_HEADER_LEN) | ++ (rack ? H2C_HDR_REC_ACK : 0) | ++ (dack ? H2C_HDR_DONE_ACK : 0)); ++ ++ rtwdev->fw.h2c_seq++; ++} ++ ++static void rtw89_h2c_pkt_set_hdr_fwdl(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ u32 len) ++{ ++ struct fwcmd_hdr *hdr; ++ ++ hdr = (struct fwcmd_hdr *)skb_push(skb, 8); ++ ++ hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) | ++ FIELD_PREP(H2C_HDR_CAT, cat) | ++ FIELD_PREP(H2C_HDR_CLASS, class) | ++ FIELD_PREP(H2C_HDR_FUNC, func) | ++ FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq)); ++ ++ hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN, ++ len + H2C_HEADER_LEN)); ++} ++ ++static int __rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len) ++{ ++ struct sk_buff *skb; ++ u32 ret = 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw hdr dl\n"); ++ return -ENOMEM; ++ } ++ ++ skb_put_data(skb, fw, len); ++ rtw89_h2c_pkt_set_hdr_fwdl(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FWDL, ++ H2C_FUNC_MAC_FWHDR_DL, len); ++ ++ ret = rtw89_h2c_tx(rtwdev, skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ ret = -1; ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return ret; ++} ++ ++static int rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len) ++{ ++ u8 val; ++ int ret; ++ ++ ret = __rtw89_fw_download_hdr(rtwdev, fw, len); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]FW header download\n"); ++ return ret; ++ } ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_FWDL_PATH_RDY, ++ 1, FWDL_WAIT_CNT, false, ++ rtwdev, R_AX_WCPU_FW_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]FWDL path ready\n"); ++ return ret; ++ } ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ return 0; ++} ++ ++static int __rtw89_fw_download_main(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_hdr_section_info *info) ++{ ++ struct sk_buff *skb; ++ const u8 *section = info->addr; ++ u32 residue_len = info->len; ++ u32 pkt_len; ++ int ret; ++ ++ while (residue_len) { ++ if (residue_len >= FWDL_SECTION_PER_PKT_LEN) ++ pkt_len = FWDL_SECTION_PER_PKT_LEN; ++ else ++ pkt_len = residue_len; ++ ++ skb = rtw89_fw_h2c_alloc_skb_no_hdr(pkt_len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, section, pkt_len); ++ ++ ret = rtw89_h2c_tx(rtwdev, skb, true); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ ret = -1; ++ goto fail; ++ } ++ ++ section += pkt_len; ++ residue_len -= pkt_len; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return ret; ++} ++ ++static int rtw89_fw_download_main(struct rtw89_dev *rtwdev, const u8 *fw, ++ struct rtw89_fw_bin_info *info) ++{ ++ struct rtw89_fw_hdr_section_info *section_info = info->section_info; ++ u8 section_num = info->section_num; ++ int ret; ++ ++ while (section_num--) { ++ ret = __rtw89_fw_download_main(rtwdev, section_info); ++ if (ret) ++ return ret; ++ section_info++; ++ } ++ ++ mdelay(5); ++ ++ ret = rtw89_fw_check_rdy(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "download firmware fail\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u16 index; ++ ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, ++ FIELD_PREP(B_AX_DBG_SEL0, FW_PROG_CNTR_DBG_SEL) | ++ FIELD_PREP(B_AX_DBG_SEL1, FW_PROG_CNTR_DBG_SEL)); ++ rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL); ++ ++ for (index = 0; index < 15; index++) { ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_PORT_SEL); ++ rtw89_err(rtwdev, "[ERR]fw PC = 0x%x\n", val32); ++ fsleep(10); ++ } ++} ++ ++static void rtw89_fw_dl_fail_dump(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u16 val16; ++ ++ val32 = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); ++ rtw89_err(rtwdev, "[ERR]fwdl 0x1E0 = 0x%x\n", val32); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_BOOT_DBG + 2); ++ rtw89_err(rtwdev, "[ERR]fwdl 0x83F2 = 0x%x\n", val16); ++ ++ rtw89_fw_prog_cnt_dump(rtwdev); ++} ++ ++int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type); ++ struct rtw89_fw_bin_info info; ++ const u8 *fw = fw_suit->data; ++ u32 len = fw_suit->size; ++ u8 val; ++ int ret; ++ ++ if (!fw || !len) { ++ rtw89_err(rtwdev, "fw type %d isn't recognized\n", type); ++ return -ENOENT; ++ } ++ ++ ret = rtw89_fw_hdr_parser(rtwdev, fw, len, &info); ++ if (ret) { ++ rtw89_err(rtwdev, "parse fw header fail\n"); ++ goto fwdl_err; ++ } ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_H2C_PATH_RDY, ++ 1, FWDL_WAIT_CNT, false, ++ rtwdev, R_AX_WCPU_FW_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]H2C path ready\n"); ++ goto fwdl_err; ++ } ++ ++ ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len); ++ if (ret) { ++ ret = -EBUSY; ++ goto fwdl_err; ++ } ++ ++ ret = rtw89_fw_download_main(rtwdev, fw, &info); ++ if (ret) { ++ ret = -EBUSY; ++ goto fwdl_err; ++ } ++ ++ fw_info->h2c_seq = 0; ++ fw_info->rec_seq = 0; ++ rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX; ++ rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX; ++ ++ return ret; ++ ++fwdl_err: ++ rtw89_fw_dl_fail_dump(rtwdev); ++ return ret; ++} ++ ++int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ ++ wait_for_completion(&fw->completion); ++ if (!fw->firmware) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void rtw89_load_firmware_cb(const struct firmware *firmware, void *context) ++{ ++ struct rtw89_fw_info *fw = context; ++ struct rtw89_dev *rtwdev = fw->rtwdev; ++ ++ if (!firmware || !firmware->data) { ++ rtw89_err(rtwdev, "failed to request firmware\n"); ++ complete_all(&fw->completion); ++ return; ++ } ++ ++ fw->firmware = firmware; ++ complete_all(&fw->completion); ++} ++ ++int rtw89_load_firmware(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ const char *fw_name = rtwdev->chip->fw_name; ++ int ret; ++ ++ fw->rtwdev = rtwdev; ++ init_completion(&fw->completion); ++ ++ ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, ++ GFP_KERNEL, fw, rtw89_load_firmware_cb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to async firmware request\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++void rtw89_unload_firmware(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ ++ rtw89_wait_firmware_completion(rtwdev); ++ ++ if (fw->firmware) ++ release_firmware(fw->firmware); ++} ++ ++#define H2C_CAM_LEN 60 ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CAM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CAM_LEN); ++ rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, skb->data); ++ rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, skb->data); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_ADDR_CAM_UPDATE, ++ H2C_FUNC_MAC_ADDR_CAM_UPD, 0, 1, ++ H2C_CAM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_BA_CAM_LEN 4 ++int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, ++ struct ieee80211_ampdu_params *params) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_BA_CAM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c ba cam\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_BA_CAM_LEN); ++ SET_BA_CAM_MACID(skb->data, macid); ++ if (!valid) ++ goto end; ++ SET_BA_CAM_VALID(skb->data, valid); ++ SET_BA_CAM_TID(skb->data, params->tid); ++ if (params->buf_size > 64) ++ SET_BA_CAM_BMAP_SIZE(skb->data, 4); ++ else ++ SET_BA_CAM_BMAP_SIZE(skb->data, 0); ++ /* If init req is set, hw will set the ssn */ ++ SET_BA_CAM_INIT_REQ(skb->data, 0); ++ SET_BA_CAM_SSN(skb->data, params->ssn); ++ ++end: ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_BA_CAM, ++ H2C_FUNC_MAC_BA_CAM, 0, 1, ++ H2C_BA_CAM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LOG_CFG_LEN 12 ++int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable) ++{ ++ struct sk_buff *skb; ++ u32 comp = enable ? BIT(RTW89_FW_LOG_COMP_INIT) | BIT(RTW89_FW_LOG_COMP_TASK) | ++ BIT(RTW89_FW_LOG_COMP_PS) | BIT(RTW89_FW_LOG_COMP_ERROR) : 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LOG_CFG_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw log cfg\n"); ++ return -ENOMEM; ++ } ++ ++ skb_put(skb, H2C_LOG_CFG_LEN); ++ SET_LOG_CFG_LEVEL(skb->data, RTW89_FW_LOG_LEVEL_SER); ++ SET_LOG_CFG_PATH(skb->data, BIT(RTW89_FW_LOG_LEVEL_C2H)); ++ SET_LOG_CFG_COMP(skb->data, comp); ++ SET_LOG_CFG_COMP_EXT(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_FW_INFO, ++ H2C_FUNC_LOG_CFG, 0, 0, ++ H2C_LOG_CFG_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_GENERAL_PKT_LEN 6 ++#define H2C_GENERAL_PKT_ID_UND 0xff ++int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_GENERAL_PKT_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_GENERAL_PKT_LEN); ++ SET_GENERAL_PKT_MACID(skb->data, macid); ++ SET_GENERAL_PKT_PROBRSP_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_PSPOLL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_NULL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_QOS_NULL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_CTS2SELF_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_FW_INFO, ++ H2C_FUNC_MAC_GENERAL_PKT, 0, 1, ++ H2C_GENERAL_PKT_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LPS_PARM_LEN 8 ++int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, ++ struct rtw89_lps_parm *lps_param) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LPS_PARM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LPS_PARM_LEN); ++ ++ SET_LPS_PARM_MACID(skb->data, lps_param->macid); ++ SET_LPS_PARM_PSMODE(skb->data, lps_param->psmode); ++ SET_LPS_PARM_LASTRPWM(skb->data, lps_param->lastrpwm); ++ SET_LPS_PARM_RLBM(skb->data, 1); ++ SET_LPS_PARM_SMARTPS(skb->data, 1); ++ SET_LPS_PARM_AWAKEINTERVAL(skb->data, 1); ++ SET_LPS_PARM_VOUAPSD(skb->data, 0); ++ SET_LPS_PARM_VIUAPSD(skb->data, 0); ++ SET_LPS_PARM_BEUAPSD(skb->data, 0); ++ SET_LPS_PARM_BKUAPSD(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_PS, ++ H2C_FUNC_MAC_LPS_PARM, 0, 1, ++ H2C_LPS_PARM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_CMC_TBL_LEN 68 ++int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct sk_buff *skb; ++ u8 ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_B; ++ u8 map_b = hal->antenna_tx == RF_AB ? 1 : 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, macid); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ SET_CMC_TBL_TXPWR_MODE(skb->data, 0); ++ SET_CMC_TBL_NTX_PATH_EN(skb->data, ntx_path); ++ SET_CMC_TBL_PATH_MAP_A(skb->data, 0); ++ SET_CMC_TBL_PATH_MAP_B(skb->data, map_b); ++ SET_CMC_TBL_PATH_MAP_C(skb->data, 0); ++ SET_CMC_TBL_PATH_MAP_D(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_A(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_B(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_C(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_D(skb->data, 0); ++ SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0); ++ SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++static void __get_sta_he_pkt_padding(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, u8 *pads) ++{ ++ bool ppe_th; ++ u8 ppe16, ppe8; ++ u8 nss = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; ++ u8 ppe_thres_hdr = sta->he_cap.ppe_thres[0]; ++ u8 ru_bitmap; ++ u8 n, idx, sh; ++ u16 ppe; ++ int i; ++ ++ if (!sta->he_cap.has_he) ++ return; ++ ++ ppe_th = FIELD_GET(IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, ++ sta->he_cap.he_cap_elem.phy_cap_info[6]); ++ if (!ppe_th) { ++ u8 pad; ++ ++ pad = FIELD_GET(IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK, ++ sta->he_cap.he_cap_elem.phy_cap_info[9]); ++ ++ for (i = 0; i < RTW89_PPE_BW_NUM; i++) ++ pads[i] = pad; ++ } ++ ++ ru_bitmap = FIELD_GET(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, ppe_thres_hdr); ++ n = hweight8(ru_bitmap); ++ n = 7 + (n * IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2) * nss; ++ ++ for (i = 0; i < RTW89_PPE_BW_NUM; i++) { ++ if (!(ru_bitmap & BIT(i))) { ++ pads[i] = 1; ++ continue; ++ } ++ ++ idx = n >> 3; ++ sh = n & 7; ++ n += IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2; ++ ++ ppe = le16_to_cpu(*((__le16 *)&sta->he_cap.ppe_thres[idx])); ++ ppe16 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK; ++ sh += IEEE80211_PPE_THRES_INFO_PPET_SIZE; ++ ppe8 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK; ++ ++ if (ppe16 != 7 && ppe8 == 7) ++ pads[i] = 2; ++ else if (ppe8 != 7) ++ pads[i] = 1; ++ else ++ pads[i] = 0; ++ } ++} ++ ++int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct sk_buff *skb; ++ u8 pads[RTW89_PPE_BW_NUM]; ++ ++ memset(pads, 0, sizeof(pads)); ++ __get_sta_he_pkt_padding(rtwdev, sta, pads); ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ SET_CMC_TBL_DISRTSFB(skb->data, 1); ++ SET_CMC_TBL_DISDATAFB(skb->data, 1); ++ SET_CMC_TBL_RTS_TXCNT_LMT_SEL(skb->data, 0); ++ SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 0); ++ if (vif->type == NL80211_IFTYPE_STATION) ++ SET_CMC_TBL_ULDL(skb->data, 1); ++ else ++ SET_CMC_TBL_ULDL(skb->data, 0); ++ SET_CMC_TBL_MULTI_PORT_ID(skb->data, rtwvif->port); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING(skb->data, pads[RTW89_CHANNEL_WIDTH_20]); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING40(skb->data, pads[RTW89_CHANNEL_WIDTH_40]); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING80(skb->data, pads[RTW89_CHANNEL_WIDTH_80]); ++ SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data, sta->he_cap.has_he); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ if (rtwsta->cctl_tx_time) { ++ SET_CMC_TBL_AMPDU_TIME_SEL(skb->data, 1); ++ SET_CMC_TBL_AMPDU_MAX_TIME(skb->data, rtwsta->ampdu_max_time); ++ } ++ if (rtwsta->cctl_tx_retry_limit) { ++ SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 1); ++ SET_CMC_TBL_DATA_TX_CNT_LMT(skb->data, rtwsta->data_tx_cnt_lmt); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_VIF_MAINTAIN_LEN 4 ++int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ enum rtw89_upd_mode upd_mode) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_VIF_MAINTAIN_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_VIF_MAINTAIN_LEN); ++ SET_FWROLE_MAINTAIN_MACID(skb->data, rtwvif->mac_id); ++ SET_FWROLE_MAINTAIN_SELF_ROLE(skb->data, rtwvif->self_role); ++ SET_FWROLE_MAINTAIN_UPD_MODE(skb->data, upd_mode); ++ SET_FWROLE_MAINTAIN_WIFI_ROLE(skb->data, rtwvif->wifi_role); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT, ++ H2C_FUNC_MAC_FWROLE_MAINTAIN, 0, 1, ++ H2C_VIF_MAINTAIN_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_JOIN_INFO_LEN 4 ++int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 dis_conn) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_JOIN_INFO_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_JOIN_INFO_LEN); ++ SET_JOININFO_MACID(skb->data, rtwvif->mac_id); ++ SET_JOININFO_OP(skb->data, dis_conn); ++ SET_JOININFO_BAND(skb->data, rtwvif->mac_idx); ++ SET_JOININFO_WMM(skb->data, rtwvif->wmm); ++ SET_JOININFO_TGR(skb->data, rtwvif->trigger); ++ SET_JOININFO_ISHESTA(skb->data, 0); ++ SET_JOININFO_DLBW(skb->data, 0); ++ SET_JOININFO_TF_MAC_PAD(skb->data, 0); ++ SET_JOININFO_DL_T_PE(skb->data, 0); ++ SET_JOININFO_PORT_ID(skb->data, rtwvif->port); ++ SET_JOININFO_NET_TYPE(skb->data, rtwvif->net_type); ++ SET_JOININFO_WIFI_ROLE(skb->data, rtwvif->wifi_role); ++ SET_JOININFO_SELF_ROLE(skb->data, rtwvif->self_role); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT, ++ H2C_FUNC_MAC_JOININFO, 0, 1, ++ H2C_JOIN_INFO_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, ++ bool pause) ++{ ++ struct rtw89_fw_macid_pause_grp h2c = {{0}}; ++ u8 len = sizeof(struct rtw89_fw_macid_pause_grp); ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_JOIN_INFO_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ h2c.mask_grp[grp] = cpu_to_le32(BIT(sh)); ++ if (pause) ++ h2c.pause_grp[grp] = cpu_to_le32(BIT(sh)); ++ skb_put_data(skb, &h2c, len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_MAC_MACID_PAUSE, 1, 0, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_EDCA_LEN 12 ++int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 ac, u32 val) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_EDCA_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c edca\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_EDCA_LEN); ++ RTW89_SET_EDCA_SEL(skb->data, 0); ++ RTW89_SET_EDCA_BAND(skb->data, rtwvif->mac_idx); ++ RTW89_SET_EDCA_WMM(skb->data, 0); ++ RTW89_SET_EDCA_AC(skb->data, ac); ++ RTW89_SET_EDCA_PARAM(skb->data, val); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_USR_EDCA, 0, 1, ++ H2C_EDCA_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_OFLD_CFG_LEN 8 ++int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev) ++{ ++ static const u8 cfg[] = {0x09, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00}; ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_OFLD_CFG_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c ofld\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, cfg, H2C_OFLD_CFG_LEN); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_OFLD_CFG, 0, 1, ++ H2C_OFLD_CFG_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_RA_LEN 16 ++int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi) ++{ ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_RA_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_RA_LEN); ++ cmd = skb->data; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra cmd msk: %llx ", ra->ra_mask); ++ ++ RTW89_SET_FWCMD_RA_MODE(cmd, ra->mode_ctrl); ++ RTW89_SET_FWCMD_RA_BW_CAP(cmd, ra->bw_cap); ++ RTW89_SET_FWCMD_RA_MACID(cmd, ra->macid); ++ RTW89_SET_FWCMD_RA_DCM(cmd, ra->dcm_cap); ++ RTW89_SET_FWCMD_RA_ER(cmd, ra->er_cap); ++ RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, ra->init_rate_lv); ++ RTW89_SET_FWCMD_RA_UPD_ALL(cmd, ra->upd_all); ++ RTW89_SET_FWCMD_RA_SGI(cmd, ra->en_sgi); ++ RTW89_SET_FWCMD_RA_LDPC(cmd, ra->ldpc_cap); ++ RTW89_SET_FWCMD_RA_STBC(cmd, ra->stbc_cap); ++ RTW89_SET_FWCMD_RA_SS_NUM(cmd, ra->ss_num); ++ RTW89_SET_FWCMD_RA_GILTF(cmd, ra->giltf); ++ RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, ra->upd_bw_nss_mask); ++ RTW89_SET_FWCMD_RA_UPD_MASK(cmd, ra->upd_mask); ++ RTW89_SET_FWCMD_RA_MASK_0(cmd, FIELD_GET(MASKBYTE0, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_1(cmd, FIELD_GET(MASKBYTE1, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_2(cmd, FIELD_GET(MASKBYTE2, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_3(cmd, FIELD_GET(MASKBYTE3, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_4(cmd, FIELD_GET(MASKBYTE4, ra->ra_mask)); ++ ++ if (csi) { ++ RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, 1); ++ RTW89_SET_FWCMD_RA_BAND_NUM(cmd, ra->band_num); ++ RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, ra->cr_tbl_sel); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, ra->fixed_csi_rate_en); ++ RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, ra->ra_csi_rate_en); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, ra->csi_mcs_ss_idx); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, ra->csi_mode); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, ra->csi_gi_ltf); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, ra->csi_bw); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA, ++ H2C_FUNC_OUTSRC_RA_MACIDCFG, 0, 0, ++ H2C_RA_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVHDR 2 ++#define H2C_LEN_CXDRVINFO_INIT (12 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_init_info *init_info = &dm->init_info; ++ struct rtw89_btc_module *module = &init_info->module; ++ struct rtw89_btc_ant_info *ant = &module->ant; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_INIT); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_init\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_INIT); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_INIT); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_INIT - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, ant->type); ++ RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, ant->num); ++ RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, ant->isolation); ++ RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, ant->single_pos); ++ RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, ant->diversity); ++ ++ RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, module->rfe_type); ++ RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, module->cv); ++ RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, module->bt_solo); ++ RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, module->bt_pos); ++ RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, module->switch_type); ++ ++ RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, init_info->wl_guard_ch); ++ RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, init_info->wl_only); ++ RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, init_info->wl_init_ok); ++ RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, init_info->dbcc_en); ++ RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, init_info->cx_other); ++ RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, init_info->bt_only); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_INIT); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_ROLE (4 + 12 * RTW89_MAX_HW_PORT_NUM + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *role_info = &wl->role_info; ++ struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role; ++ struct rtw89_btc_wl_active_role *active = role_info->active_role; ++ struct sk_buff *skb; ++ u8 *cmd; ++ int i; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_ROLE); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_role\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_ROLE); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_ROLE - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt); ++ RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode); ++ ++ RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none); ++ RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station); ++ RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap); ++ RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap); ++ RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc); ++ RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master); ++ RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh); ++ RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go); ++ RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++, active++) { ++ RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_ROLE); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_CTRL (4 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_ctrl *ctrl = &btc->ctrl; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_CTRL); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_CTRL); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_CTRL); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual); ++ RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, ctrl->igno_bt); ++ RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, ctrl->always_freerun); ++ RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, ctrl->trace_step); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_CTRL); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_RFK (4 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_rfk_info *rfk_info = &wl->rfk_info; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_RFK); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_RFK); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_RFK); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state); ++ RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, rfk_info->path_map); ++ RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, rfk_info->phy_map); ++ RTW89_SET_FWCMD_CXRFK_BAND(cmd, rfk_info->band); ++ RTW89_SET_FWCMD_CXRFK_TYPE(cmd, rfk_info->type); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_RFK); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info, ++ u16 len, u8 page) ++{ ++ struct sk_buff *skb; ++ u8 class = info->rf_path == RF_PATH_A ? ++ H2C_CL_OUTSRC_RF_REG_A : H2C_CL_OUTSRC_RF_REG_B; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c rf reg\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, info->rtw89_phy_config_rf_h2c[page], len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, class, page, 0, 0, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, ++ u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, ++ bool rack, bool dack) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for raw with hdr\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, buf, len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, h2c_class, h2c_func, rack, dack, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_no_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c raw\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, buf, len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h) ++{ ++ skb_queue_tail(&rtwdev->c2h_queue, c2h); ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work); ++} ++ ++static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ u8 category = RTW89_GET_C2H_CATEGORY(skb->data); ++ u8 class = RTW89_GET_C2H_CLASS(skb->data); ++ u8 func = RTW89_GET_C2H_FUNC(skb->data); ++ u16 len = RTW89_GET_C2H_LEN(skb->data); ++ bool dump = true; ++ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ return; ++ ++ switch (category) { ++ case RTW89_C2H_CAT_TEST: ++ break; ++ case RTW89_C2H_CAT_MAC: ++ rtw89_mac_c2h_handle(rtwdev, skb, len, class, func); ++ if (class == RTW89_MAC_C2H_CLASS_INFO && ++ func == RTW89_MAC_C2H_FUNC_C2H_LOG) ++ dump = false; ++ break; ++ case RTW89_C2H_CAT_OUTSRC: ++ if (class >= RTW89_PHY_C2H_CLASS_BTC_MIN && ++ class <= RTW89_PHY_C2H_CLASS_BTC_MAX) ++ rtw89_btc_c2h_handle(rtwdev, skb, len, class, func); ++ else ++ rtw89_phy_c2h_handle(rtwdev, skb, len, class, func); ++ break; ++ } ++ ++ if (dump) ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "C2H: ", skb->data, skb->len); ++} ++ ++void rtw89_fw_c2h_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ c2h_work); ++ struct sk_buff *skb, *tmp; ++ ++ skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { ++ skb_unlink(skb, &rtwdev->c2h_queue); ++ mutex_lock(&rtwdev->mutex); ++ rtw89_fw_c2h_cmd_handle(rtwdev, skb); ++ mutex_unlock(&rtwdev->mutex); ++ dev_kfree_skb_any(skb); ++ } ++} ++ ++static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *info) ++{ ++ static const u32 h2c_reg[RTW89_H2CREG_MAX] = { ++ R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, ++ R_AX_H2CREG_DATA2, R_AX_H2CREG_DATA3 ++ }; ++ u8 i, val, len; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, val, val == 0, 1000, 5000, false, ++ rtwdev, R_AX_H2CREG_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "FW does not process h2c registers\n"); ++ return ret; ++ } ++ ++ len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN, ++ sizeof(info->h2creg[0])); ++ ++ RTW89_SET_H2CREG_HDR_FUNC(&info->h2creg[0], info->id); ++ RTW89_SET_H2CREG_HDR_LEN(&info->h2creg[0], len); ++ for (i = 0; i < RTW89_H2CREG_MAX; i++) ++ rtw89_write32(rtwdev, h2c_reg[i], info->h2creg[i]); ++ ++ rtw89_write8(rtwdev, R_AX_H2CREG_CTRL, B_AX_H2CREG_TRIGGER); ++ ++ return 0; ++} ++ ++static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_c2h_info *info) ++{ ++ static const u32 c2h_reg[RTW89_C2HREG_MAX] = { ++ R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, ++ R_AX_C2HREG_DATA2, R_AX_C2HREG_DATA3 ++ }; ++ u32 ret; ++ u8 i, val; ++ ++ info->id = RTW89_FWCMD_C2HREG_FUNC_NULL; ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val, 1, ++ RTW89_C2H_TIMEOUT, false, rtwdev, ++ R_AX_C2HREG_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "c2h reg timeout\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < RTW89_C2HREG_MAX; i++) ++ info->c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]); ++ ++ rtw89_write8(rtwdev, R_AX_C2HREG_CTRL, 0); ++ ++ info->id = RTW89_GET_C2H_HDR_FUNC(*info->c2hreg); ++ info->content_len = (RTW89_GET_C2H_HDR_LEN(*info->c2hreg) << 2) - ++ RTW89_C2HREG_HDR_LEN; ++ ++ return 0; ++} ++ ++int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *h2c_info, ++ struct rtw89_mac_c2h_info *c2h_info) ++{ ++ u32 ret; ++ ++ if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE) ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (!h2c_info && !c2h_info) ++ return -EINVAL; ++ ++ if (!h2c_info) ++ goto recv_c2h; ++ ++ ret = rtw89_fw_write_h2c_reg(rtwdev, h2c_info); ++ if (ret) ++ return ret; ++ ++recv_c2h: ++ if (!c2h_info) ++ return 0; ++ ++ ret = rtw89_fw_read_c2h_reg(rtwdev, c2h_info); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev) ++{ ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { ++ rtw89_err(rtwdev, "[ERR]pwr is off\n"); ++ return; ++ } ++ ++ rtw89_info(rtwdev, "FW status = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM0)); ++ rtw89_info(rtwdev, "FW BADADDR = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM1)); ++ rtw89_info(rtwdev, "FW EPC/RA = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM2)); ++ rtw89_info(rtwdev, "FW MISC = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM3)); ++ rtw89_info(rtwdev, "R_AX_HALT_C2H = 0x%x\n", ++ rtw89_read32(rtwdev, R_AX_HALT_C2H)); ++ rtw89_info(rtwdev, "R_AX_SER_DBG_INFO = 0x%x\n", ++ rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); ++ ++ rtw89_fw_prog_cnt_dump(rtwdev); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +new file mode 100644 +index 000000000000..e00bb5e5d7d4 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -0,0 +1,1394 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_FW_H__ ++#define __RTW89_FW_H__ ++ ++#include "core.h" ++ ++enum rtw89_fw_dl_status { ++ RTW89_FWDL_INITIAL_STATE = 0, ++ RTW89_FWDL_FWDL_ONGOING = 1, ++ RTW89_FWDL_CHECKSUM_FAIL = 2, ++ RTW89_FWDL_SECURITY_FAIL = 3, ++ RTW89_FWDL_CV_NOT_MATCH = 4, ++ RTW89_FWDL_RSVD0 = 5, ++ RTW89_FWDL_WCPU_FWDL_RDY = 6, ++ RTW89_FWDL_WCPU_FW_INIT_RDY = 7 ++}; ++ ++#define RTW89_GET_C2H_HDR_FUNC(info) \ ++ u32_get_bits(info, GENMASK(6, 0)) ++#define RTW89_GET_C2H_HDR_LEN(info) \ ++ u32_get_bits(info, GENMASK(11, 8)) ++ ++#define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ ++ u32p_replace_bits(info, val, GENMASK(6, 0)) ++#define RTW89_SET_H2CREG_HDR_LEN(info, val) \ ++ u32p_replace_bits(info, val, GENMASK(11, 8)) ++ ++#define RTW89_H2CREG_MAX 4 ++#define RTW89_C2HREG_MAX 4 ++#define RTW89_C2HREG_HDR_LEN 2 ++#define RTW89_H2CREG_HDR_LEN 2 ++#define RTW89_C2H_TIMEOUT 1000000 ++struct rtw89_mac_c2h_info { ++ u8 id; ++ u8 content_len; ++ u32 c2hreg[RTW89_C2HREG_MAX]; ++}; ++ ++struct rtw89_mac_h2c_info { ++ u8 id; ++ u8 content_len; ++ u32 h2creg[RTW89_H2CREG_MAX]; ++}; ++ ++enum rtw89_mac_h2c_type { ++ RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, ++ RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, ++ RTW89_FWCMD_H2CREG_FUNC_FWERR, ++ RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, ++ RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, ++ RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN ++}; ++ ++enum rtw89_mac_c2h_type { ++ RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, ++ RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, ++ RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, ++ RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, ++ RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, ++ RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF ++}; ++ ++struct rtw89_c2h_phy_cap { ++ u32 func:7; ++ u32 ack:1; ++ u32 len:4; ++ u32 seq:4; ++ u32 rx_nss:8; ++ u32 bw:8; ++ ++ u32 tx_nss:8; ++ u32 prot:8; ++ u32 nic:8; ++ u32 wl_func:8; ++ ++ u32 hw_type:8; ++} __packed; ++ ++enum rtw89_fw_c2h_category { ++ RTW89_C2H_CAT_TEST, ++ RTW89_C2H_CAT_MAC, ++ RTW89_C2H_CAT_OUTSRC, ++}; ++ ++enum rtw89_fw_log_level { ++ RTW89_FW_LOG_LEVEL_OFF, ++ RTW89_FW_LOG_LEVEL_CRT, ++ RTW89_FW_LOG_LEVEL_SER, ++ RTW89_FW_LOG_LEVEL_WARN, ++ RTW89_FW_LOG_LEVEL_LOUD, ++ RTW89_FW_LOG_LEVEL_TR, ++}; ++ ++enum rtw89_fw_log_path { ++ RTW89_FW_LOG_LEVEL_UART, ++ RTW89_FW_LOG_LEVEL_C2H, ++ RTW89_FW_LOG_LEVEL_SNI, ++}; ++ ++enum rtw89_fw_log_comp { ++ RTW89_FW_LOG_COMP_VER, ++ RTW89_FW_LOG_COMP_INIT, ++ RTW89_FW_LOG_COMP_TASK, ++ RTW89_FW_LOG_COMP_CNS, ++ RTW89_FW_LOG_COMP_H2C, ++ RTW89_FW_LOG_COMP_C2H, ++ RTW89_FW_LOG_COMP_TX, ++ RTW89_FW_LOG_COMP_RX, ++ RTW89_FW_LOG_COMP_IPSEC, ++ RTW89_FW_LOG_COMP_TIMER, ++ RTW89_FW_LOG_COMP_DBGPKT, ++ RTW89_FW_LOG_COMP_PS, ++ RTW89_FW_LOG_COMP_ERROR, ++ RTW89_FW_LOG_COMP_WOWLAN, ++ RTW89_FW_LOG_COMP_SECURE_BOOT, ++ RTW89_FW_LOG_COMP_BTC, ++ RTW89_FW_LOG_COMP_BB, ++ RTW89_FW_LOG_COMP_TWT, ++ RTW89_FW_LOG_COMP_RF, ++ RTW89_FW_LOG_COMP_MCC = 20, ++}; ++ ++#define FWDL_SECTION_MAX_NUM 10 ++#define FWDL_SECTION_CHKSUM_LEN 8 ++#define FWDL_SECTION_PER_PKT_LEN 2020 ++ ++struct rtw89_fw_hdr_section_info { ++ u8 redl; ++ const u8 *addr; ++ u32 len; ++ u32 dladdr; ++}; ++ ++struct rtw89_fw_bin_info { ++ u8 section_num; ++ u32 hdr_len; ++ struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; ++}; ++ ++struct rtw89_fw_macid_pause_grp { ++ __le32 pause_grp[4]; ++ __le32 mask_grp[4]; ++} __packed; ++ ++struct rtw89_h2creg_sch_tx_en { ++ u8 func:7; ++ u8 ack:1; ++ u8 total_len:4; ++ u8 seq_num:4; ++ u16 tx_en:16; ++ u16 mask:16; ++ u8 band:1; ++ u16 rsvd:15; ++} __packed; ++ ++#define RTW89_SET_FWCMD_RA_IS_DIS(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(0)) ++#define RTW89_SET_FWCMD_RA_MODE(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(5, 1)) ++#define RTW89_SET_FWCMD_RA_BW_CAP(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_RA_MACID(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_RA_DCM(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(16)) ++#define RTW89_SET_FWCMD_RA_ER(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(17)) ++#define RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(19, 18)) ++#define RTW89_SET_FWCMD_RA_UPD_ALL(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(20)) ++#define RTW89_SET_FWCMD_RA_SGI(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(21)) ++#define RTW89_SET_FWCMD_RA_LDPC(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(22)) ++#define RTW89_SET_FWCMD_RA_STBC(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(23)) ++#define RTW89_SET_FWCMD_RA_SS_NUM(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(26, 24)) ++#define RTW89_SET_FWCMD_RA_GILTF(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(29, 27)) ++#define RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(30)) ++#define RTW89_SET_FWCMD_RA_UPD_MASK(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(31)) ++#define RTW89_SET_FWCMD_RA_MASK_0(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_MASK_1(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_RA_MASK_2(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_RA_MASK_3(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(31, 24)) ++#define RTW89_SET_FWCMD_RA_MASK_4(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x02, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x02, BIT(31)) ++#define RTW89_SET_FWCMD_RA_BAND_NUM(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, BIT(8)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, BIT(9)) ++#define RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, BIT(10)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(25, 24)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(28, 26)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(31, 29)) ++ ++#define RTW89_SET_FWCMD_SEC_IDX(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_SEC_OFFSET(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_SEC_LEN(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_SEC_TYPE(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(3, 0)) ++#define RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, BIT(4)) ++#define RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, BIT(5)) ++#define RTW89_SET_FWCMD_SEC_KEY0(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x02, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY1(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x03, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY2(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x04, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY3(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x05, GENMASK(31, 0)) ++ ++#define RTW89_SET_EDCA_SEL(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(1, 0)) ++#define RTW89_SET_EDCA_BAND(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(3)) ++#define RTW89_SET_EDCA_WMM(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, BIT(4)) ++#define RTW89_SET_EDCA_AC(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x00, GENMASK(6, 5)) ++#define RTW89_SET_EDCA_PARAM(cmd, val) \ ++ RTW89_SET_FWCMD(cmd, val, 0x01, GENMASK(31, 0)) ++#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) ++#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) ++#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) ++#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) ++ ++#define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 0)) ++#define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(28)) ++#define GET_FWSECTION_HDR_REDL(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(29)) ++#define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr)), GENMASK(31, 0)) ++ ++#define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(7, 0)) ++#define GET_FW_HDR_MINOR_VERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(15, 8)) ++#define GET_FW_HDR_SUBVERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 16)) ++#define GET_FW_HDR_SUBINDEX(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(31, 24)) ++#define GET_FW_HDR_MONTH(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(7, 0)) ++#define GET_FW_HDR_DATE(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(15, 8)) ++#define GET_FW_HDR_HOUR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(23, 16)) ++#define GET_FW_HDR_MIN(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(31, 24)) ++#define GET_FW_HDR_YEAR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 5), GENMASK(31, 0)) ++#define GET_FW_HDR_SEC_NUM(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) ++#define GET_FW_HDR_CMD_VERSERION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) ++#define SET_FW_HDR_PART_SIZE(fwhdr, val) \ ++ le32p_replace_bits((__le32 *)(fwhdr) + 7, val, GENMASK(15, 0)) ++ ++#define SET_CTRL_INFO_MACID(table, val) \ ++ le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) ++#define SET_CTRL_INFO_OPERATION(table, val) \ ++ le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)) ++#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) ++#define SET_CMC_TBL_DATARATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) ++#define SET_CMC_TBL_FORCE_TXOP(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) ++#define SET_CMC_TBL_DATA_BW(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) ++#define SET_CMC_TBL_DATA_GI_LTF(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, \ ++ GENMASK(14, 12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) ++#define SET_CMC_TBL_DARF_TC_INDEX(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) ++#define SET_CMC_TBL_ARFR_CTRL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, \ ++ GENMASK(19, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_ACQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, \ ++ BIT(20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_MGQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, \ ++ BIT(21)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_ULQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, \ ++ BIT(22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_TWTQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, \ ++ BIT(23)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DISRTSFB BIT(0) ++#define SET_CMC_TBL_DISRTSFB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, \ ++ BIT(25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DISDATAFB BIT(0) ++#define SET_CMC_TBL_DISDATAFB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, \ ++ BIT(26)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TRYRATE BIT(0) ++#define SET_CMC_TBL_TRYRATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) ++#define SET_CMC_TBL_AMPDU_DENSITY(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_DATA_RTY_LOWEST_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) ++#define SET_CMC_TBL_AMPDU_TIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) ++#define SET_CMC_TBL_AMPDU_LEN_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, \ ++ BIT(10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) ++#define SET_CMC_TBL_RTS_TXCNT_LMT_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, \ ++ BIT(11)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) ++#define SET_CMC_TBL_RTS_TXCNT_LMT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, \ ++ GENMASK(15, 12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) ++#define SET_CMC_TBL_RTSRATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, \ ++ GENMASK(24, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VCS_STBC BIT(0) ++#define SET_CMC_TBL_VCS_STBC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) ++#define SET_CMC_TBL_RTS_RTY_LOWEST_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) ++#define SET_CMC_TBL_DATA_TX_CNT_LMT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, \ ++ GENMASK(5, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) ++#define SET_CMC_TBL_DATA_TXCNT_LMT_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, \ ++ BIT(6)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) ++#define SET_CMC_TBL_MAX_AGG_NUM_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, \ ++ BIT(7)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_EN BIT(0) ++#define SET_CMC_TBL_RTS_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, \ ++ BIT(8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) ++#define SET_CMC_TBL_CTS2SELF_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) ++#define SET_CMC_TBL_CCA_RTS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) ++#define SET_CMC_TBL_HW_RTS_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) ++#define SET_CMC_TBL_RTS_DROP_DATA_MODE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, \ ++ GENMASK(14, 13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) ++#define SET_CMC_TBL_AMPDU_MAX_LEN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, \ ++ GENMASK(26, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) ++#define SET_CMC_TBL_UL_MU_DIS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) ++#define SET_CMC_TBL_AMPDU_MAX_TIME(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) ++#define SET_CMC_TBL_MAX_AGG_NUM(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, \ ++ GENMASK(7, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) ++#define SET_CMC_TBL_BA_BMAP(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, \ ++ GENMASK(9, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_VO_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, \ ++ GENMASK(18, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_VI_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, \ ++ GENMASK(21, 19)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_BE_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, \ ++ GENMASK(24, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_BK_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, \ ++ GENMASK(27, 25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) ++#define SET_CMC_TBL_SECTYPE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) ++#define SET_CMC_TBL_MULTI_PORT_ID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, \ ++ GENMASK(2, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BMC BIT(0) ++#define SET_CMC_TBL_BMC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, \ ++ BIT(3)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) ++#define SET_CMC_TBL_MBSSID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, \ ++ GENMASK(7, 4)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) ++#define SET_CMC_TBL_NAVUSEHDR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, \ ++ BIT(8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) ++#define SET_CMC_TBL_TXPWR_MODE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, \ ++ GENMASK(11, 9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_DCM BIT(0) ++#define SET_CMC_TBL_DATA_DCM(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_ER BIT(0) ++#define SET_CMC_TBL_DATA_ER(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) ++#define SET_CMC_TBL_DATA_LDPC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, \ ++ BIT(14)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_STBC BIT(0) ++#define SET_CMC_TBL_DATA_STBC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) ++#define SET_CMC_TBL_A_CTRL_BQR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, \ ++ BIT(16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) ++#define SET_CMC_TBL_A_CTRL_UPH(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, \ ++ BIT(17)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) ++#define SET_CMC_TBL_A_CTRL_BSR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, \ ++ BIT(18)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) ++#define SET_CMC_TBL_A_CTRL_CAS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, \ ++ BIT(19)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) ++#define SET_CMC_TBL_DATA_BW_ER(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, \ ++ BIT(20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) ++#define SET_CMC_TBL_LSIG_TXOP_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, \ ++ BIT(21)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) ++#define SET_CMC_TBL_CTRL_CNT_VLD(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) ++#define SET_CMC_TBL_CTRL_CNT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_RESP_REF_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) ++#define SET_CMC_TBL_ALL_ACK_SUPPORT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) ++#define SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) ++#define SET_CMC_TBL_NTX_PATH_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, \ ++ GENMASK(19, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_A(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, \ ++ GENMASK(21, 20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_B(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, \ ++ GENMASK(23, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_C(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, \ ++ GENMASK(25, 24)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_D(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, \ ++ GENMASK(27, 26)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) ++#define SET_CMC_TBL_ANTSEL_A(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, \ ++ BIT(28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) ++#define SET_CMC_TBL_ANTSEL_B(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, \ ++ BIT(29)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) ++#define SET_CMC_TBL_ANTSEL_C(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, \ ++ BIT(30)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) ++#define SET_CMC_TBL_ANTSEL_D(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, \ ++ BIT(31)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) ++#define SET_CMC_TBL_ADDR_CAM_INDEX(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, \ ++ GENMASK(7, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) ++#define SET_CMC_TBL_PAID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, \ ++ GENMASK(16, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ULDL BIT(0) ++#define SET_CMC_TBL_ULDL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, \ ++ BIT(17)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) ++#define SET_CMC_TBL_DOPPLER_CTRL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, \ ++ GENMASK(19, 18)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(21, 20)); \ ++} while (0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING40(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(23, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) ++#define SET_CMC_TBL_TXPWR_TOLERENCE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, \ ++ GENMASK(27, 24)); \ ++} while (0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING80(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(31, 30)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NC GENMASK(2, 0) ++#define SET_CMC_TBL_NC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, \ ++ GENMASK(2, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NR GENMASK(2, 0) ++#define SET_CMC_TBL_NR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, \ ++ GENMASK(5, 3)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NG GENMASK(1, 0) ++#define SET_CMC_TBL_NG(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, \ ++ GENMASK(7, 6)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CB GENMASK(1, 0) ++#define SET_CMC_TBL_CB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, \ ++ GENMASK(9, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CS GENMASK(1, 0) ++#define SET_CMC_TBL_CS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) ++#define SET_CMC_TBL_CSI_TXBF_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) ++#define SET_CMC_TBL_CSI_STBC_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) ++#define SET_CMC_TBL_CSI_LDPC_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, \ ++ BIT(14)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) ++#define SET_CMC_TBL_CSI_PARA_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_CSI_FIX_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, \ ++ GENMASK(24, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) ++#define SET_CMC_TBL_CSI_GI_LTF(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, \ ++ GENMASK(27, 25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) ++#define SET_CMC_TBL_CSI_GID_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, \ ++ BIT(29)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) ++#define SET_CMC_TBL_CSI_BW(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, \ ++ GENMASK(31, 30)); \ ++} while (0) ++ ++#define SET_FWROLE_MAINTAIN_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_FWROLE_MAINTAIN_SELF_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)) ++#define SET_FWROLE_MAINTAIN_UPD_MODE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)) ++#define SET_FWROLE_MAINTAIN_WIFI_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)) ++ ++#define SET_JOININFO_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_JOININFO_OP(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(8)) ++#define SET_JOININFO_BAND(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(9)) ++#define SET_JOININFO_WMM(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)) ++#define SET_JOININFO_TGR(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(12)) ++#define SET_JOININFO_ISHESTA(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(13)) ++#define SET_JOININFO_DLBW(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)) ++#define SET_JOININFO_TF_MAC_PAD(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)) ++#define SET_JOININFO_DL_T_PE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)) ++#define SET_JOININFO_PORT_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)) ++#define SET_JOININFO_NET_TYPE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)) ++#define SET_JOININFO_WIFI_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)) ++#define SET_JOININFO_SELF_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)) ++ ++#define SET_GENERAL_PKT_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_GENERAL_PKT_PROBRSP_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_GENERAL_PKT_PSPOLL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)) ++#define SET_GENERAL_PKT_NULL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) ++#define SET_GENERAL_PKT_QOS_NULL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)) ++#define SET_GENERAL_PKT_CTS2SELF_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) ++ ++#define SET_LOG_CFG_LEVEL(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_LOG_CFG_PATH(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_LOG_CFG_COMP(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)) ++#define SET_LOG_CFG_COMP_EXT(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)) ++ ++#define SET_BA_CAM_VALID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(0)) ++#define SET_BA_CAM_INIT_REQ(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(1)) ++#define SET_BA_CAM_ENTRY_IDX(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)) ++#define SET_BA_CAM_TID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)) ++#define SET_BA_CAM_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_BA_CAM_BMAP_SIZE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) ++#define SET_BA_CAM_SSN(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)) ++ ++#define SET_LPS_PARM_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_LPS_PARM_PSMODE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_LPS_PARM_RLBM(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) ++#define SET_LPS_PARM_SMARTPS(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)) ++#define SET_LPS_PARM_AWAKEINTERVAL(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) ++#define SET_LPS_PARM_VOUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)) ++#define SET_LPS_PARM_VIUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)) ++#define SET_LPS_PARM_BEUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)) ++#define SET_LPS_PARM_BKUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)) ++#define SET_LPS_PARM_LASTRPWM(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) ++ ++enum rtw89_btc_btf_h2c_class { ++ BTFC_SET = 0x10, ++ BTFC_GET = 0x11, ++ BTFC_FW_EVENT = 0x12, ++}; ++ ++enum rtw89_btc_btf_set { ++ SET_REPORT_EN = 0x0, ++ SET_SLOT_TABLE, ++ SET_MREG_TABLE, ++ SET_CX_POLICY, ++ SET_GPIO_DBG, ++ SET_DRV_INFO, ++ SET_DRV_EVENT, ++ SET_BT_WREG_ADDR, ++ SET_BT_WREG_VAL, ++ SET_BT_RREG_ADDR, ++ SET_BT_WL_CH_INFO, ++ SET_BT_INFO_REPORT, ++ SET_BT_IGNORE_WLAN_ACT, ++ SET_BT_TX_PWR, ++ SET_BT_LNA_CONSTRAIN, ++ SET_BT_GOLDEN_RX_RANGE, ++ SET_BT_PSD_REPORT, ++ SET_H2C_TEST, ++ SET_MAX1, ++}; ++ ++enum rtw89_btc_cxdrvinfo { ++ CXDRVINFO_INIT = 0, ++ CXDRVINFO_ROLE, ++ CXDRVINFO_DBCC, ++ CXDRVINFO_SMAP, ++ CXDRVINFO_RFK, ++ CXDRVINFO_RUN, ++ CXDRVINFO_CTRL, ++ CXDRVINFO_SCAN, ++ CXDRVINFO_MAX, ++}; ++ ++#define RTW89_SET_FWCMD_CXHDR_TYPE(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 0, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXHDR_LEN(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 1, GENMASK(7, 0)) ++ ++#define RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 2, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 3, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 4, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 5, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 5, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 7, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 8, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 8, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 8, BIT(2)) ++#define RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 10, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 11, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 11, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 11, BIT(2)) ++#define RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 11, BIT(3)) ++#define RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 11, BIT(4)) ++ ++#define RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 2, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, val) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 3, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(1)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(2)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(3)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(4)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(5)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(6)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(7)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(8)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(9)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(10)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, val) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 4, BIT(11)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6 + 12 * (n), BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6 + 12 * (n), GENMASK(3, 1)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6 + 12 * (n), BIT(4)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6 + 12 * (n), BIT(5)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 6 + 12 * (n), GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 7 + 12 * (n), BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 7 + 12 * (n), GENMASK(7, 1)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 8 + 12 * (n), GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA8(cmd, val, 9 + 12 * (n), GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 10 + 12 * (n), GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 12 + 12 * (n), GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 14 + 12 * (n), GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, val, n) \ ++ RTW89_SET_FWCMD_UA16(cmd, val, 16 + 12 * (n), GENMASK(15, 0)) ++ ++#define RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, BIT(0)) ++#define RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, BIT(1)) ++#define RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, BIT(2)) ++#define RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(18, 3)) ++ ++#define RTW89_SET_FWCMD_CXRFK_STATE(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(1, 0)) ++#define RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(5, 2)) ++#define RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_CXRFK_BAND(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(9, 8)) ++#define RTW89_SET_FWCMD_CXRFK_TYPE(cmd, val) \ ++ RTW89_SET_FWCMD_UA32(cmd, val, 2, GENMASK(17, 10)) ++ ++#define RTW89_C2H_HEADER_LEN 8 ++ ++#define RTW89_GET_C2H_CATEGORY(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(1, 0)) ++#define RTW89_GET_C2H_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(7, 2)) ++#define RTW89_GET_C2H_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(15, 8)) ++#define RTW89_GET_C2H_LEN(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 1), GENMASK(13, 0)) ++ ++#define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) ++#define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) ++ ++#define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(31, 24)) ++ ++#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++ ++#define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 0)) ++#define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++#define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(6, 0)) ++#define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(9, 8)) ++#define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(12, 10)) ++#define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(14, 13)) ++ ++#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) ++#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) ++#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ ++ FIELD_PREP(GENMASK(2, 0), mcs)) ++ ++#define RTW89_FW_HDR_SIZE 32 ++#define RTW89_FW_SECTION_HDR_SIZE 16 ++ ++#define RTW89_MFW_SIG 0xFF ++ ++struct rtw89_mfw_info { ++ u8 cv; ++ u8 type; /* enum rtw89_fw_type */ ++ u8 mp; ++ u8 rsvd; ++ __le32 shift; ++ __le32 size; ++ u8 rsvd2[4]; ++} __packed; ++ ++struct rtw89_mfw_hdr { ++ u8 sig; /* RTW89_MFW_SIG */ ++ u8 fw_nr; ++ u8 rsvd[14]; ++ struct rtw89_mfw_info info[]; ++} __packed; ++ ++struct fwcmd_hdr { ++ __le32 hdr0; ++ __le32 hdr1; ++}; ++ ++#define RTW89_H2C_RF_PAGE_SIZE 500 ++#define RTW89_H2C_RF_PAGE_NUM 3 ++struct rtw89_fw_h2c_rf_reg_info { ++ enum rtw89_rf_path rf_path; ++ __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; ++ u16 curr_idx; ++}; ++ ++#define H2C_SEC_CAM_LEN 24 ++ ++#define H2C_HEADER_LEN 8 ++#define H2C_HDR_CAT GENMASK(1, 0) ++#define H2C_HDR_CLASS GENMASK(7, 2) ++#define H2C_HDR_FUNC GENMASK(15, 8) ++#define H2C_HDR_DEL_TYPE GENMASK(19, 16) ++#define H2C_HDR_H2C_SEQ GENMASK(31, 24) ++#define H2C_HDR_TOTAL_LEN GENMASK(13, 0) ++#define H2C_HDR_REC_ACK BIT(14) ++#define H2C_HDR_DONE_ACK BIT(15) ++ ++#define FWCMD_TYPE_H2C 0 ++ ++#define H2C_CAT_MAC 0x1 ++ ++/* CLASS 0 - FW INFO */ ++#define H2C_CL_FW_INFO 0x0 ++#define H2C_FUNC_LOG_CFG 0x0 ++#define H2C_FUNC_MAC_GENERAL_PKT 0x1 ++ ++/* CLASS 2 - PS */ ++#define H2C_CL_MAC_PS 0x2 ++#define H2C_FUNC_MAC_LPS_PARM 0x0 ++ ++/* CLASS 3 - FW download */ ++#define H2C_CL_MAC_FWDL 0x3 ++#define H2C_FUNC_MAC_FWHDR_DL 0x0 ++ ++/* CLASS 5 - Frame Exchange */ ++#define H2C_CL_MAC_FR_EXCHG 0x5 ++#define H2C_FUNC_MAC_CCTLINFO_UD 0x2 ++ ++/* CLASS 6 - Address CAM */ ++#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 ++#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 ++ ++/* CLASS 8 - Media Status Report */ ++#define H2C_CL_MAC_MEDIA_RPT 0x8 ++#define H2C_FUNC_MAC_JOININFO 0x0 ++#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 ++ ++/* CLASS 9 - FW offload */ ++#define H2C_CL_MAC_FW_OFLD 0x9 ++#define H2C_FUNC_MAC_MACID_PAUSE 0x8 ++#define H2C_FUNC_USR_EDCA 0xF ++#define H2C_FUNC_OFLD_CFG 0x14 ++ ++/* CLASS 10 - Security CAM */ ++#define H2C_CL_MAC_SEC_CAM 0xa ++#define H2C_FUNC_MAC_SEC_UPD 0x1 ++ ++/* CLASS 12 - BA CAM */ ++#define H2C_CL_BA_CAM 0xc ++#define H2C_FUNC_MAC_BA_CAM 0x0 ++ ++#define H2C_CAT_OUTSRC 0x2 ++ ++#define H2C_CL_OUTSRC_RA 0x1 ++#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 ++ ++#define H2C_CL_OUTSRC_RF_REG_A 0x8 ++#define H2C_CL_OUTSRC_RF_REG_B 0x9 ++ ++int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); ++int rtw89_fw_recognize(struct rtw89_dev *rtwdev); ++int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); ++int rtw89_load_firmware(struct rtw89_dev *rtwdev); ++void rtw89_unload_firmware(struct rtw89_dev *rtwdev); ++int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); ++void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ bool rack, bool dack, u32 len); ++int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid); ++int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta); ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); ++void rtw89_fw_c2h_work(struct work_struct *work); ++int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ enum rtw89_upd_mode upd_mode); ++int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 dis_conn); ++int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, ++ bool pause); ++int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 ac, u32 val); ++int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); ++int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info, ++ u16 len, u8 page); ++int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, ++ u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, ++ bool rack, bool dack); ++int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); ++int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); ++int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, ++ struct ieee80211_ampdu_params *params); ++int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, ++ struct rtw89_lps_parm *lps_param); ++struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len); ++struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len); ++int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *h2c_info, ++ struct rtw89_mac_c2h_info *c2h_info); ++int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); ++void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); ++ ++static __always_inline void RTW89_SET_FWCMD(u8 *cmd, u32 val, u8 offset, u32 mask) ++{ ++ u32 *cmd32 = (u32 *)cmd; ++ ++ le32p_replace_bits((__le32 *)(cmd32 + offset), val, mask); ++} ++ ++static __always_inline void RTW89_SET_FWCMD_UA8(u8 *cmd, u8 val, u8 offset, u32 mask) ++{ ++ u8p_replace_bits(cmd + offset, val, mask); ++} ++ ++static __always_inline void RTW89_SET_FWCMD_UA16(u8 *cmd, u16 val, u8 offset, u32 mask) ++{ ++ le16p_replace_bits((__le16 *)(cmd + offset), val, mask); ++} ++ ++static __always_inline void RTW89_SET_FWCMD_UA32(u8 *cmd, u32 val, u8 offset, u32 mask) ++{ ++ le32p_replace_bits((__le32 *)(cmd + offset), val, mask); ++} ++ ++#endif + +From patchwork Fri Aug 20 04:35:21 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448375 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 0FA55C432BE + for ; + Fri, 20 Aug 2021 04:37:02 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id D99FE60F91 + for ; + Fri, 20 Aug 2021 04:37:01 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233203AbhHTEhi (ORCPT + ); + Fri, 20 Aug 2021 00:37:38 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39241 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232776AbhHTEhh (ORCPT + ); + Fri, 20 Aug 2021 00:37:37 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4atooF003975, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4atooF003975 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:55 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:54 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:53 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 07/24] rtw89: add MAC files +Date: Fri, 20 Aug 2021 12:35:21 +0800 +Message-ID: <20210820043538.12424-8-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Provide interfaces to access MAC function blocks including power-on/off +configuration. + +MAC initialization does power-on, and then enable HCI to download firmware. +The BB, RF, DMAC and CMAC function blocks are enabled, and then configure +TXRX settings that contains DMAC, CMAC, interrupt mask, and RPQ parameters. +DMAC is short for data MAC, including data link engine (DLE), HCI function +control (HFC), MPDU processor, security engine and so on. CMAC is short for +control MAC, including scheduler, address CAM, RX filter, CCA control, +TMAC, RMAC, protocol component and so on. + +The full MAC initialization is done for normal use case when user does +network interface up. When device is probing, driver does partial +initialization to do power-on and download firmware, because we need to +read hardware capabilities from efuse and firmware. + +MAC supports five ports, so we can have five VIFs at most. To control MAC +port, we control a set of registers, and the most important one among them +is port_cfg register named R_AX_PORT_CFG_P0. We can turn on/off the port +function and configure network type (STA or AP mode) by this register. +The address and BSSID corresponding to this port are given by address +and BSSID CAM that is set by firmware via H2C command. + +Since BT coexistence code needs to access coex registers, some help +functions are provided to make WiFi-only case work. + +To access MAC registers, normally we use rtw89_writeXX/rtw89_readYY, but +we use rtw89_mac_txpwr_write32_ZZ to access TX power register with proper +address range checking. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/mac.c | 3833 ++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/mac.h | 860 +++++ + 2 files changed, 4693 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/mac.c + create mode 100644 drivers/net/wireless/realtek/rtw89/mac.h + +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +new file mode 100644 +index 000000000000..c38d2f9cc0d1 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -0,0 +1,3833 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "util.h" ++ ++int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, ++ enum rtw89_mac_hwmod_sel sel) ++{ ++ u32 val, r_val; ++ ++ if (sel == RTW89_DMAC_SEL) { ++ r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); ++ val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); ++ } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { ++ r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); ++ val = B_AX_CMAC_EN; ++ } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { ++ r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); ++ val = B_AX_CMAC1_FEN; ++ } else { ++ return -EINVAL; ++ } ++ if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || ++ (val & r_val) != val) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) ++{ ++ u8 lte_ctrl; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, ++ 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); ++ if (ret) ++ rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); ++ ++ rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); ++ rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); ++ ++ return ret; ++} ++ ++int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) ++{ ++ u8 lte_ctrl; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, ++ 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); ++ if (ret) ++ rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); ++ ++ rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); ++ *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); ++ ++ return ret; ++} ++ ++static ++int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) ++{ ++ u32 ctrl_reg, data_reg, ctrl_data; ++ u32 val; ++ int ret; ++ ++ switch (ctrl->type) { ++ case DLE_CTRL_TYPE_WDE: ++ ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; ++ data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; ++ ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | ++ FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | ++ B_AX_WDE_DFI_ACTIVE; ++ break; ++ case DLE_CTRL_TYPE_PLE: ++ ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; ++ data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; ++ ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | ++ FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | ++ B_AX_PLE_DFI_ACTIVE; ++ break; ++ default: ++ rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); ++ return -EINVAL; ++ } ++ ++ rtw89_write32(rtwdev, ctrl_reg, ctrl_data); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), ++ 1, 1000, false, rtwdev, ctrl_reg); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", ++ ctrl_reg, ctrl_data); ++ return ret; ++ } ++ ++ ctrl->out_data = rtw89_read32(rtwdev, data_reg); ++ return 0; ++} ++ ++static int dle_dfi_quota(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_dle_dfi_quota *quota) ++{ ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ int ret; ++ ++ ctrl.type = quota->dle_type; ++ ctrl.target = DLE_DFI_TYPE_QUOTA; ++ ctrl.addr = quota->qtaid; ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); ++ return ret; ++ } ++ ++ quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); ++ quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); ++ return 0; ++} ++ ++static int dle_dfi_qempty(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_dle_dfi_qempty *qempty) ++{ ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ u32 ret; ++ ++ ctrl.type = qempty->dle_type; ++ ctrl.target = DLE_DFI_TYPE_QEMPTY; ++ ctrl.addr = qempty->grpsel; ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); ++ return ret; ++ } ++ ++ qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); ++ return 0; ++} ++ ++static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) ++{ ++ rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); ++} ++ ++static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_mac_dle_dfi_qempty qempty; ++ struct rtw89_mac_dle_dfi_quota quota; ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ u32 val, not_empty, i; ++ int ret; ++ ++ qempty.dle_type = DLE_CTRL_TYPE_PLE; ++ qempty.grpsel = 0; ++ ret = dle_dfi_qempty(rtwdev, &qempty); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); ++ ++ for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { ++ if (!(not_empty & BIT(0))) ++ continue; ++ ctrl.type = DLE_CTRL_TYPE_PLE; ++ ctrl.target = DLE_DFI_TYPE_QLNKTBL; ++ ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | ++ FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, ++ FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, ++ ctrl.out_data)); ++ } ++ ++ quota.dle_type = DLE_CTRL_TYPE_PLE; ++ quota.qtaid = 6; ++ ret = dle_dfi_quota(rtwdev, "a); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", ++ quota.rsv_pgnum, quota.use_pgnum); ++ ++ val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); ++ rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", ++ FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); ++ rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", ++ FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); ++ ++ dump_err_status_dispatcher(rtwdev); ++} ++ ++static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, ++ enum mac_ax_err_info err) ++{ ++ u32 dbg, event; ++ ++ dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); ++ event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); ++ ++ switch (event) { ++ case MAC_AX_L0_TO_L1_RX_QTA_LOST: ++ rtw89_info(rtwdev, "quota lost!\n"); ++ rtw89_mac_dump_qta_lost(rtwdev); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, ++ enum mac_ax_err_info err) ++{ ++ u32 dmac_err, cmac_err; ++ ++ if (err != MAC_AX_ERR_L1_ERR_DMAC && ++ err != MAC_AX_ERR_L0_PROMOTE_TO_L1) ++ return; ++ ++ rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); ++ rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); ++ ++ cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); ++ rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); ++ dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); ++ rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); ++ ++ if (dmac_err) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); ++ } ++ ++ if (dmac_err & B_AX_WDRLS_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_WSEC_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); ++ } ++ ++ if (dmac_err & B_AX_MPDU_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ dump_err_status_dispatcher(rtwdev); ++ } ++ ++ if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); ++ rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); ++ } ++ ++ if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); ++ dump_err_status_dispatcher(rtwdev); ++ } ++ ++ if (dmac_err & B_AX_PKTIN_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_DISPATCH_ERR_FLAG) ++ dump_err_status_dispatcher(rtwdev); ++ ++ if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); ++ } ++ ++ if (dmac_err & BIT(11)) { ++ rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", ++ rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); ++ rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); ++ } ++ ++ if (cmac_err & B_AX_DMA_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL)); ++ } ++ ++ if (cmac_err & B_AX_PHYINTF_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); ++ } ++ ++ if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); ++ rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_WMAC_RX_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); ++ rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_WMAC_TX_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); ++ rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); ++ } ++ ++ rtwdev->hci.ops->dump_err_status(rtwdev); ++ ++ if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) ++ rtw89_mac_dump_l0_to_l1(rtwdev, err); ++ ++ rtw89_info(rtwdev, "<---\n"); ++} ++ ++u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) ++{ ++ u32 err; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, ++ false, rtwdev, R_AX_HALT_C2H_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "Polling FW err status fail\n"); ++ return ret; ++ } ++ ++ err = rtw89_read32(rtwdev, R_AX_HALT_C2H); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ rtw89_fw_st_dbg_dump(rtwdev); ++ rtw89_mac_dump_err_status(rtwdev, err); ++ ++ return err; ++} ++EXPORT_SYMBOL(rtw89_mac_get_err_status); ++ ++int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) ++{ ++ u32 halt; ++ int ret = 0; ++ ++ if (err > MAC_AX_SET_ERR_MAX) { ++ rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); ++ return -EINVAL; ++ } ++ ++ ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, ++ 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); ++ return -EFAULT; ++ } ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C, err); ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_mac_set_err_status); ++ ++struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = { ++ 2, 40, 0, 0, 1, 0, 0, 0 ++}; ++ ++static int hfc_reset_param(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_param_ini param_ini = {NULL}; ++ u8 qta_mode = rtwdev->mac.dle_info.qta_mode; ++ ++ switch (rtwdev->hci.type) { ++ case RTW89_HCI_TYPE_PCIE: ++ param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; ++ param->en = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (param_ini.pub_cfg) ++ param->pub_cfg = param_ini.pub_cfg; ++ ++ if (param_ini.prec_cfg) { ++ param->prec_cfg = param_ini.prec_cfg; ++ rtwdev->hal.sw_amsdu_max_size = ++ param->prec_cfg->wp_ch07_prec * HFC_PAGE_UNIT; ++ } ++ ++ if (param_ini.ch_cfg) ++ param->ch_cfg = param_ini.ch_cfg; ++ ++ memset(¶m->ch_info, 0, sizeof(param->ch_info)); ++ memset(¶m->pub_info, 0, sizeof(param->pub_info)); ++ param->mode = param_ini.mode; ++ ++ return 0; ++} ++ ++static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; ++ struct rtw89_hfc_pub_cfg *pub_cfg = param->pub_cfg; ++ struct rtw89_hfc_prec_cfg *prec_cfg = param->prec_cfg; ++ ++ if (ch >= RTW89_DMA_CH_NUM) ++ return -EINVAL; ++ ++ if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || ++ ch_cfg[ch].max > pub_cfg->pub_max) ++ return -EINVAL; ++ if (ch_cfg[ch].grp >= grp_num) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_pub_cfg *cfg = param->pub_cfg; ++ struct rtw89_hfc_pub_info *info = ¶m->pub_info; ++ ++ if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { ++ if (rtwdev->chip->chip_id == RTL8852A) ++ return 0; ++ else ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_pub_cfg *pub_cfg = param->pub_cfg; ++ ++ if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) ++ return 0; ++ ++ return 0; ++} ++ ++static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; ++ int ret = 0; ++ u32 val = 0; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ ret = hfc_ch_cfg_chk(rtwdev, ch); ++ if (ret) ++ return ret; ++ ++ if (ch > RTW89_DMA_B1HI) ++ return -EINVAL; ++ ++ val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | ++ u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | ++ (cfg[ch].grp ? B_AX_GRP : 0); ++ rtw89_write32(rtwdev, R_AX_ACH0_PAGE_CTRL + ch * 4, val); ++ ++ return 0; ++} ++ ++static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_ch_info *info = param->ch_info; ++ struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; ++ u32 val; ++ u32 ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (ch > RTW89_DMA_H2C) ++ return -EINVAL; ++ ++ val = rtw89_read32(rtwdev, R_AX_ACH0_PAGE_INFO + ch * 4); ++ info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); ++ if (ch < RTW89_DMA_H2C) ++ info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); ++ else ++ info[ch].used = cfg[ch].min - info[ch].aval; ++ ++ return 0; ++} ++ ++static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_pub_cfg *cfg = rtwdev->mac.hfc_param.pub_cfg; ++ u32 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ ret = hfc_pub_cfg_chk(rtwdev); ++ if (ret) ++ return ret; ++ ++ val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | ++ u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); ++ rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL1, val); ++ ++ val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); ++ rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL2, val); ++ ++ return 0; ++} ++ ++static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_pub_cfg *pub_cfg = param->pub_cfg; ++ struct rtw89_hfc_prec_cfg *prec_cfg = param->prec_cfg; ++ struct rtw89_hfc_pub_info *info = ¶m->pub_info; ++ u32 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO1); ++ info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); ++ info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO3); ++ info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); ++ info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); ++ info->pub_aval = ++ u32_get_bits(rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO2), ++ B_AX_PUB_AVAL_PG_MASK); ++ info->wp_aval = ++ u32_get_bits(rtw89_read32(rtwdev, R_AX_WP_PAGE_INFO1), ++ B_AX_WP_AVAL_PG_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); ++ param->en = val & B_AX_HCI_FC_EN ? 1 : 0; ++ param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; ++ param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); ++ prec_cfg->ch011_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); ++ prec_cfg->h2c_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); ++ prec_cfg->wp_ch07_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); ++ prec_cfg->wp_ch811_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_CH_PAGE_CTRL); ++ prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); ++ prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL2); ++ pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL1); ++ prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); ++ prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL2); ++ pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL1); ++ pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); ++ pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); ++ ++ ret = hfc_pub_info_chk(rtwdev); ++ if (param->en && ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_prec_cfg *prec_cfg = param->prec_cfg; ++ u32 val; ++ ++ val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); ++ rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); ++ ++ rtw89_write32_mask(rtwdev, R_AX_HCI_FC_CTRL, ++ B_AX_HCI_FC_CH12_FULL_COND_MASK, ++ prec_cfg->h2c_full_cond); ++} ++ ++static void hfc_mix_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_pub_cfg *pub_cfg = param->pub_cfg; ++ struct rtw89_hfc_prec_cfg *prec_cfg = param->prec_cfg; ++ u32 val; ++ ++ val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | ++ u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); ++ rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); ++ ++ val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); ++ rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL2, val); ++ ++ val = u32_encode_bits(prec_cfg->wp_ch07_prec, ++ B_AX_PREC_PAGE_WP_CH07_MASK) | ++ u32_encode_bits(prec_cfg->wp_ch811_prec, ++ B_AX_PREC_PAGE_WP_CH811_MASK); ++ rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL1, val); ++ ++ val = u32_replace_bits(rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL), ++ param->mode, B_AX_HCI_FC_MODE_MASK); ++ val = u32_replace_bits(val, prec_cfg->ch011_full_cond, ++ B_AX_HCI_FC_WD_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->h2c_full_cond, ++ B_AX_HCI_FC_CH12_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, ++ B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, ++ B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); ++ rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); ++} ++ ++static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); ++ param->en = en; ++ param->h2c_en = h2c_en; ++ val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); ++ val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : ++ (val & ~B_AX_HCI_FC_CH12_EN); ++ rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); ++} ++ ++static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) ++{ ++ u8 ch; ++ u32 ret = 0; ++ ++ if (reset) ++ ret = hfc_reset_param(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ hfc_func_en(rtwdev, false, false); ++ ++ if (!en && h2c_en) { ++ hfc_h2c_cfg(rtwdev); ++ hfc_func_en(rtwdev, en, h2c_en); ++ return ret; ++ } ++ ++ for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { ++ ret = hfc_ch_ctrl(rtwdev, ch); ++ if (ret) ++ return ret; ++ } ++ ++ ret = hfc_pub_ctrl(rtwdev); ++ if (ret) ++ return ret; ++ ++ hfc_mix_cfg(rtwdev); ++ if (en || h2c_en) { ++ hfc_func_en(rtwdev, en, h2c_en); ++ udelay(10); ++ } ++ for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { ++ ret = hfc_upd_ch_info(rtwdev, ch); ++ if (ret) ++ return ret; ++ } ++ ret = hfc_upd_mix_info(rtwdev); ++ ++ return ret; ++} ++ ++#define PWR_POLL_CNT 2000 ++static int pwr_cmd_poll(struct rtw89_dev *rtwdev, ++ const struct rtw89_pwr_cfg *cfg) ++{ ++ u8 val = 0; ++ int ret; ++ u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? ++ cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; ++ ++ ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), ++ 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); ++ ++ if (!ret) ++ return 0; ++ ++ rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); ++ rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); ++ rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); ++ ++ return -EBUSY; ++} ++ ++static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, ++ u8 intf_msk, const struct rtw89_pwr_cfg *cfg) ++{ ++ const struct rtw89_pwr_cfg *cur_cfg; ++ u32 addr; ++ u8 val; ++ ++ for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { ++ if (!(cur_cfg->intf_msk & intf_msk) || ++ !(cur_cfg->cv_msk & cv_msk)) ++ continue; ++ ++ switch (cur_cfg->cmd) { ++ case PWR_CMD_WRITE: ++ addr = cur_cfg->addr; ++ ++ if (cur_cfg->base == PWR_BASE_SDIO) ++ addr |= SDIO_LOCAL_BASE_ADDR; ++ ++ val = rtw89_read8(rtwdev, addr); ++ val &= ~(cur_cfg->msk); ++ val |= (cur_cfg->val & cur_cfg->msk); ++ ++ rtw89_write8(rtwdev, addr, val); ++ break; ++ case PWR_CMD_POLL: ++ if (pwr_cmd_poll(rtwdev, cur_cfg)) ++ return -EBUSY; ++ break; ++ case PWR_CMD_DELAY: ++ if (cur_cfg->val == PWR_DELAY_US) ++ udelay(cur_cfg->addr); ++ else ++ fsleep(cur_cfg->addr * 1000); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, ++ const struct rtw89_pwr_cfg * const *cfg_seq) ++{ ++ u32 idx = 0; ++ const struct rtw89_pwr_cfg *cfg; ++ int ret; ++ ++ do { ++ cfg = cfg_seq[idx]; ++ if (!cfg) ++ break; ++ ++ ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), ++ PWR_INTF_MSK_PCIE, cfg); ++ if (ret) ++ return -EBUSY; ++ ++ idx++; ++ } while (1); ++ ++ return 0; ++} ++ ++static enum rtw89_rpwm_req_pwr_state ++rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_rpwm_req_pwr_state state; ++ ++ switch (rtwdev->ps_mode) { ++ case RTW89_PS_MODE_RFOFF: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; ++ break; ++ case RTW89_PS_MODE_CLK_GATED: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; ++ break; ++ case RTW89_PS_MODE_PWR_GATED: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; ++ break; ++ default: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; ++ break; ++ } ++ return state; ++} ++ ++static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, ++ enum rtw89_rpwm_req_pwr_state req_pwr_state) ++{ ++ u16 request; ++ ++ request = rtw89_read16(rtwdev, R_AX_RPWM); ++ request ^= request | PS_RPWM_TOGGLE; ++ ++ rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & ++ RPWM_SEQ_NUM_MAX; ++ request |= FIELD_PREP(PS_RPWM_SEQ_NUM, rtwdev->mac.rpwm_seq_num); ++ ++ request |= req_pwr_state; ++ ++ if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) ++ request |= PS_RPWM_ACK; ++ ++ rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); ++} ++ ++static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, ++ enum rtw89_rpwm_req_pwr_state req_pwr_state) ++{ ++ bool request_deep_mode; ++ bool in_deep_mode; ++ u8 rpwm_req_num; ++ u8 cpwm_rsp_seq; ++ u8 cpwm_seq; ++ u8 cpwm_status; ++ ++ if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) ++ request_deep_mode = true; ++ else ++ request_deep_mode = false; ++ ++ if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) ++ in_deep_mode = true; ++ else ++ in_deep_mode = false; ++ ++ if (request_deep_mode != in_deep_mode) ++ return -EPERM; ++ ++ if (request_deep_mode) ++ return 0; ++ ++ rpwm_req_num = rtwdev->mac.rpwm_seq_num; ++ cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, ++ PS_CPWM_RSP_SEQ_NUM); ++ ++ if (rpwm_req_num != cpwm_rsp_seq) ++ return -EPERM; ++ ++ rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & ++ CPWM_SEQ_NUM_MAX; ++ ++ cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM); ++ if (cpwm_seq != rtwdev->mac.cpwm_seq_num) ++ return -EPERM; ++ ++ cpwm_status = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_STATE); ++ if (cpwm_status != req_pwr_state) ++ return -EPERM; ++ ++ return 0; ++} ++ ++void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) ++{ ++ enum rtw89_rpwm_req_pwr_state state; ++ int ret; ++ ++ if (enter) ++ state = rtw89_mac_get_req_pwr_state(rtwdev); ++ else ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; ++ ++ rtw89_mac_send_rpwm(rtwdev, state); ++ ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, ++ 1000, 15000, false, rtwdev, state); ++ if (ret) ++ rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", ++ enter ? "entering" : "leaving"); ++} ++ ++static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) ++{ ++#define PWR_ACT 1 ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_pwr_cfg * const *cfg_seq; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ int ret; ++ u8 val; ++ ++ if (on) ++ cfg_seq = chip->pwr_on_seq; ++ else ++ cfg_seq = chip->pwr_off_seq; ++ ++ if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) ++ __rtw89_leave_ps_mode(rtwdev); ++ ++ val = rtw89_read8(rtwdev, 0x3F1) & 0x3; ++ if (on && val == PWR_ACT) { ++ rtw89_err(rtwdev, "MAC has already powered on\n"); ++ return -EBUSY; ++ } ++ ++ ret = rtw89_mac_pwr_seq(rtwdev, cfg_seq); ++ if (ret) ++ return ret; ++ ++ if (on) { ++ set_bit(RTW89_FLAG_POWERON, rtwdev->flags); ++ rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); ++ } else { ++ clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); ++ clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); ++ hal->current_channel = 0; ++ } ++ ++ return 0; ++#undef PWR_ACT ++} ++ ++void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) ++{ ++ rtw89_mac_power_switch(rtwdev, false); ++} ++ ++static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) ++{ ++ u32 func_en = 0; ++ u32 ck_en = 0; ++ u32 c1pc_en = 0; ++ u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; ++ u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; ++ ++ func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | ++ B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | ++ B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN; ++ ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | ++ B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | ++ B_AX_RMAC_CKEN; ++ c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P1_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P2_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P3_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P4_PC_EN; ++ ++ if (en) { ++ if (mac_idx == RTW89_MAC_1) { ++ rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_ISO_CMAC12PP); ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_CMAC1_FEN); ++ } ++ rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); ++ rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); ++ } else { ++ rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); ++ rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); ++ if (mac_idx == RTW89_MAC_1) { ++ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_CMAC1_FEN); ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_ISO_CMAC12PP); ++ rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); ++ } ++ } ++ ++ return 0; ++} ++ ++static int dmac_func_en(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u32 ret = 0; ++ ++ val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | ++ B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | ++ B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN | ++ B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN); ++ rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); ++ ++ val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | ++ B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | ++ B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | ++ B_AX_WD_RLS_CLK_EN); ++ rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); ++ ++ return ret; ++} ++ ++static int chip_func_en(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, B_AX_OCP_L1_MASK); ++ ++ return 0; ++} ++ ++static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = dmac_func_en(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = cmac_func_en(rtwdev, 0, true); ++ if (ret) ++ return ret; ++ ++ ret = chip_func_en(rtwdev); ++ if (ret) ++ return ret; ++ ++ return ret; ++} ++ ++/* PCIE 64 */ ++struct rtw89_dle_size wde_size0 = { ++ RTW89_WDE_PG_64, 4095, 1, ++}; ++ ++/* DLFW */ ++struct rtw89_dle_size wde_size4 = { ++ RTW89_WDE_PG_64, 0, 4096, ++}; ++ ++/* PCIE */ ++struct rtw89_dle_size ple_size0 = { ++ RTW89_PLE_PG_128, 1520, 16, ++}; ++ ++/* DLFW */ ++struct rtw89_dle_size ple_size4 = { ++ RTW89_PLE_PG_128, 64, 1472, ++}; ++ ++/* PCIE 64 */ ++struct rtw89_wde_quota wde_qt0 = { ++ 3792, 196, 0, 107, ++}; ++ ++/* DLFW */ ++struct rtw89_wde_quota wde_qt4 = { ++ 0, 0, 0, 0, ++}; ++ ++/* PCIE SCC */ ++struct rtw89_ple_quota ple_qt4 = { ++ 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8, ++}; ++ ++/* PCIE SCC */ ++struct rtw89_ple_quota ple_qt5 = { ++ 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120, ++}; ++ ++/* DLFW */ ++struct rtw89_ple_quota ple_qt13 = { ++ 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0 ++}; ++ ++static struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, ++ enum rtw89_qta_mode mode) ++{ ++ struct rtw89_mac_info *mac = &rtwdev->mac; ++ struct rtw89_dle_mem *cfg; ++ ++ cfg = &rtwdev->chip->dle_mem[mode]; ++ if (!cfg) ++ return NULL; ++ ++ if (cfg->mode != mode) { ++ rtw89_warn(rtwdev, "qta mode unmatch!\n"); ++ return NULL; ++ } ++ ++ mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; ++ mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; ++ mac->dle_info.qta_mode = mode; ++ mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; ++ mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; ++ ++ return cfg; ++} ++ ++static inline u32 dle_used_size(struct rtw89_dle_size *wde, ++ struct rtw89_dle_size *ple) ++{ ++ return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + ++ ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); ++} ++ ++static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) ++ rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, ++ B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); ++ else ++ rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, ++ B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); ++} ++ ++static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) ++ rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, ++ B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); ++ else ++ rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, ++ B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); ++} ++ ++static int dle_mix_cfg(struct rtw89_dev *rtwdev, struct rtw89_dle_mem *cfg) ++{ ++ struct rtw89_dle_size *size_cfg; ++ u32 val; ++ u8 bound = 0; ++ ++ val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); ++ size_cfg = cfg->wde_size; ++ ++ switch (size_cfg->pge_size) { ++ default: ++ case RTW89_WDE_PG_64: ++ val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, ++ B_AX_WDE_PAGE_SEL_MASK); ++ break; ++ case RTW89_WDE_PG_128: ++ val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, ++ B_AX_WDE_PAGE_SEL_MASK); ++ break; ++ case RTW89_WDE_PG_256: ++ rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); ++ return -EINVAL; ++ } ++ ++ val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); ++ val = u32_replace_bits(val, size_cfg->lnk_pge_num, ++ B_AX_WDE_FREE_PAGE_NUM_MASK); ++ rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); ++ ++ val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); ++ bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) ++ * size_cfg->pge_size / DLE_BOUND_UNIT; ++ size_cfg = cfg->ple_size; ++ ++ switch (size_cfg->pge_size) { ++ default: ++ case RTW89_PLE_PG_64: ++ rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); ++ return -EINVAL; ++ case RTW89_PLE_PG_128: ++ val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, ++ B_AX_PLE_PAGE_SEL_MASK); ++ break; ++ case RTW89_PLE_PG_256: ++ val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, ++ B_AX_PLE_PAGE_SEL_MASK); ++ break; ++ } ++ ++ val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); ++ val = u32_replace_bits(val, size_cfg->lnk_pge_num, ++ B_AX_PLE_FREE_PAGE_NUM_MASK); ++ rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); ++ ++ return 0; ++} ++ ++#define SET_QUOTA(_x, _module, _idx) \ ++ do { \ ++ val = (min_cfg->_x & \ ++ B_AX_ ## _module ## _MIN_SIZE_MASK) | \ ++ ((max_cfg->_x << 16) & \ ++ B_AX_ ## _module ## _MAX_SIZE_MASK); \ ++ rtw89_write32(rtwdev, \ ++ R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ ++ val); \ ++ } while (0) ++ ++static void wde_quota_cfg(struct rtw89_dev *rtwdev, ++ struct rtw89_wde_quota *min_cfg, ++ struct rtw89_wde_quota *max_cfg) ++{ ++ u32 val; ++ ++ SET_QUOTA(hif, WDE, 0); ++ SET_QUOTA(wcpu, WDE, 1); ++ SET_QUOTA(pkt_in, WDE, 3); ++ SET_QUOTA(cpu_io, WDE, 4); ++} ++ ++static void ple_quota_cfg(struct rtw89_dev *rtwdev, ++ struct rtw89_ple_quota *min_cfg, ++ struct rtw89_ple_quota *max_cfg) ++{ ++ u32 val; ++ ++ SET_QUOTA(cma0_tx, PLE, 0); ++ SET_QUOTA(cma1_tx, PLE, 1); ++ SET_QUOTA(c2h, PLE, 2); ++ SET_QUOTA(h2c, PLE, 3); ++ SET_QUOTA(wcpu, PLE, 4); ++ SET_QUOTA(mpdu_proc, PLE, 5); ++ SET_QUOTA(cma0_dma, PLE, 6); ++ SET_QUOTA(cma1_dma, PLE, 7); ++ SET_QUOTA(bb_rpt, PLE, 8); ++ SET_QUOTA(wd_rel, PLE, 9); ++ SET_QUOTA(cpu_io, PLE, 10); ++} ++ ++#undef SET_QUOTA ++ ++static void dle_quota_cfg(struct rtw89_dev *rtwdev, struct rtw89_dle_mem *cfg) ++{ ++ wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt); ++ ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); ++} ++ ++static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, ++ enum rtw89_qta_mode ext_mode) ++{ ++ struct rtw89_dle_mem *cfg, *ext_cfg; ++ int ret = 0; ++ u32 ini; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ if (mode == RTW89_QTA_DLFW) { ++ ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); ++ if (!ext_cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", ++ ext_mode); ++ ret = -EINVAL; ++ goto error; ++ } ++ cfg->wde_min_qt->wcpu = ext_cfg->wde_min_qt->wcpu; ++ } ++ ++ if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ dle_func_en(rtwdev, false); ++ dle_clk_en(rtwdev, true); ++ ++ ret = dle_mix_cfg(rtwdev, cfg); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); ++ goto error; ++ } ++ dle_quota_cfg(rtwdev, cfg); ++ ++ dle_func_en(rtwdev, true); ++ ++ ret = read_poll_timeout(rtw89_read32, ini, ++ (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, ++ 2000, false, rtwdev, R_AX_WDE_INI_STATUS); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); ++ return ret; ++ } ++ ++ ret = read_poll_timeout(rtw89_read32, ini, ++ (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, ++ 2000, false, rtwdev, R_AX_PLE_INI_STATUS); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); ++ return ret; ++ } ++ ++ return 0; ++error: ++ dle_func_en(rtwdev, false); ++ rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); ++ rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); ++ ++ return ret; ++} ++ ++static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) ++{ ++ u32 msk32; ++ u32 val32; ++ ++ msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | ++ B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | ++ B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | ++ B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | ++ B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | ++ B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | ++ B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | ++ B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | ++ B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | ++ B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | ++ B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | ++ B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | ++ B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; ++ val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); ++ ++ if ((val32 & msk32) == msk32) ++ return true; ++ ++ return false; ++} ++ ++static int sta_sch_init(struct rtw89_dev *rtwdev) ++{ ++ u32 p_val; ++ u8 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read8(rtwdev, R_AX_SS_CTRL); ++ val |= B_AX_SS_EN; ++ rtw89_write8(rtwdev, R_AX_SS_CTRL, val); ++ ++ ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, ++ 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); ++ return ret; ++ } ++ ++ rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); ++ ++ return 0; ++} ++ ++static int mpdu_proc_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); ++ rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); ++ rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, ++ B_AX_APPEND_FCS | B_AX_A_ICV_ERR); ++ rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); ++ ++ return 0; ++} ++ ++static int sec_eng_init(struct rtw89_dev *rtwdev) ++{ ++ u32 val = 0; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); ++ /* init clock */ ++ val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); ++ /* init TX encryption */ ++ val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); ++ val |= (B_AX_MC_DEC | B_AX_BC_DEC); ++ val &= ~B_AX_TX_PARTIAL_MODE; ++ rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); ++ ++ /* init MIC ICV append */ ++ val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); ++ val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); ++ ++ /* option init */ ++ rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); ++ ++ return 0; ++} ++ ++static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ ++ ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); ++ return ret; ++ } ++ ++ ret = hfc_init(rtwdev, true, true, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); ++ return ret; ++ } ++ ++ ret = sta_sch_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); ++ return ret; ++ } ++ ++ ret = mpdu_proc_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); ++ return ret; ++ } ++ ++ ret = sec_eng_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ u16 p_val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); ++ ++ val = rtw89_read32(rtwdev, reg); ++ val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | ++ B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), ++ 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 ret; ++ u32 reg; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); ++ ++ return 0; ++} ++ ++static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, ++ enum rtw89_machdr_frame_type type, ++ enum rtw89_mac_fwd_target fwd_target, ++ u8 mac_idx) ++{ ++ u32 reg; ++ u32 val; ++ ++ switch (fwd_target) { ++ case RTW89_FWD_DONT_CARE: ++ val = RX_FLTR_FRAME_DROP; ++ break; ++ case RTW89_FWD_TO_HOST: ++ val = RX_FLTR_FRAME_TO_HOST; ++ break; ++ case RTW89_FWD_TO_WLAN_CPU: ++ val = RX_FLTR_FRAME_TO_WLCPU; ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case RTW89_MGNT: ++ reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); ++ break; ++ case RTW89_CTRL: ++ reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); ++ break; ++ case RTW89_DATA: ++ reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); ++ return -EINVAL; ++ } ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret, i; ++ u32 mac_ftlr, plcp_ftlr; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { ++ ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, ++ mac_idx); ++ if (ret) ++ return ret; ++ } ++ mac_ftlr = rtwdev->hal.rx_fltr; ++ plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | ++ B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | ++ B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | ++ B_AX_HE_SIGB_CRC_CHK; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), ++ mac_ftlr); ++ rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), ++ plcp_ftlr); ++ ++ return 0; ++} ++ ++static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg, val32; ++ u32 b_rsp_chk_nav, b_rsp_chk_cca; ++ ++ b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | ++ B_AX_RSP_CHK_BASIC_NAV; ++ b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | ++ B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | ++ B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; ++ ++ switch (rtwdev->chip->chip_id) { ++ case RTL8852A: ++ case RTL8852B: ++ reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; ++ rtw89_write32(rtwdev, reg, val32); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; ++ rtw89_write32(rtwdev, reg, val32); ++ break; ++ default: ++ reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; ++ rtw89_write32(rtwdev, reg, val32); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; ++ rtw89_write32(rtwdev, reg, val32); ++ break; ++ } ++} ++ ++static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | ++ B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | ++ B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | ++ B_AX_CTN_CHK_INTRA_NAV | ++ B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | ++ B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | ++ B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | ++ B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); ++ val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | ++ B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | ++ B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | ++ B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); ++ ++ rtw89_write32(rtwdev, reg, val); ++ ++ _patch_dis_resp_chk(rtwdev, mac_idx); ++ ++ return 0; ++} ++ ++static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); ++ rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); ++ ++ return 0; ++} ++ ++static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); ++ ++ return 0; ++} ++ ++static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg, val, sifs; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; ++ val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); ++ ++ switch (rtwdev->chip->chip_id) { ++ case RTL8852A: ++ sifs = WMAC_SPEC_SIFS_OFDM_52A; ++ break; ++ case RTL8852B: ++ sifs = WMAC_SPEC_SIFS_OFDM_52B; ++ break; ++ default: ++ sifs = WMAC_SPEC_SIFS_OFDM_52C; ++ break; ++ } ++ val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; ++ val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); ++ ++ return 0; ++} ++ ++static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++#define TRXCFG_RMAC_CCA_TO 32 ++#define TRXCFG_RMAC_DATA_TO 15 ++#define RX_MAX_LEN_UNIT 512 ++#define PLD_RLS_MAX_PG 127 ++ int ret; ++ u32 reg, rx_max_len, rx_qta; ++ u16 val; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); ++ rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); ++ val = rtw89_read16(rtwdev, reg); ++ val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, ++ B_AX_RX_DLK_DATA_TIME_MASK); ++ val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, ++ B_AX_RX_DLK_CCA_TIME_MASK); ++ rtw89_write16(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); ++ rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); ++ if (mac_idx == RTW89_MAC_0) ++ rx_qta = rtwdev->mac.dle_info.c0_rx_qta; ++ else ++ rx_qta = rtwdev->mac.dle_info.c1_rx_qta; ++ rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; ++ rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / ++ RX_MAX_LEN_UNIT; ++ rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? ++ B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; ++ rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); ++ ++ if (rtwdev->chip->chip_id == RTL8852A && ++ rtwdev->hal.cv == CHIP_CBV) { ++ rtw89_write16_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), ++ B_AX_RX_DLK_CCA_TIME_MASK, 0); ++ rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), ++ BIT(12)); ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); ++ rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); ++ ++ return ret; ++} ++ ++static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) ++{ ++ struct rtw89_dle_mem *cfg; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); ++ return false; ++ } ++ ++ return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); ++} ++ ++static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { ++ reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, ++ B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); ++ val |= B_AX_HW_CTS2SELF_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); ++ val &= ~B_AX_PTCL_TX_ARB_TO_MODE; ++ rtw89_write32(rtwdev, reg, val); ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); ++ val |= B_AX_HW_CTS2SELF_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ ++ ret = scheduler_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = addr_cam_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = rx_fltr_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = cca_ctrl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = spatial_reuse_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", ++ mac_idx, ret); ++ return ret; ++ } ++ ++ ret = tmac_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = trxptcl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = rmac_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = cmac_com_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = ptcl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_c2h_info *c2h_info) ++{ ++ struct rtw89_mac_h2c_info h2c_info = {0}; ++ u32 ret; ++ ++ h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; ++ h2c_info.content_len = 0; ++ ++ ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); ++ if (ret) ++ return ret; ++ ++ if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_mac_c2h_info c2h_info = {0}; ++ struct rtw89_c2h_phy_cap *cap = ++ (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; ++ u32 ret; ++ ++ ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); ++ if (ret) ++ return ret; ++ ++ hal->tx_nss = cap->tx_nss ? ++ min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; ++ hal->rx_nss = cap->rx_nss ? ++ min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", ++ hal->tx_nss, cap->tx_nss, chip->tx_nss, ++ hal->rx_nss, cap->rx_nss, chip->rx_nss); ++ ++ return 0; ++} ++ ++static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, ++ u16 tx_en_u16, u16 mask_u16) ++{ ++ u32 ret; ++ struct rtw89_mac_c2h_info c2h_info = {0}; ++ struct rtw89_mac_h2c_info h2c_info = {0}; ++ struct rtw89_h2creg_sch_tx_en *h2creg = ++ (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; ++ ++ h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; ++ h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; ++ h2creg->tx_en = tx_en_u16; ++ h2creg->mask = mask_u16; ++ h2creg->band = band; ++ ++ ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); ++ if (ret) ++ return ret; ++ ++ if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 tx_en, u16 tx_en_mask) ++{ ++ u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); ++ u16 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) ++ return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, ++ tx_en, tx_en_mask); ++ ++ val = rtw89_read16(rtwdev, reg); ++ val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); ++ rtw89_write16(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 *tx_en, enum rtw89_sch_tx_sel sel) ++{ ++ int ret; ++ ++ *tx_en = rtw89_read16(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); ++ ++ switch (sel) { ++ case RTW89_SCH_TX_SEL_ALL: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_HIQ: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, ++ 0, B_AX_CTN_TXEN_HGQ); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_MG0: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, ++ 0, B_AX_CTN_TXEN_MGQ); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_MACID: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); ++ if (ret) ++ return ret; ++ break; ++ default: ++ return 0; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en) ++{ ++ int ret; ++ ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, 0xffff); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, ++ bool wd) ++{ ++ u32 val, reg; ++ int ret; ++ ++ reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; ++ val = buf_len; ++ val |= B_AX_WD_BUF_REQ_EXEC; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; ++ ++ ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, ++ 1, 2000, false, rtwdev, reg); ++ if (ret) ++ return 0xffff; ++ ++ return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); ++} ++ ++static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, ++ struct rtw89_cpuio_ctrl *ctrl_para, ++ bool wd) ++{ ++ u32 val, cmd_type, reg; ++ int ret; ++ ++ cmd_type = ctrl_para->cmd_type; ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; ++ val = 0; ++ val = u32_replace_bits(val, ctrl_para->start_pktid, ++ B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); ++ val = u32_replace_bits(val, ctrl_para->end_pktid, ++ B_AX_WD_CPUQ_OP_END_PKTID_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; ++ val = 0; ++ val = u32_replace_bits(val, ctrl_para->src_pid, ++ B_AX_CPUQ_OP_SRC_PID_MASK); ++ val = u32_replace_bits(val, ctrl_para->src_qid, ++ B_AX_CPUQ_OP_SRC_QID_MASK); ++ val = u32_replace_bits(val, ctrl_para->dst_pid, ++ B_AX_CPUQ_OP_DST_PID_MASK); ++ val = u32_replace_bits(val, ctrl_para->dst_qid, ++ B_AX_CPUQ_OP_DST_QID_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; ++ val = 0; ++ val = u32_replace_bits(val, cmd_type, ++ B_AX_CPUQ_OP_CMD_TYPE_MASK); ++ val = u32_replace_bits(val, ctrl_para->macid, ++ B_AX_CPUQ_OP_MACID_MASK); ++ val = u32_replace_bits(val, ctrl_para->pkt_num, ++ B_AX_CPUQ_OP_PKTNUM_MASK); ++ val |= B_AX_WD_CPUQ_OP_EXEC; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; ++ ++ ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, ++ 1, 2000, false, rtwdev, reg); ++ if (ret) ++ return ret; ++ ++ if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || ++ cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) ++ ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); ++ ++ return 0; ++} ++ ++static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) ++{ ++ struct rtw89_dle_mem *cfg; ++ struct rtw89_cpuio_ctrl ctrl_para = {0}; ++ u16 pkt_id; ++ int ret; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ return -EINVAL; ++ } ++ ++ if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ return -EINVAL; ++ } ++ ++ dle_quota_cfg(rtwdev, cfg); ++ ++ pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); ++ if (pkt_id == 0xffff) { ++ rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); ++ return -ENOMEM; ++ } ++ ++ ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; ++ ctrl_para.start_pktid = pkt_id; ++ ctrl_para.end_pktid = pkt_id; ++ ctrl_para.pkt_num = 0; ++ ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; ++ ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; ++ ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); ++ return -EFAULT; ++ } ++ ++ pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); ++ if (pkt_id == 0xffff) { ++ rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); ++ return -ENOMEM; ++ } ++ ++ ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; ++ ctrl_para.start_pktid = pkt_id; ++ ctrl_para.end_pktid = pkt_id; ++ ctrl_para.pkt_num = 0; ++ ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; ++ ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; ++ ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ u32 reg; ++ u8 val; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); ++ ++ ret = read_poll_timeout(rtw89_read8, val, ++ (val & B_AX_PTCL_TX_ON_STAT) == 0, ++ SW_CVR_DUR_US, ++ SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, ++ false, rtwdev, reg); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int band1_enable(struct rtw89_dev *rtwdev) ++{ ++ int ret, i; ++ u32 sleep_bak[4] = {0}; ++ u32 pause_bak[4] = {0}; ++ u16 tx_en; ++ ++ ret = rtw89_mac_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); ++ pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); ++ rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); ++ rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); ++ } ++ ++ ret = band_idle_ck_b(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); ++ return ret; ++ } ++ ++ ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); ++ rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); ++ } ++ ++ ret = rtw89_mac_resume_sch_tx(rtwdev, 0, tx_en); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_func_en(rtwdev, 1, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_init(rtwdev, 1); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); ++ ++ return 0; ++} ++ ++static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, ++ enum rtw89_mac_hwmod_sel sel) ++{ ++ u32 reg, val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); ++ if (ret) { ++ rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", ++ sel, mac_idx); ++ return ret; ++ } ++ ++ if (sel == RTW89_DMAC_SEL) { ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, ++ B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | ++ B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | ++ B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, ++ B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | ++ B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, ++ B_AX_HDT_PKT_FAIL_DBG_INT_EN | ++ B_AX_HDT_OFFSET_UNMATCH_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, ++ B_AX_CPU_SHIFT_EN_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, ++ B_AX_PLE_GETNPG_STRPG_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, ++ B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN); ++ rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, ++ B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN); ++ } else if (sel == RTW89_CMAC_SEL) { ++ reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, ++ B_AX_SORT_NON_IDLE_ERR_INT_EN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, ++ B_AX_NO_RESERVE_PAGE_ERR_IMR | ++ B_AX_RXDATA_FSM_HANG_ERROR_IMR); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); ++ val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | ++ B_AX_TX_RECORD_PKTID_ERR_INT_EN | ++ B_AX_FSM_TIMEOUT_ERR_INT_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx); ++ rtw89_write32_set(rtwdev, reg, ++ B_AX_PHY_TXON_TIMEOUT_INT_EN | ++ B_AX_CCK_CCA_TIMEOUT_INT_EN | ++ B_AX_OFDM_CCA_TIMEOUT_INT_EN | ++ B_AX_DATA_ON_TIMEOUT_INT_EN | ++ B_AX_STS_ON_TIMEOUT_INT_EN | ++ B_AX_CSI_ON_TIMEOUT_INT_EN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN | ++ B_AX_RMAC_RX_TIMEOUT_INT_EN | ++ B_AX_RMAC_CSI_TIMEOUT_INT_EN); ++ val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | ++ B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | ++ B_AX_RMAC_CCA_TIMEOUT_INT_EN | ++ B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN); ++ rtw89_write32(rtwdev, reg, val); ++ } else { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret = 0; ++ ++ if (enable) { ++ ret = band1_enable(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); ++ return ret; ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); ++ return ret; ++ } ++ } else { ++ rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int set_host_rpr(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { ++ rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, ++ B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); ++ rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, ++ B_AX_RLSRPT0_FLTR_MAP_MASK); ++ } else { ++ rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, ++ B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); ++ rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, ++ B_AX_RLSRPT0_FLTR_MAP_MASK); ++ } ++ ++ rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); ++ rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); ++ ++ return 0; ++} ++ ++static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; ++ int ret; ++ ++ ret = dmac_init(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_init(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); ++ return ret; ++ } ++ ++ if (is_qta_dbcc(rtwdev, qta_mode)) { ++ ret = rtw89_mac_dbcc_enable(rtwdev, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); ++ return ret; ++ } ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); ++ return ret; ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); ++ return ret; ++ } ++ ++ ret = set_host_rpr(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) ++{ ++ clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ ++ rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); ++} ++ ++static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, ++ bool dlfw) ++{ ++ u32 val; ++ int ret; ++ ++ if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) ++ return -EFAULT; ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); ++ ++ val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); ++ val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); ++ val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, ++ B_AX_WCPU_FWDL_STS_MASK); ++ ++ if (dlfw) ++ val |= B_AX_WCPU_FWDL_EN; ++ ++ rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); ++ rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, ++ boot_reason); ++ rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); ++ ++ if (!dlfw) { ++ mdelay(5); ++ ++ ret = rtw89_fw_check_rdy(rtwdev); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_fw_dl_pre_init(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ int ret; ++ ++ val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | ++ B_AX_PKT_BUF_EN; ++ rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); ++ ++ val = B_AX_DISPATCHER_CLK_EN; ++ rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); ++ ++ ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); ++ return ret; ++ } ++ ++ ret = hfc_init(rtwdev, true, false, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, ++ B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); ++} ++ ++void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, ++ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); ++ rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, ++ B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | ++ B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); ++ rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); ++} ++ ++void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, ++ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); ++ rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, ++ B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | ++ B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); ++ rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); ++} ++ ++int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_power_switch(rtwdev, true); ++ if (ret) { ++ rtw89_mac_power_switch(rtwdev, false); ++ ret = rtw89_mac_power_switch(rtwdev, true); ++ if (ret) ++ return ret; ++ } ++ ++ rtw89_mac_hci_func_en(rtwdev); ++ ++ if (rtwdev->hci.ops->mac_pre_init) { ++ ret = rtwdev->hci.ops->mac_pre_init(rtwdev); ++ if (ret) ++ return ret; ++ } ++ ++ ret = rtw89_mac_fw_dl_pre_init(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_disable_cpu(rtwdev); ++ ret = rtw89_mac_enable_cpu(rtwdev, 0, true); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_partial_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ rtw89_mac_enable_bb_rf(rtwdev); ++ if (ret) ++ goto fail; ++ ++ ret = rtw89_mac_sys_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ ret = rtw89_mac_trx_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ if (rtwdev->hci.ops->mac_post_init) { ++ ret = rtwdev->hci.ops->mac_post_init(rtwdev); ++ if (ret) ++ goto fail; ++ } ++ ++ rtw89_fw_h2c_set_ofld_cfg(rtwdev); ++ ++ return ret; ++fail: ++ rtw89_mac_power_switch(rtwdev, false); ++ ++ return ret; ++} ++ ++static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ u8 i; ++ ++ for (i = 0; i < 4; i++) { ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, ++ DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); ++ } ++} ++ ++static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, ++ CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); ++} ++ ++static int rtw89_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) ++{ ++ u8 sh = FIELD_GET(GENMASK(4, 0), macid); ++ u8 grp = macid >> 5; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); ++ ++ return 0; ++} ++ ++static const struct rtw89_port_reg rtw_port_base = { ++ .port_cfg = R_AX_PORT_CFG_P0, ++ .tbtt_prohib = R_AX_TBTT_PROHIB_P0, ++ .bcn_area = R_AX_BCN_AREA_P0, ++ .bcn_early = R_AX_BCNERLYINT_CFG_P0, ++ .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, ++ .tbtt_agg = R_AX_TBTT_AGG_P0, ++ .bcn_space = R_AX_BCN_SPACE_CFG_P0, ++ .bcn_forcetx = R_AX_BCN_FORCETX_P0, ++ .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, ++ .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, ++ .dtim_ctrl = R_AX_DTIM_CTRL_P0, ++ .tbtt_shift = R_AX_TBTT_SHIFT_P0, ++ .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, ++ .tsftr_l = R_AX_TSFTR_LOW_P0, ++ .tsftr_h = R_AX_TSFTR_HIGH_P0 ++}; ++ ++#define BCN_INTERVAL 100 ++#define BCN_ERLY_DEF 160 ++#define BCN_SETUP_DEF 2 ++#define BCN_HOLD_DEF 200 ++#define BCN_MASK_DEF 0 ++#define TBTT_ERLY_DEF 5 ++#define BCN_SET_UNIT 32 ++#define BCN_ERLY_SET_DLY (10 * 2) ++ ++static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) ++ return; ++ ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); ++ rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); ++ rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); ++ ++ msleep(vif->bss_conf.beacon_int + 1); ++ ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | ++ B_AX_BRK_SETUP); ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); ++ rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); ++} ++ ++static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); ++} ++ ++static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); ++} ++ ++static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, ++ rtwvif->net_type); ++} ++ ++static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; ++ u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); ++} ++ ++static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ u32 bit = B_AX_RX_BSSID_FIT_EN; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); ++} ++ ++static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); ++} ++ ++static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); ++} ++ ++static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, ++ bcn_int); ++} ++ ++static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, ++ B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, ++ B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, ++ B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); ++} ++ ++static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, ++ B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ static const u32 masks[RTW89_PORT_NUM] = { ++ B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, ++ B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, ++ B_AX_BSS_COLOB_AX_PORT_4_MASK, ++ }; ++ u8 port = rtwvif->port; ++ u32 reg_base; ++ u32 reg; ++ u8 bss_color; ++ ++ bss_color = vif->bss_conf.he_bss_color.color; ++ reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; ++ reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); ++ rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); ++} ++ ++static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ u32 reg; ++ ++ if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) ++ return; ++ ++ if (port == 0) { ++ reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); ++ rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); ++ } ++} ++ ++static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ u32 reg; ++ u32 val; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); ++ if (port == 0) ++ val &= ~BIT(0); ++ rtw89_write32(rtwdev, reg, val); ++} ++ ++static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); ++} ++ ++static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, ++ BCN_ERLY_DEF); ++} ++ ++int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_mac_port_update(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); ++ rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); ++ ++ ret = rtw89_set_macid_pause(rtwdev, rtwvif->mac_id, false); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_CREATE); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_cam_init(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif->mac_id); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_REMOVE); ++ if (ret) ++ return ret; ++ ++ rtw89_cam_deinit(rtwdev, rtwvif); ++ ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ ++ if (port >= RTW89_PORT_NUM) ++ return -EINVAL; ++ ++ rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); ++ rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); ++ rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); ++ fsleep(BCN_ERLY_SET_DLY); ++ rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); ++ ++ return 0; ++} ++ ++int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, ++ RTW89_MAX_MAC_ID_NUM); ++ if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) ++ return -ENOSPC; ++ ++ ret = rtw89_mac_vif_init(rtwdev, rtwvif); ++ if (ret) ++ goto release_mac_id; ++ ++ return 0; ++ ++release_mac_id: ++ rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); ++ ++ return ret; ++} ++ ++int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); ++ rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); ++ ++ return ret; ++} ++ ++static void ++rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++} ++ ++static void ++rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", ++ RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); ++} ++ ++static void ++rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", ++ RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); ++} ++ ++static void ++rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), ++ RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); ++} ++ ++static void (*rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, ++ [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, ++ [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = NULL, ++ [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, ++ [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, ++}; ++ ++static void (*rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, ++ [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, ++ [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, ++}; ++ ++void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ void (*handler)(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = NULL; ++ ++ switch (class) { ++ case RTW89_MAC_C2H_CLASS_INFO: ++ if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) ++ handler = rtw89_mac_c2h_info_handler[func]; ++ break; ++ case RTW89_MAC_C2H_CLASS_OFLD: ++ if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) ++ handler = rtw89_mac_c2h_ofld_handler[func]; ++ break; ++ case RTW89_MAC_C2H_CLASS_FWDBG: ++ return; ++ default: ++ rtw89_info(rtwdev, "c2h class %d not support\n", class); ++ return; ++ } ++ if (!handler) { ++ rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, ++ func); ++ return; ++ } ++ handler(rtwdev, skb, len); ++} ++ ++bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *cr) ++{ ++ struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; ++ enum rtw89_qta_mode mode = dle_mem->mode; ++ u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); ++ ++ if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { ++ rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", ++ addr); ++ goto error; ++ } ++ ++ if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) ++ if (mode == RTW89_QTA_SCC) { ++ rtw89_err(rtwdev, ++ "[TXPWR] addr=0x%x but hw not enable\n", ++ addr); ++ goto error; ++ } ++ ++ *cr = addr; ++ return true; ++ ++error: ++ rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", ++ addr, phy_idx); ++ ++ return false; ++} ++ ++int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) ++{ ++ u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); ++ int ret = 0; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (!enable) { ++ rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); ++ return ret; ++ } ++ ++ rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | ++ B_AX_APP_MAC_INFO_RPT | ++ B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | ++ B_AX_PPDU_STAT_RPT_CRC32); ++ rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, ++ RTW89_PRPT_DEST_HOST); ++ ++ return ret; ++} ++ ++void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++#define MAC_AX_TIME_TH_SH 5 ++#define MAC_AX_LEN_TH_SH 4 ++#define MAC_AX_TIME_TH_MAX 255 ++#define MAC_AX_LEN_TH_MAX 255 ++#define MAC_AX_TIME_TH_DEF 88 ++#define MAC_AX_LEN_TH_DEF 4080 ++ struct ieee80211_hw *hw = rtwdev->hw; ++ u32 rts_threshold = hw->wiphy->rts_threshold; ++ u32 time_th, len_th; ++ u32 reg; ++ ++ if (rts_threshold == (u32)-1) { ++ time_th = MAC_AX_TIME_TH_DEF; ++ len_th = MAC_AX_LEN_TH_DEF; ++ } else { ++ time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; ++ len_th = rts_threshold; ++ } ++ ++ time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); ++ len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); ++ rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); ++ rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); ++} ++ ++void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) ++{ ++ bool empty; ++ int ret; ++ ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ return; ++ ++ ret = read_poll_timeout(dle_is_txq_empty, empty, empty, ++ 10000, 200000, false, rtwdev); ++ if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) ++ rtw89_info(rtwdev, "timed out to flush queues\n"); ++} ++ ++int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) ++{ ++ u8 val; ++ u16 val16; ++ u32 val32; ++ int ret; ++ ++ rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); ++ rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); ++ rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); ++ rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); ++ rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); ++ rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); ++ val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; ++ rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); ++ ++ ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); ++ if (ret) { ++ rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); ++ return ret; ++ } ++ val32 = val32 & B_AX_WL_RX_CTRL; ++ ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); ++ if (ret) { ++ rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); ++ return ret; ++ } ++ ++ switch (coex->pta_mode) { ++ case RTW89_MAC_AX_COEX_RTK_MODE: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); ++ val &= ~B_AX_BTMODE_MASK; ++ val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); ++ ++ val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); ++ rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); ++ ++ val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); ++ val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; ++ val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); ++ rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); ++ break; ++ case RTW89_MAC_AX_COEX_CSR_MODE: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); ++ val &= ~B_AX_BTMODE_MASK; ++ val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); ++ val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); ++ val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); ++ val16 &= ~B_AX_BT_STAT_DELAY_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); ++ val16 |= B_AX_ENHANCED_BT; ++ rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); ++ ++ rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (coex->direction) { ++ case RTW89_MAC_AX_COEX_INNER: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = (val & ~BIT(2)) | BIT(1); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ case RTW89_MAC_AX_COEX_OUTPUT: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = val | BIT(1) | BIT(0); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ case RTW89_MAC_AX_COEX_INPUT: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = val & ~(BIT(2) | BIT(1)); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, ++ const struct rtw89_mac_ax_coex_gnt *gnt_cfg) ++{ ++ u32 val, ret; ++ ++ ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); ++ if (ret) { ++ rtw89_err(rtwdev, "Read LTE fail!\n"); ++ return ret; ++ } ++ val = (gnt_cfg->band[0].gnt_bt ? ++ B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL : 0) | ++ (gnt_cfg->band[0].gnt_bt_sw_en ? ++ B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL : 0) | ++ (gnt_cfg->band[0].gnt_wl ? ++ B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL : 0) | ++ (gnt_cfg->band[0].gnt_wl_sw_en ? ++ B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL : 0) | ++ (gnt_cfg->band[1].gnt_bt ? ++ B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL : 0) | ++ (gnt_cfg->band[1].gnt_bt_sw_en ? ++ B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL : 0) | ++ (gnt_cfg->band[1].gnt_wl ? ++ B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL : 0) | ++ (gnt_cfg->band[1].gnt_wl_sw_en ? ++ B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL : 0); ++ ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); ++ if (ret) { ++ rtw89_err(rtwdev, "Write LTE fail!\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) ++{ ++ u32 reg; ++ u8 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); ++ val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0); ++ rtw89_write8(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) ++{ ++ u32 fw_sb; ++ ++ fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); ++ fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); ++ fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; ++ else ++ fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; ++ val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); ++ val = B_AX_TOGGLE | ++ FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | ++ FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); ++ rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); ++} ++ ++u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) ++{ ++ return rtw89_read32(rtwdev, R_AX_SCOREBOARD); ++} ++ ++int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); ++ ++ val = wl ? val | BIT(2) : val & ~BIT(2); ++ rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); ++ ++ return 0; ++} ++ ++bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); ++ ++ return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); ++} ++ ++static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) ++{ ++ u32 reg; ++ u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | ++ B_AX_BFMEE_HE_NDPA_EN; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); ++ if (en) { ++ set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ rtw89_write32_set(rtwdev, reg, mask); ++ } else { ++ clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ rtw89_write32_clr(rtwdev, reg, mask); ++ } ++} ++ ++static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ u32 val32; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ /* AP mode set tx gid to 63 */ ++ /* STA mode set tx gid to 0(default) */ ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); ++ rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); ++ val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); ++ val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); ++ rtw89_write32(rtwdev, reg, val32); ++ rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | ++ B_AX_BFMEE_USE_NSTS | ++ B_AX_BFMEE_CSI_GID_SEL | ++ B_AX_BFMEE_CSI_FORCE_RETE_EN); ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); ++ rtw89_write32(rtwdev, reg, ++ u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | ++ u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | ++ u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); ++ ++ return 0; ++} ++ ++static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u8 mac_idx = rtwvif->mac_idx; ++ u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; ++ u8 port_sel = rtwvif->port; ++ u8 sound_dim = 3, t; ++ u8 *phy_cap = sta->he_cap.he_cap_elem.phy_cap_info; ++ u32 reg; ++ u16 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || ++ (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { ++ ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); ++ stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); ++ t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, ++ phy_cap[5]); ++ sound_dim = min(sound_dim, t); ++ } ++ if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { ++ ldpc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); ++ stbc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); ++ t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, ++ sta->vht_cap.cap); ++ sound_dim = min(sound_dim, t); ++ } ++ nc = min(nc, sound_dim); ++ nr = min(nr, sound_dim); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); ++ ++ val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); ++ ++ if (port_sel == 0) ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ else ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); ++ ++ rtw89_write16(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); ++ u32 reg; ++ u8 mac_idx = rtwvif->mac_idx; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (sta->he_cap.has_he) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); ++ } ++ if (sta->vht_cap.vht_supported) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); ++ } ++ if (sta->ht_cap.ht_supported) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); ++ } ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); ++ rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); ++ rtw89_write32(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), ++ rrsc); ++ ++ return 0; ++} ++ ++void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ if (rtw89_sta_has_beamformer_cap(sta)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BF, ++ "initialize bfee for new association\n"); ++ rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); ++ rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); ++ rtw89_mac_csi_rrsc(rtwdev, vif, sta); ++ } ++} ++ ++void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); ++} ++ ++void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u8 mac_idx = rtwvif->mac_idx; ++ __le32 *p; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); ++ ++ p = (__le32 *)conf->mu_group.membership; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), ++ le32_to_cpu(p[0])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), ++ le32_to_cpu(p[1])); ++ ++ p = (__le32 *)conf->mu_group.position; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), ++ le32_to_cpu(p[0])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), ++ le32_to_cpu(p[1])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), ++ le32_to_cpu(p[2])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), ++ le32_to_cpu(p[3])); ++} ++ ++struct rtw89_mac_bf_monitor_iter_data { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_sta *down_sta; ++ int count; ++}; ++ ++static ++void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_mac_bf_monitor_iter_data *iter_data = ++ (struct rtw89_mac_bf_monitor_iter_data *)data; ++ struct ieee80211_sta *down_sta = iter_data->down_sta; ++ int *count = &iter_data->count; ++ ++ if (down_sta == sta) ++ return; ++ ++ if (rtw89_sta_has_beamformer_cap(sta)) ++ (*count)++; ++} ++ ++void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool disconnect) ++{ ++ struct rtw89_mac_bf_monitor_iter_data data; ++ ++ data.rtwdev = rtwdev; ++ data.down_sta = disconnect ? sta : NULL; ++ data.count = 0; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_mac_bf_monitor_calc_iter, ++ &data); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); ++ if (data.count) ++ set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); ++ else ++ clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); ++} ++ ++void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ struct rtw89_vif *rtwvif; ++ bool en = stats->tx_tfc_lv > stats->rx_tfc_lv ? false : true; ++ bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ ++ if (en == old) ++ return; ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); ++} ++ ++static int ++__rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 tx_time) ++{ ++#define MAC_AX_DFLT_TX_TIME 5280 ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_time) { ++ rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, ++ max_tx_time >> 5); ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ bool resume, u32 tx_time) ++{ ++ int ret = 0; ++ ++ if (!resume) { ++ rtwsta->cctl_tx_time = true; ++ ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); ++ } else { ++ ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); ++ rtwsta->cctl_tx_time = false; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 *tx_time) ++{ ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_time) { ++ *tx_time = (rtwsta->ampdu_max_time + 1) << 9; ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); ++ *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, ++ bool resume, u8 tx_retry) ++{ ++ int ret = 0; ++ ++ rtwsta->data_tx_cnt_lmt = tx_retry; ++ ++ if (!resume) { ++ rtwsta->cctl_tx_retry_limit = true; ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ } else { ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ rtwsta->cctl_tx_retry_limit = false; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, u8 *tx_retry) ++{ ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_retry_limit) { ++ *tx_retry = rtwsta->data_tx_cnt_lmt; ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); ++ *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ u8 mac_idx = rtwvif->mac_idx; ++ u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; ++ u32 reg; ++ u32 ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); ++ if (en) ++ rtw89_write16_set(rtwdev, reg, set); ++ else ++ rtw89_write16_clr(rtwdev, reg, set); ++ ++ return 0; ++} +diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h +new file mode 100644 +index 000000000000..e1c9f48583c8 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac.h +@@ -0,0 +1,860 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_MAC_H__ ++#define __RTW89_MAC_H__ ++ ++#include "core.h" ++ ++#define MAC_MEM_DUMP_PAGE_SIZE 0x40000 ++#define ADDR_CAM_ENT_SIZE 0x40 ++#define BSSID_CAM_ENT_SIZE 0x08 ++#define HFC_PAGE_UNIT 64 ++ ++enum rtw89_mac_hwmod_sel { ++ RTW89_DMAC_SEL = 0, ++ RTW89_CMAC_SEL = 1, ++ ++ RTW89_MAC_INVALID, ++}; ++ ++enum rtw89_mac_fwd_target { ++ RTW89_FWD_DONT_CARE = 0, ++ RTW89_FWD_TO_HOST = 1, ++ RTW89_FWD_TO_WLAN_CPU = 2 ++}; ++ ++enum rtw89_mac_wd_dma_intvl { ++ RTW89_MAC_WD_DMA_INTVL_0S, ++ RTW89_MAC_WD_DMA_INTVL_256NS, ++ RTW89_MAC_WD_DMA_INTVL_512NS, ++ RTW89_MAC_WD_DMA_INTVL_768NS, ++ RTW89_MAC_WD_DMA_INTVL_1US, ++ RTW89_MAC_WD_DMA_INTVL_1_5US, ++ RTW89_MAC_WD_DMA_INTVL_2US, ++ RTW89_MAC_WD_DMA_INTVL_4US, ++ RTW89_MAC_WD_DMA_INTVL_8US, ++ RTW89_MAC_WD_DMA_INTVL_16US, ++ RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE ++}; ++ ++enum rtw89_mac_multi_tag_num { ++ RTW89_MAC_TAG_NUM_1, ++ RTW89_MAC_TAG_NUM_2, ++ RTW89_MAC_TAG_NUM_3, ++ RTW89_MAC_TAG_NUM_4, ++ RTW89_MAC_TAG_NUM_5, ++ RTW89_MAC_TAG_NUM_6, ++ RTW89_MAC_TAG_NUM_7, ++ RTW89_MAC_TAG_NUM_8, ++ RTW89_MAC_TAG_NUM_DEF = 0xFE ++}; ++ ++enum rtw89_mac_lbc_tmr { ++ RTW89_MAC_LBC_TMR_8US = 0, ++ RTW89_MAC_LBC_TMR_16US, ++ RTW89_MAC_LBC_TMR_32US, ++ RTW89_MAC_LBC_TMR_64US, ++ RTW89_MAC_LBC_TMR_128US, ++ RTW89_MAC_LBC_TMR_256US, ++ RTW89_MAC_LBC_TMR_512US, ++ RTW89_MAC_LBC_TMR_1MS, ++ RTW89_MAC_LBC_TMR_2MS, ++ RTW89_MAC_LBC_TMR_4MS, ++ RTW89_MAC_LBC_TMR_8MS, ++ RTW89_MAC_LBC_TMR_DEF = 0xFE ++}; ++ ++enum rtw89_mac_cpuio_op_cmd_type { ++ CPUIO_OP_CMD_GET_1ST_PID = 0, ++ CPUIO_OP_CMD_GET_NEXT_PID = 1, ++ CPUIO_OP_CMD_ENQ_TO_TAIL = 4, ++ CPUIO_OP_CMD_ENQ_TO_HEAD = 5, ++ CPUIO_OP_CMD_DEQ = 8, ++ CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, ++ CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 ++}; ++ ++enum rtw89_mac_wde_dle_port_id { ++ WDE_DLE_PORT_ID_DISPATCH = 0, ++ WDE_DLE_PORT_ID_PKTIN = 1, ++ WDE_DLE_PORT_ID_CMAC0 = 3, ++ WDE_DLE_PORT_ID_CMAC1 = 4, ++ WDE_DLE_PORT_ID_CPU_IO = 6, ++ WDE_DLE_PORT_ID_WDRLS = 7, ++ WDE_DLE_PORT_ID_END = 8 ++}; ++ ++enum rtw89_mac_wde_dle_queid_wdrls { ++ WDE_DLE_QUEID_TXOK = 0, ++ WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, ++ WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, ++ WDE_DLE_QUEID_DROP_MACID_DROP = 3, ++ WDE_DLE_QUEID_NO_REPORT = 4 ++}; ++ ++enum rtw89_mac_ple_dle_port_id { ++ PLE_DLE_PORT_ID_DISPATCH = 0, ++ PLE_DLE_PORT_ID_MPDU = 1, ++ PLE_DLE_PORT_ID_SEC = 2, ++ PLE_DLE_PORT_ID_CMAC0 = 3, ++ PLE_DLE_PORT_ID_CMAC1 = 4, ++ PLE_DLE_PORT_ID_WDRLS = 5, ++ PLE_DLE_PORT_ID_CPU_IO = 6, ++ PLE_DLE_PORT_ID_PLRLS = 7, ++ PLE_DLE_PORT_ID_END = 8 ++}; ++ ++enum rtw89_mac_ple_dle_queid_plrls { ++ PLE_DLE_QUEID_NO_REPORT = 0x0 ++}; ++ ++enum rtw89_machdr_frame_type { ++ RTW89_MGNT = 0, ++ RTW89_CTRL = 1, ++ RTW89_DATA = 2, ++}; ++ ++enum rtw89_mac_dle_dfi_type { ++ DLE_DFI_TYPE_FREEPG = 0, ++ DLE_DFI_TYPE_QUOTA = 1, ++ DLE_DFI_TYPE_PAGELLT = 2, ++ DLE_DFI_TYPE_PKTINFO = 3, ++ DLE_DFI_TYPE_PREPKTLLT = 4, ++ DLE_DFI_TYPE_NXTPKTLLT = 5, ++ DLE_DFI_TYPE_QLNKTBL = 6, ++ DLE_DFI_TYPE_QEMPTY = 7, ++}; ++ ++enum rtw89_mac_dle_wde_quota_id { ++ WDE_QTAID_HOST_IF = 0, ++ WDE_QTAID_WLAN_CPU = 1, ++ WDE_QTAID_DATA_CPU = 2, ++ WDE_QTAID_PKTIN = 3, ++ WDE_QTAID_CPUIO = 4, ++}; ++ ++enum rtw89_mac_dle_ple_quota_id { ++ PLE_QTAID_B0_TXPL = 0, ++ PLE_QTAID_B1_TXPL = 1, ++ PLE_QTAID_C2H = 2, ++ PLE_QTAID_H2C = 3, ++ PLE_QTAID_WLAN_CPU = 4, ++ PLE_QTAID_MPDU = 5, ++ PLE_QTAID_CMAC0_RX = 6, ++ PLE_QTAID_CMAC1_RX = 7, ++ PLE_QTAID_CMAC1_BBRPT = 8, ++ PLE_QTAID_WDRLS = 9, ++ PLE_QTAID_CPUIO = 10, ++}; ++ ++enum rtw89_mac_dle_ctrl_type { ++ DLE_CTRL_TYPE_WDE = 0, ++ DLE_CTRL_TYPE_PLE = 1, ++ DLE_CTRL_TYPE_NUM = 2, ++}; ++ ++enum rtw89_mac_ax_l0_to_l1_event { ++ MAC_AX_L0_TO_L1_CHIF_IDLE = 0, ++ MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, ++ MAC_AX_L0_TO_L1_RLS_PKID = 2, ++ MAC_AX_L0_TO_L1_PTCL_IDLE = 3, ++ MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, ++ MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, ++ MAC_AX_L0_TO_L1_PCIE_STUCK = 6, ++ MAC_AX_L0_TO_L1_EVENT_MAX = 15, ++}; ++ ++enum rtw89_mac_dbg_port_sel { ++ /* CMAC 0 related */ ++ RTW89_DBG_PORT_SEL_PTCL_C0 = 0, ++ RTW89_DBG_PORT_SEL_SCH_C0, ++ RTW89_DBG_PORT_SEL_TMAC_C0, ++ RTW89_DBG_PORT_SEL_RMAC_C0, ++ RTW89_DBG_PORT_SEL_RMACST_C0, ++ RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, ++ RTW89_DBG_PORT_SEL_TRXPTCL_C0, ++ RTW89_DBG_PORT_SEL_TX_INFOL_C0, ++ RTW89_DBG_PORT_SEL_TX_INFOH_C0, ++ RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, ++ RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, ++ /* CMAC 1 related */ ++ RTW89_DBG_PORT_SEL_PTCL_C1, ++ RTW89_DBG_PORT_SEL_SCH_C1, ++ RTW89_DBG_PORT_SEL_TMAC_C1, ++ RTW89_DBG_PORT_SEL_RMAC_C1, ++ RTW89_DBG_PORT_SEL_RMACST_C1, ++ RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, ++ RTW89_DBG_PORT_SEL_TRXPTCL_C1, ++ RTW89_DBG_PORT_SEL_TX_INFOL_C1, ++ RTW89_DBG_PORT_SEL_TX_INFOH_C1, ++ RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, ++ RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, ++ /* DLE related */ ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, ++ RTW89_DBG_PORT_SEL_PKTINFO, ++ /* PCIE related */ ++ RTW89_DBG_PORT_SEL_PCIE_TXDMA, ++ RTW89_DBG_PORT_SEL_PCIE_RXDMA, ++ RTW89_DBG_PORT_SEL_PCIE_CVT, ++ RTW89_DBG_PORT_SEL_PCIE_CXPL, ++ RTW89_DBG_PORT_SEL_PCIE_IO, ++ RTW89_DBG_PORT_SEL_PCIE_MISC, ++ RTW89_DBG_PORT_SEL_PCIE_MISC2, ++ ++ /* keep last */ ++ RTW89_DBG_PORT_SEL_LAST, ++ RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, ++ RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, ++}; ++ ++/* SRAM mem dump */ ++#define R_AX_INDIR_ACCESS_ENTRY 0x40000 ++ ++#define STA_SCHED_BASE_ADDR 0x18808000 ++#define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 ++#define SECURITY_CAM_BASE_ADDR 0x18814000 ++#define WOW_CAM_BASE_ADDR 0x18815000 ++#define CMAC_TBL_BASE_ADDR 0x18840000 ++#define ADDR_CAM_BASE_ADDR 0x18850000 ++#define BSSID_CAM_BASE_ADDR 0x18853000 ++#define BA_CAM_BASE_ADDR 0x18854000 ++#define BCN_IE_CAM0_BASE_ADDR 0x18855000 ++#define SHARED_BUF_BASE_ADDR 0x18700000 ++#define DMAC_TBL_BASE_ADDR 0x18800000 ++#define SHCUT_MACHDR_BASE_ADDR 0x18800800 ++#define BCN_IE_CAM1_BASE_ADDR 0x188A0000 ++ ++#define CCTL_INFO_SIZE 32 ++ ++enum rtw89_mac_mem_sel { ++ RTW89_MAC_MEM_SHARED_BUF, ++ RTW89_MAC_MEM_DMAC_TBL, ++ RTW89_MAC_MEM_SHCUT_MACHDR, ++ RTW89_MAC_MEM_STA_SCHED, ++ RTW89_MAC_MEM_RXPLD_FLTR_CAM, ++ RTW89_MAC_MEM_SECURITY_CAM, ++ RTW89_MAC_MEM_WOW_CAM, ++ RTW89_MAC_MEM_CMAC_TBL, ++ RTW89_MAC_MEM_ADDR_CAM, ++ RTW89_MAC_MEM_BA_CAM, ++ RTW89_MAC_MEM_BCN_IE_CAM0, ++ RTW89_MAC_MEM_BCN_IE_CAM1, ++ ++ /* keep last */ ++ RTW89_MAC_MEM_LAST, ++ RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST, ++ RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST, ++}; ++ ++enum rtw89_rpwm_req_pwr_state { ++ RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, ++}; ++ ++struct rtw89_pwr_cfg { ++ u16 addr; ++ u8 cv_msk; ++ u8 intf_msk; ++ u8 base:4; ++ u8 cmd:4; ++ u8 msk; ++ u8 val; ++}; ++ ++enum rtw89_mac_c2h_ofld_func { ++ RTW89_MAC_C2H_FUNC_EFUSE_DUMP, ++ RTW89_MAC_C2H_FUNC_READ_RSP, ++ RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, ++ RTW89_MAC_C2H_FUNC_BCN_RESEND, ++ RTW89_MAC_C2H_FUNC_MACID_PAUSE, ++ RTW89_MAC_C2H_FUNC_OFLD_MAX, ++}; ++ ++enum rtw89_mac_c2h_info_func { ++ RTW89_MAC_C2H_FUNC_REC_ACK, ++ RTW89_MAC_C2H_FUNC_DONE_ACK, ++ RTW89_MAC_C2H_FUNC_C2H_LOG, ++ RTW89_MAC_C2H_FUNC_INFO_MAX, ++}; ++ ++enum rtw89_mac_c2h_class { ++ RTW89_MAC_C2H_CLASS_INFO, ++ RTW89_MAC_C2H_CLASS_OFLD, ++ RTW89_MAC_C2H_CLASS_TWT, ++ RTW89_MAC_C2H_CLASS_WOW, ++ RTW89_MAC_C2H_CLASS_MCC, ++ RTW89_MAC_C2H_CLASS_FWDBG, ++ RTW89_MAC_C2H_CLASS_MAX, ++}; ++ ++struct rtw89_mac_ax_coex { ++#define RTW89_MAC_AX_COEX_RTK_MODE 0 ++#define RTW89_MAC_AX_COEX_CSR_MODE 1 ++ u8 pta_mode; ++#define RTW89_MAC_AX_COEX_INNER 0 ++#define RTW89_MAC_AX_COEX_OUTPUT 1 ++#define RTW89_MAC_AX_COEX_INPUT 2 ++ u8 direction; ++}; ++ ++struct rtw89_mac_ax_plt { ++#define RTW89_MAC_AX_PLT_LTE_RX BIT(0) ++#define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) ++#define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) ++#define RTW89_MAC_AX_PLT_GNT_WL BIT(3) ++ u8 band; ++ u8 tx; ++ u8 rx; ++}; ++ ++enum rtw89_mac_bf_rrsc_rate { ++ RTW89_MAC_BF_RRSC_6M = 0, ++ RTW89_MAC_BF_RRSC_9M = 1, ++ RTW89_MAC_BF_RRSC_12M, ++ RTW89_MAC_BF_RRSC_18M, ++ RTW89_MAC_BF_RRSC_24M, ++ RTW89_MAC_BF_RRSC_36M, ++ RTW89_MAC_BF_RRSC_48M, ++ RTW89_MAC_BF_RRSC_54M, ++ RTW89_MAC_BF_RRSC_HT_MSC0, ++ RTW89_MAC_BF_RRSC_HT_MSC1, ++ RTW89_MAC_BF_RRSC_HT_MSC2, ++ RTW89_MAC_BF_RRSC_HT_MSC3, ++ RTW89_MAC_BF_RRSC_HT_MSC4, ++ RTW89_MAC_BF_RRSC_HT_MSC5, ++ RTW89_MAC_BF_RRSC_HT_MSC6, ++ RTW89_MAC_BF_RRSC_HT_MSC7, ++ RTW89_MAC_BF_RRSC_VHT_MSC0, ++ RTW89_MAC_BF_RRSC_VHT_MSC1, ++ RTW89_MAC_BF_RRSC_VHT_MSC2, ++ RTW89_MAC_BF_RRSC_VHT_MSC3, ++ RTW89_MAC_BF_RRSC_VHT_MSC4, ++ RTW89_MAC_BF_RRSC_VHT_MSC5, ++ RTW89_MAC_BF_RRSC_VHT_MSC6, ++ RTW89_MAC_BF_RRSC_VHT_MSC7, ++ RTW89_MAC_BF_RRSC_HE_MSC0, ++ RTW89_MAC_BF_RRSC_HE_MSC1, ++ RTW89_MAC_BF_RRSC_HE_MSC2, ++ RTW89_MAC_BF_RRSC_HE_MSC3, ++ RTW89_MAC_BF_RRSC_HE_MSC4, ++ RTW89_MAC_BF_RRSC_HE_MSC5, ++ RTW89_MAC_BF_RRSC_HE_MSC6, ++ RTW89_MAC_BF_RRSC_HE_MSC7 = 31, ++ RTW89_MAC_BF_RRSC_MAX = 32 ++}; ++ ++#define RTW89_R32_EA 0xEAEAEAEA ++#define RTW89_R32_DEAD 0xDEADBEEF ++#define MAC_REG_POOL_COUNT 10 ++#define ACCESS_CMAC(_addr) \ ++ ({typeof(_addr) __addr = (_addr); \ ++ __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) ++ ++#define PTCL_IDLE_POLL_CNT 10000 ++#define SW_CVR_DUR_US 8 ++#define SW_CVR_CNT 8 ++ ++#define DLE_BOUND_UNIT (8 * 1024) ++#define DLE_WAIT_CNT 2000 ++#define TRXCFG_WAIT_CNT 2000 ++ ++#define RTW89_WDE_PG_64 64 ++#define RTW89_WDE_PG_128 128 ++#define RTW89_WDE_PG_256 256 ++ ++#define S_AX_WDE_PAGE_SEL_64 0 ++#define S_AX_WDE_PAGE_SEL_128 1 ++#define S_AX_WDE_PAGE_SEL_256 2 ++ ++#define RTW89_PLE_PG_64 64 ++#define RTW89_PLE_PG_128 128 ++#define RTW89_PLE_PG_256 256 ++ ++#define S_AX_PLE_PAGE_SEL_64 0 ++#define S_AX_PLE_PAGE_SEL_128 1 ++#define S_AX_PLE_PAGE_SEL_256 2 ++ ++#define SDIO_LOCAL_BASE_ADDR 0x80000000 ++ ++#define PWR_CMD_WRITE 0 ++#define PWR_CMD_POLL 1 ++#define PWR_CMD_DELAY 2 ++#define PWR_CMD_END 3 ++ ++#define PWR_INTF_MSK_SDIO BIT(0) ++#define PWR_INTF_MSK_USB BIT(1) ++#define PWR_INTF_MSK_PCIE BIT(2) ++#define PWR_INTF_MSK_ALL 0x7 ++ ++#define PWR_BASE_MAC 0 ++#define PWR_BASE_USB 1 ++#define PWR_BASE_PCIE 2 ++#define PWR_BASE_SDIO 3 ++ ++#define PWR_CV_MSK_A BIT(0) ++#define PWR_CV_MSK_B BIT(1) ++#define PWR_CV_MSK_C BIT(2) ++#define PWR_CV_MSK_D BIT(3) ++#define PWR_CV_MSK_E BIT(4) ++#define PWR_CV_MSK_F BIT(5) ++#define PWR_CV_MSK_G BIT(6) ++#define PWR_CV_MSK_TEST BIT(7) ++#define PWR_CV_MSK_ALL 0xFF ++ ++#define PWR_DELAY_US 0 ++#define PWR_DELAY_MS 1 ++ ++/* STA scheduler */ ++#define SS_MACID_SH 8 ++#define SS_TX_LEN_MSK 0x1FFFFF ++#define SS_CTRL1_R_TX_LEN 5 ++#define SS_CTRL1_R_NEXT_LINK 20 ++#define SS_LINK_SIZE 256 ++ ++/* MAC debug port */ ++#define TMAC_DBG_SEL_C0 0xA5 ++#define RMAC_DBG_SEL_C0 0xA6 ++#define TRXPTCL_DBG_SEL_C0 0xA7 ++#define TMAC_DBG_SEL_C1 0xB5 ++#define RMAC_DBG_SEL_C1 0xB6 ++#define TRXPTCL_DBG_SEL_C1 0xB7 ++#define FW_PROG_CNTR_DBG_SEL 0xF2 ++#define PCIE_TXDMA_DBG_SEL 0x30 ++#define PCIE_RXDMA_DBG_SEL 0x31 ++#define PCIE_CVT_DBG_SEL 0x32 ++#define PCIE_CXPL_DBG_SEL 0x33 ++#define PCIE_IO_DBG_SEL 0x37 ++#define PCIE_MISC_DBG_SEL 0x38 ++#define PCIE_MISC2_DBG_SEL 0x00 ++#define MAC_DBG_SEL 1 ++#define RMAC_CMAC_DBG_SEL 1 ++ ++/* TRXPTCL dbg port sel */ ++#define TRXPTRL_DBG_SEL_TMAC 0 ++#define TRXPTRL_DBG_SEL_RMAC 1 ++ ++struct rtw89_cpuio_ctrl { ++ u16 pkt_num; ++ u16 start_pktid; ++ u16 end_pktid; ++ u8 cmd_type; ++ u8 macid; ++ u8 src_pid; ++ u8 src_qid; ++ u8 dst_pid; ++ u8 dst_qid; ++ u16 pktid; ++}; ++ ++struct rtw89_mac_dbg_port_info { ++ u32 sel_addr; ++ u8 sel_byte; ++ u32 sel_msk; ++ u32 srt; ++ u32 end; ++ u32 rd_addr; ++ u8 rd_byte; ++ u32 rd_msk; ++}; ++ ++#define QLNKTBL_ADDR_INFO_SEL BIT(0) ++#define QLNKTBL_ADDR_INFO_SEL_0 0 ++#define QLNKTBL_ADDR_INFO_SEL_1 1 ++#define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) ++#define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) ++ ++struct rtw89_mac_dle_dfi_ctrl { ++ enum rtw89_mac_dle_ctrl_type type; ++ u32 target; ++ u32 addr; ++ u32 out_data; ++}; ++ ++struct rtw89_mac_dle_dfi_quota { ++ enum rtw89_mac_dle_ctrl_type dle_type; ++ u32 qtaid; ++ u16 rsv_pgnum; ++ u16 use_pgnum; ++}; ++ ++struct rtw89_mac_dle_dfi_qempty { ++ enum rtw89_mac_dle_ctrl_type dle_type; ++ u32 grpsel; ++ u32 qempty; ++}; ++ ++/* Define DBG and recovery enum */ ++enum mac_ax_err_info { ++ /* Get error info */ ++ ++ /* L0 */ ++ MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, ++ MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, ++ MAC_AX_ERR_L0_RESET_DONE = 0x0003, ++ MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, ++ ++ /* L1 */ ++ MAC_AX_ERR_L1_ERR_DMAC = 0x1000, ++ MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, ++ MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, ++ MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, ++ MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, ++ ++ /* L2 */ ++ /* address hole (master) */ ++ MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, ++ MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, ++ MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, ++ MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, ++ MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, ++ MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, ++ MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, ++ MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, ++ ++ /* AHB bridge timeout (master) */ ++ MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, ++ MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, ++ MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, ++ MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, ++ MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, ++ MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, ++ MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, ++ MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, ++ ++ /* APB_SA bridge timeout (master + slave) */ ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, ++ ++ /* APB_BBRF bridge timeout (master) */ ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, ++ MAC_AX_ERR_L2_RESET_DONE = 0x2400, ++ MAC_AX_ERR_CPU_EXCEPTION = 0x3000, ++ MAC_AX_GET_ERR_MAX, ++ MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, ++ ++ /* set error info */ ++ MAC_AX_ERR_L1_DISABLE_EN = 0x0001, ++ MAC_AX_ERR_L1_RCVY_EN = 0x0002, ++ MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, ++ MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, ++ MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, ++ MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, ++ MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, ++ MAC_AX_ERR_L0_RCVY_EN = 0x0013, ++ MAC_AX_SET_ERR_MAX, ++}; ++ ++extern struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie; ++extern struct rtw89_dle_size wde_size0; ++extern struct rtw89_dle_size wde_size4; ++extern struct rtw89_dle_size ple_size0; ++extern struct rtw89_dle_size ple_size4; ++extern struct rtw89_wde_quota wde_qt0; ++extern struct rtw89_wde_quota wde_qt4; ++extern struct rtw89_ple_quota ple_qt4; ++extern struct rtw89_ple_quota ple_qt5; ++extern struct rtw89_ple_quota ple_qt13; ++ ++static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) ++{ ++ return band == 0 ? reg_base : (reg_base + 0x2000); ++} ++ ++static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) ++{ ++ return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); ++} ++ ++static inline u32 ++rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ return rtw89_read32_mask(rtwdev, reg, mask); ++} ++ ++static inline void ++rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, ++ u32 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32(rtwdev, reg, data); ++} ++ ++static inline void ++rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask, u32 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_mask(rtwdev, reg, mask, data); ++} ++ ++static inline void ++rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask, u16 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write16_mask(rtwdev, reg, mask, data); ++} ++ ++static inline void ++rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_clr(rtwdev, reg, bit); ++} ++ ++static inline void ++rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u16 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write16_clr(rtwdev, reg, bit); ++} ++ ++static inline void ++rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_set(rtwdev, reg, bit); ++} ++ ++void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); ++int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); ++int rtw89_mac_init(struct rtw89_dev *rtwdev); ++int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, ++ enum rtw89_mac_hwmod_sel sel); ++int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); ++int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); ++int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); ++void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); ++u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); ++int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); ++void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); ++int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 *tx_en, enum rtw89_sch_tx_sel sel); ++int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en); ++int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); ++void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); ++void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); ++int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); ++int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, ++ const struct rtw89_mac_ax_coex_gnt *gnt_cfg); ++int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); ++void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); ++u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); ++bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); ++int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); ++bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *cr); ++void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); ++void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf); ++void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool disconnect); ++void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); ++int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en); ++ ++static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) ++ return; ++ ++ _rtw89_mac_bf_monitor_track(rtwdev); ++} ++ ++static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ *val = rtw89_read32(rtwdev, cr); ++ return 0; ++} ++ ++static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ rtw89_write32(rtwdev, cr, val); ++ return 0; ++} ++ ++static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 mask, u32 val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ rtw89_write32_mask(rtwdev, cr, mask, val); ++ return 0; ++} ++ ++int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ bool resume, u32 tx_time); ++int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 *tx_time); ++int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, ++ bool resume, u8 tx_retry); ++int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, u8 *tx_retry); ++ ++#endif + +From patchwork Fri Aug 20 04:35:22 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448373 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 52712C4320E + for ; + Fri, 20 Aug 2021 04:37:04 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 3A39F60F91 + for ; + Fri, 20 Aug 2021 04:37:04 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S232406AbhHTEhk (ORCPT + ); + Fri, 20 Aug 2021 00:37:40 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39245 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233581AbhHTEhj (ORCPT + ); + Fri, 20 Aug 2021 00:37:39 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4awafF003983, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4awafF003983 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:36:58 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:36:58 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:36:57 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 08/24] rtw89: implement mac80211 ops +Date: Fri, 20 Aug 2021 12:35:22 +0800 +Message-ID: <20210820043538.12424-9-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_all_Bitcoin, bb} +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Implement ops to interactive with mac80211. The ops contain start/stop, +TX, add/remove vif, config, sta state, key, ampdu action, +sw_scan_start/complete, and so on. To avoid racing between ieee80211 +delayed work and ioctl, all of them are protected by rtwdev->mutex. +To yield better TX performance, wake TX queue is implemented. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/mac80211.c | 673 ++++++++++++++++++ + 1 file changed, 673 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/mac80211.c + +diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c +new file mode 100644 +index 000000000000..9149ae8798d1 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -0,0 +1,673 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++#include "ser.h" ++ ++static void rtw89_ops_tx(struct ieee80211_hw *hw, ++ struct ieee80211_tx_control *control, ++ struct sk_buff *skb) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_vif *vif = info->control.vif; ++ struct ieee80211_sta *sta = control->sta; ++ int ret, qsel; ++ ++ ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb: %d\n", ret); ++ ieee80211_free_txskb(hw, skb); ++ } ++ rtw89_core_tx_kick_off(rtwdev, qsel); ++} ++ ++static void rtw89_ops_wake_tx_queue(struct ieee80211_hw *hw, ++ struct ieee80211_txq *txq) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ ieee80211_schedule_txq(hw, txq); ++ queue_work(rtwdev->txq_wq, &rtwdev->txq_work); ++} ++ ++static int rtw89_ops_start(struct ieee80211_hw *hw) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret; ++ ++ mutex_lock(&rtwdev->mutex); ++ ret = rtw89_core_start(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static void rtw89_ops_stop(struct ieee80211_hw *hw) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_core_stop(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static int rtw89_ops_config(struct ieee80211_hw *hw, u32 changed) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if ((changed & IEEE80211_CONF_CHANGE_IDLE) && ++ !(hw->conf.flags & IEEE80211_CONF_IDLE)) ++ rtw89_leave_ips(rtwdev); ++ ++ if (changed & IEEE80211_CONF_CHANGE_PS) { ++ if (hw->conf.flags & IEEE80211_CONF_PS) { ++ rtwdev->lps_enabled = true; ++ } else { ++ rtw89_leave_lps(rtwdev); ++ rtwdev->lps_enabled = false; ++ } ++ } ++ ++ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) ++ rtw89_set_channel(rtwdev); ++ ++ if ((changed & IEEE80211_CONF_CHANGE_IDLE) && ++ (hw->conf.flags & IEEE80211_CONF_IDLE)) ++ rtw89_enter_ips(rtwdev); ++ ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static int rtw89_ops_add_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ list_add_tail(&rtwvif->list, &rtwdev->rtwvifs_list); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ rtw89_traffic_stats_init(rtwdev, &rtwvif->stats); ++ rtw89_vif_type_mapping(vif, false); ++ rtwvif->port = rtw89_core_acquire_bit_map(rtwdev->hw_port, ++ RTW89_MAX_HW_PORT_NUM); ++ if (rtwvif->port == RTW89_MAX_HW_PORT_NUM) { ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ rtwvif->bcn_hit_cond = 0; ++ rtwvif->mac_idx = RTW89_MAC_0; ++ rtwvif->phy_idx = RTW89_PHY_0; ++ rtwvif->hit_rule = 0; ++ ether_addr_copy(rtwvif->mac_addr, vif->addr); ++ ++ ret = rtw89_mac_add_vif(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ goto out; ++ } ++ ++ rtw89_core_txq_init(rtwdev, vif->txq); ++ ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, NULL, BTC_ROLE_START); ++out: ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static void rtw89_ops_remove_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, NULL, BTC_ROLE_STOP); ++ rtw89_mac_remove_vif(rtwdev, rtwvif); ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ list_del_init(&rtwvif->list); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_configure_filter(struct ieee80211_hw *hw, ++ unsigned int changed_flags, ++ unsigned int *new_flags, ++ u64 multicast) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ *new_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_FCSFAIL | ++ FIF_BCN_PRBRESP_PROMISC; ++ ++ if (changed_flags & FIF_ALLMULTI) { ++ if (*new_flags & FIF_ALLMULTI) ++ rtwdev->hal.rx_fltr &= ~B_AX_A_MC; ++ else ++ rtwdev->hal.rx_fltr |= B_AX_A_MC; ++ } ++ if (changed_flags & FIF_FCSFAIL) { ++ if (*new_flags & FIF_FCSFAIL) ++ rtwdev->hal.rx_fltr |= B_AX_A_CRC32_ERR; ++ else ++ rtwdev->hal.rx_fltr &= ~B_AX_A_CRC32_ERR; ++ } ++ if (changed_flags & FIF_OTHER_BSS) { ++ if (*new_flags & FIF_OTHER_BSS) ++ rtwdev->hal.rx_fltr &= ~B_AX_A_A1_MATCH; ++ else ++ rtwdev->hal.rx_fltr |= B_AX_A_A1_MATCH; ++ } ++ if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { ++ if (*new_flags & FIF_BCN_PRBRESP_PROMISC) { ++ rtwdev->hal.rx_fltr &= ~B_AX_A_BCN_CHK_EN; ++ rtwdev->hal.rx_fltr &= ~B_AX_A_BC; ++ rtwdev->hal.rx_fltr &= ~B_AX_A_A1_MATCH; ++ } else { ++ rtwdev->hal.rx_fltr |= B_AX_A_BCN_CHK_EN; ++ rtwdev->hal.rx_fltr |= B_AX_A_BC; ++ rtwdev->hal.rx_fltr |= B_AX_A_A1_MATCH; ++ } ++ } ++ ++ rtw89_write32_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), ++ B_AX_RX_FLTR_CFG_MASK, ++ rtwdev->hal.rx_fltr); ++ if (!rtwdev->dbcc_en) ++ goto out; ++ rtw89_write32_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_1), ++ B_AX_RX_FLTR_CFG_MASK, ++ rtwdev->hal.rx_fltr); ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static const u8 ac_to_fw_idx[IEEE80211_NUM_ACS] = { ++ [IEEE80211_AC_VO] = 3, ++ [IEEE80211_AC_VI] = 2, ++ [IEEE80211_AC_BE] = 0, ++ [IEEE80211_AC_BK] = 1, ++}; ++ ++static u8 rtw89_aifsn_to_aifs(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u8 aifsn) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ u8 slot_time; ++ u8 sifs; ++ ++ slot_time = vif->bss_conf.use_short_slot ? 9 : 20; ++ sifs = rtwdev->hal.current_band_type == RTW89_BAND_5G ? 16 : 10; ++ ++ return aifsn * slot_time + sifs; ++} ++ ++static void ____rtw89_conf_tx_edca(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ struct ieee80211_tx_queue_params *params = &rtwvif->tx_params[ac]; ++ u32 val; ++ u8 ecw_max, ecw_min; ++ u8 aifs; ++ ++ /* 2^ecw - 1 = cw; ecw = log2(cw + 1) */ ++ ecw_max = ilog2(params->cw_max + 1); ++ ecw_min = ilog2(params->cw_min + 1); ++ aifs = rtw89_aifsn_to_aifs(rtwdev, rtwvif, params->aifs); ++ val = FIELD_PREP(FW_EDCA_PARAM_TXOPLMT_MSK, params->txop) | ++ FIELD_PREP(FW_EDCA_PARAM_CWMAX_MSK, ecw_max) | ++ FIELD_PREP(FW_EDCA_PARAM_CWMIN_MSK, ecw_min) | ++ FIELD_PREP(FW_EDCA_PARAM_AIFS_MSK, aifs); ++ rtw89_fw_h2c_set_edca(rtwdev, rtwvif, ac_to_fw_idx[ac], val); ++} ++ ++static const u32 ac_to_mu_edca_param[IEEE80211_NUM_ACS] = { ++ [IEEE80211_AC_VO] = R_AX_MUEDCA_VO_PARAM_0, ++ [IEEE80211_AC_VI] = R_AX_MUEDCA_VI_PARAM_0, ++ [IEEE80211_AC_BE] = R_AX_MUEDCA_BE_PARAM_0, ++ [IEEE80211_AC_BK] = R_AX_MUEDCA_BK_PARAM_0, ++}; ++ ++static void ____rtw89_conf_tx_mu_edca(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ struct ieee80211_tx_queue_params *params = &rtwvif->tx_params[ac]; ++ struct ieee80211_he_mu_edca_param_ac_rec *mu_edca; ++ u8 aifs, aifsn; ++ u16 timer_32us; ++ u32 reg; ++ u32 val; ++ ++ if (!params->mu_edca) ++ return; ++ ++ mu_edca = ¶ms->mu_edca_param_rec; ++ aifsn = FIELD_GET(GENMASK(3, 0), mu_edca->aifsn); ++ aifs = aifsn ? rtw89_aifsn_to_aifs(rtwdev, rtwvif, aifsn) : 0; ++ timer_32us = mu_edca->mu_edca_timer << 8; ++ ++ val = FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK, timer_32us) | ++ FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_CW_MASK, mu_edca->ecw_min_max) | ++ FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK, aifs); ++ reg = rtw89_mac_reg_by_idx(ac_to_mu_edca_param[ac], rtwvif->mac_idx); ++ rtw89_write32(rtwdev, reg, val); ++ ++ rtw89_mac_set_hw_muedca_ctrl(rtwdev, rtwvif, true); ++} ++ ++static void __rtw89_conf_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ ____rtw89_conf_tx_edca(rtwdev, rtwvif, ac); ++ ____rtw89_conf_tx_mu_edca(rtwdev, rtwvif, ac); ++} ++ ++static void rtw89_conf_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u16 ac; ++ ++ for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) ++ __rtw89_conf_tx(rtwdev, rtwvif, ac); ++} ++ ++static void rtw89_station_mode_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf) ++{ ++ struct ieee80211_sta *sta; ++ ++ if (vif->type != NL80211_IFTYPE_STATION) ++ return; ++ ++ sta = ieee80211_find_sta(vif, conf->bssid); ++ if (!sta) { ++ rtw89_err(rtwdev, "can't find sta to set sta_assoc state\n"); ++ return; ++ } ++ rtw89_core_sta_assoc(rtwdev, vif, sta); ++} ++ ++static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf, ++ u32 changed) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if (changed & BSS_CHANGED_ASSOC) { ++ if (conf->assoc) { ++ rtw89_station_mode_sta_assoc(rtwdev, vif, conf); ++ rtw89_phy_set_bss_color(rtwdev, vif); ++ rtw89_chip_cfg_txpwr_ul_tb_offset(rtwdev, vif); ++ rtw89_mac_port_update(rtwdev, rtwvif); ++ } ++ } ++ ++ if (changed & BSS_CHANGED_BSSID) { ++ ether_addr_copy(rtwvif->bssid, conf->bssid); ++ rtw89_cam_bssid_changed(rtwdev, rtwvif); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ } ++ ++ if (changed & BSS_CHANGED_ERP_SLOT) ++ rtw89_conf_tx(rtwdev, rtwvif); ++ ++ if (changed & BSS_CHANGED_HE_BSS_COLOR) ++ rtw89_phy_set_bss_color(rtwdev, vif); ++ ++ if (changed & BSS_CHANGED_MU_GROUPS) ++ rtw89_mac_bf_set_gid_table(rtwdev, vif, conf); ++ ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static int rtw89_ops_conf_tx(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, u16 ac, ++ const struct ieee80211_tx_queue_params *params) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtwvif->tx_params[ac] = *params; ++ __rtw89_conf_tx(rtwdev, rtwvif, ac); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static int __rtw89_ops_sta_state(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ enum ieee80211_sta_state old_state, ++ enum ieee80211_sta_state new_state) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ if (old_state == IEEE80211_STA_NOTEXIST && ++ new_state == IEEE80211_STA_NONE) ++ return rtw89_core_sta_add(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_AUTH && ++ new_state == IEEE80211_STA_ASSOC) { ++ if (vif->type == NL80211_IFTYPE_STATION) ++ return 0; /* defer to bss_info_changed to have vif info */ ++ return rtw89_core_sta_assoc(rtwdev, vif, sta); ++ } ++ ++ if (old_state == IEEE80211_STA_ASSOC && ++ new_state == IEEE80211_STA_AUTH) ++ return rtw89_core_sta_disassoc(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_AUTH && ++ new_state == IEEE80211_STA_NONE) ++ return rtw89_core_sta_disconnect(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_NONE && ++ new_state == IEEE80211_STA_NOTEXIST) ++ return rtw89_core_sta_remove(rtwdev, vif, sta); ++ ++ return 0; ++} ++ ++static int rtw89_ops_sta_state(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ enum ieee80211_sta_state old_state, ++ enum ieee80211_sta_state new_state) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ret = __rtw89_ops_sta_state(hw, vif, sta, old_state, new_state); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static int rtw89_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ switch (cmd) { ++ case SET_KEY: ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_EAPOL_END); ++ ret = rtw89_cam_sec_key_add(rtwdev, vif, sta, key); ++ if (ret && ret != -EOPNOTSUPP) { ++ rtw89_err(rtwdev, "failed to add key to sec cam\n"); ++ goto out; ++ } ++ break; ++ case DISABLE_KEY: ++ rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, ++ false); ++ rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, false); ++ ret = rtw89_cam_sec_key_del(rtwdev, vif, sta, key, true); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to remove key from sec cam\n"); ++ goto out; ++ } ++ break; ++ } ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static int rtw89_ops_ampdu_action(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_ampdu_params *params) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct ieee80211_sta *sta = params->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ u16 tid = params->tid; ++ struct ieee80211_txq *txq = sta->txq[tid]; ++ struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ ++ switch (params->action) { ++ case IEEE80211_AMPDU_TX_START: ++ return IEEE80211_AMPDU_TX_START_IMMEDIATE; ++ case IEEE80211_AMPDU_TX_STOP_CONT: ++ case IEEE80211_AMPDU_TX_STOP_FLUSH: ++ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: ++ mutex_lock(&rtwdev->mutex); ++ clear_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags); ++ rtw89_fw_h2c_ba_cam(rtwdev, false, rtwsta->mac_id, params); ++ mutex_unlock(&rtwdev->mutex); ++ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); ++ break; ++ case IEEE80211_AMPDU_TX_OPERATIONAL: ++ mutex_lock(&rtwdev->mutex); ++ set_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags); ++ rtwsta->ampdu_params[tid].agg_num = params->buf_size; ++ rtwsta->ampdu_params[tid].amsdu = params->amsdu; ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_fw_h2c_ba_cam(rtwdev, true, rtwsta->mac_id, params); ++ mutex_unlock(&rtwdev->mutex); ++ break; ++ case IEEE80211_AMPDU_RX_START: ++ case IEEE80211_AMPDU_RX_STOP: ++ break; ++ default: ++ WARN_ON(1); ++ return -ENOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ if (test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static void rtw89_ops_sta_statistics(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct station_info *sinfo) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ sinfo->txrate = rtwsta->ra_report.txrate; ++ sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); ++} ++ ++static void rtw89_ops_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ u32 queues, bool drop) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_lps(rtwdev); ++ rtw89_hci_flush_queues(rtwdev, queues, drop); ++ rtw89_mac_flush_txq(rtwdev, queues, drop); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++struct rtw89_iter_bitrate_mask_data { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_vif *vif; ++ const struct cfg80211_bitrate_mask *mask; ++}; ++ ++static void rtw89_ra_mask_info_update_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_iter_bitrate_mask_data *br_data = data; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); ++ ++ if (vif != br_data->vif) ++ return; ++ ++ rtwsta->use_cfg_mask = true; ++ rtwsta->mask = *br_data->mask; ++ rtw89_phy_ra_updata_sta(br_data->rtwdev, sta); ++} ++ ++static void rtw89_ra_mask_info_update(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ struct rtw89_iter_bitrate_mask_data br_data = { .rtwdev = rtwdev, ++ .vif = vif, ++ .mask = mask}; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_ra_mask_info_update_iter, ++ &br_data); ++} ++ ++static int rtw89_ops_set_bitrate_mask(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_ra_mask_info_update(rtwdev, vif, mask); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ++int rtw89_ops_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ if (rx_ant != hw->wiphy->available_antennas_rx) ++ return -EINVAL; ++ ++ mutex_lock(&rtwdev->mutex); ++ hal->antenna_tx = tx_ant; ++ hal->antenna_rx = rx_ant; ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ++int rtw89_ops_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ *tx_ant = hal->antenna_tx; ++ *rx_ant = hal->antenna_rx; ++ ++ return 0; ++} ++ ++static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ const u8 *mac_addr) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtwdev->scanning = true; ++ rtw89_leave_lps(rtwdev); ++ rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, hal->current_band_type); ++ rtw89_hci_recalc_int_mit(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_sw_scan_complete(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); ++ rtwdev->scanning = false; ++ rtwdev->dig.bypass_dig = true; ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_reconfig_complete(struct ieee80211_hw *hw, ++ enum ieee80211_reconfig_type reconfig_type) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ if (reconfig_type == IEEE80211_RECONFIG_TYPE_RESTART) ++ rtw89_ser_recfg_done(rtwdev); ++} ++ ++const struct ieee80211_ops rtw89_ops = { ++ .tx = rtw89_ops_tx, ++ .wake_tx_queue = rtw89_ops_wake_tx_queue, ++ .start = rtw89_ops_start, ++ .stop = rtw89_ops_stop, ++ .config = rtw89_ops_config, ++ .add_interface = rtw89_ops_add_interface, ++ .remove_interface = rtw89_ops_remove_interface, ++ .configure_filter = rtw89_ops_configure_filter, ++ .bss_info_changed = rtw89_ops_bss_info_changed, ++ .conf_tx = rtw89_ops_conf_tx, ++ .sta_state = rtw89_ops_sta_state, ++ .set_key = rtw89_ops_set_key, ++ .ampdu_action = rtw89_ops_ampdu_action, ++ .set_rts_threshold = rtw89_ops_set_rts_threshold, ++ .sta_statistics = rtw89_ops_sta_statistics, ++ .flush = rtw89_ops_flush, ++ .set_bitrate_mask = rtw89_ops_set_bitrate_mask, ++ .set_antenna = rtw89_ops_set_antenna, ++ .get_antenna = rtw89_ops_get_antenna, ++ .sw_scan_start = rtw89_ops_sw_scan_start, ++ .sw_scan_complete = rtw89_ops_sw_scan_complete, ++ .reconfig_complete = rtw89_ops_reconfig_complete, ++ .set_sar_specs = rtw89_ops_set_sar_specs, ++}; ++EXPORT_SYMBOL(rtw89_ops); + +From patchwork Fri Aug 20 04:35:23 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448377 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 90902C4338F + for ; + Fri, 20 Aug 2021 04:37:11 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 61FDD60F91 + for ; + Fri, 20 Aug 2021 04:37:11 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S234628AbhHTEhr (ORCPT + ); + Fri, 20 Aug 2021 00:37:47 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39248 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232629AbhHTEho (ORCPT + ); + Fri, 20 Aug 2021 00:37:44 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4b2heD004000, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4b2heD004000 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:02 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:01 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:01 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 09/24] rtw89: add pci files +Date: Fri, 20 Aug 2021 12:35:23 +0800 +Message-ID: <20210820043538.12424-10-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +DMA data to/from device via TX/RX rings. There are totally 13 TX rings -- +8 AC rings, 2 MGMT rings, 2 HI rings and one FW CMD ring. There are +totally 2 RX rings -- one is RX ring, and the other is report ring. + +FW CMD TX ring is a special TX ring that is used to download firmware or +send H2C to firmware. The other TX rings are used to send normal data(skb), +and if the skb is sent, RX report ring will receive a report that tells +driver to free the skb. Normal RX packets, C2H and PPDU status are +received by RX rings accordingly. + +One TX ring contains TX BD and TX WD. Both are allocated by +dma_alloc_coherent(), but their size can be different (#TX_BD <= #TX_WD). +When a skb is going to send, use a tx_req to hold skb and corresponding +description data, and then fill the request data to a free TX BD and a +free TX WD, finally kick off the TX BD. When TX BD DMA is done, read index +of register is increasing, and then TX BD can be freed, but free WD and skb +until report is received. + +Since CMD TX ring doesn't send normal data, it doesn't need to wait for +sending data in air. Therefore, TX BD, TX WD and cmd skb can be freed, when +read index of register is increasing. + +One entry of RX ring contains a RX BD and a skb. The skb is used to store +RX WD and frame. RX BD is allocated by dma_alloc_coherent(), and fill RX +size and point RX DMA address to skb->data. If size of RX packet exceeds +filled RX size, the packet will be divided into multiple RX BD with FS and +LS bit. + +TX BD OK interrupt for normal AC ring is masked out, because it causes +frequent context switch. We defer to reclaim it until report is received. +The exception is FW CMD ring that doesn't wait for report, so we reclaim +it in interrupt. + +With wake TX queue, we submit a bunch of TX skb in one go, and then kick +off DMA by writing write index of TX BD after the TX BD/WD/skb are filled. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/pci.c | 3060 ++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/pci.h | 616 +++++ + 2 files changed, 3676 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/pci.c + create mode 100644 drivers/net/wireless/realtek/rtw89/pci.h + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +new file mode 100644 +index 000000000000..d5a033cf93cc +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -0,0 +1,3060 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#include ++ ++#include "mac.h" ++#include "pci.h" ++#include "reg.h" ++#include "ser.h" ++ ++static bool rtw89_pci_disable_clkreq; ++static bool rtw89_pci_disable_aspm_l1; ++static bool rtw89_pci_disable_l1ss; ++module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); ++module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); ++module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); ++MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); ++MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); ++MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); ++ ++static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ int ret; ++ ++ rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, ++ rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), ++ 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, ++ rtwdev, R_AX_PCIE_INIT_CFG1); ++ ++ if (ret) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_dma_ring *bd_ring, ++ u32 cur_idx, bool tx) ++{ ++ u32 cnt, cur_rp, wp, rp, len; ++ ++ rp = bd_ring->rp; ++ wp = bd_ring->wp; ++ len = bd_ring->len; ++ ++ cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); ++ if (tx) ++ cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); ++ else ++ cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); ++ ++ bd_ring->rp = cur_rp; ++ ++ return cnt; ++} ++ ++static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 addr_idx = bd_ring->addr_idx; ++ u32 cnt, idx; ++ ++ idx = rtw89_read32(rtwdev, addr_idx); ++ cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); ++ ++ return cnt; ++} ++ ++static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, ++ u32 cnt, bool release_all) ++{ ++ struct rtw89_pci_tx_data *tx_data; ++ struct sk_buff *skb; ++ u32 qlen; ++ ++ while (cnt--) { ++ skb = skb_dequeue(&rtwpci->h2c_queue); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); ++ return; ++ } ++ skb_queue_tail(&rtwpci->h2c_release_queue, skb); ++ } ++ ++ qlen = skb_queue_len(&rtwpci->h2c_release_queue); ++ if (!release_all) ++ qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; ++ ++ while (qlen--) { ++ skb = skb_dequeue(&rtwpci->h2c_release_queue); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to release fwcmd\n"); ++ return; ++ } ++ tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, ++ DMA_TO_DEVICE); ++ dev_kfree_skb_any(skb); ++ } ++} ++ ++static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; ++ u32 cnt; ++ ++ cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); ++ if (!cnt) ++ return; ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); ++} ++ ++static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 addr_idx = bd_ring->addr_idx; ++ u32 cnt, idx; ++ ++ idx = rtw89_read32(rtwdev, addr_idx); ++ cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); ++ ++ return cnt; ++} ++ ++static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ dma_addr_t dma; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ ++static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ dma_addr_t dma; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ ++static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rxbd_info *rxbd_info; ++ struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ ++ rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; ++ rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS); ++ rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS); ++ rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE); ++ rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG); ++ ++ return 0; ++} ++ ++static bool ++rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, ++ struct sk_buff *new, ++ const struct sk_buff *skb, u32 offset, ++ const struct rtw89_pci_rx_info *rx_info, ++ const struct rtw89_rx_desc_info *desc_info) ++{ ++ u32 copy_len = rx_info->len - offset; ++ ++ if (unlikely(skb_tailroom(new) < copy_len)) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", ++ rx_info->len, desc_info->pkt_size, offset, fs, ls); ++ rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", ++ skb->data, rx_info->len); ++ /* length of a single segment skb is desc_info->pkt_size */ ++ if (fs && ls) { ++ copy_len = desc_info->pkt_size; ++ } else { ++ rtw89_info(rtwdev, "drop rx data due to invalid length\n"); ++ return false; ++ } ++ } ++ ++ skb_put_data(new, skb->data + offset, copy_len); ++ ++ return true; ++} ++ ++static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc; ++ struct sk_buff *new = rx_ring->diliver_skb; ++ struct sk_buff *skb; ++ u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); ++ u32 offset; ++ u32 cnt = 1; ++ bool fs, ls; ++ int ret; ++ ++ skb = rx_ring->buf[bd_ring->wp]; ++ rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ++ ++ ret = rtw89_pci_rxbd_info_update(rtwdev, skb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", ++ bd_ring->wp, ret); ++ goto err_sync_device; ++ } ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ fs = rx_info->fs; ++ ls = rx_info->ls; ++ ++ if (fs) { ++ if (new) { ++ rtw89_err(rtwdev, "skb should not be ready before first segment start\n"); ++ goto err_sync_device; ++ } ++ if (desc_info->ready) { ++ rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); ++ goto err_sync_device; ++ } ++ ++ rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); ++ ++ new = dev_alloc_skb(desc_info->pkt_size); ++ if (!new) ++ goto err_sync_device; ++ ++ rx_ring->diliver_skb = new; ++ ++ /* first segment has RX desc */ ++ offset = desc_info->offset; ++ offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : ++ sizeof(struct rtw89_rxdesc_short); ++ } else { ++ offset = sizeof(struct rtw89_pci_rxbd_info); ++ if (!new) { ++ rtw89_warn(rtwdev, "no last skb\n"); ++ goto err_sync_device; ++ } ++ } ++ if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) ++ goto err_sync_device; ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++ ++ if (!desc_info->ready) { ++ rtw89_warn(rtwdev, "no rx desc information\n"); ++ goto err_free_resource; ++ } ++ if (ls) { ++ rtw89_core_rx(rtwdev, desc_info, new); ++ rx_ring->diliver_skb = NULL; ++ desc_info->ready = false; ++ } ++ ++ return cnt; ++ ++err_sync_device: ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++err_free_resource: ++ if (new) ++ dev_kfree_skb_any(new); ++ rx_ring->diliver_skb = NULL; ++ desc_info->ready = false; ++ ++ return cnt; ++} ++ ++static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 rx_cnt; ++ ++ while (cnt && rtwdev->napi_budget_countdown > 0) { ++ rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); ++ if (!rx_cnt) { ++ rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); ++ ++ /* skip the rest RXBD bufs */ ++ rtw89_pci_rxbd_increase(rx_ring, cnt); ++ break; ++ } ++ ++ cnt -= rx_cnt; ++ } ++ ++ rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); ++} ++ ++static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, int budget) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ int countdown = rtwdev->napi_budget_countdown; ++ u32 cnt; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; ++ ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (!cnt) ++ return 0; ++ ++ cnt = min_t(u32, budget, cnt); ++ ++ rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); ++ ++ /* In case of flushing pending SKBs, the countdown may exceed. */ ++ if (rtwdev->napi_budget_countdown <= 0) ++ return budget; ++ ++ return budget - countdown; ++} ++ ++static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct sk_buff *skb, u8 tx_status) ++{ ++ struct ieee80211_tx_info *info; ++ ++ info = IEEE80211_SKB_CB(skb); ++ ieee80211_tx_info_clear_status(info); ++ ++ if (info->flags & IEEE80211_TX_CTL_NO_ACK) ++ info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; ++ if (tx_status == RTW89_TX_DONE) { ++ info->flags |= IEEE80211_TX_STAT_ACK; ++ tx_ring->tx_acked++; ++ } else { ++ if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "failed to TX of status %x\n", tx_status); ++ switch (tx_status) { ++ case RTW89_TX_RETRY_LIMIT: ++ tx_ring->tx_retry_lmt++; ++ break; ++ case RTW89_TX_LIFE_TIME: ++ tx_ring->tx_life_time++; ++ break; ++ case RTW89_TX_MACID_DROP: ++ tx_ring->tx_mac_id_drop++; ++ break; ++ default: ++ rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); ++ break; ++ } ++ } ++ ++ ieee80211_tx_status_ni(rtwdev->hw, skb); ++} ++ ++static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd *txwd; ++ u32 cnt; ++ ++ cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); ++ while (cnt--) { ++ txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); ++ if (!txwd) { ++ rtw89_warn(rtwdev, "No busy txwd pages available\n"); ++ break; ++ } ++ ++ list_del_init(&txwd->list); ++ } ++} ++ ++static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ int i; ++ ++ for (i = 0; i < wd_ring->page_num; i++) { ++ txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); ++ if (!txwd) ++ break; ++ ++ list_del_init(&txwd->list); ++ } ++} ++ ++static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd, u16 seq, ++ u8 tx_status) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_data *tx_data; ++ struct sk_buff *skb, *tmp; ++ u8 txch = tx_ring->txch; ++ ++ if (!list_empty(&txwd->list)) { ++ rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", ++ txch, seq); ++ return; ++ } ++ ++ /* currently, support for only one frame */ ++ if (skb_queue_len(&txwd->queue) != 1) { ++ rtw89_warn(rtwdev, "empty pending queue %d page %d\n", ++ txch, seq); ++ return; ++ } ++ ++ skb_queue_walk_safe(&txwd->queue, skb, tmp) { ++ skb_unlink(skb, &txwd->queue); ++ ++ tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, ++ DMA_TO_DEVICE); ++ ++ rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); ++ } ++ ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++} ++ ++static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rpp_fmt *rpp) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_tx_wd_ring *wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ u16 seq; ++ u8 qsel, tx_status, txch; ++ ++ seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); ++ qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); ++ tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); ++ txch = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ if (txch == RTW89_TXCH_CH12) { ++ rtw89_warn(rtwdev, "should no fwcmd release report\n"); ++ return; ++ } ++ ++ tx_ring = &rtwpci->tx_rings[txch]; ++ rtw89_pci_reclaim_txbd(rtwdev, tx_ring); ++ wd_ring = &tx_ring->wd_ring; ++ txwd = &wd_ring->pages[seq]; ++ ++ rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); ++} ++ ++static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ int i; ++ ++ for (i = 0; i < wd_ring->page_num; i++) { ++ txwd = &wd_ring->pages[i]; ++ ++ if (!list_empty(&txwd->list)) ++ continue; ++ ++ rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); ++ } ++} ++ ++static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 max_cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_pci_rpp_fmt *rpp; ++ struct rtw89_rx_desc_info desc_info = {}; ++ struct sk_buff *skb; ++ u32 cnt = 0; ++ u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); ++ u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); ++ u32 offset; ++ int ret; ++ ++ skb = rx_ring->buf[bd_ring->wp]; ++ rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ++ ++ ret = rtw89_pci_rxbd_info_update(rtwdev, skb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", ++ bd_ring->wp, ret); ++ goto err_sync_device; ++ } ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ if (!rx_info->fs || !rx_info->ls) { ++ rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); ++ return cnt; ++ } ++ ++ rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); ++ ++ /* first segment has RX desc */ ++ offset = desc_info.offset; ++ offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : ++ sizeof(struct rtw89_rxdesc_short); ++ for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { ++ rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); ++ rtw89_pci_release_rpp(rtwdev, rpp); ++ } ++ ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++ cnt++; ++ ++ return cnt; ++ ++err_sync_device: ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ return 0; ++} ++ ++static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 release_cnt; ++ ++ while (cnt) { ++ release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); ++ if (!release_cnt) { ++ rtw89_err(rtwdev, "failed to release TX skbs\n"); ++ ++ /* skip the rest RXBD bufs */ ++ rtw89_pci_rxbd_increase(rx_ring, cnt); ++ break; ++ } ++ ++ cnt -= release_cnt; ++ } ++ ++ rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); ++} ++ ++static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, int budget) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 cnt; ++ int work_done; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (cnt == 0) ++ goto out_unlock; ++ ++ rtw89_pci_release_tx(rtwdev, rx_ring, cnt); ++ ++out_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ /* always release all RPQ */ ++ work_done = min_t(int, cnt, budget); ++ rtwdev->napi_budget_countdown -= work_done; ++ ++ return work_done; ++} ++ ++static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ struct rtw89_pci_dma_ring *bd_ring; ++ u32 reg_idx; ++ u16 hw_idx, hw_idx_next, host_idx; ++ int i; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ bd_ring = &rx_ring->bd_ring; ++ ++ reg_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); ++ hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); ++ host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); ++ hw_idx_next = (hw_idx + 1) % bd_ring->len; ++ ++ if (hw_idx_next == host_idx) ++ rtw89_warn(rtwdev, "%d RXD unavailable\n", i); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "%d RXD unavailable, idx=0x%08x, len=%d\n", ++ i, reg_idx, bd_ring->len); ++ } ++} ++ ++static void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, ++ struct rtw89_pci_isrs *isrs) ++{ ++ isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; ++ isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; ++ isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; ++ ++ rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); ++} ++ ++static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00) ++{ ++ /* write 1 clear */ ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00); ++} ++ ++static void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); ++} ++ ++static void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ rtw89_write32(rtwdev, R_AX_HIMR0, 0); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); ++} ++ ++static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) ++{ ++ struct rtw89_dev *rtwdev = dev; ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_isrs isrs; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtw89_pci_recognize_intrs(rtwdev, rtwpci, &isrs); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ if (unlikely(isrs.isrs[0] & B_AX_RDU_INT)) ++ rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); ++ ++ if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN)) ++ rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); ++ ++ if (likely(rtwpci->running)) { ++ local_bh_disable(); ++ napi_schedule(&rtwdev->napi); ++ local_bh_enable(); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) ++{ ++ struct rtw89_dev *rtwdev = dev; ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ irqreturn_t irqret = IRQ_WAKE_THREAD; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ ++ /* If interrupt event is on the road, it is still trigger interrupt ++ * even we have done pci_stop() to turn off IMR. ++ */ ++ if (unlikely(!rtwpci->running)) { ++ irqret = IRQ_HANDLED; ++ goto exit; ++ } ++ ++ rtw89_pci_disable_intr(rtwdev, rtwpci); ++exit: ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ return irqret; ++} ++ ++#define case_TXCHADDRS(txch) \ ++ case RTW89_TXCH_##txch: \ ++ *addr_num = R_AX_##txch##_TXBD_NUM; \ ++ *addr_idx = R_AX_##txch##_TXBD_IDX; \ ++ *addr_bdram = R_AX_##txch##_BDRAM_CTRL; \ ++ *addr_desa_l = R_AX_##txch##_TXBD_DESA_L; \ ++ *addr_desa_h = R_AX_##txch##_TXBD_DESA_H; \ ++ break ++ ++static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch, ++ u32 *addr_num, ++ u32 *addr_idx, ++ u32 *addr_bdram, ++ u32 *addr_desa_l, ++ u32 *addr_desa_h) ++{ ++ switch (txch) { ++ case_TXCHADDRS(ACH0); ++ case_TXCHADDRS(ACH1); ++ case_TXCHADDRS(ACH2); ++ case_TXCHADDRS(ACH3); ++ case_TXCHADDRS(ACH4); ++ case_TXCHADDRS(ACH5); ++ case_TXCHADDRS(ACH6); ++ case_TXCHADDRS(ACH7); ++ case_TXCHADDRS(CH8); ++ case_TXCHADDRS(CH9); ++ case_TXCHADDRS(CH10); ++ case_TXCHADDRS(CH11); ++ case_TXCHADDRS(CH12); ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#undef case_TXCHADDRS ++ ++#define case_RXCHADDRS(rxch) \ ++ case RTW89_RXCH_##rxch: \ ++ *addr_num = R_AX_##rxch##_RXBD_NUM; \ ++ *addr_idx = R_AX_##rxch##_RXBD_IDX; \ ++ *addr_desa_l = R_AX_##rxch##_RXBD_DESA_L; \ ++ *addr_desa_h = R_AX_##rxch##_RXBD_DESA_H; \ ++ break ++ ++static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch, ++ u32 *addr_num, ++ u32 *addr_idx, ++ u32 *addr_desa_l, ++ u32 *addr_desa_h) ++{ ++ switch (rxch) { ++ case_RXCHADDRS(RXQ); ++ case_RXCHADDRS(RPQ); ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#undef case_RXCHADDRS ++ ++static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; ++ ++ /* reserved 1 desc check ring is full or not */ ++ if (bd_ring->rp > bd_ring->wp) ++ return bd_ring->rp - bd_ring->wp - 1; ++ ++ return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; ++} ++ ++static ++u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; ++ u32 cnt; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); ++ cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ return cnt; ++} ++ ++static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, ++ u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ u32 bd_cnt, wd_cnt, min_cnt = 0; ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 cnt; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ wd_cnt = wd_ring->curr_num; ++ ++ if (wd_cnt == 0 || bd_cnt == 0) { ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (!cnt) ++ goto out_unlock; ++ rtw89_pci_release_tx(rtwdev, rx_ring, cnt); ++ } ++ ++ bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ wd_cnt = wd_ring->curr_num; ++ min_cnt = min(bd_cnt, wd_cnt); ++ if (min_cnt == 0) ++ rtw89_warn(rtwdev, "still no tx resource after reclaim\n"); ++ ++out_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ return min_cnt; ++} ++ ++static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, ++ u8 txch) ++{ ++ if (txch == RTW89_TXCH_CH12) ++ return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); ++ ++ return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); ++} ++ ++static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 host_idx, addr; ++ ++ addr = bd_ring->addr_idx; ++ host_idx = bd_ring->wp; ++ rtw89_write16(rtwdev, addr, host_idx); ++} ++ ++static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, ++ int n_txbd) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 host_idx, len; ++ ++ len = bd_ring->len; ++ host_idx = bd_ring->wp + n_txbd; ++ host_idx = host_idx < len ? host_idx : host_idx - len; ++ ++ bd_ring->wp = host_idx; ++} ++ ++static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ __rtw89_pci_tx_kick_off(rtwdev, tx_ring); ++ spin_unlock_bh(&rtwpci->trx_lock); ++} ++ ++static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 cur_idx, cur_rp; ++ u8 i; ++ ++ /* Because the time taked by the I/O is a bit dynamic, it's hard to ++ * define a reasonable fixed total timeout to use read_poll_timeout* ++ * helper. Instead, we can ensure a reasonable polling times, so we ++ * just use for loop with udelay here. ++ */ ++ for (i = 0; i < 60; i++) { ++ cur_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); ++ cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); ++ if (cur_rp == bd_ring->wp) ++ return; ++ ++ udelay(1); ++ } ++ ++ if (!drop) ++ rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); ++} ++ ++static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, ++ bool drop) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ /* It may be unnecessary to flush FWCMD queue. */ ++ if (i == RTW89_TXCH_CH12) ++ continue; ++ ++ if (txchs & BIT(i)) ++ __pci_flush_txch(rtwdev, i, drop); ++ } ++} ++ ++static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, ++ bool drop) ++{ ++ __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); ++} ++ ++static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_txwd_body *txwd_body; ++ struct rtw89_txwd_info *txwd_info; ++ struct rtw89_pci_tx_wp_info *txwp_info; ++ struct rtw89_pci_tx_addr_info_32 *txaddr_info; ++ struct pci_dev *pdev = rtwpci->pdev; ++ struct sk_buff *skb = tx_req->skb; ++ struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ bool en_wd_info = desc_info->en_wd_info; ++ u32 txwd_len; ++ u32 txwp_len; ++ u32 txaddr_info_len; ++ dma_addr_t dma; ++ int ret; ++ ++ rtw89_core_fill_txdesc(rtwdev, desc_info, txwd->vaddr); ++ ++ dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) { ++ rtw89_err(rtwdev, "failed to map skb dma data\n"); ++ ret = -EBUSY; ++ goto err; ++ } ++ ++ tx_data->dma = dma; ++ ++ txaddr_info_len = sizeof(*txaddr_info); ++ txwp_len = sizeof(*txwp_info); ++ txwd_len = sizeof(*txwd_body); ++ txwd_len += en_wd_info ? sizeof(*txwd_info) : 0; ++ ++ txwp_info = txwd->vaddr + txwd_len; ++ txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); ++ txwp_info->seq1 = 0; ++ txwp_info->seq2 = 0; ++ txwp_info->seq3 = 0; ++ ++ tx_ring->tx_cnt++; ++ txaddr_info = txwd->vaddr + txwd_len + txwp_len; ++ txaddr_info->length = cpu_to_le16(skb->len); ++ txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | ++ RTW89_PCI_ADDR_NUM(1)); ++ txaddr_info->dma = cpu_to_le32(dma); ++ ++ txwd->len = txwd_len + txwp_len + txaddr_info_len; ++ ++ skb_queue_tail(&txwd->queue, skb); ++ ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_bd_32 *txbd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_txwd_body *txwd_body; ++ struct pci_dev *pdev = rtwpci->pdev; ++ struct sk_buff *skb = tx_req->skb; ++ struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_addr_t dma; ++ ++ txwd_body = (struct rtw89_txwd_body *)skb_push(skb, sizeof(*txwd_body)); ++ memset(txwd_body, 0, sizeof(*txwd_body)); ++ rtw89_core_fill_txdesc(rtwdev, desc_info, txwd_body); ++ ++ dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) { ++ rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); ++ return -EBUSY; ++ } ++ ++ tx_data->dma = dma; ++ txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); ++ txbd->length = cpu_to_le16(skb->len); ++ txbd->dma = cpu_to_le32(tx_data->dma); ++ skb_queue_tail(&rtwpci->h2c_queue, skb); ++ ++ rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); ++ ++ return 0; ++} ++ ++static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_bd_32 *txbd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci_tx_wd *txwd; ++ int ret; ++ ++ /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD ++ * buffer with WD BODY only. So here we don't need to check the free ++ * pages of the wd ring. ++ */ ++ if (tx_ring->txch == RTW89_TXCH_CH12) ++ return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); ++ ++ txwd = rtw89_pci_dequeue_txwd(tx_ring); ++ if (!txwd) { ++ rtw89_err(rtwdev, "no available TXWD\n"); ++ ret = -ENOSPC; ++ goto err; ++ } ++ ++ ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); ++ goto err_enqueue_wd; ++ } ++ ++ list_add_tail(&txwd->list, &tx_ring->busy_pages); ++ ++ txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); ++ txbd->length = cpu_to_le16(txwd->len); ++ txbd->dma = cpu_to_le32(txwd->paddr); ++ ++ rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); ++ ++ return 0; ++ ++err_enqueue_wd: ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++err: ++ return ret; ++} ++ ++static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, ++ u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_tx_bd_32 *txbd; ++ u32 n_avail_txbd; ++ int ret = 0; ++ ++ /* check the tx type and dma channel for fw cmd queue */ ++ if ((txch == RTW89_TXCH_CH12 || ++ tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && ++ (txch != RTW89_TXCH_CH12 || ++ tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { ++ rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); ++ return -EINVAL; ++ } ++ ++ tx_ring = &rtwpci->tx_rings[txch]; ++ spin_lock_bh(&rtwpci->trx_lock); ++ ++ n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); ++ if (n_avail_txbd == 0) { ++ rtw89_err(rtwdev, "no available TXBD\n"); ++ ret = -ENOSPC; ++ goto err_unlock; ++ } ++ ++ txbd = rtw89_pci_get_next_txbd(tx_ring); ++ ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to submit TXBD\n"); ++ goto err_unlock; ++ } ++ ++ spin_unlock_bh(&rtwpci->trx_lock); ++ return 0; ++ ++err_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ return ret; ++} ++ ++static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ int ret; ++ ++ ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct rtw89_pci_bd_ram bd_ram_table[RTW89_TXCH_NUM] = { ++ [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, ++}; ++ ++static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_rx_ring *rx_ring; ++ struct rtw89_pci_dma_ring *bd_ring; ++ const struct rtw89_pci_bd_ram *bd_ram; ++ u32 addr_num; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 val32; ++ int i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ bd_ring = &tx_ring->bd_ring; ++ bd_ram = &bd_ram_table[i]; ++ addr_num = bd_ring->addr_num; ++ addr_bdram = bd_ring->addr_bdram; ++ addr_desa_l = bd_ring->addr_desa_l; ++ bd_ring->wp = 0; ++ bd_ring->rp = 0; ++ ++ val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | ++ FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | ++ FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); ++ ++ rtw89_write16(rtwdev, addr_num, bd_ring->len); ++ rtw89_write32(rtwdev, addr_bdram, val32); ++ rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); ++ } ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ bd_ring = &rx_ring->bd_ring; ++ addr_num = bd_ring->addr_num; ++ addr_desa_l = bd_ring->addr_desa_l; ++ bd_ring->wp = 0; ++ bd_ring->rp = 0; ++ rx_ring->diliver_skb = NULL; ++ rx_ring->diliver_desc.ready = false; ++ ++ rtw89_write16(rtwdev, addr_num, bd_ring->len); ++ rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); ++ } ++} ++ ++static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ rtw89_pci_release_busy_txwd(rtwdev, tx_ring); ++ rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); ++} ++ ++static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int txch; ++ ++ rtw89_pci_reset_trx_rings(rtwdev); ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { ++ if (txch == RTW89_TXCH_CH12) { ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, ++ skb_queue_len(&rtwpci->h2c_queue), true); ++ continue; ++ } ++ rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); ++ } ++ spin_unlock_bh(&rtwpci->trx_lock); ++} ++ ++static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ ++ rtw89_core_napi_start(rtwdev); ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtwpci->running = true; ++ rtw89_pci_enable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ return 0; ++} ++ ++static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtwpci->running = false; ++ rtw89_pci_disable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ synchronize_irq(pdev->irq); ++ rtw89_core_napi_stop(rtwdev); ++} ++ ++static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); ++ ++static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 val = readl(rtwpci->mmap + addr); ++ int count; ++ ++ for (count = 0; ; count++) { ++ if (val != RTW89_R32_DEAD) ++ return val; ++ if (count >= MAC_REG_POOL_COUNT) { ++ rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); ++ return RTW89_R32_DEAD; ++ } ++ rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); ++ val = readl(rtwpci->mmap + addr); ++ } ++ ++ return val; ++} ++ ++static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 addr32, val32, shift; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readb(rtwpci->mmap + addr); ++ ++ addr32 = addr & ~0x3; ++ shift = (addr & 0x3) * 8; ++ val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); ++ return val32 >> shift; ++} ++ ++static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 addr32, val32, shift; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readw(rtwpci->mmap + addr); ++ ++ addr32 = addr & ~0x3; ++ shift = (addr & 0x3) * 8; ++ val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); ++ return val32 >> shift; ++} ++ ++static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readl(rtwpci->mmap + addr); ++ ++ return rtw89_pci_ops_read32_cmac(rtwdev, addr); ++} ++ ++static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writeb(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writew(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writel(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) { ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_TXHCI_EN | B_AX_RXHCI_EN); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_PCIEIO); ++ } else { ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_PCIEIO); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_TXHCI_EN | B_AX_RXHCI_EN); ++ } ++} ++ ++static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) ++{ ++ u16 val; ++ ++ rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); ++ ++ val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); ++ switch (speed) { ++ case PCIE_PHY_GEN1: ++ if (addr < 0x20) ++ val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); ++ else ++ val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); ++ break; ++ case PCIE_PHY_GEN2: ++ if (addr < 0x20) ++ val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); ++ else ++ val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); ++ return -EINVAL; ++ }; ++ rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); ++ rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); ++ ++ return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, ++ false, rtwdev, R_AX_MDIO_CFG); ++} ++ ++static int ++rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) ++{ ++ int ret; ++ ++ ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); ++ return ret; ++ } ++ *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); ++ ++ return 0; ++} ++ ++static int ++rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) ++{ ++ int ret; ++ ++ rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); ++ ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) ++{ ++ int ret; ++ u16 val; ++ ++ ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) ++{ ++ int ret; ++ u16 val; ++ ++ ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data) ++{ ++ u16 write_addr; ++ u16 remainder = addr & ~(B_AX_DBI_ADDR_MSK | B_AX_DBI_WREN_MSK); ++ u8 flag; ++ int ret; ++ ++ write_addr = addr & B_AX_DBI_ADDR_MSK; ++ write_addr |= u16_encode_bits(BIT(remainder), B_AX_DBI_WREN_MSK); ++ rtw89_write8(rtwdev, R_AX_DBI_WDATA + remainder, data); ++ rtw89_write16(rtwdev, R_AX_DBI_FLAG, write_addr); ++ rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16); ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, ++ 10 * RTW89_PCI_WR_RETRY_CNT, false, ++ rtwdev, R_AX_DBI_FLAG + 2); ++ if (ret) ++ WARN(flag, "failed to write to DBI register, addr=0x%04x\n", ++ addr); ++ ++ return ret; ++} ++ ++static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value) ++{ ++ u16 read_addr = addr & B_AX_DBI_ADDR_MSK; ++ u8 flag; ++ int ret; ++ ++ rtw89_write16(rtwdev, R_AX_DBI_FLAG, read_addr); ++ rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16); ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, ++ 10 * RTW89_PCI_WR_RETRY_CNT, false, ++ rtwdev, R_AX_DBI_FLAG + 2); ++ ++ if (!ret) { ++ read_addr = R_AX_DBI_RDATA + (addr & 3); ++ *value = rtw89_read8(rtwdev, read_addr); ++ } else { ++ WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); ++ ret = -EIO; ++ } ++ ++ return ret; ++} ++ ++static int rtw89_dbi_write8_set(struct rtw89_dev *rtwdev, u16 addr, u8 bit) ++{ ++ u8 value; ++ int ret; ++ ++ ret = rtw89_dbi_read8(rtwdev, addr, &value); ++ if (ret) ++ return ret; ++ ++ value |= bit; ++ ret = rtw89_dbi_write8(rtwdev, addr, value); ++ ++ return ret; ++} ++ ++static int rtw89_dbi_write8_clr(struct rtw89_dev *rtwdev, u16 addr, u8 bit) ++{ ++ u8 value; ++ int ret; ++ ++ ret = rtw89_dbi_read8(rtwdev, addr, &value); ++ if (ret) ++ return ret; ++ ++ value &= ~bit; ++ ret = rtw89_dbi_write8(rtwdev, addr, value); ++ ++ return ret; ++} ++ ++static int ++__get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) ++{ ++ u16 val, tar; ++ int ret; ++ ++ /* Enable counter */ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ++ fsleep(300); ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ++ tar = tar & 0x0FFF; ++ if (tar == 0 || tar == 0x0FFF) { ++ rtw89_err(rtwdev, "[ERR]Get target failed.\n"); ++ return -EINVAL; ++ } ++ ++ *target = tar; ++ ++ return 0; ++} ++ ++static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) ++{ ++ enum rtw89_pcie_phy phy_rate; ++ u16 val16, mgn_set, div_set, tar; ++ u8 val8, bdr_ori; ++ bool l1_flag = false; ++ int ret = 0; ++ ++ if ((rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) || ++ rtwdev->chip->chip_id == RTL8852C) ++ return 0; ++ ++ ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_PHY_RATE, &val8); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_PHY_RATE); ++ return ret; ++ } ++ ++ if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { ++ phy_rate = PCIE_PHY_GEN1; ++ } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { ++ phy_rate = PCIE_PHY_GEN2; ++ } else { ++ rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); ++ return -EOPNOTSUPP; ++ } ++ /* Disable L1BD */ ++ ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ ++ if (bdr_ori & RTW89_PCIE_BIT_L1) { ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL, ++ bdr_ori & ~RTW89_PCIE_BIT_L1); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ l1_flag = true; ++ } ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ if (val16 & B_AX_CALIB_EN) { ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, ++ val16 & ~B_AX_CALIB_EN, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ } ++ ++ if (!autook_en) ++ goto end; ++ /* Set div */ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ /* Obtain div and margin */ ++ ret = __get_target(rtwdev, &tar, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); ++ goto end; ++ } ++ ++ mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; ++ ++ if (mgn_set >= 128) { ++ div_set = 0x0003; ++ mgn_set = 0x000F; ++ } else if (mgn_set >= 64) { ++ div_set = 0x0003; ++ mgn_set >>= 3; ++ } else if (mgn_set >= 32) { ++ div_set = 0x0002; ++ mgn_set >>= 2; ++ } else if (mgn_set >= 16) { ++ div_set = 0x0001; ++ mgn_set >>= 1; ++ } else if (mgn_set == 0) { ++ rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); ++ goto end; ++ } else { ++ div_set = 0x0000; ++ } ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ val16 |= u16_encode_bits(div_set, B_AX_DIV); ++ ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ ret = __get_target(rtwdev, &tar, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); ++ goto end; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", ++ tar, div_set, mgn_set); ++ ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, ++ (tar & 0x0FFF) | (mgn_set << 12), phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); ++ goto end; ++ } ++ ++ /* Enable function */ ++ ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ /* CLK delay = 0 */ ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_0); ++ ++end: ++ /* Set L1BD to ori */ ++ if (l1_flag) { ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL, bdr_ori); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return 0; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, ++ PCIE_PHY_GEN1); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, ++ PCIE_PHY_GEN2); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); ++} ++ ++static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); ++} ++ ++static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return 0; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, ++ PCIE_PHY_GEN1); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, ++ PCIE_PHY_GEN2); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); ++} ++ ++static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return; ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_WLSUS_AFT_PDN); ++} ++ ++static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, ++ B_AX_SIC_EN_FORCE_CLKREQ); ++} ++ ++static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, ++ B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, ++ B_AX_EN_CHKDSC_NO_RX_STUCK); ++} ++ ++static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev) ++{ ++ u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | ++ B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | ++ B_AX_CLR_CH12_IDX; ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | ++ B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; ++ /* clear DMA indexes */ ++ rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR2, ++ B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); ++ rtw89_write32_set(rtwdev, R_AX_RXBD_RWPTR_CLR, ++ B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); ++} ++ ++static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852A) { ++ /* ltr sw trigger */ ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); ++ } ++ rtw89_pci_ctrl_dma_all(rtwdev, false); ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev) ++{ ++ u32 dma_busy; ++ u32 check; ++ u32 lbc; ++ int ret; ++ ++ rtw89_pci_rxdma_prefth(rtwdev); ++ rtw89_pci_l1off_pwroff(rtwdev); ++ rtw89_pci_deglitch_setting(rtwdev); ++ ret = rtw89_pci_l2_rxen_lat(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_pci_aphy_pwrcut(rtwdev); ++ rtw89_pci_hci_ldo(rtwdev); ++ ++ ret = rtw89_pci_auto_refclk_cal(rtwdev, false); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_pci_set_sic(rtwdev); ++ rtw89_pci_set_dbg(rtwdev); ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_AUXCLK_GATE); ++ ++ lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); ++ lbc = u32_replace_bits(lbc, RTW89_MAC_LBC_TMR_128US, B_AX_LBC_TIMER); ++ lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; ++ rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); ++ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_WPDMA); ++ ++ /* stop DMA activities */ ++ rtw89_pci_ctrl_dma_all(rtwdev, false); ++ ++ /* check PCI at idle state */ ++ check = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; ++ ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, ++ 100, 3000, false, rtwdev, R_AX_PCIE_DMA_BUSY1); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to poll io busy\n"); ++ return ret; ++ } ++ ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ /* configure TX/RX op modes */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE | ++ B_AX_RX_TRUNC_MODE); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RXBD_MODE); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, 7); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, 3); ++ /* multi-tag mode */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_LATENCY_CONTROL); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_MAX_TAG_NUM, ++ RTW89_MAC_TAG_NUM_8); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, ++ RTW89_MAC_WD_DMA_INTVL_256NS); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, ++ RTW89_MAC_WD_DMA_INTVL_256NS); ++ ++ /* fill TRX BD indexes */ ++ rtw89_pci_ops_reset(rtwdev); ++ ++ ret = rtw89_pci_rst_bdram_pcie(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "reset bdram busy\n"); ++ return ret; ++ } ++ ++ /* enable FW CMD queue to download firmware */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_CH12); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); ++ ++ /* start DMA activities */ ++ rtw89_pci_ctrl_dma_all(rtwdev, true); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ ++ rtw89_write32_clr(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN); ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_EN); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, ++ PCI_LTR_SPC_500US); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, ++ PCI_LTR_IDLE_TIMER_800US); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); ++ rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x88e088e0); ++ rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_pci_ltr_set(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "pci ltr set fail\n"); ++ return ret; ++ } ++ if (rtwdev->chip->chip_id == RTL8852A) { ++ /* ltr sw trigger */ ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); ++ } ++ /* ADDR info 8-byte mode */ ++ rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, ++ B_AX_HOST_ADDR_INFO_8B_SEL); ++ rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); ++ ++ /* enable DMA for all queues */ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); ++ ++ /* Release PCI IO */ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); ++ ++ return 0; ++} ++ ++static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int ret; ++ ++ ret = pci_enable_device(pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to enable pci device\n"); ++ return ret; ++ } ++ ++ pci_set_master(pdev); ++ pci_set_drvdata(pdev, rtwdev->hw); ++ ++ rtwpci->pdev = pdev; ++ ++ return 0; ++} ++ ++static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ pci_clear_master(pdev); ++ pci_disable_device(pdev); ++} ++ ++static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long resource_len; ++ u8 bar_id = 2; ++ int ret; ++ ++ ret = pci_request_regions(pdev, KBUILD_MODNAME); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request pci regions\n"); ++ goto err; ++ } ++ ++ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n"); ++ goto err_release_regions; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); ++ goto err_release_regions; ++ } ++ ++ resource_len = pci_resource_len(pdev, bar_id); ++ rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); ++ if (!rtwpci->mmap) { ++ rtw89_err(rtwdev, "failed to map pci io\n"); ++ ret = -EIO; ++ goto err_release_regions; ++ } ++ ++ return 0; ++ ++err_release_regions: ++ pci_release_regions(pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ if (rtwpci->mmap) { ++ pci_iounmap(pdev, rtwpci->mmap); ++ pci_release_regions(pdev); ++ } ++} ++ ++static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ u8 *head = wd_ring->head; ++ dma_addr_t dma = wd_ring->dma; ++ u32 page_size = wd_ring->page_size; ++ u32 page_num = wd_ring->page_num; ++ u32 ring_sz = page_size * page_num; ++ ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ wd_ring->head = NULL; ++} ++ ++static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ int ring_sz; ++ u8 *head; ++ dma_addr_t dma; ++ ++ head = tx_ring->bd_ring.head; ++ dma = tx_ring->bd_ring.dma; ++ ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ tx_ring->bd_ring.head = NULL; ++} ++ ++static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ int i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); ++ rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); ++ } ++} ++ ++static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ struct sk_buff *skb; ++ dma_addr_t dma; ++ u32 buf_sz; ++ u8 *head; ++ int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; ++ int i; ++ ++ buf_sz = rx_ring->buf_sz; ++ for (i = 0; i < rx_ring->bd_ring.len; i++) { ++ skb = rx_ring->buf[i]; ++ if (!skb) ++ continue; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ rx_ring->buf[i] = NULL; ++ } ++ ++ head = rx_ring->bd_ring.head; ++ dma = rx_ring->bd_ring.dma; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ rx_ring->bd_ring.head = NULL; ++} ++ ++static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_rx_ring *rx_ring; ++ int i; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); ++ } ++} ++ ++static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ rtw89_pci_free_rx_rings(rtwdev, pdev); ++ rtw89_pci_free_tx_rings(rtwdev, pdev); ++} ++ ++static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ struct sk_buff *skb, int buf_sz, u32 idx) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_pci_rx_bd_32 *rx_bd; ++ dma_addr_t dma; ++ ++ if (!skb) ++ return -EINVAL; ++ ++ dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) ++ return -EBUSY; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); ++ ++ memset(rx_bd, 0, sizeof(*rx_bd)); ++ rx_bd->buf_size = cpu_to_le16(buf_sz); ++ rx_bd->dma = cpu_to_le32(dma); ++ rx_info->dma = dma; ++ ++ return 0; ++} ++ ++static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ enum rtw89_tx_channel txch) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ dma_addr_t dma; ++ dma_addr_t cur_paddr; ++ u8 *head; ++ u8 *cur_vaddr; ++ u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; ++ u32 page_num = RTW89_PCI_TXWD_NUM_MAX; ++ u32 ring_sz = page_size * page_num; ++ u32 page_offset; ++ int i; ++ ++ /* FWCMD queue doesn't use txwd as pages */ ++ if (txch == RTW89_TXCH_CH12) ++ return 0; ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) ++ return -ENOMEM; ++ ++ INIT_LIST_HEAD(&wd_ring->free_pages); ++ wd_ring->head = head; ++ wd_ring->dma = dma; ++ wd_ring->page_size = page_size; ++ wd_ring->page_num = page_num; ++ ++ page_offset = 0; ++ for (i = 0; i < page_num; i++) { ++ txwd = &wd_ring->pages[i]; ++ cur_paddr = dma + page_offset; ++ cur_vaddr = head + page_offset; ++ ++ skb_queue_head_init(&txwd->queue); ++ INIT_LIST_HEAD(&txwd->list); ++ txwd->paddr = cur_paddr; ++ txwd->vaddr = cur_vaddr; ++ txwd->len = page_size; ++ txwd->seq = i; ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++ ++ page_offset += page_size; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ u32 desc_size, u32 len, ++ enum rtw89_tx_channel txch) ++{ ++ int ring_sz = desc_size * len; ++ u8 *head; ++ dma_addr_t dma; ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ int ret; ++ ++ ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); ++ goto err; ++ } ++ ++ ret = rtw89_pci_get_txch_addrs(txch, &addr_num, &addr_idx, &addr_bdram, ++ &addr_desa_l, &addr_desa_h); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get address of txch %d", txch); ++ goto err_free_wd_ring; ++ } ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) { ++ ret = -ENOMEM; ++ goto err_free_wd_ring; ++ } ++ ++ INIT_LIST_HEAD(&tx_ring->busy_pages); ++ tx_ring->bd_ring.head = head; ++ tx_ring->bd_ring.dma = dma; ++ tx_ring->bd_ring.len = len; ++ tx_ring->bd_ring.desc_size = desc_size; ++ tx_ring->bd_ring.addr_num = addr_num; ++ tx_ring->bd_ring.addr_idx = addr_idx; ++ tx_ring->bd_ring.addr_bdram = addr_bdram; ++ tx_ring->bd_ring.addr_desa_l = addr_desa_l; ++ tx_ring->bd_ring.addr_desa_h = addr_desa_h; ++ tx_ring->bd_ring.wp = 0; ++ tx_ring->bd_ring.rp = 0; ++ tx_ring->txch = txch; ++ ++ return 0; ++ ++err_free_wd_ring: ++ rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); ++err: ++ return ret; ++} ++ ++static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ u32 desc_size; ++ u32 len; ++ u32 i, tx_allocated; ++ int ret; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ desc_size = sizeof(struct rtw89_pci_tx_bd_32); ++ len = RTW89_PCI_TXBD_NUM_MAX; ++ ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, ++ desc_size, len, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ tx_allocated = i; ++ for (i = 0; i < tx_allocated; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 desc_size, u32 len, u32 rxch) ++{ ++ struct sk_buff *skb; ++ u8 *head; ++ dma_addr_t dma; ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ int ring_sz = desc_size * len; ++ int buf_sz = RTW89_PCI_RX_BUF_SIZE; ++ int i, allocated; ++ int ret; ++ ++ ret = rtw89_pci_get_rxch_addrs(rxch, &addr_num, &addr_idx, ++ &addr_desa_l, &addr_desa_h); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); ++ return ret; ++ } ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ rx_ring->bd_ring.head = head; ++ rx_ring->bd_ring.dma = dma; ++ rx_ring->bd_ring.len = len; ++ rx_ring->bd_ring.desc_size = desc_size; ++ rx_ring->bd_ring.addr_num = addr_num; ++ rx_ring->bd_ring.addr_idx = addr_idx; ++ rx_ring->bd_ring.addr_desa_l = addr_desa_l; ++ rx_ring->bd_ring.addr_desa_h = addr_desa_h; ++ rx_ring->bd_ring.wp = 0; ++ rx_ring->bd_ring.rp = 0; ++ rx_ring->buf_sz = buf_sz; ++ rx_ring->diliver_skb = NULL; ++ rx_ring->diliver_desc.ready = false; ++ ++ for (i = 0; i < len; i++) { ++ skb = dev_alloc_skb(buf_sz); ++ if (!skb) { ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ ++ memset(skb->data, 0, buf_sz); ++ rx_ring->buf[i] = skb; ++ ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, ++ buf_sz, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init rx buf %d\n", i); ++ dev_kfree_skb_any(skb); ++ rx_ring->buf[i] = NULL; ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ allocated = i; ++ for (i = 0; i < allocated; i++) { ++ skb = rx_ring->buf[i]; ++ if (!skb) ++ continue; ++ dma = *((dma_addr_t *)skb->cb); ++ dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ rx_ring->buf[i] = NULL; ++ } ++ ++ head = rx_ring->bd_ring.head; ++ dma = rx_ring->bd_ring.dma; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ rx_ring->bd_ring.head = NULL; ++err: ++ return ret; ++} ++ ++static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 desc_size; ++ u32 len; ++ int i, rx_allocated; ++ int ret; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ desc_size = sizeof(struct rtw89_pci_rx_bd_32); ++ len = RTW89_PCI_RXBD_NUM_MAX; ++ ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, ++ desc_size, len, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ rx_allocated = i; ++ for (i = 0; i < rx_allocated; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ int ret; ++ ++ ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); ++ goto err; ++ } ++ ++ ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); ++ goto err_free_tx_rings; ++ } ++ ++ return 0; ++ ++err_free_tx_rings: ++ rtw89_pci_free_tx_rings(rtwdev, pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ skb_queue_head_init(&rtwpci->h2c_queue); ++ skb_queue_head_init(&rtwpci->h2c_release_queue); ++} ++ ++static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int ret; ++ ++ ret = rtw89_pci_setup_mapping(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup pci mapping\n"); ++ goto err; ++ } ++ ++ ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); ++ goto err_pci_unmap; ++ } ++ ++ rtw89_pci_h2c_init(rtwdev, rtwpci); ++ ++ spin_lock_init(&rtwpci->irq_lock); ++ spin_lock_init(&rtwpci->trx_lock); ++ ++ return 0; ++ ++err_pci_unmap: ++ rtw89_pci_clear_mapping(rtwdev, pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ rtw89_pci_free_trx_rings(rtwdev, pdev); ++ rtw89_pci_clear_mapping(rtwdev, pdev); ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, ++ skb_queue_len(&rtwpci->h2c_queue), true); ++} ++ ++static void rtw89_pci_default_intr_mask(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; ++ rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | ++ B_AX_RXDMA_INT_EN | ++ B_AX_RXP1DMA_INT_EN | ++ B_AX_RPQDMA_INT_EN | ++ B_AX_RXDMA_STUCK_INT_EN | ++ B_AX_RDU_INT_EN | ++ B_AX_RPQBD_FULL_INT_EN | ++ B_AX_HS0ISR_IND_INT_EN; ++ ++ rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; ++} ++ ++static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ unsigned long flags = 0; ++ int ret; ++ ++ flags |= PCI_IRQ_LEGACY | PCI_IRQ_MSI; ++ ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); ++ if (ret < 0) { ++ rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); ++ goto err; ++ } ++ ++ ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, ++ rtw89_pci_interrupt_handler, ++ rtw89_pci_interrupt_threadfn, ++ IRQF_SHARED, KBUILD_MODNAME, rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request threaded irq\n"); ++ goto err_free_vector; ++ } ++ ++ rtw89_pci_default_intr_mask(rtwdev); ++ ++ return 0; ++ ++err_free_vector: ++ pci_free_irq_vectors(pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); ++ pci_free_irq_vectors(pdev); ++} ++ ++static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret; ++ ++ if (rtw89_pci_disable_clkreq) ++ return; ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_CLK); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_CLK); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret; ++ ++ if (rtw89_pci_disable_aspm_l1) ++ return; ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_L1); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_L1); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_link_ps(struct rtw89_dev *rtwdev, bool enter) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ /* Like CLKREQ, ASPM is also implemented by two HW modules, and can ++ * only be enabled when host supports it. ++ * ++ * And ASPM mechanism should be enabled when driver/firmware enters ++ * power save mode, without having heavy traffic. Because we've ++ * experienced some inter-operability issues that the link tends ++ * to enter L1 state on the fly even when driver is having high ++ * throughput. This is probably because the ASPM behavior slightly ++ * varies from different SOC. ++ */ ++ if (rtwpci->link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) ++ rtw89_pci_aspm_set(rtwdev, enter); ++} ++ ++static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; ++ u32 val = 0; ++ ++ if (!rtwdev->scanning && ++ (tx_tfc_lv >= RTW89_TFC_HIGH || rx_tfc_lv >= RTW89_TFC_HIGH)) ++ val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | ++ FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | ++ FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | ++ FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); ++ ++ rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val); ++} ++ ++static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ u16 link_ctrl; ++ int ret; ++ ++ /* Though there is standard PCIE configuration space to set the ++ * link control register, but by Realtek's design, driver should ++ * check if host supports CLKREQ/ASPM to enable the HW module. ++ * ++ * These functions are implemented by two HW modules associated, ++ * one is responsible to access PCIE configuration space to ++ * follow the host settings, and another is in charge of doing ++ * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes ++ * the host does not support it, and due to some reasons or wrong ++ * settings (ex. CLKREQ# not Bi-Direction), it could lead to device ++ * loss if HW misbehaves on the link. ++ * ++ * Hence it's designed that driver should first check the PCIE ++ * configuration space is sync'ed and enabled, then driver can turn ++ * on the other module that is actually working on the mechanism. ++ */ ++ ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); ++ return; ++ } ++ ++ if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) ++ rtw89_pci_clkreq_set(rtwdev, true); ++ ++ rtwpci->link_ctrl = link_ctrl; ++} ++ ++static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret; ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_TIMER_CTRL, ++ RTW89_PCIE_BIT_L1SUB); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_TIMER_CTRL, ++ RTW89_PCIE_BIT_L1SUB); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ u32 l1ss_cap_ptr, l1ss_ctrl; ++ ++ if (rtw89_pci_disable_l1ss) ++ return; ++ ++ l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); ++ if (!l1ss_cap_ptr) ++ return; ++ ++ pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); ++ ++ if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) ++ rtw89_pci_l1ss_set(rtwdev, true); ++} ++ ++static void rtw89_pci_ctrl_dma_all_pcie(struct rtw89_dev *rtwdev, u8 en) ++{ ++ u32 val32; ++ ++ if (en == MAC_AX_FUNC_EN) { ++ val32 = B_AX_STOP_PCIEIO; ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, val32); ++ ++ val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ } else { ++ val32 = B_AX_STOP_PCIEIO; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, val32); ++ ++ val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ } ++} ++ ++static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev) ++{ ++ int ret = 0; ++ u32 sts; ++ u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, ++ 10, 1000, false, rtwdev, ++ R_AX_PCIE_DMA_BUSY1); ++ if (ret) { ++ rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", ++ rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); ++ return -EINVAL; ++ } ++ return ret; ++} ++ ++static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev) ++{ ++ u32 val, dma_rst = 0; ++ int ret; ++ ++ rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_DIS); ++ ret = rtw89_pci_poll_io_idle(rtwdev); ++ if (ret) { ++ val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, ++ "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", ++ R_AX_DBG_ERR_FLAG, val); ++ if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) ++ dma_rst |= B_AX_HCI_TXDMA_EN; ++ if (val & B_AX_RX_STUCK) ++ dma_rst |= B_AX_HCI_RXDMA_EN; ++ val = rtw89_read32(rtwdev, R_AX_HCI_FUNC_EN); ++ rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val & ~dma_rst); ++ rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val | dma_rst); ++ ret = rtw89_pci_poll_io_idle(rtwdev); ++ val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, ++ "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", ++ R_AX_DBG_ERR_FLAG, val); ++ } ++ ++ return ret; ++} ++ ++static void rtw89_pci_ctrl_hci_dma_en(struct rtw89_dev *rtwdev, u8 en) ++{ ++ u32 val32; ++ ++ if (en == MAC_AX_FUNC_EN) { ++ val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; ++ rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, val32); ++ } else { ++ val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; ++ rtw89_write32_clr(rtwdev, R_AX_HCI_FUNC_EN, val32); ++ } ++} ++ ++static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev) ++{ ++ int ret = 0; ++ u32 val32, sts; ++ ++ val32 = B_AX_RST_BDRAM; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, sts, ++ (sts & B_AX_RST_BDRAM) == 0x0, 1, 100, ++ true, rtwdev, R_AX_PCIE_INIT_CFG1); ++ return ret; ++} ++ ++static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev) ++{ ++ u32 ret; ++ ++ rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_DIS); ++ rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_EN); ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ ret = rtw89_pci_rst_bdram(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_EN); ++ return ret; ++} ++ ++static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, ++ enum rtw89_lv1_rcvy_step step) ++{ ++ int ret; ++ ++ switch (step) { ++ case RTW89_LV1_RCVY_STEP_1: ++ ret = rtw89_pci_lv1rst_stop_dma(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); ++ ++ break; ++ ++ case RTW89_LV1_RCVY_STEP_2: ++ ret = rtw89_pci_lv1rst_start_dma(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) ++{ ++ rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); ++ rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); ++ rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); ++} ++ ++static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ int work_done; ++ ++ rtwdev->napi_budget_countdown = budget; ++ ++ rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT); ++ work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); ++ if (work_done == budget) ++ return budget; ++ ++ rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT); ++ work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); ++ if (work_done < budget && napi_complete_done(napi, work_done)) { ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ if (likely(rtwpci->running)) ++ rtw89_pci_enable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ } ++ ++ return work_done; ++} ++ ++static int __maybe_unused rtw89_pci_suspend(struct device *dev) ++{ ++ struct ieee80211_hw *hw = dev_get_drvdata(dev); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); ++ ++ return 0; ++} ++ ++static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ /* Hardware need write the reg twice to ensure the setting work */ ++ rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE, ++ RTW89_PCIE_BIT_CFG_RST_MSTATE); ++ rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE, ++ RTW89_PCIE_BIT_CFG_RST_MSTATE); ++} ++ ++static int __maybe_unused rtw89_pci_resume(struct device *dev) ++{ ++ struct ieee80211_hw *hw = dev_get_drvdata(dev); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); ++ rtw89_pci_l2_hci_ldo(rtwdev); ++ rtw89_pci_link_cfg(rtwdev); ++ rtw89_pci_l1ss_cfg(rtwdev); ++ ++ return 0; ++} ++ ++SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); ++EXPORT_SYMBOL(rtw89_pm_ops); ++ ++static const struct rtw89_hci_ops rtw89_pci_ops = { ++ .tx_write = rtw89_pci_ops_tx_write, ++ .tx_kick_off = rtw89_pci_ops_tx_kick_off, ++ .flush_queues = rtw89_pci_ops_flush_queues, ++ .reset = rtw89_pci_ops_reset, ++ .start = rtw89_pci_ops_start, ++ .stop = rtw89_pci_ops_stop, ++ .link_ps = rtw89_pci_link_ps, ++ .recalc_int_mit = rtw89_pci_recalc_int_mit, ++ ++ .read8 = rtw89_pci_ops_read8, ++ .read16 = rtw89_pci_ops_read16, ++ .read32 = rtw89_pci_ops_read32, ++ .write8 = rtw89_pci_ops_write8, ++ .write16 = rtw89_pci_ops_write16, ++ .write32 = rtw89_pci_ops_write32, ++ ++ .mac_pre_init = rtw89_pci_ops_mac_pre_init, ++ .mac_post_init = rtw89_pci_ops_mac_post_init, ++ .deinit = rtw89_pci_ops_deinit, ++ ++ .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, ++ .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, ++ .dump_err_status = rtw89_pci_ops_dump_err_status, ++ .napi_poll = rtw89_pci_napi_poll, ++}; ++ ++static int rtw89_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id) ++{ ++ struct ieee80211_hw *hw; ++ struct rtw89_dev *rtwdev; ++ int driver_data_size; ++ int ret; ++ ++ driver_data_size = sizeof(struct rtw89_dev) + sizeof(struct rtw89_pci); ++ hw = ieee80211_alloc_hw(driver_data_size, &rtw89_ops); ++ if (!hw) { ++ dev_err(&pdev->dev, "failed to allocate hw\n"); ++ return -ENOMEM; ++ } ++ ++ rtwdev = hw->priv; ++ rtwdev->hw = hw; ++ rtwdev->dev = &pdev->dev; ++ rtwdev->hci.ops = &rtw89_pci_ops; ++ rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; ++ rtwdev->hci.rpwm_addr = R_AX_PCIE_HRPWM; ++ rtwdev->hci.cpwm_addr = R_AX_CPWM; ++ ++ SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); ++ ++ switch (id->driver_data) { ++ case RTL8852A: ++ rtwdev->chip = &rtw8852a_chip_info; ++ break; ++ default: ++ return -ENOENT; ++ } ++ ++ ret = rtw89_core_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to initialise core\n"); ++ goto err_release_hw; ++ } ++ ++ ret = rtw89_pci_claim_device(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to claim pci device\n"); ++ goto err_core_deinit; ++ } ++ ++ ret = rtw89_pci_setup_resource(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup pci resource\n"); ++ goto err_declaim_pci; ++ } ++ ++ ret = rtw89_chip_info_setup(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup chip information\n"); ++ goto err_clear_resource; ++ } ++ ++ rtw89_pci_link_cfg(rtwdev); ++ rtw89_pci_l1ss_cfg(rtwdev); ++ ++ ret = rtw89_core_register(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register core\n"); ++ goto err_clear_resource; ++ } ++ ++ rtw89_core_napi_init(rtwdev); ++ ++ ret = rtw89_pci_request_irq(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request pci irq\n"); ++ goto err_unregister; ++ } ++ ++ return 0; ++ ++err_unregister: ++ rtw89_core_napi_deinit(rtwdev); ++ rtw89_core_unregister(rtwdev); ++err_clear_resource: ++ rtw89_pci_clear_resource(rtwdev, pdev); ++err_declaim_pci: ++ rtw89_pci_declaim_device(rtwdev, pdev); ++err_core_deinit: ++ rtw89_core_deinit(rtwdev); ++err_release_hw: ++ ieee80211_free_hw(hw); ++ ++ return ret; ++} ++ ++static void rtw89_pci_remove(struct pci_dev *pdev) ++{ ++ struct ieee80211_hw *hw = pci_get_drvdata(pdev); ++ struct rtw89_dev *rtwdev; ++ ++ rtwdev = hw->priv; ++ ++ rtw89_pci_free_irq(rtwdev, pdev); ++ rtw89_core_napi_deinit(rtwdev); ++ rtw89_core_unregister(rtwdev); ++ rtw89_pci_clear_resource(rtwdev, pdev); ++ rtw89_pci_declaim_device(rtwdev, pdev); ++ rtw89_core_deinit(rtwdev); ++ ieee80211_free_hw(hw); ++} ++ ++static const struct pci_device_id rtw89_pci_id_table[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8852), .driver_data = RTL8852A }, ++ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xa85a), .driver_data = RTL8852A }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(pci, rtw89_pci_id_table); ++ ++static struct pci_driver rtw89_pci_driver = { ++ .name = "rtw89_pci", ++ .id_table = rtw89_pci_id_table, ++ .probe = rtw89_pci_probe, ++ .remove = rtw89_pci_remove, ++ .driver.pm = &rtw89_pm_ops, ++}; ++module_pci_driver(rtw89_pci_driver); ++ ++MODULE_AUTHOR("Realtek Corporation"); ++MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h +new file mode 100644 +index 000000000000..7693181f71a8 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/pci.h +@@ -0,0 +1,616 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PCI_H__ ++#define __RTW89_PCI_H__ ++ ++#include "txrx.h" ++ ++#define MDIO_PG0_G1 0 ++#define MDIO_PG1_G1 1 ++#define MDIO_PG0_G2 2 ++#define MDIO_PG1_G2 3 ++#define RAC_ANA10 0x10 ++#define RAC_ANA19 0x19 ++#define RAC_ANA1F 0x1F ++#define RAC_ANA24 0x24 ++#define B_AX_DEGLITCH GENMASK(11, 8) ++#define RAC_ANA26 0x26 ++#define B_AX_RXEN GENMASK(15, 14) ++#define RAC_CTRL_PPR_V1 0x30 ++#define B_AX_CLK_CALIB_EN BIT(12) ++#define B_AX_CALIB_EN BIT(13) ++#define B_AX_DIV GENMASK(15, 14) ++#define RAC_SET_PPR_V1 0x31 ++ ++#define R_AX_DBI_FLAG 0x1090 ++#define B_AX_DBI_RFLAG BIT(17) ++#define B_AX_DBI_WFLAG BIT(16) ++#define B_AX_DBI_WREN_MSK GENMASK(15, 12) ++#define B_AX_DBI_ADDR_MSK GENMASK(11, 2) ++#define R_AX_DBI_WDATA 0x1094 ++#define R_AX_DBI_RDATA 0x1098 ++ ++#define R_AX_MDIO_WDATA 0x10A4 ++#define R_AX_MDIO_RDATA 0x10A6 ++ ++#define RTW89_PCI_WR_RETRY_CNT 20 ++ ++/* Interrupts */ ++#define R_AX_HIMR0 0x01A0 ++#define B_AX_HALT_C2H_INT_EN BIT(21) ++#define R_AX_HISR0 0x01A4 ++ ++#define R_AX_MDIO_CFG 0x10A0 ++#define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12) ++#define B_AX_MDIO_RFLAG BIT(9) ++#define B_AX_MDIO_WFLAG BIT(8) ++#define B_AX_MDIO_ADDR_MASK GENMASK(4, 0) ++ ++#define R_AX_PCIE_HIMR00 0x10B0 ++#define B_AX_HC00ISR_IND_INT_EN BIT(27) ++#define B_AX_HD1ISR_IND_INT_EN BIT(26) ++#define B_AX_HD0ISR_IND_INT_EN BIT(25) ++#define B_AX_HS0ISR_IND_INT_EN BIT(24) ++#define B_AX_RETRAIN_INT_EN BIT(21) ++#define B_AX_RPQBD_FULL_INT_EN BIT(20) ++#define B_AX_RDU_INT_EN BIT(19) ++#define B_AX_RXDMA_STUCK_INT_EN BIT(18) ++#define B_AX_TXDMA_STUCK_INT_EN BIT(17) ++#define B_AX_PCIE_HOTRST_INT_EN BIT(16) ++#define B_AX_PCIE_FLR_INT_EN BIT(15) ++#define B_AX_PCIE_PERST_INT_EN BIT(14) ++#define B_AX_TXDMA_CH12_INT_EN BIT(13) ++#define B_AX_TXDMA_CH9_INT_EN BIT(12) ++#define B_AX_TXDMA_CH8_INT_EN BIT(11) ++#define B_AX_TXDMA_ACH7_INT_EN BIT(10) ++#define B_AX_TXDMA_ACH6_INT_EN BIT(9) ++#define B_AX_TXDMA_ACH5_INT_EN BIT(8) ++#define B_AX_TXDMA_ACH4_INT_EN BIT(7) ++#define B_AX_TXDMA_ACH3_INT_EN BIT(6) ++#define B_AX_TXDMA_ACH2_INT_EN BIT(5) ++#define B_AX_TXDMA_ACH1_INT_EN BIT(4) ++#define B_AX_TXDMA_ACH0_INT_EN BIT(3) ++#define B_AX_RPQDMA_INT_EN BIT(2) ++#define B_AX_RXP1DMA_INT_EN BIT(1) ++#define B_AX_RXDMA_INT_EN BIT(0) ++ ++#define R_AX_PCIE_HISR00 0x10B4 ++#define B_AX_HC00ISR_IND_INT BIT(27) ++#define B_AX_HD1ISR_IND_INT BIT(26) ++#define B_AX_HD0ISR_IND_INT BIT(25) ++#define B_AX_HS0ISR_IND_INT BIT(24) ++#define B_AX_RETRAIN_INT BIT(21) ++#define B_AX_RPQBD_FULL_INT BIT(20) ++#define B_AX_RDU_INT BIT(19) ++#define B_AX_RXDMA_STUCK_INT BIT(18) ++#define B_AX_TXDMA_STUCK_INT BIT(17) ++#define B_AX_PCIE_HOTRST_INT BIT(16) ++#define B_AX_PCIE_FLR_INT BIT(15) ++#define B_AX_PCIE_PERST_INT BIT(14) ++#define B_AX_TXDMA_CH12_INT BIT(13) ++#define B_AX_TXDMA_CH9_INT BIT(12) ++#define B_AX_TXDMA_CH8_INT BIT(11) ++#define B_AX_TXDMA_ACH7_INT BIT(10) ++#define B_AX_TXDMA_ACH6_INT BIT(9) ++#define B_AX_TXDMA_ACH5_INT BIT(8) ++#define B_AX_TXDMA_ACH4_INT BIT(7) ++#define B_AX_TXDMA_ACH3_INT BIT(6) ++#define B_AX_TXDMA_ACH2_INT BIT(5) ++#define B_AX_TXDMA_ACH1_INT BIT(4) ++#define B_AX_TXDMA_ACH0_INT BIT(3) ++#define B_AX_RPQDMA_INT BIT(2) ++#define B_AX_RXP1DMA_INT BIT(1) ++#define B_AX_RXDMA_INT BIT(0) ++ ++#define R_AX_PCIE_HIMR10 0x13B0 ++#define B_AX_HC10ISR_IND_INT_EN BIT(28) ++#define B_AX_TXDMA_CH11_INT_EN BIT(12) ++#define B_AX_TXDMA_CH10_INT_EN BIT(11) ++ ++#define R_AX_PCIE_HISR10 0x13B4 ++#define B_AX_HC10ISR_IND_INT BIT(28) ++#define B_AX_TXDMA_CH11_INT BIT(12) ++#define B_AX_TXDMA_CH10_INT BIT(11) ++ ++/* TX/RX */ ++#define R_AX_RXQ_RXBD_IDX 0x1050 ++#define R_AX_RPQ_RXBD_IDX 0x1054 ++#define R_AX_ACH0_TXBD_IDX 0x1058 ++#define R_AX_ACH1_TXBD_IDX 0x105C ++#define R_AX_ACH2_TXBD_IDX 0x1060 ++#define R_AX_ACH3_TXBD_IDX 0x1064 ++#define R_AX_ACH4_TXBD_IDX 0x1068 ++#define R_AX_ACH5_TXBD_IDX 0x106C ++#define R_AX_ACH6_TXBD_IDX 0x1070 ++#define R_AX_ACH7_TXBD_IDX 0x1074 ++#define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */ ++#define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ ++#define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */ ++#define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ ++#define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */ ++#define TXBD_HW_IDX_MASK GENMASK(27, 16) ++#define TXBD_HOST_IDX_MASK GENMASK(11, 0) ++ ++#define R_AX_ACH0_TXBD_DESA_L 0x1110 ++#define R_AX_ACH0_TXBD_DESA_H 0x1114 ++#define R_AX_ACH1_TXBD_DESA_L 0x1118 ++#define R_AX_ACH1_TXBD_DESA_H 0x111C ++#define R_AX_ACH2_TXBD_DESA_L 0x1120 ++#define R_AX_ACH2_TXBD_DESA_H 0x1124 ++#define R_AX_ACH3_TXBD_DESA_L 0x1128 ++#define R_AX_ACH3_TXBD_DESA_H 0x112C ++#define R_AX_ACH4_TXBD_DESA_L 0x1130 ++#define R_AX_ACH4_TXBD_DESA_H 0x1134 ++#define R_AX_ACH5_TXBD_DESA_L 0x1138 ++#define R_AX_ACH5_TXBD_DESA_H 0x113C ++#define R_AX_ACH6_TXBD_DESA_L 0x1140 ++#define R_AX_ACH6_TXBD_DESA_H 0x1144 ++#define R_AX_ACH7_TXBD_DESA_L 0x1148 ++#define R_AX_ACH7_TXBD_DESA_H 0x114C ++#define R_AX_CH8_TXBD_DESA_L 0x1150 ++#define R_AX_CH8_TXBD_DESA_H 0x1154 ++#define R_AX_CH9_TXBD_DESA_L 0x1158 ++#define R_AX_CH9_TXBD_DESA_H 0x115C ++#define R_AX_CH10_TXBD_DESA_L 0x1358 ++#define R_AX_CH10_TXBD_DESA_H 0x135C ++#define R_AX_CH11_TXBD_DESA_L 0x1360 ++#define R_AX_CH11_TXBD_DESA_H 0x1364 ++#define R_AX_CH12_TXBD_DESA_L 0x1160 ++#define R_AX_CH12_TXBD_DESA_H 0x1164 ++#define R_AX_RXQ_RXBD_DESA_L 0x1100 ++#define R_AX_RXQ_RXBD_DESA_H 0x1104 ++#define R_AX_RPQ_RXBD_DESA_L 0x1108 ++#define R_AX_RPQ_RXBD_DESA_H 0x110C ++#define B_AX_DESC_NUM_MSK GENMASK(11, 0) ++ ++#define R_AX_RXQ_RXBD_NUM 0x1020 ++#define R_AX_RPQ_RXBD_NUM 0x1022 ++#define R_AX_ACH0_TXBD_NUM 0x1024 ++#define R_AX_ACH1_TXBD_NUM 0x1026 ++#define R_AX_ACH2_TXBD_NUM 0x1028 ++#define R_AX_ACH3_TXBD_NUM 0x102A ++#define R_AX_ACH4_TXBD_NUM 0x102C ++#define R_AX_ACH5_TXBD_NUM 0x102E ++#define R_AX_ACH6_TXBD_NUM 0x1030 ++#define R_AX_ACH7_TXBD_NUM 0x1032 ++#define R_AX_CH8_TXBD_NUM 0x1034 ++#define R_AX_CH9_TXBD_NUM 0x1036 ++#define R_AX_CH10_TXBD_NUM 0x1338 ++#define R_AX_CH11_TXBD_NUM 0x133A ++#define R_AX_CH12_TXBD_NUM 0x1038 ++ ++#define R_AX_ACH0_BDRAM_CTRL 0x1200 ++#define R_AX_ACH1_BDRAM_CTRL 0x1204 ++#define R_AX_ACH2_BDRAM_CTRL 0x1208 ++#define R_AX_ACH3_BDRAM_CTRL 0x120C ++#define R_AX_ACH4_BDRAM_CTRL 0x1210 ++#define R_AX_ACH5_BDRAM_CTRL 0x1214 ++#define R_AX_ACH6_BDRAM_CTRL 0x1218 ++#define R_AX_ACH7_BDRAM_CTRL 0x121C ++#define R_AX_CH8_BDRAM_CTRL 0x1220 ++#define R_AX_CH9_BDRAM_CTRL 0x1224 ++#define R_AX_CH10_BDRAM_CTRL 0x1320 ++#define R_AX_CH11_BDRAM_CTRL 0x1324 ++#define R_AX_CH12_BDRAM_CTRL 0x1228 ++#define BDRAM_SIDX_MASK GENMASK(7, 0) ++#define BDRAM_MAX_MASK GENMASK(15, 8) ++#define BDRAM_MIN_MASK GENMASK(23, 16) ++ ++#define R_AX_PCIE_INIT_CFG1 0x1000 ++#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) ++#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) ++#define B_AX_PCIE_PERST_KEEP_REG BIT(21) ++#define B_AX_PCIE_FLR_KEEP_REG BIT(20) ++#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) ++#define B_AX_RXBD_MODE BIT(18) ++#define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14) ++#define B_AX_RXHCI_EN BIT(13) ++#define B_AX_LATENCY_CONTROL BIT(12) ++#define B_AX_TXHCI_EN BIT(11) ++#define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8) ++#define B_AX_TX_TRUNC_MODE BIT(5) ++#define B_AX_RX_TRUNC_MODE BIT(4) ++#define B_AX_RST_BDRAM BIT(3) ++#define B_AX_DIS_RXDMA_PRE BIT(2) ++ ++#define R_AX_TXDMA_ADDR_H 0x10F0 ++#define R_AX_RXDMA_ADDR_H 0x10F4 ++ ++#define R_AX_PCIE_DMA_STOP1 0x1010 ++#define B_AX_STOP_PCIEIO BIT(20) ++#define B_AX_STOP_WPDMA BIT(19) ++#define B_AX_STOP_CH12 BIT(18) ++#define B_AX_STOP_CH9 BIT(17) ++#define B_AX_STOP_CH8 BIT(16) ++#define B_AX_STOP_ACH7 BIT(15) ++#define B_AX_STOP_ACH6 BIT(14) ++#define B_AX_STOP_ACH5 BIT(13) ++#define B_AX_STOP_ACH4 BIT(12) ++#define B_AX_STOP_ACH3 BIT(11) ++#define B_AX_STOP_ACH2 BIT(10) ++#define B_AX_STOP_ACH1 BIT(9) ++#define B_AX_STOP_ACH0 BIT(8) ++#define B_AX_STOP_RPQ BIT(1) ++#define B_AX_STOP_RXQ BIT(0) ++#define B_AX_TX_STOP1_ALL GENMASK(18, 8) ++ ++#define R_AX_PCIE_DMA_STOP2 0x1310 ++#define B_AX_STOP_CH11 BIT(1) ++#define B_AX_STOP_CH10 BIT(0) ++#define B_AX_TX_STOP2_ALL GENMASK(1, 0) ++ ++#define R_AX_TXBD_RWPTR_CLR1 0x1014 ++#define B_AX_CLR_CH12_IDX BIT(10) ++#define B_AX_CLR_CH9_IDX BIT(9) ++#define B_AX_CLR_CH8_IDX BIT(8) ++#define B_AX_CLR_ACH7_IDX BIT(7) ++#define B_AX_CLR_ACH6_IDX BIT(6) ++#define B_AX_CLR_ACH5_IDX BIT(5) ++#define B_AX_CLR_ACH4_IDX BIT(4) ++#define B_AX_CLR_ACH3_IDX BIT(3) ++#define B_AX_CLR_ACH2_IDX BIT(2) ++#define B_AX_CLR_ACH1_IDX BIT(1) ++#define B_AX_CLR_ACH0_IDX BIT(0) ++#define B_AX_TXBD_CLR1_ALL GENMASK(10, 0) ++ ++#define R_AX_RXBD_RWPTR_CLR 0x1018 ++#define B_AX_CLR_RPQ_IDX BIT(1) ++#define B_AX_CLR_RXQ_IDX BIT(0) ++#define B_AX_RXBD_CLR_ALL GENMASK(1, 0) ++ ++#define R_AX_TXBD_RWPTR_CLR2 0x1314 ++#define B_AX_CLR_CH11_IDX BIT(1) ++#define B_AX_CLR_CH10_IDX BIT(0) ++#define B_AX_TXBD_CLR2_ALL GENMASK(1, 0) ++ ++#define R_AX_PCIE_DMA_BUSY1 0x101C ++#define B_AX_PCIEIO_RX_BUSY BIT(22) ++#define B_AX_PCIEIO_TX_BUSY BIT(21) ++#define B_AX_PCIEIO_BUSY BIT(20) ++#define B_AX_WPDMA_BUSY BIT(19) ++ ++#define R_AX_PCIE_DMA_BUSY2 0x131C ++#define B_AX_CH11_BUSY BIT(1) ++#define B_AX_CH10_BUSY BIT(0) ++ ++/* Configure */ ++#define R_AX_PCIE_INIT_CFG1 0x1000 ++#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) ++#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) ++#define B_AX_DIS_RXDMA_PRE BIT(2) ++ ++#define R_AX_PCIE_INIT_CFG2 0x1004 ++#define B_AX_WD_ITVL_IDLE GENMASK(27, 24) ++#define B_AX_WD_ITVL_ACT GENMASK(19, 16) ++ ++#define R_AX_PCIE_PS_CTRL 0x1008 ++#define B_AX_L1OFF_PWR_OFF_EN BIT(5) ++ ++#define R_AX_INT_MIT_RX 0x10D4 ++#define B_AX_RXMIT_RXP2_SEL BIT(19) ++#define B_AX_RXMIT_RXP1_SEL BIT(18) ++#define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16) ++#define AX_RXTIMER_UNIT_64US 0 ++#define AX_RXTIMER_UNIT_128US 1 ++#define AX_RXTIMER_UNIT_256US 2 ++#define AX_RXTIMER_UNIT_512US 3 ++#define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8) ++#define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0) ++ ++#define R_AX_DBG_ERR_FLAG 0x11C4 ++#define B_AX_PCIE_RPQ_FULL BIT(29) ++#define B_AX_PCIE_RXQ_FULL BIT(28) ++#define B_AX_CPL_STATUS_MASK GENMASK(27, 25) ++#define B_AX_RX_STUCK BIT(22) ++#define B_AX_TX_STUCK BIT(21) ++#define B_AX_PCIEDBG_TXERR0 BIT(16) ++#define B_AX_PCIE_RXP1_ERR0 BIT(4) ++#define B_AX_PCIE_TXBD_LEN0 BIT(1) ++#define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) ++ ++#define R_AX_LBC_WATCHDOG 0x11D8 ++#define B_AX_LBC_TIMER GENMASK(7, 4) ++#define B_AX_LBC_FLAG BIT(1) ++#define B_AX_LBC_EN BIT(0) ++ ++#define R_AX_PCIE_EXP_CTRL 0x13F0 ++#define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) ++#define B_AX_MAX_TAG_NUM GENMASK(18, 16) ++#define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) ++ ++#define R_AX_PCIE_RX_PREF_ADV 0x13F4 ++#define B_AX_RXDMA_PREF_ADV_EN BIT(0) ++ ++#define RTW89_PCI_TXBD_NUM_MAX 256 ++#define RTW89_PCI_RXBD_NUM_MAX 256 ++#define RTW89_PCI_TXWD_NUM_MAX 512 ++#define RTW89_PCI_TXWD_PAGE_SIZE 128 ++#define RTW89_PCI_ADDRINFO_MAX 4 ++#define RTW89_PCI_RX_BUF_SIZE 11460 ++ ++#define RTW89_PCI_POLL_BDRAM_RST_CNT 100 ++#define RTW89_PCI_MULTITAG 8 ++ ++/* PCIE CFG register */ ++#define RTW89_PCIE_TIMER_CTRL 0x0718 ++#define RTW89_PCIE_BIT_L1SUB BIT(5) ++#define RTW89_PCIE_L1_CTRL 0x0719 ++#define RTW89_PCIE_BIT_CLK BIT(4) ++#define RTW89_PCIE_BIT_L1 BIT(3) ++#define RTW89_PCIE_CLK_CTRL 0x0725 ++#define RTW89_PCIE_RST_MSTATE 0x0B48 ++#define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0) ++#define RTW89_PCIE_PHY_RATE 0x82 ++#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0) ++#define INTF_INTGRA_MINREF_V1 90 ++#define INTF_INTGRA_HOSTREF_V1 100 ++ ++enum rtw89_pcie_phy { ++ PCIE_PHY_GEN1, ++ PCIE_PHY_GEN2, ++ PCIE_PHY_GEN1_UNDEFINE = 0x7F, ++}; ++ ++enum mac_ax_func_sw { ++ MAC_AX_FUNC_DIS, ++ MAC_AX_FUNC_EN, ++}; ++ ++enum rtw89_pcie_clkdly_hw { ++ PCIE_CLKDLY_HW_0 = 0, ++ PCIE_CLKDLY_HW_30US = 0x1, ++ PCIE_CLKDLY_HW_50US = 0x2, ++ PCIE_CLKDLY_HW_100US = 0x3, ++ PCIE_CLKDLY_HW_150US = 0x4, ++ PCIE_CLKDLY_HW_200US = 0x5 ++}; ++ ++struct rtw89_pci_bd_ram { ++ u8 start_idx; ++ u8 max_num; ++ u8 min_num; ++}; ++ ++struct rtw89_pci_tx_data { ++ dma_addr_t dma; ++}; ++ ++struct rtw89_pci_rx_info { ++ dma_addr_t dma; ++ u32 fs:1, ls:1, tag:11, len:14; ++}; ++ ++#define RTW89_PCI_TXBD_OPTION_LS BIT(14) ++ ++struct rtw89_pci_tx_bd_32 { ++ __le16 length; ++ __le16 option; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_TXWP_VALID BIT(15) ++ ++struct rtw89_pci_tx_wp_info { ++ __le16 seq0; ++ __le16 seq1; ++ __le16 seq2; ++ __le16 seq3; ++} __packed; ++ ++#define RTW89_PCI_ADDR_MSDU_LS BIT(15) ++#define RTW89_PCI_ADDR_LS BIT(14) ++#define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6)) ++#define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0)) ++ ++struct rtw89_pci_tx_addr_info_32 { ++ __le16 length; ++ __le16 option; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_RPP_POLLUTED BIT(31) ++#define RTW89_PCI_RPP_SEQ GENMASK(30, 16) ++#define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13) ++#define RTW89_TX_DONE 0x0 ++#define RTW89_TX_RETRY_LIMIT 0x1 ++#define RTW89_TX_LIFE_TIME 0x2 ++#define RTW89_TX_MACID_DROP 0x3 ++#define RTW89_PCI_RPP_QSEL GENMASK(12, 8) ++#define RTW89_PCI_RPP_MACID GENMASK(7, 0) ++ ++struct rtw89_pci_rpp_fmt { ++ __le32 dword; ++} __packed; ++ ++struct rtw89_pci_rx_bd_32 { ++ __le16 buf_size; ++ __le16 rsvd; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_RXBD_FS BIT(15) ++#define RTW89_PCI_RXBD_LS BIT(14) ++#define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0) ++#define RTW89_PCI_RXBD_TAG GENMASK(28, 16) ++ ++struct rtw89_pci_rxbd_info { ++ __le32 dword; ++}; ++ ++struct rtw89_pci_tx_wd { ++ struct list_head list; ++ struct sk_buff_head queue; ++ ++ void *vaddr; ++ dma_addr_t paddr; ++ u32 len; ++ u32 seq; ++}; ++ ++struct rtw89_pci_dma_ring { ++ void *head; ++ u8 desc_size; ++ dma_addr_t dma; ++ ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ ++ u32 len; ++ u32 wp; /* host idx */ ++ u32 rp; /* hw idx */ ++}; ++ ++struct rtw89_pci_tx_wd_ring { ++ void *head; ++ dma_addr_t dma; ++ ++ struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX]; ++ struct list_head free_pages; ++ ++ u32 page_size; ++ u32 page_num; ++ u32 curr_num; ++}; ++ ++#define RTW89_RX_TAG_MAX 0x1fff ++ ++struct rtw89_pci_tx_ring { ++ struct rtw89_pci_tx_wd_ring wd_ring; ++ struct rtw89_pci_dma_ring bd_ring; ++ struct list_head busy_pages; ++ u8 txch; ++ bool dma_enabled; ++ u16 tag; /* range from 0x0001 ~ 0x1fff */ ++ ++ u64 tx_cnt; ++ u64 tx_acked; ++ u64 tx_retry_lmt; ++ u64 tx_life_time; ++ u64 tx_mac_id_drop; ++}; ++ ++struct rtw89_pci_rx_ring { ++ struct rtw89_pci_dma_ring bd_ring; ++ struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; ++ u32 buf_sz; ++ struct sk_buff *diliver_skb; ++ struct rtw89_rx_desc_info diliver_desc; ++}; ++ ++struct rtw89_pci_isrs { ++ u32 halt_c2h_isrs; ++ u32 isrs[2]; ++}; ++ ++struct rtw89_pci { ++ struct pci_dev *pdev; ++ ++ /* protect HW irq related registers */ ++ spinlock_t irq_lock; ++ /* protect TRX resources (exclude RXQ) */ ++ spinlock_t trx_lock; ++ bool running; ++ struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; ++ struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; ++ struct sk_buff_head h2c_queue; ++ struct sk_buff_head h2c_release_queue; ++ ++ u32 halt_c2h_intrs; ++ u32 intrs[2]; ++ u16 link_ctrl; ++ void __iomem *mmap; ++}; ++ ++static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ ++ BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > ++ sizeof(info->status.status_driver_data)); ++ ++ return (struct rtw89_pci_rx_info *)skb->cb; ++} ++ ++static inline struct rtw89_pci_rx_bd_32 * ++RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u8 *head = bd_ring->head; ++ u32 desc_size = bd_ring->desc_size; ++ u32 offset = idx * desc_size; ++ ++ return (struct rtw89_pci_rx_bd_32 *)(head + offset); ++} ++ ++static inline void ++rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ ++ bd_ring->wp += cnt; ++ ++ if (bd_ring->wp >= bd_ring->len) ++ bd_ring->wp -= bd_ring->len; ++} ++ ++static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ ++ return (struct rtw89_pci_tx_data *)info->status.status_driver_data; ++} ++ ++static inline struct rtw89_pci_tx_bd_32 * ++rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ struct rtw89_pci_tx_bd_32 *tx_bd, *head; ++ ++ head = bd_ring->head; ++ tx_bd = head + bd_ring->wp; ++ ++ return tx_bd; ++} ++ ++static inline struct rtw89_pci_tx_wd * ++rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ ++ txwd = list_first_entry_or_null(&wd_ring->free_pages, ++ struct rtw89_pci_tx_wd, list); ++ if (!txwd) ++ return NULL; ++ ++ list_del_init(&txwd->list); ++ txwd->len = 0; ++ wd_ring->curr_num--; ++ ++ return txwd; ++} ++ ++static inline void ++rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ ++ memset(txwd->vaddr, 0, wd_ring->page_size); ++ list_add_tail(&txwd->list, &wd_ring->free_pages); ++ wd_ring->curr_num++; ++} ++ ++static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) ++{ ++ return val == 0xffffffff || val == 0xeaeaeaea; ++} ++ ++extern const struct dev_pm_ops rtw89_pm_ops; ++ ++#endif + +From patchwork Fri Aug 20 04:35:24 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448379 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id F25B3C432BE + for ; + Fri, 20 Aug 2021 04:37:14 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id C808160F91 + for ; + Fri, 20 Aug 2021 04:37:14 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S234853AbhHTEhu (ORCPT + ); + Fri, 20 Aug 2021 00:37:50 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39253 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233877AbhHTEhr (ORCPT + ); + Fri, 20 Aug 2021 00:37:47 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4b6cdD004017, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4b6cdD004017 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:06 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:05 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:04 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 10/24] rtw89: add phy files +Date: Fri, 20 Aug 2021 12:35:24 +0800 +Message-ID: <20210820043538.12424-11-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Implement PHY functions, such as read/write PHY and RF registers, parser of +table, RA, CFO and DIG. + +To manipulate PHY registers, we provide basic interfaces to read/write PHY +registers, and indirectly access to RF registers with rf_mutex protection. + +The formatted tables of PHY and RF parameters that are written in +rtw8852a_table.c need a parser to set to registers. + +RA (Rate adaptive) +RA is used to tell firmware rate mask that is used to transmit data; +the rate mask is decided by association capability and rssi strength. +RA report reported by firmware via C2H is used to calculate amsdu length. + +CFO (Central frequency offset) tracking +Track CFO by accumulating CFO reported by RX PPDU status. Then, we have +average offset to adjust CFO crystal in track work every 2 seconds. + +DIG (Dynamic initial gain) tracking +Track DIG by average RSSI reported by RX PPDU status basically, and +also measure channel loading to make decision. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/phy.c | 2748 ++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/phy.h | 305 +++ + 2 files changed, 3053 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/phy.c + create mode 100644 drivers/net/wireless/realtek/rtw89/phy.h + +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +new file mode 100644 +index 000000000000..8548f15e9941 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -0,0 +1,2748 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "fw.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++ ++static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, ++ const struct rtw89_ra_report *report) ++{ ++ const struct rate_info *txrate = &report->txrate; ++ u32 bit_rate = report->bit_rate; ++ u8 mcs; ++ ++ /* lower than ofdm, do not aggregate */ ++ if (bit_rate < 550) ++ return 1; ++ ++ /* prevent hardware rate fallback to G mode rate */ ++ if (txrate->flags & RATE_INFO_FLAGS_MCS) ++ mcs = txrate->mcs & 0x07; ++ else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) ++ mcs = txrate->mcs; ++ else ++ mcs = 0; ++ ++ if (mcs <= 2) ++ return 1; ++ ++ /* lower than 20M vht 2ss mcs8, make it small */ ++ if (bit_rate < 1800) ++ return 1200; ++ ++ /* lower than 40M vht 2ss mcs9, make it medium */ ++ if (bit_rate < 4000) ++ return 2600; ++ ++ /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ ++ if (bit_rate < 7000) ++ return 3500; ++ ++ return rtwdev->chip->max_amsdu_limit; ++} ++ ++static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) ++{ ++ u64 ra_mask = 0; ++ u8 mcs_cap; ++ int i, nss; ++ ++ for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { ++ mcs_cap = mcs_map & 0x3; ++ switch (mcs_cap) { ++ case 2: ++ ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; ++ break; ++ case 1: ++ ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; ++ break; ++ case 0: ++ ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return ra_mask; ++} ++ ++static u64 get_he_ra_mask(struct ieee80211_sta *sta) ++{ ++ struct ieee80211_sta_he_cap cap = sta->he_cap; ++ u16 mcs_map; ++ ++ switch (sta->bandwidth) { ++ case IEEE80211_STA_RX_BW_160: ++ if (cap.he_cap_elem.phy_cap_info[0] & ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); ++ else ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); ++ break; ++ default: ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); ++ } ++ ++ /* MCS11, MCS9, MCS7 */ ++ return get_mcs_ra_mask(mcs_map, 11, 2); ++} ++ ++#define RA_FLOOR_TABLE_SIZE 7 ++#define RA_FLOOR_UP_GAP 3 ++static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ u8 ratr_state) ++{ ++ u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; ++ u8 rssi_lv = 0; ++ u8 i; ++ ++ rssi >>= 1; ++ for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { ++ if (i >= ratr_state) ++ rssi_lv_t[i] += RA_FLOOR_UP_GAP; ++ if (rssi < rssi_lv_t[i]) { ++ rssi_lv = i; ++ break; ++ } ++ } ++ if (rssi_lv == 0) ++ return 0xffffffffffffffffULL; ++ else if (rssi_lv == 1) ++ return 0xfffffffffffffff0ULL; ++ else if (rssi_lv == 2) ++ return 0xffffffffffffffe0ULL; ++ else if (rssi_lv == 3) ++ return 0xffffffffffffffc0ULL; ++ else if (rssi_lv == 4) ++ return 0xffffffffffffff80ULL; ++ else if (rssi_lv >= 5) ++ return 0xffffffffffffff00ULL; ++ ++ return 0xffffffffffffffffULL; ++} ++ ++static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); ++ struct cfg80211_bitrate_mask *mask = &rtwsta->mask; ++ enum nl80211_band band; ++ u64 cfg_mask; ++ ++ if (!rtwsta->use_cfg_mask) ++ return -1; ++ ++ switch (hal->current_band_type) { ++ case RTW89_BAND_2G: ++ band = NL80211_BAND_2GHZ; ++ cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, ++ RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); ++ break; ++ case RTW89_BAND_5G: ++ band = NL80211_BAND_5GHZ; ++ cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, ++ RA_MASK_OFDM_RATES); ++ break; ++ default: ++ rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); ++ return -1; ++ } ++ ++ if (sta->he_cap.has_he) { ++ cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], ++ RA_MASK_HE_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], ++ RA_MASK_HE_2SS_RATES); ++ } else if (sta->vht_cap.vht_supported) { ++ cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], ++ RA_MASK_VHT_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], ++ RA_MASK_VHT_2SS_RATES); ++ } else if (sta->ht_cap.ht_supported) { ++ cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], ++ RA_MASK_HT_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], ++ RA_MASK_HT_2SS_RATES); ++ } ++ ++ return cfg_mask; ++} ++ ++static const u64 ++rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, ++ RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; ++static const u64 ++rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, ++ RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; ++static const u64 ++rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, ++ RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; ++ ++static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool csi) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; ++ u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); ++ u64 high_rate_mask = 0; ++ u64 ra_mask = 0; ++ u8 mode = 0; ++ u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; ++ u8 bw_mode = 0; ++ u8 stbc_en = 0; ++ u8 ldpc_en = 0; ++ u8 i; ++ bool sgi = false; ++ ++ memset(ra, 0, sizeof(*ra)); ++ /* Set the ra mask from sta's capability */ ++ if (sta->he_cap.has_he) { ++ mode |= RTW89_RA_MODE_HE; ++ csi_mode = RTW89_RA_RPT_MODE_HE; ++ ra_mask |= get_he_ra_mask(sta); ++ high_rate_masks = rtw89_ra_mask_he_rates; ++ if (sta->he_cap.he_cap_elem.phy_cap_info[2] & ++ IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) ++ stbc_en = 1; ++ if (sta->he_cap.he_cap_elem.phy_cap_info[1] & ++ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) ++ ldpc_en = 1; ++ } else if (sta->vht_cap.vht_supported) { ++ u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); ++ ++ mode |= RTW89_RA_MODE_VHT; ++ csi_mode = RTW89_RA_RPT_MODE_VHT; ++ /* MCS9, MCS8, MCS7 */ ++ ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); ++ high_rate_masks = rtw89_ra_mask_vht_rates; ++ if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) ++ stbc_en = 1; ++ if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) ++ ldpc_en = 1; ++ } else if (sta->ht_cap.ht_supported) { ++ mode |= RTW89_RA_MODE_HT; ++ csi_mode = RTW89_RA_RPT_MODE_HT; ++ ra_mask |= ((u64)sta->ht_cap.mcs.rx_mask[3] << 48) | ++ ((u64)sta->ht_cap.mcs.rx_mask[2] << 36) | ++ (sta->ht_cap.mcs.rx_mask[1] << 24) | ++ (sta->ht_cap.mcs.rx_mask[0] << 12); ++ high_rate_masks = rtw89_ra_mask_ht_rates; ++ if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) ++ stbc_en = 1; ++ if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) ++ ldpc_en = 1; ++ } ++ ++ if (rtwdev->hal.current_band_type == RTW89_BAND_2G) { ++ if (sta->supp_rates[NL80211_BAND_2GHZ] <= 0xf) ++ mode |= RTW89_RA_MODE_CCK; ++ else ++ mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; ++ } else { ++ mode |= RTW89_RA_MODE_OFDM; ++ } ++ ++ if (mode >= RTW89_RA_MODE_HT) { ++ for (i = 0; i < rtwdev->hal.tx_nss; i++) ++ high_rate_mask |= high_rate_masks[i]; ++ ra_mask &= high_rate_mask; ++ if (mode & RTW89_RA_MODE_OFDM) ++ ra_mask |= RA_MASK_SUBOFDM_RATES; ++ if (mode & RTW89_RA_MODE_CCK) ++ ra_mask |= RA_MASK_SUBCCK_RATES; ++ } else if (mode & RTW89_RA_MODE_OFDM) { ++ if (mode & RTW89_RA_MODE_CCK) ++ ra_mask |= RA_MASK_SUBCCK_RATES; ++ ra_mask |= RA_MASK_OFDM_RATES; ++ } else { ++ ra_mask = RA_MASK_CCK_RATES; ++ } ++ ++ if (mode != RTW89_RA_MODE_CCK) { ++ ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); ++ ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); ++ } ++ ++ switch (sta->bandwidth) { ++ case IEEE80211_STA_RX_BW_80: ++ bw_mode = RTW89_CHANNEL_WIDTH_80; ++ sgi = sta->vht_cap.vht_supported && ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); ++ break; ++ case IEEE80211_STA_RX_BW_40: ++ bw_mode = RTW89_CHANNEL_WIDTH_40; ++ sgi = sta->ht_cap.ht_supported && ++ (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); ++ break; ++ default: ++ bw_mode = RTW89_CHANNEL_WIDTH_20; ++ sgi = sta->ht_cap.ht_supported && ++ (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); ++ break; ++ } ++ ++ if (sta->he_cap.he_cap_elem.phy_cap_info[3] & ++ IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) ++ ra->dcm_cap = 1; ++ ++ ra->bw_cap = bw_mode; ++ ra->mode_ctrl = mode; ++ ra->macid = rtwsta->mac_id; ++ ra->stbc_cap = stbc_en; ++ ra->ldpc_cap = ldpc_en; ++ ra->ss_num = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; ++ ra->en_sgi = sgi; ++ ra->ra_mask = ra_mask; ++ ++ if (!csi) ++ return; ++ ++ ra->fixed_csi_rate_en = false; ++ ra->ra_csi_rate_en = true; ++ ra->cr_tbl_sel = false; ++ ra->band_num = rtwvif->phy_idx; ++ ra->csi_bw = bw_mode; ++ ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; ++ ra->csi_mcs_ss_idx = 5; ++ ra->csi_mode = csi_mode; ++} ++ ++void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ ++ rtw89_phy_ra_sta_update(rtwdev, sta, false); ++ ra->upd_mask = 1; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", ++ ra->macid, ++ ra->bw_cap, ++ ra->ss_num, ++ ra->en_sgi, ++ ra->giltf); ++ ++ rtw89_fw_h2c_ra(rtwdev, ra, false); ++} ++ ++static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; ++ ++ rtw89_phy_ra_updata_sta(rtwdev, sta); ++} ++ ++void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) ++{ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_ra_updata_sta_iter, ++ rtwdev); ++} ++ ++void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; ++ bool csi = rtw89_sta_has_beamformer_cap(sta); ++ ++ rtw89_phy_ra_sta_update(rtwdev, sta, csi); ++ ++ if (rssi > 40) ++ ra->init_rate_lv = 1; ++ else if (rssi > 20) ++ ra->init_rate_lv = 2; ++ else if (rssi > 1) ++ ra->init_rate_lv = 3; ++ else ++ ra->init_rate_lv = 0; ++ ra->upd_all = 1; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", ++ ra->macid, ++ ra->mode_ctrl, ++ ra->bw_cap, ++ ra->ss_num, ++ ra->init_rate_lv); ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", ++ ra->dcm_cap, ++ ra->er_cap, ++ ra->ldpc_cap, ++ ra->stbc_cap, ++ ra->en_sgi, ++ ra->giltf); ++ ++ rtw89_fw_h2c_ra(rtwdev, ra, csi); ++} ++ ++u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_bandwidth dbw) ++{ ++ enum rtw89_bandwidth cbw = param->bandwidth; ++ u8 pri_ch = param->primary_chan; ++ u8 central_ch = param->center_chan; ++ u8 txsc_idx = 0; ++ u8 tmp = 0; ++ ++ if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) ++ return txsc_idx; ++ ++ switch (cbw) { ++ case RTW89_CHANNEL_WIDTH_40: ++ txsc_idx = pri_ch > central_ch ? 1 : 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ if (pri_ch > central_ch) ++ txsc_idx = (pri_ch - central_ch) >> 1; ++ else ++ txsc_idx = ((central_ch - pri_ch) >> 1) + 1; ++ } else { ++ txsc_idx = pri_ch > central_ch ? 9 : 10; ++ } ++ break; ++ case RTW89_CHANNEL_WIDTH_160: ++ if (pri_ch > central_ch) ++ tmp = (pri_ch - central_ch) >> 1; ++ else ++ tmp = ((central_ch - pri_ch) >> 1) + 1; ++ ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ txsc_idx = tmp; ++ } else if (dbw == RTW89_CHANNEL_WIDTH_40) { ++ if (tmp == 1 || tmp == 3) ++ txsc_idx = 9; ++ else if (tmp == 5 || tmp == 7) ++ txsc_idx = 11; ++ else if (tmp == 2 || tmp == 4) ++ txsc_idx = 10; ++ else if (tmp == 6 || tmp == 8) ++ txsc_idx = 12; ++ else ++ return 0xff; ++ } else { ++ txsc_idx = pri_ch > central_ch ? 13 : 14; ++ } ++ break; ++ case RTW89_CHANNEL_WIDTH_80_80: ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ if (pri_ch > central_ch) ++ txsc_idx = (10 - (pri_ch - central_ch)) >> 1; ++ else ++ txsc_idx = ((central_ch - pri_ch) >> 1) + 5; ++ } else if (dbw == RTW89_CHANNEL_WIDTH_40) { ++ txsc_idx = pri_ch > central_ch ? 10 : 12; ++ } else { ++ txsc_idx = 14; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return txsc_idx; ++} ++ ++u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const u32 *base_addr = chip->rf_base_addr; ++ u32 val, direct_addr; ++ ++ if (rf_path >= rtwdev->chip->rf_path_num) { ++ rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); ++ return INV_RF_DATA; ++ } ++ ++ addr &= 0xff; ++ direct_addr = base_addr[rf_path] + (addr << 2); ++ mask &= RFREG_MASK; ++ ++ val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); ++ ++ return val; ++} ++EXPORT_SYMBOL(rtw89_phy_read_rf); ++ ++bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const u32 *base_addr = chip->rf_base_addr; ++ u32 direct_addr; ++ ++ if (rf_path >= rtwdev->chip->rf_path_num) { ++ rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); ++ return false; ++ } ++ ++ addr &= 0xff; ++ direct_addr = base_addr[rf_path] + (addr << 2); ++ mask &= RFREG_MASK; ++ ++ rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); ++ ++ /* delay to ensure writing properly */ ++ udelay(1); ++ ++ return true; ++} ++EXPORT_SYMBOL(rtw89_phy_write_rf); ++ ++static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ chip->ops->bb_reset(rtwdev, phy_idx); ++} ++ ++static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *extra_data) ++{ ++ if (reg->addr == 0xfe) ++ mdelay(50); ++ else if (reg->addr == 0xfd) ++ mdelay(5); ++ else if (reg->addr == 0xfc) ++ mdelay(1); ++ else if (reg->addr == 0xfb) ++ udelay(50); ++ else if (reg->addr == 0xfa) ++ udelay(5); ++ else if (reg->addr == 0xf9) ++ udelay(1); ++ else ++ rtw89_phy_write32(rtwdev, reg->addr, reg->data); ++} ++ ++static void ++rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ struct rtw89_fw_h2c_rf_reg_info *info) ++{ ++ u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; ++ u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; ++ ++ info->rtw89_phy_config_rf_h2c[page][idx] = ++ cpu_to_le32((reg->addr << 20) | reg->data); ++ info->curr_idx++; ++} ++ ++static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info) ++{ ++ u16 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; ++ u16 len = (info->curr_idx % RTW89_H2C_RF_PAGE_SIZE) * 4; ++ u8 i; ++ int ret = 0; ++ ++ if (page > RTW89_H2C_RF_PAGE_NUM) { ++ rtw89_warn(rtwdev, ++ "rf reg h2c total page num %d larger than %d (RTW89_H2C_RF_PAGE_NUM)\n", ++ page, RTW89_H2C_RF_PAGE_NUM); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < page; i++) { ++ ret = rtw89_fw_h2c_rf_reg(rtwdev, info, ++ RTW89_H2C_RF_PAGE_SIZE * 4, i); ++ if (ret) ++ return ret; ++ } ++ ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len, i); ++ if (ret) ++ return ret; ++ info->curr_idx = 0; ++ ++ return 0; ++} ++ ++static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *extra_data) ++{ ++ if (reg->addr == 0xfe) { ++ mdelay(50); ++ } else if (reg->addr == 0xfd) { ++ mdelay(5); ++ } else if (reg->addr == 0xfc) { ++ mdelay(1); ++ } else if (reg->addr == 0xfb) { ++ udelay(50); ++ } else if (reg->addr == 0xfa) { ++ udelay(5); ++ } else if (reg->addr == 0xf9) { ++ udelay(1); ++ } else { ++ rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); ++ rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, ++ (struct rtw89_fw_h2c_rf_reg_info *)extra_data); ++ } ++} ++ ++static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_table *table, ++ u32 *headline_size, u32 *headline_idx, ++ u8 rfe, u8 cv) ++{ ++ const struct rtw89_reg2_def *reg; ++ u32 headline; ++ u32 compare, target; ++ u8 rfe_para, cv_para; ++ u8 cv_max = 0; ++ bool case_matched = false; ++ u32 i; ++ ++ for (i = 0; i < table->n_regs; i++) { ++ reg = &table->regs[i]; ++ headline = get_phy_headline(reg->addr); ++ if (headline != PHY_HEADLINE_VALID) ++ break; ++ } ++ *headline_size = i; ++ if (*headline_size == 0) ++ return 0; ++ ++ /* case 1: RFE match, CV match */ ++ compare = get_phy_compare(rfe, cv); ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ target = get_phy_target(reg->addr); ++ if (target == compare) { ++ *headline_idx = i; ++ return 0; ++ } ++ } ++ ++ /* case 2: RFE match, CV don't care */ ++ compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ target = get_phy_target(reg->addr); ++ if (target == compare) { ++ *headline_idx = i; ++ return 0; ++ } ++ } ++ ++ /* case 3: RFE match, CV max in table */ ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ rfe_para = get_phy_cond_rfe(reg->addr); ++ cv_para = get_phy_cond_cv(reg->addr); ++ if (rfe_para == rfe) { ++ if (cv_para >= cv_max) { ++ cv_max = cv_para; ++ *headline_idx = i; ++ case_matched = true; ++ } ++ } ++ } ++ ++ if (case_matched) ++ return 0; ++ ++ /* case 4: RFE don't care, CV max in table */ ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ rfe_para = get_phy_cond_rfe(reg->addr); ++ cv_para = get_phy_cond_cv(reg->addr); ++ if (rfe_para == PHY_COND_DONT_CARE) { ++ if (cv_para >= cv_max) { ++ cv_max = cv_para; ++ *headline_idx = i; ++ case_matched = true; ++ } ++ } ++ } ++ ++ if (case_matched) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_table *table, ++ void (*config)(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *data), ++ void *extra_data) ++{ ++ const struct rtw89_reg2_def *reg; ++ enum rtw89_rf_path rf_path = table->rf_path; ++ u8 rfe = rtwdev->efuse.rfe_type; ++ u8 cv = rtwdev->hal.cv; ++ u32 i; ++ u32 headline_size = 0, headline_idx = 0; ++ u32 target = 0, cfg_target; ++ u8 cond; ++ bool is_matched = true; ++ bool target_found = false; ++ int ret; ++ ++ ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, ++ &headline_idx, rfe, cv); ++ if (ret) { ++ rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); ++ return; ++ } ++ ++ cfg_target = get_phy_target(table->regs[headline_idx].addr); ++ for (i = headline_size; i < table->n_regs; i++) { ++ reg = &table->regs[i]; ++ cond = get_phy_cond(reg->addr); ++ switch (cond) { ++ case PHY_COND_BRANCH_IF: ++ case PHY_COND_BRANCH_ELIF: ++ target = get_phy_target(reg->addr); ++ break; ++ case PHY_COND_BRANCH_ELSE: ++ is_matched = false; ++ if (!target_found) { ++ rtw89_warn(rtwdev, "failed to load CR %x/%x\n", ++ reg->addr, reg->data); ++ return; ++ } ++ break; ++ case PHY_COND_BRANCH_END: ++ is_matched = true; ++ target_found = false; ++ break; ++ case PHY_COND_CHECK: ++ if (target_found) { ++ is_matched = false; ++ break; ++ } ++ ++ if (target == cfg_target) { ++ is_matched = true; ++ target_found = true; ++ } else { ++ is_matched = false; ++ target_found = false; ++ } ++ break; ++ default: ++ if (is_matched) ++ config(rtwdev, reg, rf_path, extra_data); ++ break; ++ } ++ } ++} ++ ++void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *bb_table = chip->bb_table; ++ ++ rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); ++ rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); ++ rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); ++} ++ ++static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32(rtwdev, 0x8080, 0x4); ++ udelay(1); ++ return rtw89_phy_read32(rtwdev, 0x8080); ++} ++ ++void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *rf_table; ++ struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; ++ u8 path; ++ ++ rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); ++ if (!rf_reg_info) ++ return; ++ ++ for (path = RF_PATH_A; path < chip->rf_path_num; path++) { ++ rf_reg_info->rf_path = path; ++ rf_table = chip->rf_table[path]; ++ rtw89_phy_init_reg(rtwdev, rf_table, rtw89_phy_config_rf_reg, ++ (void *)rf_reg_info); ++ if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) ++ rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", ++ path); ++ } ++ kfree(rf_reg_info); ++} ++ ++static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *nctl_table; ++ u32 val; ++ int ret; ++ ++ /* IQK/DPK clock & reset */ ++ rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); ++ rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); ++ rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); ++ rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); ++ ++ /* check 0x8080 */ ++ rtw89_phy_write32(rtwdev, 0x8000, 0x8); ++ ++ ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, ++ 1000, false, rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "failed to poll nctl block\n"); ++ ++ nctl_table = chip->nctl_table; ++ rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); ++} ++ ++static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ u32 phy_page = addr >> 8; ++ u32 ofst = 0; ++ ++ switch (phy_page) { ++ case 0x6: ++ case 0x7: ++ case 0x8: ++ case 0x9: ++ case 0xa: ++ case 0xb: ++ case 0xc: ++ case 0xd: ++ case 0x19: ++ case 0x1a: ++ case 0x1b: ++ ofst = 0x2000; ++ break; ++ default: ++ /* warning case */ ++ ofst = 0; ++ break; ++ } ++ ++ if (phy_page >= 0x40 && phy_page <= 0x4f) ++ ofst = 0x2000; ++ ++ return ofst; ++} ++ ++void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 data, enum rtw89_phy_idx phy_idx) ++{ ++ if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) ++ addr += rtw89_phy0_phy1_offset(rtwdev, addr); ++ rtw89_phy_write32_mask(rtwdev, addr, mask, data); ++} ++ ++void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 val) ++{ ++ rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); ++ ++ if (!rtwdev->dbcc_en) ++ return; ++ ++ rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); ++} ++ ++void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_reg3_tbl *tbl) ++{ ++ const struct rtw89_reg3_def *reg3; ++ int i; ++ ++ for (i = 0; i < tbl->size; i++) { ++ reg3 = &tbl->reg3[i]; ++ rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); ++ } ++} ++ ++const u8 rtw89_rs_idx_max[] = { ++ [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, ++ [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, ++ [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, ++ [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, ++ [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, ++}; ++ ++const u8 rtw89_rs_nss_max[] = { ++ [RTW89_RS_CCK] = 1, ++ [RTW89_RS_OFDM] = 1, ++ [RTW89_RS_MCS] = RTW89_NSS_MAX, ++ [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, ++ [RTW89_RS_OFFSET] = 1, ++}; ++ ++static const u8 _byr_of_rs[] = { ++ [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), ++ [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), ++ [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), ++ [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), ++ [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), ++}; ++ ++#define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) ++#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) ++#define _byr_chk(rs, nss, idx) \ ++ ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) ++ ++void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl) ++{ ++ const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; ++ const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; ++ s8 *byr; ++ u32 data; ++ u8 i, idx; ++ ++ for (; cfg < end; cfg++) { ++ byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); ++ data = cfg->data; ++ ++ for (i = 0; i < cfg->len; i++, data >>= 8) { ++ idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); ++ byr[idx] = (s8)(data & 0xff); ++ } ++ } ++} ++ ++#define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ ++({ \ ++ const struct rtw89_chip_info *__c = (rtwdev)->chip; \ ++ (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ ++}) ++ ++s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_rate_desc *rate_desc) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ s8 *byr; ++ u8 idx; ++ ++ if (rate_desc->rs == RTW89_RS_CCK) ++ band = RTW89_BAND_2G; ++ ++ if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", ++ rate_desc->rs, rate_desc->nss, rate_desc->idx); ++ ++ return 0; ++ } ++ ++ byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); ++ idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); ++ ++ return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); ++} ++ ++static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel) ++{ ++ switch (channel) { ++ case 1 ... 14: ++ return channel - 1; ++ case 36 ... 64: ++ return (channel - 36) / 2; ++ case 100 ... 144: ++ return ((channel - 100) / 2) + 15; ++ case 149 ... 177: ++ return ((channel - 149) / 2) + 38; ++ default: ++ rtw89_warn(rtwdev, "unknown channel: %d\n", channel); ++ return 0; ++ } ++} ++ ++s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, ++ u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ s8 lmt = 0, sar; ++ ++ switch (band) { ++ case RTW89_BAND_2G: ++ lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; ++ break; ++ case RTW89_BAND_5G: ++ lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; ++ break; ++ default: ++ rtw89_warn(rtwdev, "unknown band type: %d\n", band); ++ return 0; ++ } ++ ++ lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); ++ sar = rtw89_query_sar(rtwdev); ++ ++ return min(lmt, sar); ++} ++ ++#define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ ++ do { \ ++ u8 __i; \ ++ for (__i = 0; __i < RTW89_BF_NUM; __i++) \ ++ ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ ++ bw, ntx, \ ++ rs, __i, \ ++ (ch)); \ ++ } while (0) ++ ++static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch); ++} ++ ++static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_CCK, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch); ++} ++ ++static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ s8 val_0p5_n[RTW89_BF_NUM]; ++ s8 val_0p5_p[RTW89_BF_NUM]; ++ u8 i; ++ ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch - 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch - 4); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch + 4); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, ++ ntx, RTW89_RS_MCS, ch); ++ ++ __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch - 4); ++ __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch + 4); ++ ++ for (i = 0; i < RTW89_BF_NUM; i++) ++ lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); ++} ++ ++void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ ++ memset(lmt, 0, sizeof(*lmt)); ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch); ++ break; ++ } ++} ++ ++static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ u8 ru, u8 ntx, u8 ch) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ s8 lmt_ru = 0, sar; ++ ++ switch (band) { ++ case RTW89_BAND_2G: ++ lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; ++ break; ++ case RTW89_BAND_5G: ++ lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; ++ break; ++ default: ++ rtw89_warn(rtwdev, "unknown band type: %d\n", band); ++ return 0; ++ } ++ ++ lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); ++ sar = rtw89_query_sar(rtwdev); ++ ++ return min(lmt_ru, sar); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 2); ++ lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 2); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 2); ++ lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 2); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 2); ++ lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 2); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 6); ++ lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 2); ++ lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 2); ++ lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 6); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 6); ++ lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 2); ++ lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 2); ++ lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 6); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 6); ++ lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 2); ++ lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 2); ++ lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 6); ++} ++ ++void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ ++ memset(lmt_ru, 0, sizeof(*lmt_ru)); ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ } ++} ++ ++struct rtw89_phy_iter_ra_data { ++ struct rtw89_dev *rtwdev; ++ struct sk_buff *c2h; ++}; ++ ++static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; ++ struct rtw89_dev *rtwdev = ra_data->rtwdev; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_report *ra_report = &rtwsta->ra_report; ++ struct sk_buff *c2h = ra_data->c2h; ++ u8 mode, rate, bw, giltf, mac_id; ++ ++ mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); ++ if (mac_id != rtwsta->mac_id) ++ return; ++ ++ memset(ra_report, 0, sizeof(*ra_report)); ++ ++ rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); ++ bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); ++ giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); ++ mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); ++ ++ switch (mode) { ++ case RTW89_RA_RPT_MODE_LEGACY: ++ ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate); ++ break; ++ case RTW89_RA_RPT_MODE_HT: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; ++ rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), ++ FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); ++ ra_report->txrate.mcs = rate; ++ if (giltf) ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; ++ break; ++ case RTW89_RA_RPT_MODE_VHT: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; ++ ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); ++ ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; ++ if (giltf) ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; ++ break; ++ case RTW89_RA_RPT_MODE_HE: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; ++ ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); ++ ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; ++ if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; ++ else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; ++ else ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; ++ break; ++ } ++ ++ if (bw == RTW89_CHANNEL_WIDTH_80) ++ ra_report->txrate.bw = RATE_INFO_BW_80; ++ else if (bw == RTW89_CHANNEL_WIDTH_40) ++ ra_report->txrate.bw = RATE_INFO_BW_40; ++ else ++ ra_report->txrate.bw = RATE_INFO_BW_20; ++ ++ ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); ++ ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | ++ FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); ++ sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); ++ rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; ++} ++ ++static void ++rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ struct rtw89_phy_iter_ra_data ra_data; ++ ++ ra_data.rtwdev = rtwdev; ++ ra_data.c2h = c2h; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_c2h_ra_rpt_iter, ++ &ra_data); ++} ++ ++static void (*rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, ++ [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, ++ [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, ++}; ++ ++void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ void (*handler)(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = NULL; ++ ++ switch (class) { ++ case RTW89_PHY_C2H_CLASS_RA: ++ if (func < RTW89_PHY_C2H_FUNC_RA_MAX) ++ handler = rtw89_phy_c2h_ra_handler[func]; ++ break; ++ default: ++ rtw89_info(rtwdev, "c2h class %d not support\n", class); ++ return; ++ } ++ if (!handler) { ++ rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, ++ func); ++ return; ++ } ++ handler(rtwdev, skb, len); ++} ++ ++static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) ++{ ++ u32 reg_mask; ++ ++ if (sc_xo) ++ reg_mask = B_AX_XTAL_SC_XO_MASK; ++ else ++ reg_mask = B_AX_XTAL_SC_XI_MASK; ++ ++ return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); ++} ++ ++static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, ++ u8 val) ++{ ++ u32 reg_mask; ++ ++ if (sc_xo) ++ reg_mask = B_AX_XTAL_SC_XO_MASK; ++ else ++ reg_mask = B_AX_XTAL_SC_XI_MASK; ++ ++ rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); ++} ++ ++static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, ++ u8 crystal_cap, bool force) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 sc_xi_val, sc_xo_val; ++ ++ if (!force && cfo->crystal_cap == crystal_cap) ++ return; ++ crystal_cap = clamp_t(u8, crystal_cap, 0, 127); ++ rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); ++ rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); ++ sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); ++ sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); ++ cfo->crystal_cap = sc_xi_val; ++ cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", ++ cfo->x_cap_ofst); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); ++} ++ ++static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 cap; ++ ++ cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; ++ cfo->is_adjust = false; ++ if (cfo->crystal_cap == cfo->def_x_cap) ++ return; ++ cap = cfo->crystal_cap; ++ cap += (cap > cfo->def_x_cap ? -1 : 1); ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, ++ cfo->def_x_cap); ++} ++ ++static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) ++{ ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ s32 cfo_avg_312; ++ s32 dcfo_comp; ++ int sign; ++ ++ if (!is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", ++ is_linked); ++ return; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); ++ if (curr_cfo == 0) ++ return; ++ dcfo_comp = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); ++ sign = curr_cfo > 0 ? 1 : -1; ++ cfo_avg_312 = (curr_cfo << 3) / 5 + sign * dcfo_comp; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); ++ if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) ++ cfo_avg_312 = -cfo_avg_312; ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK, ++ cfo_avg_312); ++} ++ ++static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); ++ rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); ++} ++ ++static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ ++ cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; ++ cfo->crystal_cap = cfo->crystal_cap_default; ++ cfo->def_x_cap = cfo->crystal_cap; ++ cfo->is_adjust = false; ++ cfo->x_cap_ofst = 0; ++ cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; ++ cfo->apply_compensation = false; ++ cfo->residual_cfo_acc = 0; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", ++ cfo->crystal_cap_default); ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); ++ rtw89_dcfo_comp_init(rtwdev); ++ cfo->cfo_timer_ms = 2000; ++ cfo->cfo_trig_by_timer_en = false; ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++} ++ ++static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, ++ s32 curr_cfo) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s8 crystal_cap = cfo->crystal_cap; ++ s32 cfo_abs = abs(curr_cfo); ++ int sign; ++ ++ if (!cfo->is_adjust) { ++ if (cfo_abs > CFO_TRK_ENABLE_TH) ++ cfo->is_adjust = true; ++ } else { ++ if (cfo_abs < CFO_TRK_STOP_TH) ++ cfo->is_adjust = false; ++ } ++ if (!cfo->is_adjust) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); ++ return; ++ } ++ sign = curr_cfo > 0 ? 1 : -1; ++ if (cfo_abs > CFO_TRK_STOP_TH_4) ++ crystal_cap += 7 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_3) ++ crystal_cap += 5 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_2) ++ crystal_cap += 3 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_1) ++ crystal_cap += 1 * sign; ++ else ++ return; ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "X_cap{Curr,Default}={0x%x,0x%x}\n", ++ cfo->crystal_cap, cfo->def_x_cap); ++} ++ ++static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s32 cfo_khz_all = 0; ++ s32 cfo_cnt_all = 0; ++ s32 cfo_all_avg = 0; ++ u8 i; ++ ++ if (rtwdev->total_sta_assoc != 1) ++ return 0; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ cfo_khz_all += cfo->cfo_tail[i]; ++ cfo_cnt_all += cfo->cfo_cnt[i]; ++ cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); ++ cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "CFO track for macid = %d\n", i); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", ++ cfo_khz_all, cfo_cnt_all, cfo_all_avg); ++ return cfo_all_avg; ++} ++ ++static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ s32 target_cfo = 0; ++ s32 cfo_khz_all = 0; ++ s32 cfo_khz_all_tp_wgt = 0; ++ s32 cfo_avg = 0; ++ s32 max_cfo_lb = BIT(31); ++ s32 min_cfo_ub = GENMASK(30, 0); ++ u16 cfo_cnt_all = 0; ++ u8 active_entry_cnt = 0; ++ u8 sta_cnt = 0; ++ u32 tp_all = 0; ++ u64 active_entry = 0; ++ u8 i; ++ u8 cfo_tol = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); ++ if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ cfo_khz_all += cfo->cfo_tail[i]; ++ cfo_cnt_all += cfo->cfo_cnt[i]; ++ cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", ++ cfo_khz_all, cfo_cnt_all, cfo_avg); ++ target_cfo = cfo_avg; ++ } ++ } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ active_entry |= BIT_ULL(i); ++ cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], ++ (s32)cfo->cfo_cnt[i]); ++ cfo_khz_all += cfo->cfo_avg[i]; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Macid=%d, cfo_avg=%d\n", i, ++ cfo->cfo_avg[i]); ++ } ++ sta_cnt = rtwdev->total_sta_assoc; ++ cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", ++ cfo_khz_all, sta_cnt, cfo_avg); ++ target_cfo = cfo_avg; ++ } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); ++ cfo_tol = cfo->sta_cfo_tolerance; ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ sta_cnt++; ++ if (cfo->cfo_cnt[i] != 0) { ++ cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], ++ (s32)cfo->cfo_cnt[i]); ++ active_entry_cnt++; ++ } else { ++ cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; ++ } ++ max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); ++ min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); ++ cfo_khz_all += cfo->cfo_avg[i]; ++ /* need tp for each entry */ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "[%d] cfo_avg=%d, tp=tbd\n", ++ i, cfo->cfo_avg[i]); ++ if (sta_cnt >= rtwdev->total_sta_assoc) ++ break; ++ } ++ tp_all = stats->rx_throughput; /* need tp for each entry */ ++ cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", ++ sta_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", ++ active_entry_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", ++ cfo_khz_all_tp_wgt, cfo_avg); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", ++ max_cfo_lb, min_cfo_ub); ++ if (max_cfo_lb <= min_cfo_ub) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "cfo win_size=%d\n", ++ min_cfo_ub - max_cfo_lb); ++ target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "No intersection of cfo torlence windows\n"); ++ target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); ++ } ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) ++ cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); ++ return target_cfo; ++} ++ ++static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); ++ memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); ++ cfo->packet_count = 0; ++ cfo->packet_count_pre = 0; ++ cfo->cfo_avg_pre = 0; ++} ++ ++static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s32 new_cfo = 0; ++ bool x_cap_update = false; ++ u8 pre_x_cap = cfo->crystal_cap; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", ++ rtwdev->total_sta_assoc); ++ if (rtwdev->total_sta_assoc == 0) { ++ rtw89_phy_cfo_reset(rtwdev); ++ return; ++ } ++ if (cfo->packet_count == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); ++ return; ++ } ++ if (cfo->packet_count == cfo->packet_count_pre) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); ++ return; ++ } ++ if (rtwdev->total_sta_assoc == 1) ++ new_cfo = rtw89_phy_average_cfo_calc(rtwdev); ++ else ++ new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); ++ if (new_cfo == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); ++ return; ++ } ++ rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); ++ cfo->cfo_avg_pre = new_cfo; ++ x_cap_update = cfo->crystal_cap == pre_x_cap ? false : true; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", ++ cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, ++ cfo->x_cap_ofst); ++ if (x_cap_update) { ++ if (new_cfo > 0) ++ new_cfo -= CFO_SW_COMP_FINE_TUNE; ++ else ++ new_cfo += CFO_SW_COMP_FINE_TUNE; ++ } ++ rtw89_dcfo_comp(rtwdev, new_cfo); ++ rtw89_phy_cfo_statistics_reset(rtwdev); ++} ++ ++void rtw89_phy_cfo_track_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ cfo_track_work.work); ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ mutex_lock(&rtwdev->mutex); ++ if (!cfo->cfo_trig_by_timer_en) ++ goto out; ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_phy_cfo_dm(rtwdev); ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, ++ msecs_to_jiffies(cfo->cfo_timer_ms)); ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, ++ msecs_to_jiffies(cfo->cfo_timer_ms)); ++} ++ ++void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ ++ switch (cfo->phy_cfo_status) { ++ case RTW89_PHY_DCFO_STATE_NORMAL: ++ if (stats->tx_throughput >= CFO_TP_UPPER) { ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; ++ cfo->cfo_trig_by_timer_en = true; ++ cfo->cfo_timer_ms = CFO_COMP_PERIOD; ++ rtw89_phy_cfo_start_work(rtwdev); ++ } ++ break; ++ case RTW89_PHY_DCFO_STATE_ENHANCE: ++ if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) { ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->cfo_trig_by_timer_en = false; ++ } ++ if (cfo->cfo_trig_by_timer_en == 1) ++ cfo->phy_cfo_trk_cnt++; ++ if (stats->tx_throughput <= CFO_TP_LOWER) { ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->cfo_trig_by_timer_en = false; ++ } ++ break; ++ default: ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++ cfo->phy_cfo_trk_cnt = 0; ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", ++ stats->tx_throughput, cfo->phy_cfo_status, ++ cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); ++ if (cfo->cfo_trig_by_timer_en) ++ return; ++ rtw89_phy_cfo_dm(rtwdev); ++} ++ ++void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 macid = phy_ppdu->mac_id; ++ ++ cfo->cfo_tail[macid] += cfo_val; ++ cfo->cfo_cnt[macid]++; ++ cfo->packet_count++; ++} ++ ++static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ int i; ++ u8 th; ++ ++ for (i = 0; i < rtwdev->chip->rf_path_num; i++) { ++ th = rtw89_chip_get_thermal(rtwdev, i); ++ if (th) ++ ewma_thermal_add(&phystat->avg_thermal[i], th); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "path(%d) thermal cur=%u avg=%ld", i, th, ++ ewma_thermal_read(&phystat->avg_thermal[i])); ++ } ++} ++ ++struct rtw89_phy_iter_rssi_data { ++ struct rtw89_dev *rtwdev; ++ struct rtw89_phy_ch_info *ch_info; ++}; ++ ++static void rtw89_phy_stat_rssi_update_iter(void *data, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_phy_iter_rssi_data *rssi_data = ++ (struct rtw89_phy_iter_rssi_data *)data; ++ struct rtw89_dev *rtwdev = rssi_data->rtwdev; ++ struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; ++ unsigned long rssi_curr; ++ ++ rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); ++ ++ if (rssi_curr < ch_info->rssi_min) { ++ ch_info->rssi_min = rssi_curr; ++ ch_info->rssi_min_macid = rtwsta->mac_id; ++ } ++ ++ if (rtwsta->prev_rssi == 0) { ++ rtwsta->prev_rssi = rssi_curr; ++ } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { ++ rtwsta->prev_rssi = rssi_curr; ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.wl_sta_notify_work); ++ } ++} ++ ++static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_iter_rssi_data rssi_data; ++ ++ rssi_data.rtwdev = rtwdev; ++ rssi_data.ch_info = &rtwdev->ch_info; ++ rssi_data.ch_info->rssi_min = U8_MAX; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_stat_rssi_update_iter, ++ &rssi_data); ++} ++ ++static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ int i; ++ ++ for (i = 0; i < rtwdev->chip->rf_path_num; i++) ++ ewma_thermal_init(&phystat->avg_thermal[i]); ++ ++ rtw89_phy_stat_thermal_update(rtwdev); ++ ++ memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); ++ memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); ++} ++ ++void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ ++ rtw89_phy_stat_thermal_update(rtwdev); ++ rtw89_phy_stat_rssi_update(rtwdev); ++ ++ phystat->last_pkt_stat = phystat->cur_pkt_stat; ++ memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); ++} ++ ++static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); ++} ++ ++static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); ++} ++ ++static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ env->ccx_manual_ctrl = false; ++ env->ccx_ongoing = false; ++ env->ccx_rac_lv = RTW89_RAC_RELEASE; ++ env->ccx_rpt_stamp = 0; ++ env->ccx_period = 0; ++ env->ccx_unit_idx = RTW89_CCX_32_US; ++ env->ccx_trigger_time = 0; ++ env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, ++ RTW89_CCX_EDCCA_BW20_0); ++} ++ ++static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, ++ u16 score) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u32 numer = 0; ++ u16 ret = 0; ++ ++ numer = report * score + (env->ccx_period >> 1); ++ if (env->ccx_period) ++ ret = numer / env->ccx_period; ++ ++ return ret >= score ? score - 1 : ret; ++} ++ ++static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, ++ u16 time_ms, u32 *period, ++ u32 *unit_idx) ++{ ++ u32 idx; ++ u8 quotient; ++ ++ if (time_ms >= CCX_MAX_PERIOD) ++ time_ms = CCX_MAX_PERIOD; ++ ++ quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; ++ ++ if (quotient < 4) ++ idx = RTW89_CCX_4_US; ++ else if (quotient < 8) ++ idx = RTW89_CCX_8_US; ++ else if (quotient < 16) ++ idx = RTW89_CCX_16_US; ++ else ++ idx = RTW89_CCX_32_US; ++ ++ *unit_idx = idx; ++ *period = (time_ms * MS_TO_4US_RATIO) >> idx; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[Trigger Time] period:%d, unit_idx:%d\n", ++ *period, *unit_idx); ++} ++ ++static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "lv:(%d)->(0)\n", env->ccx_rac_lv); ++ ++ env->ccx_ongoing = false; ++ env->ccx_rac_lv = RTW89_RAC_RELEASE; ++ env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++} ++ ++static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, ++ struct rtw89_ccx_para_info *para) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ bool is_update = env->ifs_clm_app != para->ifs_clm_app; ++ u8 i = 0; ++ u16 *ifs_th_l = env->ifs_clm_th_l; ++ u16 *ifs_th_h = env->ifs_clm_th_h; ++ u32 ifs_th0_us = 0, ifs_th_times = 0; ++ u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; ++ ++ if (!is_update) ++ goto ifs_update_finished; ++ ++ switch (para->ifs_clm_app) { ++ case RTW89_IFS_CLM_INIT: ++ case RTW89_IFS_CLM_BACKGROUND: ++ case RTW89_IFS_CLM_ACS: ++ case RTW89_IFS_CLM_DBG: ++ case RTW89_IFS_CLM_DIG: ++ case RTW89_IFS_CLM_TDMA_DIG: ++ ifs_th0_us = IFS_CLM_TH0_UPPER; ++ ifs_th_times = IFS_CLM_TH_MUL; ++ break; ++ case RTW89_IFS_CLM_DBG_MANUAL: ++ ifs_th0_us = para->ifs_clm_manual_th0; ++ ifs_th_times = para->ifs_clm_manual_th_times; ++ break; ++ default: ++ break; ++ } ++ ++ /* Set sampling threshold for 4 different regions, unit in idx_cnt. ++ * low[i] = high[i-1] + 1 ++ * high[i] = high[i-1] * ifs_th_times ++ */ ++ ifs_th_l[IFS_CLM_TH_START_IDX] = 0; ++ ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; ++ ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, ++ ifs_th0_us); ++ for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { ++ ifs_th_l[i] = ifs_th_h[i - 1] + 1; ++ ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; ++ ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); ++ } ++ ++ifs_update_finished: ++ if (!is_update) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "No need to update IFS_TH\n"); ++ ++ return is_update; ++} ++ ++static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, ++ env->ifs_clm_th_l[0]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, ++ env->ifs_clm_th_l[1]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, ++ env->ifs_clm_th_l[2]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, ++ env->ifs_clm_th_l[3]); ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, ++ env->ifs_clm_th_h[0]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, ++ env->ifs_clm_th_h[1]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, ++ env->ifs_clm_th_h[2]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, ++ env->ifs_clm_th_h[3]); ++ ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Update IFS_T%d_th{low, high} : {%d, %d}\n", ++ i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); ++} ++ ++static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ struct rtw89_ccx_para_info para = {0}; ++ ++ env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++ env->ifs_clm_mntr_time = 0; ++ ++ para.ifs_clm_app = RTW89_IFS_CLM_INIT; ++ if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) ++ rtw89_phy_ifs_clm_set_th_reg(rtwdev); ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, ++ true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); ++} ++ ++static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, ++ enum rtw89_env_racing_lv level) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ int ret = 0; ++ ++ if (level >= RTW89_RAC_MAX_NUM) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[WARNING] Wrong LV=%d\n", level); ++ return -EINVAL; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, ++ env->ccx_rac_lv, level); ++ ++ if (env->ccx_ongoing) { ++ if (level <= env->ccx_rac_lv) ++ ret = -EINVAL; ++ else ++ env->ccx_ongoing = false; ++ } ++ ++ if (ret == 0) ++ env->ccx_rac_lv = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", ++ !ret); ++ ++ return ret; ++} ++ ++static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); ++ ++ env->ccx_rpt_stamp++; ++ env->ccx_ongoing = true; ++} ++ ++static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ u32 res = 0; ++ ++ env->ifs_clm_tx_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); ++ env->ifs_clm_edcca_excl_cca_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, ++ PERCENT); ++ env->ifs_clm_cck_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); ++ env->ifs_clm_ofdm_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); ++ env->ifs_clm_cck_cca_excl_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, ++ PERCENT); ++ env->ifs_clm_ofdm_cca_excl_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, ++ PERCENT); ++ env->ifs_clm_cck_fa_permil = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); ++ env->ifs_clm_ofdm_fa_permil = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); ++ ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { ++ if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { ++ env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; ++ } else { ++ env->ifs_clm_ifs_avg[i] = ++ rtw89_phy_ccx_idx_to_us(rtwdev, ++ env->ifs_clm_avg[i]); ++ } ++ ++ res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); ++ res += env->ifs_clm_his[i] >> 1; ++ if (env->ifs_clm_his[i]) ++ res /= env->ifs_clm_his[i]; ++ else ++ res = 0; ++ env->ifs_clm_cca_avg[i] = res; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", ++ env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_cca_excl_fa_ratio, ++ env->ifs_clm_ofdm_cca_excl_fa_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Time:[his, ifs_avg(us), cca_avg(us)]\n"); ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", ++ i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], ++ env->ifs_clm_cca_avg[i]); ++} ++ ++static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Get IFS_CLM report Fail\n"); ++ return false; ++ } ++ ++ env->ifs_clm_tx = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, ++ B_IFS_CLM_TX_CNT_MSK); ++ env->ifs_clm_edcca_excl_cca = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, ++ B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); ++ env->ifs_clm_cckcca_excl_fa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, ++ B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); ++ env->ifs_clm_ofdmcca_excl_fa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, ++ B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); ++ env->ifs_clm_cckfa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, ++ B_IFS_CLM_CCK_FA_MSK); ++ env->ifs_clm_ofdmfa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, ++ B_IFS_CLM_OFDM_FA_MSK); ++ ++ env->ifs_clm_his[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); ++ env->ifs_clm_his[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); ++ env->ifs_clm_his[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); ++ env->ifs_clm_his[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); ++ ++ env->ifs_clm_avg[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); ++ env->ifs_clm_avg[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); ++ env->ifs_clm_avg[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); ++ env->ifs_clm_avg[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); ++ ++ env->ifs_clm_cca[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); ++ env->ifs_clm_cca[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); ++ env->ifs_clm_cca[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); ++ env->ifs_clm_cca[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); ++ ++ env->ifs_clm_total_ifs = ++ rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", ++ env->ifs_clm_total_ifs); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", ++ env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], ++ env->ifs_clm_avg[i], env->ifs_clm_cca[i]); ++ ++ rtw89_phy_ifs_clm_get_utility(rtwdev); ++ ++ return true; ++} ++ ++static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, ++ struct rtw89_ccx_para_info *para) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u32 period = 0; ++ u32 unit_idx = 0; ++ ++ if (para->mntr_time == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[WARN] MNTR_TIME is 0\n"); ++ return -EINVAL; ++ } ++ ++ if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) ++ return -EINVAL; ++ ++ if (para->mntr_time != env->ifs_clm_mntr_time) { ++ rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, ++ &period, &unit_idx); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, ++ B_IFS_CLM_PERIOD_MSK, period); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, ++ B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Update IFS-CLM time ((%d)) -> ((%d))\n", ++ env->ifs_clm_mntr_time, para->mntr_time); ++ ++ env->ifs_clm_mntr_time = para->mntr_time; ++ env->ccx_period = (u16)period; ++ env->ccx_unit_idx = (u8)unit_idx; ++ } ++ ++ if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { ++ env->ifs_clm_app = para->ifs_clm_app; ++ rtw89_phy_ifs_clm_set_th_reg(rtwdev); ++ } ++ ++ return 0; ++} ++ ++void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ struct rtw89_ccx_para_info para = {0}; ++ u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; ++ ++ env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; ++ if (env->ccx_manual_ctrl) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "CCX in manual ctrl\n"); ++ return; ++ } ++ ++ /* only ifs_clm for now */ ++ if (rtw89_phy_ifs_clm_get_result(rtwdev)) ++ env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; ++ ++ rtw89_phy_ccx_racing_release(rtwdev); ++ para.mntr_time = 1900; ++ para.rac_lv = RTW89_RAC_LV_1; ++ para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++ ++ if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) ++ chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; ++ if (chk_result) ++ rtw89_phy_ccx_trigger(rtwdev); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "get_result=0x%x, chk_result:0x%x\n", ++ env->ccx_watchdog_result, chk_result); ++} ++ ++static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ const struct rtw89_phy_dig_gain_cfg *cfg; ++ const char *msg; ++ u8 i; ++ s8 gain_base; ++ s8 *gain_arr; ++ u32 tmp; ++ ++ switch (type) { ++ case RTW89_DIG_GAIN_LNA_G: ++ gain_arr = dig->lna_gain_g; ++ gain_base = LNA0_GAIN; ++ cfg = chip->dig_table->cfg_lna_g; ++ msg = "lna_gain_g"; ++ break; ++ case RTW89_DIG_GAIN_TIA_G: ++ gain_arr = dig->tia_gain_g; ++ gain_base = TIA0_GAIN_G; ++ cfg = chip->dig_table->cfg_tia_g; ++ msg = "tia_gain_g"; ++ break; ++ case RTW89_DIG_GAIN_LNA_A: ++ gain_arr = dig->lna_gain_a; ++ gain_base = LNA0_GAIN; ++ cfg = chip->dig_table->cfg_lna_a; ++ msg = "lna_gain_a"; ++ break; ++ case RTW89_DIG_GAIN_TIA_A: ++ gain_arr = dig->tia_gain_a; ++ gain_base = TIA0_GAIN_A; ++ cfg = chip->dig_table->cfg_tia_a; ++ msg = "tia_gain_a"; ++ break; ++ default: ++ return; ++ } ++ ++ for (i = 0; i < cfg->size; i++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, ++ cfg->table[i].mask); ++ tmp >>= DIG_GAIN_SHIFT; ++ gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; ++ gain_base += DIG_GAIN; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", ++ msg, i, gain_arr[i]); ++ } ++} ++ ++static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u32 tmp; ++ u8 i; ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, ++ B_PATH0_IB_PKPW_MSK); ++ dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); ++ dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, ++ B_PATH0_IB_PBK_MSK); ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", ++ dig->ib_pkpwr, dig->ib_pbk); ++ ++ for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) ++ rtw89_phy_dig_read_gain_table(rtwdev, i); ++} ++ ++static const u8 rssi_nolink = 22; ++static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; ++static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; ++static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; ++static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; ++ ++static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ ++ if (is_linked) { ++ dig->igi_rssi = ch_info->rssi_min >> 1; ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); ++ dig->igi_rssi = rssi_nolink; ++ } ++} ++ ++static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ const u16 *fa_th_src = NULL; ++ ++ switch (rtwdev->hal.current_band_type) { ++ case RTW89_BAND_2G: ++ dig->lna_gain = dig->lna_gain_g; ++ dig->tia_gain = dig->tia_gain_g; ++ fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; ++ dig->force_gaincode_idx_en = false; ++ dig->dyn_pd_th_en = true; ++ break; ++ case RTW89_BAND_5G: ++ default: ++ dig->lna_gain = dig->lna_gain_a; ++ dig->tia_gain = dig->tia_gain_a; ++ fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; ++ dig->force_gaincode_idx_en = true; ++ dig->dyn_pd_th_en = true; ++ break; ++ } ++ memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); ++ memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); ++} ++ ++static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; ++static const u8 igi_max_performance_mode = 0x5a; ++static const u8 dynamic_pd_threshold_max; ++ ++static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ ++ dig->cur_gaincode.lna_idx = LNA_IDX_MAX; ++ dig->cur_gaincode.tia_idx = TIA_IDX_MAX; ++ dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; ++ dig->force_gaincode.lna_idx = LNA_IDX_MAX; ++ dig->force_gaincode.tia_idx = TIA_IDX_MAX; ++ dig->force_gaincode.rxb_idx = RXB_IDX_MAX; ++ ++ dig->dyn_igi_max = igi_max_performance_mode; ++ dig->dyn_igi_min = dynamic_igi_min; ++ dig->dyn_pd_th_max = dynamic_pd_threshold_max; ++ dig->pd_low_th_ofst = pd_low_th_offset; ++ dig->is_linked_pre = false; ++} ++ ++static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_dig_update_gain_para(rtwdev); ++ rtw89_phy_dig_reset(rtwdev); ++} ++ ++static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 lna_idx; ++ ++ if (rssi < dig->igi_rssi_th[0]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX6; ++ else if (rssi < dig->igi_rssi_th[1]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX5; ++ else if (rssi < dig->igi_rssi_th[2]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX4; ++ else if (rssi < dig->igi_rssi_th[3]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX3; ++ else if (rssi < dig->igi_rssi_th[4]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX2; ++ else ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX1; ++ ++ return lna_idx; ++} ++ ++static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 tia_idx; ++ ++ if (rssi < dig->igi_rssi_th[0]) ++ tia_idx = RTW89_DIG_GAIN_TIA_IDX1; ++ else ++ tia_idx = RTW89_DIG_GAIN_TIA_IDX0; ++ ++ return tia_idx; ++} ++ ++#define IB_PBK_BASE 110 ++#define WB_RSSI_BASE 10 ++static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ struct rtw89_agc_gaincode_set *set) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ s8 lna_gain = dig->lna_gain[set->lna_idx]; ++ s8 tia_gain = dig->tia_gain[set->tia_idx]; ++ s32 wb_rssi = rssi + lna_gain + tia_gain; ++ s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; ++ u8 rxb_idx; ++ ++ rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; ++ rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", ++ wb_rssi, rxb_idx_tmp); ++ ++ return rxb_idx; ++} ++ ++static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ struct rtw89_agc_gaincode_set *set) ++{ ++ set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); ++ set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); ++ set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", ++ rssi, set->lna_idx, set->tia_idx, set->rxb_idx); ++} ++ ++#define IGI_OFFSET_MAX 25 ++#define IGI_OFFSET_MUL 2 ++static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ enum rtw89_dig_noisy_level noisy_lv; ++ u8 igi_offset = dig->fa_rssi_ofst; ++ u16 fa_ratio = 0; ++ ++ fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; ++ ++ if (fa_ratio < dig->fa_th[0]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL0; ++ else if (fa_ratio < dig->fa_th[1]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL1; ++ else if (fa_ratio < dig->fa_th[2]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL2; ++ else if (fa_ratio < dig->fa_th[3]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL3; ++ else ++ noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; ++ ++ if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) ++ igi_offset = 0; ++ else ++ igi_offset += noisy_lv * IGI_OFFSET_MUL; ++ ++ igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); ++ dig->fa_rssi_ofst = igi_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", ++ dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", ++ env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, ++ env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, ++ noisy_lv, igi_offset); ++} ++ ++static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, ++ B_PATH0_LNA_INIT_IDX_MSK, lna_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, ++ B_PATH1_LNA_INIT_IDX_MSK, lna_idx); ++} ++ ++static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, ++ B_PATH0_TIA_INIT_IDX_MSK, tia_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, ++ B_PATH1_TIA_INIT_IDX_MSK, tia_idx); ++} ++ ++static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, ++ B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, ++ B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); ++} ++ ++static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, ++ const struct rtw89_agc_gaincode_set set) ++{ ++ rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); ++ rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); ++ rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", ++ set.lna_idx, set.tia_idx, set.rxb_idx); ++} ++ ++static const struct rtw89_reg_def sdagc_config[4] = { ++ {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++}; ++ ++static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, ++ bool enable) ++{ ++ u8 i = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) ++ rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, ++ sdagc_config[i].mask, enable); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); ++} ++ ++static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, ++ bool enable) ++{ ++ enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; ++ u32 val = 0; ++ ++ under_region += PD_TH_SB_FLTR_CMP_VAL; ++ ++ switch (cbw) { ++ case RTW89_CHANNEL_WIDTH_40: ++ under_region += PD_TH_BW40_CMP_VAL; ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ under_region += PD_TH_BW80_CMP_VAL; ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ fallthrough; ++ default: ++ under_region += PD_TH_BW20_CMP_VAL; ++ break; ++ } ++ ++ dig->dyn_pd_th_max = dig->igi_rssi; ++ ++ final_rssi = min_t(u8, rssi, dig->igi_rssi); ++ final_rssi = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, ++ PD_TH_MAX_RSSI + under_region); ++ ++ if (enable) { ++ val = (final_rssi - under_region - PD_TH_MIN_RSSI) >> 1; ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "dyn_max=%d, final_rssi=%d, total=%d, PD_low=%d\n", ++ dig->igi_rssi, final_rssi, under_region, val); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "Dynamic PD th dsiabled, Set PD_low_bd=0\n"); ++ } ++ ++ rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, ++ val); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, ++ B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); ++} ++ ++void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ ++ dig->bypass_dig = false; ++ rtw89_phy_dig_para_reset(rtwdev); ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); ++ rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); ++ rtw89_phy_dig_update_para(rtwdev); ++} ++ ++#define IGI_RSSI_MIN 10 ++void rtw89_phy_dig(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ ++ if (unlikely(dig->bypass_dig)) { ++ dig->bypass_dig = false; ++ return; ++ } ++ ++ if (!dig->is_linked_pre && is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); ++ rtw89_phy_dig_update_para(rtwdev); ++ } else if (dig->is_linked_pre && !is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); ++ rtw89_phy_dig_update_para(rtwdev); ++ } ++ dig->is_linked_pre = is_linked; ++ ++ rtw89_phy_dig_igi_offset_by_env(rtwdev); ++ rtw89_phy_dig_update_rssi_info(rtwdev); ++ ++ dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? ++ dig->igi_rssi - IGI_RSSI_MIN : 0; ++ dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; ++ dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; ++ ++ dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, ++ dig->dyn_igi_max); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", ++ dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, ++ dig->igi_fa_rssi); ++ ++ if (dig->force_gaincode_idx_en) { ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "Force gaincode index enabled.\n"); ++ } else { ++ rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, ++ &dig->cur_gaincode); ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); ++ } ++ ++ rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); ++ ++ if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); ++ else ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); ++} ++ ++static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_ccx_top_setting_init(rtwdev); ++ rtw89_phy_ifs_clm_setting_init(rtwdev); ++} ++ ++void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ rtw89_phy_stat_init(rtwdev); ++ ++ rtw89_chip_bb_sethw(rtwdev); ++ ++ rtw89_phy_env_monitor_init(rtwdev); ++ rtw89_phy_dig_init(rtwdev); ++ rtw89_phy_cfo_init(rtwdev); ++ ++ rtw89_phy_init_rf_nctl(rtwdev); ++ rtw89_chip_rfk_init(rtwdev); ++ rtw89_load_txpwr_table(rtwdev, chip->byr_table); ++ rtw89_chip_set_txpwr_ctrl(rtwdev); ++ rtw89_chip_power_trim(rtwdev); ++} ++ ++void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) ++{ ++ enum rtw89_phy_idx phy_idx = RTW89_PHY_0; ++ u8 bss_color; ++ ++ if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) ++ return; ++ ++ bss_color = vif->bss_conf.he_bss_color.color; ++ ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, ++ vif->bss_conf.aid, phy_idx); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h +new file mode 100644 +index 000000000000..53d71d29e577 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/phy.h +@@ -0,0 +1,305 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PHY_H__ ++#define __RTW89_PHY_H__ ++ ++#include "core.h" ++ ++#define RTW89_PHY_ADDR_OFFSET 0x10000 ++ ++#define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) ++#define PHY_HEADLINE_VALID 0xf ++#define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) ++#define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ ++ FIELD_PREP(GENMASK(7, 0), cv)) ++ ++#define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) ++#define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) ++#define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) ++#define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) ++#define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) ++#define PHY_COND_BRANCH_IF 0x8 ++#define PHY_COND_BRANCH_ELIF 0x9 ++#define PHY_COND_BRANCH_ELSE 0xa ++#define PHY_COND_BRANCH_END 0xb ++#define PHY_COND_CHECK 0x4 ++#define PHY_COND_DONT_CARE 0xff ++ ++#define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) ++#define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) ++#define RA_MASK_SUBCCK_RATES 0x5ULL ++#define RA_MASK_SUBOFDM_RATES 0x10ULL ++#define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) ++#define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) ++#define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) ++#define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) ++#define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) ++#define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) ++#define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) ++#define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) ++#define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) ++#define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) ++#define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) ++#define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) ++ ++#define CFO_TRK_ENABLE_TH (2 << 2) ++#define CFO_TRK_STOP_TH_4 (30 << 2) ++#define CFO_TRK_STOP_TH_3 (20 << 2) ++#define CFO_TRK_STOP_TH_2 (10 << 2) ++#define CFO_TRK_STOP_TH_1 (00 << 2) ++#define CFO_TRK_STOP_TH (2 << 2) ++#define CFO_SW_COMP_FINE_TUNE (2 << 2) ++#define CFO_PERIOD_CNT 15 ++#define CFO_TP_UPPER 100 ++#define CFO_TP_LOWER 50 ++#define CFO_COMP_PERIOD 250 ++#define CFO_COMP_WEIGHT 8 ++#define MAX_CFO_TOLERANCE 30 ++ ++#define CCX_MAX_PERIOD 2097 ++#define CCX_MAX_PERIOD_UNIT 32 ++#define MS_TO_4US_RATIO 250 ++#define ENV_MNTR_FAIL_DWORD 0xffffffff ++#define ENV_MNTR_IFSCLM_HIS_MAX 127 ++#define PERMIL 1000 ++#define PERCENT 100 ++#define IFS_CLM_TH0_UPPER 64 ++#define IFS_CLM_TH_MUL 4 ++#define IFS_CLM_TH_START_IDX 0 ++ ++#define TIA0_GAIN_A 12 ++#define TIA0_GAIN_G 16 ++#define LNA0_GAIN (-24) ++#define U4_MAX_BIT 3 ++#define U8_MAX_BIT 7 ++#define DIG_GAIN_SHIFT 2 ++#define DIG_GAIN 8 ++ ++#define LNA_IDX_MAX 6 ++#define LNA_IDX_MIN 0 ++#define TIA_IDX_MAX 1 ++#define TIA_IDX_MIN 0 ++#define RXB_IDX_MAX 31 ++#define RXB_IDX_MIN 0 ++ ++#define PD_TH_MAX_RSSI 70 ++#define PD_TH_MIN_RSSI 8 ++#define PD_TH_BW80_CMP_VAL 6 ++#define PD_TH_BW40_CMP_VAL 3 ++#define PD_TH_BW20_CMP_VAL 0 ++#define PD_TH_CMP_VAL 3 ++#define PD_TH_SB_FLTR_CMP_VAL 7 ++ ++#define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) ++#define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) ++#define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) ++#define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) ++#define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) ++ ++enum rtw89_phy_c2h_ra_func { ++ RTW89_PHY_C2H_FUNC_STS_RPT, ++ RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, ++ RTW89_PHY_C2H_FUNC_TXSTS, ++ RTW89_PHY_C2H_FUNC_RA_MAX, ++}; ++ ++enum rtw89_phy_c2h_class { ++ RTW89_PHY_C2H_CLASS_RUA, ++ RTW89_PHY_C2H_CLASS_RA, ++ RTW89_PHY_C2H_CLASS_DM, ++ RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, ++ RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, ++ RTW89_PHY_C2H_CLASS_MAX, ++}; ++ ++enum rtw89_env_monitor_result_level { ++ RTW89_PHY_ENV_MON_CCX_FAIL = 0, ++ RTW89_PHY_ENV_MON_NHM = BIT(0), ++ RTW89_PHY_ENV_MON_CLM = BIT(1), ++ RTW89_PHY_ENV_MON_FAHM = BIT(2), ++ RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), ++ RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), ++}; ++ ++#define CCX_US_BASE_RATIO 4 ++enum rtw89_ccx_unit { ++ RTW89_CCX_4_US = 0, ++ RTW89_CCX_8_US = 1, ++ RTW89_CCX_16_US = 2, ++ RTW89_CCX_32_US = 3 ++}; ++ ++enum rtw89_dig_gain_type { ++ RTW89_DIG_GAIN_LNA_G = 0, ++ RTW89_DIG_GAIN_TIA_G = 1, ++ RTW89_DIG_GAIN_LNA_A = 2, ++ RTW89_DIG_GAIN_TIA_A = 3, ++ RTW89_DIG_GAIN_MAX = 4 ++}; ++ ++enum rtw89_dig_gain_lna_idx { ++ RTW89_DIG_GAIN_LNA_IDX1 = 1, ++ RTW89_DIG_GAIN_LNA_IDX2 = 2, ++ RTW89_DIG_GAIN_LNA_IDX3 = 3, ++ RTW89_DIG_GAIN_LNA_IDX4 = 4, ++ RTW89_DIG_GAIN_LNA_IDX5 = 5, ++ RTW89_DIG_GAIN_LNA_IDX6 = 6 ++}; ++ ++enum rtw89_dig_gain_tia_idx { ++ RTW89_DIG_GAIN_TIA_IDX0 = 0, ++ RTW89_DIG_GAIN_TIA_IDX1 = 1 ++}; ++ ++struct rtw89_txpwr_byrate_cfg { ++ enum rtw89_band band; ++ enum rtw89_nss nss; ++ enum rtw89_rate_section rs; ++ u8 shf; ++ u8 len; ++ u32 data; ++}; ++ ++#define DELTA_SWINGIDX_SIZE 30 ++ ++struct rtw89_txpwr_track_cfg { ++ const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; ++ const u8 *delta_swingidx_2gb_n; ++ const u8 *delta_swingidx_2gb_p; ++ const u8 *delta_swingidx_2ga_n; ++ const u8 *delta_swingidx_2ga_p; ++ const u8 *delta_swingidx_2g_cck_b_n; ++ const u8 *delta_swingidx_2g_cck_b_p; ++ const u8 *delta_swingidx_2g_cck_a_n; ++ const u8 *delta_swingidx_2g_cck_a_p; ++}; ++ ++struct rtw89_phy_dig_gain_cfg { ++ const struct rtw89_reg_def *table; ++ u8 size; ++}; ++ ++struct rtw89_phy_dig_gain_table { ++ const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; ++ const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; ++ const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; ++ const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; ++}; ++ ++struct rtw89_phy_reg3_tbl { ++ const struct rtw89_reg3_def *reg3; ++ int size; ++}; ++ ++#define DECLARE_PHY_REG3_TBL(_name) \ ++const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ ++ .reg3 = _name, \ ++ .size = ARRAY_SIZE(_name), \ ++} ++ ++static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, ++ u32 addr, u8 data) ++{ ++ rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, ++ u32 addr, u16 data) ++{ ++ rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, ++ u32 addr, u32 data) ++{ ++ rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, ++ u32 addr, u32 bits) ++{ ++ rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); ++} ++ ++static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, ++ u32 addr, u32 bits) ++{ ++ rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); ++} ++ ++static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, ++ u32 addr, u32 mask, u32 data) ++{ ++ rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); ++} ++ ++static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, ++ u32 addr, u32 mask) ++{ ++ return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); ++} ++ ++void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_reg3_tbl *tbl); ++u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_bandwidth dbw); ++u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask); ++bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data); ++void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); ++void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev); ++void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); ++void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 data, enum rtw89_phy_idx phy_idx); ++void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl); ++s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_rate_desc *rate_desc); ++void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx); ++void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx); ++s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, ++ u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); ++void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); ++void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); ++void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); ++void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_cfo_track_work(struct work_struct *work); ++void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, ++ struct rtw89_rx_phy_ppdu *phy_ppdu); ++void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 val); ++void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); ++void rtw89_phy_dig(struct rtw89_dev *rtwdev); ++void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); ++ ++#endif + +From patchwork Fri Aug 20 04:35:25 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448383 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, + USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id B40A6C4338F + for ; + Fri, 20 Aug 2021 04:37:19 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 8D24460F91 + for ; + Fri, 20 Aug 2021 04:37:19 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S234614AbhHTEhz (ORCPT + ); + Fri, 20 Aug 2021 00:37:55 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39255 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S234483AbhHTEhu (ORCPT + ); + Fri, 20 Aug 2021 00:37:50 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4b8llD004029, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4b8llD004029 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:08 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:08 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:07 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 11/24] rtw89: define register names +Date: Fri, 20 Aug 2021 12:35:25 +0800 +Message-ID: <20210820043538.12424-12-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +There are three register domains -- MAC, PHY and RF whose ranges are +0x0000~0xFFFF, 0x10000~0x1FFFF and 0x00~0xFF respectively. + +Since we access PHY register via a set of PHY access interfaces which do +0x10000 offset by themselves, so PHY registers are listed in range of +0x0000~0xFFFF. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/reg.h | 2135 ++++++++++++++++++++++ + 1 file changed, 2135 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/reg.h + +diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h +new file mode 100644 +index 000000000000..aff8565d2e58 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/reg.h +@@ -0,0 +1,2135 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_REG_H__ ++#define __RTW89_REG_H__ ++ ++#define R_AX_SYS_WL_EFUSE_CTRL 0x000A ++#define B_AX_AUTOLOAD_SUS BIT(5) ++ ++#define R_AX_SYS_FUNC_EN 0x0002 ++#define B_AX_FEN_BB_GLB_RSTN BIT(1) ++#define B_AX_FEN_BBRSTB BIT(0) ++ ++#define R_AX_SYS_PW_CTRL 0x0004 ++#define B_AX_PSUS_OFF_CAPC_EN BIT(14) ++ ++#define R_AX_SYS_CLK_CTRL 0x0008 ++#define B_AX_CPU_CLK_EN BIT(14) ++ ++#define R_AX_RSV_CTRL 0x001C ++#define B_AX_R_DIS_PRST BIT(6) ++#define B_AX_WLOCK_1C_BIT6 BIT(5) ++ ++#define R_AX_EFUSE_CTRL_1 0x0038 ++#define B_AX_EF_PGPD_MASK GENMASK(30, 28) ++#define B_AX_EF_RDT BIT(27) ++#define B_AX_EF_VDDQST_MASK GENMASK(26, 24) ++#define B_AX_EF_PGTS_MASK GENMASK(23, 20) ++#define B_AX_EF_PD_DIS BIT(11) ++#define B_AX_EF_POR BIT(10) ++#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8) ++ ++#define R_AX_SPSLDO_ON_CTRL0 0x0200 ++#define B_AX_OCP_L1_MASK GENMASK(15, 13) ++ ++#define R_AX_EFUSE_CTRL 0x0030 ++#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30) ++#define B_AX_EF_RDY BIT(29) ++#define B_AX_EF_COMP_RESULT BIT(28) ++#define B_AX_EF_ADDR_MASK GENMASK(26, 16) ++#define B_AX_EF_DATA_MASK GENMASK(15, 0) ++ ++#define R_AX_GPIO_MUXCFG 0x0040 ++#define B_AX_BOOT_MODE BIT(19) ++#define B_AX_WL_EECS_EXT_32K_SEL BIT(18) ++#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) ++#define B_AX_SECSIC_SEL BIT(16) ++#define B_AX_ENHTP BIT(14) ++#define B_AX_BT_AOD_GPIO3 BIT(13) ++#define B_AX_ENSIC BIT(12) ++#define B_AX_SIC_SWRST BIT(11) ++#define B_AX_PO_WIFI_PTA_PINS BIT(10) ++#define B_AX_PO_BT_PTA_PINS BIT(9) ++#define B_AX_ENUARTTX BIT(8) ++#define B_AX_BTMODE_MASK GENMASK(7, 6) ++#define MAC_AX_BT_MODE_0_3 0 ++#define MAC_AX_BT_MODE_2 2 ++#define B_AX_ENBT BIT(5) ++#define B_AX_EROM_EN BIT(4) ++#define B_AX_ENUARTRX BIT(2) ++#define B_AX_GPIOSEL_MASK GENMASK(1, 0) ++ ++#define R_AX_DBG_CTRL 0x0058 ++#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30) ++#define B_AX_DBG_SEL1_16BIT BIT(27) ++#define B_AX_DBG_SEL1 GENMASK(23, 16) ++#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14) ++#define B_AX_DBG_SEL0_16BIT BIT(11) ++#define B_AX_DBG_SEL0 GENMASK(7, 0) ++ ++#define R_AX_SYS_SDIO_CTRL 0x0070 ++#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) ++#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) ++#define B_AX_PCIE_AUXCLK_GATE BIT(11) ++#define B_AX_LTE_MUX_CTRL_PATH BIT(26) ++ ++#define R_AX_PLATFORM_ENABLE 0x0088 ++#define B_AX_WCPU_EN BIT(1) ++ ++#define R_AX_SCOREBOARD 0x00AC ++#define B_AX_TOGGLE BIT(31) ++#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24) ++#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0) ++#define B_MAC_AX_BTGS1_NOTIFY BIT(0) ++#define MAC_AX_NOTIFY_TP_MAJOR 0x81 ++#define MAC_AX_NOTIFY_PWR_MAJOR 0x80 ++ ++#define R_AX_DBG_PORT_SEL 0x00C0 ++#define B_AX_DEBUG_ST_MASK GENMASK(31, 0) ++ ++#define R_AX_SYS_CFG1 0x00F0 ++#define B_AX_CHIP_VER_MASK GENMASK(15, 12) ++ ++#define R_AX_SYS_STATUS1 0x00F4 ++#define B_AX_SEL_0XC0_MASK GENMASK(17, 16) ++ ++#define R_AX_HALT_H2C_CTRL 0x0160 ++#define R_AX_HALT_H2C 0x0168 ++#define B_AX_HALT_H2C_TRIGGER BIT(0) ++#define R_AX_HALT_C2H_CTRL 0x0164 ++#define R_AX_HALT_C2H 0x016C ++ ++#define R_AX_WCPU_FW_CTRL 0x01E0 ++#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5) ++#define B_AX_FWDL_PATH_RDY BIT(2) ++#define B_AX_H2C_PATH_RDY BIT(1) ++#define B_AX_WCPU_FWDL_EN BIT(0) ++ ++#define R_AX_RPWM 0x01E4 ++#define R_AX_PCIE_HRPWM 0x10C0 ++#define PS_RPWM_TOGGLE BIT(15) ++#define PS_RPWM_ACK BIT(14) ++#define PS_RPWM_SEQ_NUM GENMASK(13, 12) ++#define PS_RPWM_STATE 0x7 ++#define RPWM_SEQ_NUM_MAX 3 ++#define PS_CPWM_SEQ_NUM GENMASK(13, 12) ++#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8) ++#define PS_CPWM_STATE GENMASK(2, 0) ++#define CPWM_SEQ_NUM_MAX 3 ++ ++#define R_AX_BOOT_REASON 0x01E6 ++#define B_AX_BOOT_REASON_MASK GENMASK(2, 0) ++ ++#define R_AX_LDM 0x01E8 ++#define B_AX_EN_32K BIT(31) ++ ++#define R_AX_UDM0 0x01F0 ++#define R_AX_UDM1 0x01F4 ++#define R_AX_UDM2 0x01F8 ++#define R_AX_UDM3 0x01FC ++ ++#define R_AX_XTAL_ON_CTRL0 0x0280 ++#define B_AX_XTAL_SC_LPS BIT(31) ++#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) ++#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) ++#define B_AX_XTAL_SC_MASK GENMASK(6, 0) ++ ++#define R_AX_GPIO0_7_FUNC_SEL 0x02D0 ++ ++#define R_AX_WLRF_CTRL 0x02F0 ++#define B_AX_WLRF1_CTRL_7 BIT(15) ++#define B_AX_WLRF1_CTRL_1 BIT(9) ++#define B_AX_WLRF_CTRL_7 BIT(7) ++#define B_AX_WLRF_CTRL_1 BIT(1) ++ ++#define R_AX_FILTER_MODEL_ADDR 0x0C04 ++ ++#define R_AX_PCIE_DBG_CTRL 0x11C0 ++#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16) ++#define B_AX_DBG_SEL_MASK GENMASK(15, 13) ++#define B_AX_PCIE_DBG_SEL BIT(12) ++#define B_AX_MRD_TIMEOUT_EN BIT(10) ++#define B_AX_ASFF_FULL_NO_STK BIT(1) ++#define B_AX_EN_STUCK_DBG BIT(0) ++ ++#define R_AX_PHYREG_SET 0x8040 ++#define PHYREG_SET_ALL_CYCLE 0x8 ++ ++#define R_AX_HD0IMR 0x8110 ++#define B_AX_WDT_PTFM_INT_EN BIT(5) ++#define B_AX_CPWM_INT_EN BIT(2) ++#define B_AX_GT3_INT_EN BIT(1) ++#define B_AX_C2H_INT_EN BIT(0) ++#define R_AX_HD0ISR 0x8114 ++#define B_AX_C2H_INT BIT(0) ++ ++#define R_AX_H2CREG_DATA0 0x8140 ++#define R_AX_H2CREG_DATA1 0x8144 ++#define R_AX_H2CREG_DATA2 0x8148 ++#define R_AX_H2CREG_DATA3 0x814C ++#define R_AX_C2HREG_DATA0 0x8150 ++#define R_AX_C2HREG_DATA1 0x8154 ++#define R_AX_C2HREG_DATA2 0x8158 ++#define R_AX_C2HREG_DATA3 0x815C ++#define R_AX_H2CREG_CTRL 0x8160 ++#define B_AX_H2CREG_TRIGGER BIT(0) ++#define R_AX_C2HREG_CTRL 0x8164 ++#define B_AX_C2HREG_TRIGGER BIT(0) ++#define R_AX_CPWM 0x8170 ++ ++#define R_AX_HCI_FUNC_EN 0x8380 ++#define B_AX_HCI_RXDMA_EN BIT(1) ++#define B_AX_HCI_TXDMA_EN BIT(0) ++ ++#define R_AX_BOOT_DBG 0x83F0 ++ ++#define R_AX_DMAC_FUNC_EN 0x8400 ++#define B_AX_MAC_FUNC_EN BIT(30) ++#define B_AX_DMAC_FUNC_EN BIT(29) ++#define B_AX_MPDU_PROC_EN BIT(28) ++#define B_AX_WD_RLS_EN BIT(27) ++#define B_AX_DLE_WDE_EN BIT(26) ++#define B_AX_TXPKT_CTRL_EN BIT(25) ++#define B_AX_STA_SCH_EN BIT(24) ++#define B_AX_DLE_PLE_EN BIT(23) ++#define B_AX_PKT_BUF_EN BIT(22) ++#define B_AX_DMAC_TBL_EN BIT(21) ++#define B_AX_PKT_IN_EN BIT(20) ++#define B_AX_DLE_CPUIO_EN BIT(19) ++#define B_AX_DISPATCHER_EN BIT(18) ++#define B_AX_MAC_SEC_EN BIT(16) ++ ++#define R_AX_DMAC_CLK_EN 0x8404 ++#define B_AX_WD_RLS_CLK_EN BIT(27) ++#define B_AX_DLE_WDE_CLK_EN BIT(26) ++#define B_AX_TXPKT_CTRL_CLK_EN BIT(25) ++#define B_AX_STA_SCH_CLK_EN BIT(24) ++#define B_AX_DLE_PLE_CLK_EN BIT(23) ++#define B_AX_PKT_IN_CLK_EN BIT(20) ++#define B_AX_DLE_CPUIO_CLK_EN BIT(19) ++#define B_AX_DISPATCHER_CLK_EN BIT(18) ++#define B_AX_MAC_SEC_CLK_EN BIT(16) ++ ++#define PCI_LTR_IDLE_TIMER_1US 0 ++#define PCI_LTR_IDLE_TIMER_10US 1 ++#define PCI_LTR_IDLE_TIMER_100US 2 ++#define PCI_LTR_IDLE_TIMER_200US 3 ++#define PCI_LTR_IDLE_TIMER_400US 4 ++#define PCI_LTR_IDLE_TIMER_800US 5 ++#define PCI_LTR_IDLE_TIMER_1_6MS 6 ++#define PCI_LTR_IDLE_TIMER_3_2MS 7 ++#define PCI_LTR_IDLE_TIMER_R_ERR 0xFD ++#define PCI_LTR_IDLE_TIMER_DEF 0xFE ++#define PCI_LTR_IDLE_TIMER_IGNORE 0xFF ++ ++#define PCI_LTR_SPC_10US 0 ++#define PCI_LTR_SPC_100US 1 ++#define PCI_LTR_SPC_500US 2 ++#define PCI_LTR_SPC_1MS 3 ++#define PCI_LTR_SPC_R_ERR 0xFD ++#define PCI_LTR_SPC_DEF 0xFE ++#define PCI_LTR_SPC_IGNORE 0xFF ++ ++#define R_AX_LTR_CTRL_0 0x8410 ++#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12) ++#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) ++#define B_AX_APP_LTR_ACT BIT(5) ++#define B_AX_APP_LTR_IDLE BIT(4) ++#define B_AX_LTR_EN BIT(1) ++#define B_AX_LTR_HW_EN BIT(0) ++ ++#define R_AX_LTR_CTRL_1 0x8414 ++#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16) ++#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0) ++ ++#define R_AX_LTR_IDLE_LATENCY 0x8418 ++ ++#define R_AX_LTR_ACTIVE_LATENCY 0x841C ++ ++#define R_AX_SER_DBG_INFO 0x8424 ++#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28) ++ ++#define R_AX_DLE_EMPTY0 0x8430 ++#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) ++#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) ++#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) ++#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) ++#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) ++#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) ++#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) ++#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) ++#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) ++#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) ++#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) ++#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) ++#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) ++#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) ++#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) ++#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) ++ ++#define R_AX_DMAC_ERR_ISR 0x8524 ++#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) ++#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) ++#define B_AX_DISPATCH_ERR_FLAG BIT(8) ++#define B_AX_PKTIN_ERR_FLAG BIT(7) ++#define B_AX_PLE_DLE_ERR_FLAG BIT(6) ++#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) ++#define B_AX_WDE_DLE_ERR_FLAG BIT(4) ++#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) ++#define B_AX_MPDU_ERR_FLAG BIT(2) ++#define B_AX_WSEC_ERR_FLAG BIT(1) ++#define B_AX_WDRLS_ERR_FLAG BIT(0) ++ ++#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 ++#define B_AX_PL_PAGE_128B_SEL BIT(9) ++#define B_AX_WD_PAGE_64B_SEL BIT(8) ++#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 ++#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 ++#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C ++#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 ++#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) ++ ++#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 ++#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) ++#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) ++ ++#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 ++#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) ++ ++#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 ++ ++#define R_AX_HCI_FC_CTRL 0x8A00 ++#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) ++#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) ++#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) ++#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) ++#define B_AX_HCI_FC_CH12_EN BIT(3) ++#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1) ++#define B_AX_HCI_FC_EN BIT(0) ++ ++#define R_AX_CH_PAGE_CTRL 0x8A04 ++#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16) ++#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0) ++ ++#define B_AX_MAX_PG_MASK GENMASK(28, 16) ++#define B_AX_MIN_PG_MASK GENMASK(12, 0) ++#define B_AX_GRP BIT(31) ++#define R_AX_ACH0_PAGE_CTRL 0x8A10 ++#define R_AX_ACH1_PAGE_CTRL 0x8A14 ++#define R_AX_ACH2_PAGE_CTRL 0x8A18 ++#define R_AX_ACH3_PAGE_CTRL 0x8A1C ++#define R_AX_ACH4_PAGE_CTRL 0x8A20 ++#define R_AX_ACH5_PAGE_CTRL 0x8A24 ++#define R_AX_ACH6_PAGE_CTRL 0x8A28 ++#define R_AX_ACH7_PAGE_CTRL 0x8A2C ++#define R_AX_CH8_PAGE_CTRL 0x8A30 ++#define R_AX_CH9_PAGE_CTRL 0x8A34 ++#define R_AX_CH10_PAGE_CTRL 0x8A38 ++#define R_AX_CH11_PAGE_CTRL 0x8A3C ++ ++#define B_AX_AVAL_PG_MASK GENMASK(27, 16) ++#define B_AX_USE_PG_MASK GENMASK(12, 0) ++#define R_AX_ACH0_PAGE_INFO 0x8A50 ++#define R_AX_ACH1_PAGE_INFO 0x8A54 ++#define R_AX_ACH2_PAGE_INFO 0x8A58 ++#define R_AX_ACH3_PAGE_INFO 0x8A5C ++#define R_AX_ACH4_PAGE_INFO 0x8A60 ++#define R_AX_ACH5_PAGE_INFO 0x8A64 ++#define R_AX_ACH6_PAGE_INFO 0x8A68 ++#define R_AX_ACH7_PAGE_INFO 0x8A6C ++#define R_AX_CH8_PAGE_INFO 0x8A70 ++#define R_AX_CH9_PAGE_INFO 0x8A74 ++#define R_AX_CH10_PAGE_INFO 0x8A78 ++#define R_AX_CH11_PAGE_INFO 0x8A7C ++#define R_AX_CH12_PAGE_INFO 0x8A80 ++ ++#define R_AX_PUB_PAGE_INFO3 0x8A8C ++#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16) ++#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_CTRL1 0x8A90 ++#define B_AX_PUBPG_G1_MASK GENMASK(28, 16) ++#define B_AX_PUBPG_G0_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_CTRL2 0x8A94 ++#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_INFO1 0x8A98 ++#define B_AX_G1_USE_PG_MASK GENMASK(28, 16) ++#define B_AX_G0_USE_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_INFO2 0x8A9C ++#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_WP_PAGE_CTRL1 0x8AA0 ++#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) ++#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) ++ ++#define R_AX_WP_PAGE_CTRL2 0x8AA4 ++#define B_AX_WP_THRD_MASK GENMASK(12, 0) ++ ++#define R_AX_WP_PAGE_INFO1 0x8AA8 ++#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16) ++ ++#define R_AX_WDE_PKTBUF_CFG 0x8C08 ++#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8) ++#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0) ++#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) ++#define R_AX_WDE_ERR_FLAG_CFG 0x8C34 ++#define R_AX_WDE_ERR_IMR 0x8C38 ++#define R_AX_WDE_ERR_ISR 0x8C3C ++ ++#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_WDE_QTA0_CFG 0x8C40 ++#define R_AX_WDE_QTA1_CFG 0x8C44 ++#define R_AX_WDE_QTA2_CFG 0x8C48 ++#define R_AX_WDE_QTA3_CFG 0x8C4C ++#define R_AX_WDE_QTA4_CFG 0x8C50 ++ ++#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0) ++#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0) ++#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16) ++#define B_AX_DLE_USE_PGNUM GENMASK(27, 16) ++#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0) ++#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0) ++ ++#define R_AX_WDE_INI_STATUS 0x8D00 ++#define B_AX_WDE_Q_MGN_INI_RDY BIT(1) ++#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) ++#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) ++#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 ++#define B_AX_WDE_DFI_ACTIVE BIT(31) ++#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 ++#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_PLE_PKTBUF_CFG 0x9008 ++#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8) ++#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0) ++#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) ++#define R_AX_PLE_ERR_FLAG_CFG 0x9034 ++ ++#define R_AX_PLE_ERR_IMR 0x9038 ++#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) ++ ++#define R_AX_PLE_ERR_FLAG_ISR 0x903C ++#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_PLE_QTA0_CFG 0x9040 ++#define R_AX_PLE_QTA1_CFG 0x9044 ++#define R_AX_PLE_QTA2_CFG 0x9048 ++#define R_AX_PLE_QTA3_CFG 0x904C ++#define R_AX_PLE_QTA4_CFG 0x9050 ++#define R_AX_PLE_QTA5_CFG 0x9054 ++#define R_AX_PLE_QTA6_CFG 0x9058 ++#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_PLE_QTA7_CFG 0x905C ++#define R_AX_PLE_QTA8_CFG 0x9060 ++#define R_AX_PLE_QTA9_CFG 0x9064 ++#define R_AX_PLE_QTA10_CFG 0x9068 ++ ++#define R_AX_PLE_INI_STATUS 0x9100 ++#define B_AX_PLE_Q_MGN_INI_RDY BIT(1) ++#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) ++#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) ++#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 ++#define B_AX_PLE_DFI_ACTIVE BIT(31) ++#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 ++#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_WDRLS_CFG 0x9408 ++#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) ++#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0) ++ ++#define R_AX_RLSRPT0_CFG0 0x9410 ++#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) ++#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16) ++#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8) ++#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0) ++ ++#define R_AX_RLSRPT0_CFG1 0x9414 ++#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16) ++#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) ++ ++#define R_AX_WDRLS_ERR_IMR 0x9430 ++#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) ++#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) ++#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) ++#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) ++#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) ++#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) ++#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) ++#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) ++#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) ++#define R_AX_WDRLS_ERR_ISR 0x9434 ++ ++#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C ++#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C ++#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C ++#define R_AX_LA_ERRFLAG 0x966C ++ ++#define R_AX_WD_BUF_REQ 0x9800 ++#define R_AX_PL_BUF_REQ 0x9820 ++#define B_AX_WD_BUF_REQ_EXEC BIT(31) ++#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) ++#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) ++ ++#define R_AX_WD_BUF_STATUS 0x9804 ++#define R_AX_PL_BUF_STATUS 0x9824 ++#define B_AX_WD_BUF_STAT_DONE BIT(31) ++#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) ++ ++#define R_AX_WD_CPUQ_OP_0 0x9810 ++#define R_AX_PL_CPUQ_OP_0 0x9830 ++#define B_AX_WD_CPUQ_OP_EXEC BIT(31) ++#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) ++#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16) ++#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) ++ ++#define R_AX_WD_CPUQ_OP_1 0x9814 ++#define R_AX_PL_CPUQ_OP_1 0x9834 ++#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22) ++#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16) ++#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6) ++#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0) ++ ++#define R_AX_WD_CPUQ_OP_2 0x9818 ++#define R_AX_PL_CPUQ_OP_2 0x9838 ++#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) ++#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) ++ ++#define R_AX_WD_CPUQ_OP_STATUS 0x981C ++#define R_AX_PL_CPUQ_OP_STATUS 0x983C ++#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) ++#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) ++#define R_AX_CPUIO_ERR_IMR 0x9840 ++#define R_AX_CPUIO_ERR_ISR 0x9844 ++ ++#define R_AX_SEC_ERR_IMR_ISR 0x991C ++ ++#define R_AX_PKTIN_SETTING 0x9A00 ++#define B_AX_WD_ADDR_INFO_LENGTH BIT(1) ++#define R_AX_PKTIN_ERR_IMR 0x9A20 ++#define R_AX_PKTIN_ERR_ISR 0x9A24 ++ ++#define R_AX_MPDU_TX_ERR_ISR 0x9BF0 ++#define R_AX_MPDU_TX_ERR_IMR 0x9BF4 ++ ++#define R_AX_MPDU_PROC 0x9C00 ++#define B_AX_A_ICV_ERR BIT(1) ++#define B_AX_APPEND_FCS BIT(0) ++ ++#define R_AX_ACTION_FWD0 0x9C04 ++#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 ++ ++#define R_AX_TF_FWD 0x9C14 ++#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 ++ ++#define R_AX_HW_RPT_FWD 0x9C18 ++#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0) ++#define RTW89_PRPT_DEST_HOST 1 ++#define RTW89_PRPT_DEST_WLCPU 2 ++ ++#define R_AX_CUT_AMSDU_CTRL 0x9C40 ++#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 ++ ++#define R_AX_MPDU_RX_ERR_ISR 0x9CF0 ++#define R_AX_MPDU_RX_ERR_IMR 0x9CF4 ++ ++#define R_AX_SEC_ENG_CTRL 0x9D00 ++#define B_AX_TX_PARTIAL_MODE BIT(11) ++#define B_AX_CLK_EN_CGCMP BIT(10) ++#define B_AX_CLK_EN_WAPI BIT(9) ++#define B_AX_CLK_EN_WEP_TKIP BIT(8) ++#define B_AX_BMC_MGNT_DEC BIT(5) ++#define B_AX_UC_MGNT_DEC BIT(4) ++#define B_AX_MC_DEC BIT(3) ++#define B_AX_BC_DEC BIT(2) ++#define B_AX_SEC_RX_DEC BIT(1) ++#define B_AX_SEC_TX_ENC BIT(0) ++ ++#define R_AX_SEC_MPDU_PROC 0x9D04 ++#define B_AX_APPEND_ICV BIT(1) ++#define B_AX_APPEND_MIC BIT(0) ++ ++#define R_AX_SEC_CAM_ACCESS 0x9D10 ++#define R_AX_SEC_CAM_RDATA 0x9D14 ++#define R_AX_SEC_CAM_WDATA 0x9D18 ++#define R_AX_SEC_DEBUG 0x9D1C ++#define R_AX_SEC_TX_DEBUG 0x9D20 ++#define R_AX_SEC_RX_DEBUG 0x9D24 ++#define R_AX_SEC_TRX_PKT_CNT 0x9D28 ++#define R_AX_SEC_TRX_BLK_CNT 0x9D2C ++ ++#define R_AX_SS_CTRL 0x9E10 ++#define B_AX_SS_INIT_DONE_1 BIT(31) ++#define B_AX_SS_WARM_INIT_FLG BIT(29) ++#define B_AX_SS_EN BIT(0) ++ ++#define R_AX_SS_MACID_PAUSE_0 0x9EB0 ++#define B_AX_SS_MACID31_0_PAUSE_SH 0 ++#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_1 0x9EB4 ++#define B_AX_SS_MACID63_32_PAUSE_SH 0 ++#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_2 0x9EB8 ++#define B_AX_SS_MACID95_64_PAUSE_SH 0 ++#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_3 0x9EBC ++#define B_AX_SS_MACID127_96_PAUSE_SH 0 ++#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 ++#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 ++ ++#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C ++#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C ++#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) ++#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) ++#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) ++#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) ++ ++#define R_AX_DBG_FUN_INTF_CTL 0x9F30 ++#define B_AX_DFI_ACTIVE BIT(31) ++#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_DBG_FUN_INTF_DATA 0x9F34 ++#define B_AX_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_AFE_CTRL1 0x0024 ++ ++#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) ++#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) ++#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) ++#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) ++#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) ++ ++#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 ++#define B_AX_CMAC1_FEN BIT(30) ++#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) ++#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) ++#define B_AX_R_SYM_ISO_CMAC12PP BIT(5) ++ ++#define R_AX_CMAC_REG_START 0xC000 ++ ++#define R_AX_CMAC_FUNC_EN 0xC000 ++#define R_AX_CMAC_FUNC_EN_C1 0xE000 ++#define B_AX_CMAC_CRPRT BIT(31) ++#define B_AX_CMAC_EN BIT(30) ++#define B_AX_CMAC_TXEN BIT(29) ++#define B_AX_CMAC_RXEN BIT(28) ++#define B_AX_FORCE_CMACREG_GCKEN BIT(15) ++#define B_AX_PHYINTF_EN BIT(5) ++#define B_AX_CMAC_DMA_EN BIT(4) ++#define B_AX_PTCLTOP_EN BIT(3) ++#define B_AX_SCHEDULER_EN BIT(2) ++#define B_AX_TMAC_EN BIT(1) ++#define B_AX_RMAC_EN BIT(0) ++ ++#define R_AX_CK_EN 0xC004 ++#define R_AX_CK_EN_C1 0xE004 ++#define B_AX_CMAC_ALLCKEN GENMASK(31, 0) ++#define B_AX_CMAC_CKEN BIT(30) ++#define B_AX_PHYINTF_CKEN BIT(5) ++#define B_AX_CMAC_DMA_CKEN BIT(4) ++#define B_AX_PTCLTOP_CKEN BIT(3) ++#define B_AX_SCHEDULER_CKEN BIT(2) ++#define B_AX_TMAC_CKEN BIT(1) ++#define B_AX_RMAC_CKEN BIT(0) ++ ++#define R_AX_WMAC_RFMOD 0xC010 ++#define R_AX_WMAC_RFMOD_C1 0xE010 ++#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0) ++ ++#define R_AX_GID_POSITION0 0xC070 ++#define R_AX_GID_POSITION0_C1 0xE070 ++#define R_AX_GID_POSITION1 0xC074 ++#define R_AX_GID_POSITION1_C1 0xE074 ++#define R_AX_GID_POSITION2 0xC078 ++#define R_AX_GID_POSITION2_C1 0xE078 ++#define R_AX_GID_POSITION3 0xC07C ++#define R_AX_GID_POSITION3_C1 0xE07C ++#define R_AX_GID_POSITION_EN0 0xC080 ++#define R_AX_GID_POSITION_EN0_C1 0xE080 ++#define R_AX_GID_POSITION_EN1 0xC084 ++#define R_AX_GID_POSITION_EN1_C1 0xE084 ++ ++#define R_AX_TX_SUB_CARRIER_VALUE 0xC088 ++#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 ++#define B_AX_TXSC_80M_MASK GENMASK(11, 8) ++#define B_AX_TXSC_40M_MASK GENMASK(7, 4) ++#define B_AX_TXSC_20M_MASK GENMASK(3, 0) ++ ++#define R_AX_CMAC_ERR_ISR 0xC164 ++#define R_AX_CMAC_ERR_ISR_C1 0xE164 ++#define B_AX_WMAC_TX_ERR_IND BIT(7) ++#define B_AX_WMAC_RX_ERR_IND BIT(6) ++#define B_AX_TXPWR_CTRL_ERR_IND BIT(5) ++#define B_AX_PHYINTF_ERR_IND BIT(4) ++#define B_AX_DMA_TOP_ERR_IND BIT(3) ++#define B_AX_PTCL_TOP_ERR_IND BIT(1) ++#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) ++ ++#define R_AX_MACID_SLEEP_0 0xC2C0 ++#define R_AX_MACID_SLEEP_0_C1 0xE2C0 ++#define B_AX_MACID31_0_SLEEP_SH 0 ++#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_1 0xC2C4 ++#define R_AX_MACID_SLEEP_1_C1 0xE2C4 ++#define B_AX_MACID63_32_SLEEP_SH 0 ++#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_2 0xC2C8 ++#define R_AX_MACID_SLEEP_2_C1 0xE2C8 ++#define B_AX_MACID95_64_SLEEP_SH 0 ++#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_3 0xC2CC ++#define R_AX_MACID_SLEEP_3_C1 0xE2CC ++#define B_AX_MACID127_96_SLEEP_SH 0 ++#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0) ++ ++#define SCH_PREBKF_24US 0x18 ++#define R_AX_PREBKF_CFG_0 0xC338 ++#define R_AX_PREBKF_CFG_0_C1 0xE338 ++#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0) ++ ++#define R_AX_CCA_CFG_0 0xC340 ++#define R_AX_CCA_CFG_0_C1 0xE340 ++#define B_AX_BTCCA_BRK_TXOP_EN BIT(9) ++#define B_AX_BTCCA_EN BIT(5) ++#define B_AX_EDCCA_EN BIT(4) ++#define B_AX_SEC80_EN BIT(3) ++#define B_AX_SEC40_EN BIT(2) ++#define B_AX_SEC20_EN BIT(1) ++#define B_AX_CCA_EN BIT(0) ++ ++#define R_AX_CTN_TXEN 0xC348 ++#define R_AX_CTN_TXEN_C1 0xE348 ++#define B_AX_CTN_TXEN_TWT_1 BIT(15) ++#define B_AX_CTN_TXEN_TWT_0 BIT(14) ++#define B_AX_CTN_TXEN_ULQ BIT(13) ++#define B_AX_CTN_TXEN_BCNQ BIT(12) ++#define B_AX_CTN_TXEN_HGQ BIT(11) ++#define B_AX_CTN_TXEN_CPUMGQ BIT(10) ++#define B_AX_CTN_TXEN_MGQ1 BIT(9) ++#define B_AX_CTN_TXEN_MGQ BIT(8) ++#define B_AX_CTN_TXEN_VO_1 BIT(7) ++#define B_AX_CTN_TXEN_VI_1 BIT(6) ++#define B_AX_CTN_TXEN_BK_1 BIT(5) ++#define B_AX_CTN_TXEN_BE_1 BIT(4) ++#define B_AX_CTN_TXEN_VO_0 BIT(3) ++#define B_AX_CTN_TXEN_VI_0 BIT(2) ++#define B_AX_CTN_TXEN_BK_0 BIT(1) ++#define B_AX_CTN_TXEN_BE_0 BIT(0) ++ ++#define R_AX_MUEDCA_BE_PARAM_0 0xC350 ++#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 ++#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16) ++#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8) ++#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0) ++ ++#define R_AX_MUEDCA_BK_PARAM_0 0xC354 ++#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 ++#define R_AX_MUEDCA_VI_PARAM_0 0xC358 ++#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 ++#define R_AX_MUEDCA_VO_PARAM_0 0xC35C ++#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C ++ ++#define R_AX_MUEDCA_EN 0xC370 ++#define R_AX_MUEDCA_EN_C1 0xE370 ++#define B_AX_MUEDCA_WMM_SEL BIT(8) ++#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) ++#define B_AX_MUEDCA_EN_0 BIT(0) ++ ++#define R_AX_CCA_CONTROL 0xC390 ++#define R_AX_CCA_CONTROL_C1 0xE390 ++#define B_AX_TB_CHK_TX_NAV BIT(31) ++#define B_AX_TB_CHK_BASIC_NAV BIT(30) ++#define B_AX_TB_CHK_BTCCA BIT(29) ++#define B_AX_TB_CHK_EDCCA BIT(28) ++#define B_AX_TB_CHK_CCA_S80 BIT(27) ++#define B_AX_TB_CHK_CCA_S40 BIT(26) ++#define B_AX_TB_CHK_CCA_S20 BIT(25) ++#define B_AX_TB_CHK_CCA_P20 BIT(24) ++#define B_AX_SIFS_CHK_BTCCA BIT(21) ++#define B_AX_SIFS_CHK_EDCCA BIT(20) ++#define B_AX_SIFS_CHK_CCA_S80 BIT(19) ++#define B_AX_SIFS_CHK_CCA_S40 BIT(18) ++#define B_AX_SIFS_CHK_CCA_S20 BIT(17) ++#define B_AX_SIFS_CHK_CCA_P20 BIT(16) ++#define B_AX_CTN_CHK_TXNAV BIT(8) ++#define B_AX_CTN_CHK_INTRA_NAV BIT(7) ++#define B_AX_CTN_CHK_BASIC_NAV BIT(6) ++#define B_AX_CTN_CHK_BTCCA BIT(5) ++#define B_AX_CTN_CHK_EDCCA BIT(4) ++#define B_AX_CTN_CHK_CCA_S80 BIT(3) ++#define B_AX_CTN_CHK_CCA_S40 BIT(2) ++#define B_AX_CTN_CHK_CCA_S20 BIT(1) ++#define B_AX_CTN_CHK_CCA_P20 BIT(0) ++ ++#define R_AX_SCHEDULE_ERR_IMR 0xC3E8 ++#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 ++#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) ++#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) ++ ++#define R_AX_SCHEDULE_ERR_ISR 0xC3EC ++#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC ++ ++#define R_AX_SCH_DBG_SEL 0xC3F4 ++#define R_AX_SCH_DBG_SEL_C1 0xE3F4 ++#define B_AX_SCH_DBG_EN BIT(16) ++#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8) ++#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_SCH_DBG 0xC3F8 ++#define R_AX_SCH_DBG_C1 0xE3F8 ++#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0) ++ ++#define R_AX_PORT_CFG_P0 0xC400 ++#define R_AX_PORT_CFG_P1 0xC440 ++#define R_AX_PORT_CFG_P2 0xC480 ++#define R_AX_PORT_CFG_P3 0xC4C0 ++#define R_AX_PORT_CFG_P4 0xC500 ++#define B_AX_BRK_SETUP BIT(16) ++#define B_AX_TBTT_UPD_SHIFT_SEL BIT(15) ++#define B_AX_BCN_DROP_ALLOW BIT(14) ++#define B_AX_TBTT_PROHIB_EN BIT(13) ++#define B_AX_BCNTX_EN BIT(12) ++#define B_AX_NET_TYPE_MASK GENMASK(11, 10) ++#define B_AX_BCN_FORCETX_EN BIT(9) ++#define B_AX_TXBCN_BTCCA_EN BIT(8) ++#define B_AX_BCNERR_CNT_EN BIT(7) ++#define B_AX_BCN_AGRES BIT(6) ++#define B_AX_TSFTR_RST BIT(5) ++#define B_AX_RX_BSSID_FIT_EN BIT(4) ++#define B_AX_TSF_UDT_EN BIT(3) ++#define B_AX_PORT_FUNC_EN BIT(2) ++#define B_AX_TXBCN_RPT_EN BIT(1) ++#define B_AX_RXBCN_RPT_EN BIT(0) ++ ++#define R_AX_TBTT_PROHIB_P0 0xC404 ++#define R_AX_TBTT_PROHIB_P1 0xC444 ++#define R_AX_TBTT_PROHIB_P2 0xC484 ++#define R_AX_TBTT_PROHIB_P3 0xC4C4 ++#define R_AX_TBTT_PROHIB_P4 0xC504 ++#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16) ++#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_AREA_P0 0xC408 ++#define R_AX_BCN_AREA_P1 0xC448 ++#define R_AX_BCN_AREA_P2 0xC488 ++#define R_AX_BCN_AREA_P3 0xC4C8 ++#define R_AX_BCN_AREA_P4 0xC508 ++#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16) ++#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0) ++ ++#define R_AX_BCNERLYINT_CFG_P0 0xC40C ++#define R_AX_BCNERLYINT_CFG_P1 0xC44C ++#define R_AX_BCNERLYINT_CFG_P2 0xC48C ++#define R_AX_BCNERLYINT_CFG_P3 0xC4CC ++#define R_AX_BCNERLYINT_CFG_P4 0xC50C ++#define B_AX_BCNERLY_MASK GENMASK(11, 0) ++ ++#define R_AX_TBTTERLYINT_CFG_P0 0xC40E ++#define R_AX_TBTTERLYINT_CFG_P1 0xC44E ++#define R_AX_TBTTERLYINT_CFG_P2 0xC48E ++#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE ++#define R_AX_TBTTERLYINT_CFG_P4 0xC50E ++#define B_AX_TBTTERLY_MASK GENMASK(11, 0) ++ ++#define R_AX_TBTT_AGG_P0 0xC412 ++#define R_AX_TBTT_AGG_P1 0xC452 ++#define R_AX_TBTT_AGG_P2 0xC492 ++#define R_AX_TBTT_AGG_P3 0xC4D2 ++#define R_AX_TBTT_AGG_P4 0xC512 ++#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8) ++ ++#define R_AX_BCN_SPACE_CFG_P0 0xC414 ++#define R_AX_BCN_SPACE_CFG_P1 0xC454 ++#define R_AX_BCN_SPACE_CFG_P2 0xC494 ++#define R_AX_BCN_SPACE_CFG_P3 0xC4D4 ++#define R_AX_BCN_SPACE_CFG_P4 0xC514 ++#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16) ++#define B_AX_BCN_SPACE_MASK GENMASK(15, 0) ++ ++#define R_AX_BCN_FORCETX_P0 0xC418 ++#define R_AX_BCN_FORCETX_P1 0xC458 ++#define R_AX_BCN_FORCETX_P2 0xC498 ++#define R_AX_BCN_FORCETX_P3 0xC4D8 ++#define R_AX_BCN_FORCETX_P4 0xC518 ++#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16) ++#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0) ++#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_ERR_CNT_P0 0xC420 ++#define R_AX_BCN_ERR_CNT_P1 0xC460 ++#define R_AX_BCN_ERR_CNT_P2 0xC4A0 ++#define R_AX_BCN_ERR_CNT_P3 0xC4E0 ++#define R_AX_BCN_ERR_CNT_P4 0xC520 ++#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24) ++#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16) ++#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0) ++#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_ERR_FLAG_P0 0xC424 ++#define R_AX_BCN_ERR_FLAG_P1 0xC464 ++#define R_AX_BCN_ERR_FLAG_P2 0xC4A4 ++#define R_AX_BCN_ERR_FLAG_P3 0xC4E4 ++#define R_AX_BCN_ERR_FLAG_P4 0xC524 ++#define B_AX_BCN_ERR_FLAG_OTHERS BIT(6) ++#define B_AX_BCN_ERR_FLAG_MAC BIT(5) ++#define B_AX_BCN_ERR_FLAG_TXON BIT(4) ++#define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3) ++#define B_AX_BCN_ERR_FLAG_INVALID BIT(2) ++#define B_AX_BCN_ERR_FLAG_CMP BIT(1) ++#define B_AX_BCN_ERR_FLAG_LOCK BIT(0) ++ ++#define R_AX_DTIM_CTRL_P0 0xC426 ++#define R_AX_DTIM_CTRL_P1 0xC466 ++#define R_AX_DTIM_CTRL_P2 0xC4A6 ++#define R_AX_DTIM_CTRL_P3 0xC4E6 ++#define R_AX_DTIM_CTRL_P4 0xC526 ++#define B_AX_DTIM_NUM_MASK GENMASK(15, 0) ++#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0) ++ ++#define R_AX_TBTT_SHIFT_P0 0xC428 ++#define R_AX_TBTT_SHIFT_P1 0xC468 ++#define R_AX_TBTT_SHIFT_P2 0xC4A8 ++#define R_AX_TBTT_SHIFT_P3 0xC4E8 ++#define R_AX_TBTT_SHIFT_P4 0xC528 ++#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0) ++ ++#define R_AX_BCN_CNT_TMR_P0 0xC434 ++#define R_AX_BCN_CNT_TMR_P1 0xC474 ++#define R_AX_BCN_CNT_TMR_P2 0xC4B4 ++#define R_AX_BCN_CNT_TMR_P3 0xC4F4 ++#define R_AX_BCN_CNT_TMR_P4 0xC534 ++#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0) ++ ++#define R_AX_TSFTR_LOW_P0 0xC438 ++#define R_AX_TSFTR_LOW_P1 0xC478 ++#define R_AX_TSFTR_LOW_P2 0xC4B8 ++#define R_AX_TSFTR_LOW_P3 0xC4F8 ++#define R_AX_TSFTR_LOW_P4 0xC538 ++#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0) ++ ++#define R_AX_TSFTR_HIGH_P0 0xC43C ++#define R_AX_TSFTR_HIGH_P1 0xC47C ++#define R_AX_TSFTR_HIGH_P2 0xC4BC ++#define R_AX_TSFTR_HIGH_P3 0xC4FC ++#define R_AX_TSFTR_HIGH_P4 0xC53C ++#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0) ++ ++#define R_AX_MBSSID_CTRL 0xC568 ++#define R_AX_MBSSID_CTRL_C1 0xE568 ++#define B_AX_P0MB_ALL_MASK GENMASK(23, 1) ++#define B_AX_P0MB_NUM_MASK GENMASK(19, 16) ++#define B_AX_P0MB15_EN BIT(15) ++#define B_AX_P0MB14_EN BIT(14) ++#define B_AX_P0MB13_EN BIT(13) ++#define B_AX_P0MB12_EN BIT(12) ++#define B_AX_P0MB11_EN BIT(11) ++#define B_AX_P0MB10_EN BIT(10) ++#define B_AX_P0MB9_EN BIT(9) ++#define B_AX_P0MB8_EN BIT(8) ++#define B_AX_P0MB7_EN BIT(7) ++#define B_AX_P0MB6_EN BIT(6) ++#define B_AX_P0MB5_EN BIT(5) ++#define B_AX_P0MB4_EN BIT(4) ++#define B_AX_P0MB3_EN BIT(3) ++#define B_AX_P0MB2_EN BIT(2) ++#define B_AX_P0MB1_EN BIT(1) ++ ++#define R_AX_AMPDU_AGG_LIMIT 0xC610 ++#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24) ++#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) ++#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) ++#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0) ++ ++#define R_AX_AGG_LEN_HT_0 0xC614 ++#define R_AX_AGG_LEN_HT_0_C1 0xE614 ++#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) ++#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) ++#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) ++ ++#define S_AX_CTS2S_TH_SEC_256B 1 ++#define R_AX_SIFS_SETTING 0xC624 ++#define R_AX_SIFS_SETTING_C1 0xE624 ++#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) ++#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) ++#define B_AX_HW_CTS2SELF_EN BIT(16) ++#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 ++#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) ++#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) ++#define S_AX_CTS2S_TH_1K 4 ++ ++#define R_AX_TXRATE_CHK 0xC628 ++#define R_AX_TXRATE_CHK_C1 0xE628 ++#define B_AX_DEFT_RATE_MASK GENMASK(15, 7) ++#define B_AX_BAND_MODE BIT(4) ++#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2) ++#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) ++#define B_AX_CHECK_CCK_EN BIT(0) ++ ++#define R_AX_TXCNT 0xC62C ++#define R_AX_TXCNT_C1 0xE62C ++#define B_AX_ADD_TXCNT_BY BIT(31) ++#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24) ++#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16) ++ ++#define R_AX_MBSSID_DROP_0 0xC63C ++#define R_AX_MBSSID_DROP_0_C1 0xE63C ++#define B_AX_GI_LTF_FB_SEL BIT(30) ++#define B_AX_RATE_SEL_MASK GENMASK(29, 24) ++#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16) ++#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0) ++ ++#define R_AX_BT_PLT 0xC67C ++#define R_AX_BT_PLT_C1 0xE67C ++#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) ++#define B_AX_BT_PLT_RST BIT(9) ++#define B_AX_PLT_EN BIT(8) ++#define B_AX_RX_PLT_GNT_LTE_RX BIT(7) ++#define B_AX_RX_PLT_GNT_BT_RX BIT(6) ++#define B_AX_RX_PLT_GNT_BT_TX BIT(5) ++#define B_AX_RX_PLT_GNT_WL BIT(4) ++#define B_AX_TX_PLT_GNT_LTE_RX BIT(3) ++#define B_AX_TX_PLT_GNT_BT_RX BIT(2) ++#define B_AX_TX_PLT_GNT_BT_TX BIT(1) ++#define B_AX_TX_PLT_GNT_WL BIT(0) ++ ++#define R_AX_PTCL_BSS_COLOR_0 0xC6A0 ++#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 ++#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24) ++#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16) ++#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8) ++#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_BSS_COLOR_1 0xC6A4 ++#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 ++#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_IMR0 0xC6C0 ++#define R_AX_PTCL_IMR0_C1 0xE6C0 ++#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) ++#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) ++ ++#define R_AX_PTCL_ISR0 0xC6C4 ++#define R_AX_PTCL_ISR0_C1 0xE6C4 ++ ++#define S_AX_PTCL_TO_2MS 0x3F ++#define R_AX_PTCL_FSM_MON 0xC6E8 ++#define R_AX_PTCL_FSM_MON_C1 0xE6E8 ++#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) ++#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_TX_CTN_SEL 0xC6EC ++#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC ++#define B_AX_PTCL_TX_ON_STAT BIT(7) ++ ++#define R_AX_PTCL_DBG_INFO 0xC6F0 ++#define R_AX_PTCL_DBG_INFO_C1 0xE6F0 ++#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0) ++#define R_AX_PTCL_DBG 0xC6F4 ++#define R_AX_PTCL_DBG_C1 0xE6F4 ++#define B_AX_PTCL_DBG_EN BIT(8) ++#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_DLE_CTRL 0xC800 ++#define R_AX_DLE_CTRL_C1 0xE800 ++#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) ++#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) ++#define R_AX_RXDMA_PKT_INFO_0 0xC814 ++#define R_AX_RXDMA_PKT_INFO_1 0xC818 ++#define R_AX_RXDMA_PKT_INFO_2 0xC81C ++ ++#define R_AX_TCR1 0xCA04 ++#define R_AX_TCR1_C1 0xEA04 ++#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28) ++#define B_AX_TCR_CCK_LOCK_CLK BIT(27) ++#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) ++#define B_AX_TCR_USTIME GENMASK(23, 16) ++#define B_AX_TCR_SMOOTH_VAL BIT(15) ++#define B_AX_TCR_SMOOTH_CTRL BIT(14) ++#define B_AX_CS_REQ_VAL BIT(13) ++#define B_AX_CS_REQ_SEL BIT(12) ++#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8) ++#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0) ++ ++#define R_AX_PPWRBIT_SETTING 0xCA0C ++#define R_AX_PPWRBIT_SETTING_C1 0xEA0C ++ ++#define R_AX_MACTX_DBG_SEL_CNT 0xCA20 ++#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 ++#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24) ++#define B_AX_MACTX_DMA_CNT GENMASK(23, 16) ++#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) ++#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) ++#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) ++#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) ++#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0) ++ ++#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 ++#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 ++#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0) ++ ++#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 ++#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 ++#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0) ++ ++#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC ++#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC ++#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0) ++ ++#define R_AX_RSP_CHK_SIG 0xCC00 ++#define R_AX_RSP_CHK_SIG_C1 0xEC00 ++#define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) ++#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) ++#define B_AX_RSP_CHK_BASIC_NAV BIT(21) ++#define B_AX_RSP_CHK_INTRA_NAV BIT(20) ++#define B_AX_RSP_CHK_TXNAV BIT(19) ++#define B_AX_TXDATA_END_PS_OPT BIT(18) ++#define B_AX_CHECK_SOUNDING_SEQ BIT(17) ++#define B_AX_RXBA_IGNOREA2 BIT(16) ++#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8) ++#define B_AX_ACKTO_MASK GENMASK(7, 0) ++ ++#define R_AX_TRXPTCL_RESP_0 0xCC04 ++#define R_AX_TRXPTCL_RESP_0_C1 0xEC04 ++#define B_AX_WMAC_RESP_STBC_EN BIT(31) ++#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) ++#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) ++#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) ++#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) ++#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) ++#define B_AX_RSP_CHK_BTCCA BIT(25) ++#define B_AX_RSP_CHK_EDCCA BIT(24) ++#define B_AX_RSP_CHK_CCA BIT(23) ++#define B_AX_WMAC_LDPC_EN BIT(22) ++#define B_AX_WMAC_SGIEN BIT(21) ++#define B_AX_WMAC_SPLCPEN BIT(20) ++#define B_AX_WMAC_BESP_EARLY_TXBA BIT(17) ++#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) ++#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) ++#define WMAC_SPEC_SIFS_OFDM_52A 0x15 ++#define WMAC_SPEC_SIFS_OFDM_52B 0x11 ++#define WMAC_SPEC_SIFS_OFDM_52C 0x11 ++#define WMAC_SPEC_SIFS_CCK 0xA ++ ++#define R_AX_MAC_LOOPBACK 0xCC20 ++#define R_AX_MAC_LOOPBACK_C1 0xEC20 ++#define B_AX_MACLBK_EN BIT(0) ++ ++#define R_AX_RXTRIG_TEST_USER_2 0xCCB0 ++#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 ++#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24) ++#define B_AX_RXTRIG_RU26_DIS BIT(21) ++#define B_AX_RXTRIG_FCSCHK_EN BIT(20) ++#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) ++#define B_AX_RXTRIG_EN BIT(16) ++#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 ++#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 ++#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 ++#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 ++#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 ++#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 ++#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0) ++ ++#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC ++#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC ++ ++#define R_AX_DBGSEL_TRXPTCL 0xCCF4 ++#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 ++#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) ++ ++#define R_AX_PHYINFO_ERR_IMR 0xCCFC ++#define R_AX_PHYINFO_ERR_IMR_C1 0xECFC ++#define B_AX_CSI_ON_TIMEOUT BIT(29) ++#define B_AX_STS_ON_TIMEOUT BIT(28) ++#define B_AX_DATA_ON_TIMEOUT BIT(27) ++#define B_AX_OFDM_CCA_TIMEOUT BIT(26) ++#define B_AX_CCK_CCA_TIMEOUT BIT(25) ++#define B_AXC_PHY_TXON_TIMEOUT BIT(24) ++#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21) ++#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20) ++#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19) ++#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18) ++#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17) ++#define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16) ++#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0) ++ ++#define R_AX_PHYINFO_ERR_ISR 0xCCFC ++#define R_AX_PHYINFO_ERR_ISR_C1 0xECFC ++ ++#define R_AX_BFMER_CTRL_0 0xCD78 ++#define R_AX_BFMER_CTRL_0_C1 0xED78 ++#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24) ++#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16) ++#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8) ++#define B_AX_BFMER_NDP_BFEN BIT(2) ++#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) ++ ++#define R_AX_BFMEE_RESP_OPTION 0xCD80 ++#define R_AX_BFMEE_RESP_OPTION_C1 0xED80 ++#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24) ++#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20) ++#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17) ++#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) ++#define BFRP_RX_STANDBY_TIMER 0x0 ++#define NDP_RX_STANDBY_TIMER 0xFF ++#define B_AX_BFMEE_HE_NDPA_EN BIT(2) ++#define B_AX_BFMEE_VHT_NDPA_EN BIT(1) ++#define B_AX_BFMEE_HT_NDPA_EN BIT(0) ++ ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 ++#define B_AX_BFMEE_CSISEQ_SEL BIT(29) ++#define B_AX_BFMEE_BFPARAM_SEL BIT(28) ++#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) ++#define B_AX_BFMEE_BF_PORT_SEL BIT(23) ++#define B_AX_BFMEE_USE_NSTS BIT(22) ++#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) ++#define B_AX_BFMEE_CSI_GID_SEL BIT(20) ++#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18) ++#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) ++#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) ++#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) ++#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) ++#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) ++#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) ++#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) ++#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) ++#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) ++#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) ++#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) ++ ++#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C ++#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C ++#define CSI_RRSC_BMAP 0x29292911 ++ ++#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 ++#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 ++#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16) ++#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8) ++#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0) ++#define CSI_INIT_RATE_HE 0x3 ++#define CSI_INIT_RATE_VHT 0x3 ++#define CSI_INIT_RATE_HT 0x3 ++ ++#define R_AX_RCR 0xCE00 ++#define R_AX_RCR_C1 0xEE00 ++#define B_AX_STOP_RX_IN BIT(11) ++#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8) ++#define B_AX_CH_EN_MASK GENMASK(3, 0) ++ ++#define R_AX_DLK_PROTECT_CTL 0xCE02 ++#define R_AX_DLK_PROTECT_CTL_C1 0xEE02 ++#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) ++#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) ++ ++#define R_AX_PLCP_HDR_FLTR 0xCE04 ++#define R_AX_PLCP_HDR_FLTR_C1 0xEE04 ++#define B_AX_DIS_CHK_MIN_LEN BIT(8) ++#define B_AX_HE_SIGB_CRC_CHK BIT(6) ++#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) ++#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) ++#define B_AX_SIGA_CRC_CHK BIT(3) ++#define B_AX_LSIG_PARITY_CHK_EN BIT(2) ++#define B_AX_CCK_SIG_CHK BIT(1) ++#define B_AX_CCK_CRC_CHK BIT(0) ++ ++#define R_AX_RX_FLTR_OPT 0xCE20 ++#define R_AX_RX_FLTR_OPT_C1 0xEE20 ++#define B_AX_UID_FILTER_MASK GENMASK(31, 24) ++#define B_AX_UNSPT_FILTER_SH 22 ++#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22) ++#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) ++#define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f ++#define B_AX_A_FTM_REQ BIT(14) ++#define B_AX_A_ERR_PKT BIT(13) ++#define B_AX_A_UNSUP_PKT BIT(12) ++#define B_AX_A_CRC32_ERR BIT(11) ++#define B_AX_A_PWR_MGNT BIT(10) ++#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8) ++#define B_AX_A_BCN_CHK_EN BIT(7) ++#define B_AX_A_MC_LIST_CAM_MATCH BIT(6) ++#define B_AX_A_BC_CAM_MATCH BIT(5) ++#define B_AX_A_UC_CAM_MATCH BIT(4) ++#define B_AX_A_MC BIT(3) ++#define B_AX_A_BC BIT(2) ++#define B_AX_A_A1_MATCH BIT(1) ++#define B_AX_SNIFFER_MODE BIT(0) ++#define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC | \ ++ B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH | \ ++ B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ | \ ++ u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \ ++ B_AX_A_BCN_CHK_EN) ++#define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK) ++ ++#define R_AX_CTRL_FLTR 0xCE24 ++#define R_AX_CTRL_FLTR_C1 0xEE24 ++#define R_AX_MGNT_FLTR 0xCE28 ++#define R_AX_MGNT_FLTR_C1 0xEE28 ++#define R_AX_DATA_FLTR 0xCE2C ++#define R_AX_DATA_FLTR_C1 0xEE2C ++#define RX_FLTR_FRAME_DROP 0x00000000 ++#define RX_FLTR_FRAME_TO_HOST 0x55555555 ++#define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA ++ ++#define R_AX_ADDR_CAM_CTRL 0xCE34 ++#define R_AX_ADDR_CAM_CTRL_C1 0xEE34 ++#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16) ++#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) ++#define B_AX_ADDR_CAM_CLR BIT(8) ++#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) ++#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) ++#define B_AX_ADDR_CAM_EN BIT(0) ++ ++#define R_AX_RESPBA_CAM_CTRL 0xCE3C ++#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C ++#define B_AX_SSN_SEL BIT(2) ++ ++#define R_AX_PPDU_STAT 0xCE40 ++#define R_AX_PPDU_STAT_C1 0xEE40 ++#define B_AX_PPDU_STAT_RPT_TRIG BIT(8) ++#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) ++#define B_AX_PPDU_STAT_RPT_A1M BIT(4) ++#define B_AX_APP_PLCP_HDR_RPT BIT(3) ++#define B_AX_APP_RX_CNT_RPT BIT(2) ++#define B_AX_APP_MAC_INFO_RPT BIT(1) ++#define B_AX_PPDU_STAT_RPT_EN BIT(0) ++ ++#define R_AX_RX_SR_CTRL 0xCE4A ++#define R_AX_RX_SR_CTRL_C1 0xEE4A ++#define B_AX_SR_EN BIT(0) ++ ++#define R_AX_RX_STATE_MONITOR 0xCEF0 ++#define R_AX_RX_STATE_MONITOR_C1 0xEEF0 ++#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) ++#define B_AX_STATE_CUR_MASK GENMASK(31, 16) ++#define B_AX_STATE_NXT_MASK GENMASK(13, 8) ++#define B_AX_STATE_UPD BIT(7) ++#define B_AX_STATE_SEL_MASK GENMASK(4, 0) ++ ++#define R_AX_RMAC_ERR_ISR 0xCEF4 ++#define R_AX_RMAC_ERR_ISR_C1 0xEEF4 ++#define B_AX_RXERR_INTPS_EN BIT(31) ++#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) ++#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) ++#define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17) ++#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) ++#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) ++#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) ++#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) ++#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) ++#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) ++#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) ++#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) ++#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) ++#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) ++#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) ++#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) ++#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) ++ ++#define R_AX_RMAC_PLCP_MON 0xCEF8 ++#define R_AX_RMAC_PLCP_MON_C1 0xEEF8 ++#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0) ++#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28) ++#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0) ++ ++#define R_AX_RX_DEBUG_SELECT 0xCEFC ++#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC ++#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_PWR_RATE_CTRL 0xD200 ++#define R_AX_PWR_RATE_CTRL_C1 0xF200 ++#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) ++#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) ++ ++#define R_AX_PWR_RATE_OFST_CTRL 0xD204 ++#define R_AX_PWR_COEXT_CTRL 0xD220 ++#define B_AX_TXAGC_BT_EN BIT(1) ++#define B_AX_TXAGC_BT_MASK GENMASK(11, 3) ++ ++#define R_AX_PWR_UL_CTRL0 0xD240 ++#define R_AX_PWR_UL_CTRL2 0xD248 ++#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) ++#define B_AX_PWR_UL_CTRL2_MASK 0x07700007 ++#define R_AX_PWR_UL_TB_CTRL 0xD288 ++#define B_AX_PWR_UL_TB_CTRL_EN BIT(31) ++#define R_AX_PWR_UL_TB_1T 0xD28C ++#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) ++#define R_AX_PWR_UL_TB_2T 0xD290 ++#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) ++#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 ++#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 ++#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 ++#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 ++#define R_AX_PWR_LMT_TABLE0 0xD2EC ++#define R_AX_PWR_LMT_TABLE19 0xD338 ++#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 ++#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 ++#define R_AX_PWR_RU_LMT_TABLE0 0xD33C ++#define R_AX_PWR_RU_LMT_TABLE11 0xD368 ++#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 ++#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 ++#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C ++#define R_AX_PWR_MACID_LMT_TABLE127 0xD568 ++ ++#define R_AX_TXPWR_IMR 0xD9E0 ++#define R_AX_TXPWR_IMR_C1 0xF9E0 ++#define R_AX_TXPWR_ISR 0xD9E4 ++#define R_AX_TXPWR_ISR_C1 0xF9E4 ++ ++#define R_AX_BTC_CFG 0xDA00 ++#define B_AX_DIS_BTC_CLK_G BIT(2) ++ ++#define R_AX_WL_PRI_MSK 0xDA10 ++#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) ++ ++#define R_AX_BTC_FUNC_EN 0xDA20 ++#define R_AX_BTC_FUNC_EN_C1 0xFA20 ++#define B_AX_PTA_WL_TX_EN BIT(1) ++#define B_AX_PTA_EDCCA_EN BIT(0) ++ ++#define R_BTC_BREAK_TABLE 0xDA2C ++#define BTC_BREAK_PARAM 0xf0ffffff ++ ++#define R_BTC_BT_COEX_MSK_TABLE 0xDA30 ++#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) ++ ++#define R_AX_BT_COEX_CFG_2 0xDA34 ++#define R_AX_BT_COEX_CFG_2_C1 0xFA34 ++#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12) ++#define B_AX_GNT_BT_POLARITY BIT(8) ++#define B_AX_TIMER_MASK GENMASK(7, 0) ++#define MAC_AX_CSR_RATE 80 ++ ++#define R_AX_CSR_MODE 0xDA40 ++#define R_AX_CSR_MODE_C1 0xFA40 ++#define B_AX_BT_CNT_RST BIT(16) ++#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12) ++#define MAC_AX_CSR_DELAY 0 ++#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8) ++#define MAC_AX_CSR_TRX_TO 4 ++#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4) ++#define MAC_AX_CSR_PRI_TO 5 ++#define B_AX_WL_ACT_MSK BIT(3) ++#define B_AX_STATIS_BT_EN BIT(2) ++#define B_AX_WL_ACT_MASK_ENABLE BIT(1) ++#define B_AX_ENHANCED_BT BIT(0) ++ ++#define R_AX_BT_STAST_HIGH 0xDA44 ++#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16) ++#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0) ++#define R_AX_BT_STAST_LOW 0xDA48 ++#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0) ++#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16) ++ ++#define R_AX_TDMA_MODE 0xDA4C ++#define R_AX_TDMA_MODE_C1 0xFA4C ++#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16) ++#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8) ++#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6) ++#define B_AX_TDMA_BT_START_NOTIFY BIT(5) ++#define B_AX_ENABLE_TDMA_FW_MODE BIT(4) ++#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) ++#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) ++#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) ++#define B_AX_RTK_BT_ENABLE BIT(0) ++ ++#define R_AX_BT_COEX_CFG_5 0xDA6C ++#define R_AX_BT_COEX_CFG_5_C1 0xFA6C ++#define B_AX_BT_TIME_MASK GENMASK(31, 6) ++#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0) ++#define MAC_AX_RTK_RATE 5 ++ ++#define R_AX_LTE_CTRL 0xDAF0 ++#define R_AX_LTE_WDATA 0xDAF4 ++#define R_AX_LTE_RDATA 0xDAF8 ++ ++#define CMAC1_START_ADDR 0xE000 ++#define CMAC1_END_ADDR 0xFFFF ++#define R_AX_CMAC_REG_END 0xFFFF ++ ++#define R_AX_LTE_SW_CFG_1 0x0038 ++#define R_AX_LTE_SW_CFG_1_C1 0x2038 ++#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) ++#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) ++#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) ++#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) ++#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) ++#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) ++#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) ++#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) ++#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) ++#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) ++#define B_AX_LTE_PATTERN_2_EN BIT(17) ++#define B_AX_LTE_PATTERN_1_EN BIT(16) ++#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) ++#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) ++#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) ++#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) ++#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) ++#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) ++#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) ++#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) ++#define B_AX_LTECOEX_FUN_EN BIT(7) ++#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) ++#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4) ++#define B_AX_LTECOEX_UART_MUX BIT(3) ++#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0) ++ ++#define R_AX_LTE_SW_CFG_2 0x003C ++#define R_AX_LTE_SW_CFG_2_C1 0x203C ++#define B_AX_WL_RX_CTRL BIT(8) ++#define B_AX_GNT_WL_RX_SW_VAL BIT(7) ++#define B_AX_GNT_WL_RX_SW_CTRL BIT(6) ++#define B_AX_GNT_WL_TX_SW_VAL BIT(5) ++#define B_AX_GNT_WL_TX_SW_CTRL BIT(4) ++#define B_AX_GNT_BT_RX_SW_VAL BIT(3) ++#define B_AX_GNT_BT_RX_SW_CTRL BIT(2) ++#define B_AX_GNT_BT_TX_SW_VAL BIT(1) ++#define B_AX_GNT_BT_TX_SW_CTRL BIT(0) ++ ++#define RR_MOD 0x00 ++#define RR_MOD_IQK GENMASK(19, 4) ++#define RR_MOD_DPK GENMASK(19, 5) ++#define RR_MOD_MASK GENMASK(19, 16) ++#define RR_MOD_V_DOWN 0x0 ++#define RR_MOD_V_STANDBY 0x1 ++#define RR_MOD_V_TX 0x2 ++#define RR_MOD_V_RX 0x3 ++#define RR_MOD_V_TXIQK 0x4 ++#define RR_MOD_V_DPK 0x5 ++#define RR_MOD_V_RXK1 0x6 ++#define RR_MOD_V_RXK2 0x7 ++#define RR_MOD_M_RXG GENMASK(13, 4) ++#define RR_MOD_M_RXBB GENMASK(9, 5) ++#define RR_MODOPT 0x01 ++#define RR_MODOPT_M_TXPWR GENMASK(5, 0) ++#define RR_WLSEL 0x02 ++#define RR_WLSEL_AG GENMASK(18, 16) ++#define RR_RSV1 0x05 ++#define RR_RSV1_RST BIT(0) ++#define RR_DTXLOK 0x08 ++#define RR_RSV2 0x09 ++#define RR_CFGCH 0x18 ++#define RR_BTC 0x1a ++#define RR_BTC_TXBB GENMASK(14, 12) ++#define RR_BTC_RXBB GENMASK(11, 10) ++#define RR_RCKC 0x1b ++#define RR_RCKC_CA GENMASK(14, 10) ++#define RR_RCKS 0x1c ++#define RR_RCKO 0x1d ++#define RR_RCKO_OFF GENMASK(13, 9) ++#define RR_RXKPLL 0x1e ++#define RR_RXKPLL_OFF GENMASK(5, 0) ++#define RR_RXKPLL_POW BIT(19) ++#define RR_RSV4 0x1f ++#define RR_RXK 0x20 ++#define RR_RXK_PLLEN BIT(5) ++#define RR_RXK_SEL5G BIT(7) ++#define RR_RXK_SEL2G BIT(8) ++#define RR_LUTWA 0x33 ++#define RR_LUTWA_MASK GENMASK(9, 0) ++#define RR_LUTWD1 0x3e ++#define RR_LUTWD0 0x3f ++#define RR_TM 0x42 ++#define RR_TM_TRI BIT(19) ++#define RR_TM_VAL GENMASK(6, 1) ++#define RR_TM2 0x43 ++#define RR_TM2_OFF GENMASK(19, 16) ++#define RR_TXG1 0x51 ++#define RR_TXG1_ATT2 BIT(19) ++#define RR_TXG1_ATT1 BIT(11) ++#define RR_TXG2 0x52 ++#define RR_TXG2_ATT0 BIT(11) ++#define RR_BSPAD 0x54 ++#define RR_TXGA 0x55 ++#define RR_TXGA_LOK_EN BIT(0) ++#define RR_TXGA_TRK_EN BIT(7) ++#define RR_GAINTX 0x56 ++#define RR_GAINTX_ALL GENMASK(15, 0) ++#define RR_GAINTX_PAD GENMASK(9, 5) ++#define RR_GAINTX_BB GENMASK(4, 0) ++#define RR_TXMO 0x58 ++#define RR_TXMO_COI GENMASK(19, 15) ++#define RR_TXMO_COQ GENMASK(14, 10) ++#define RR_TXMO_FII GENMASK(9, 6) ++#define RR_TXMO_FIQ GENMASK(5, 2) ++#define RR_TXA 0x5d ++#define RR_TXA_TRK GENMASK(19, 14) ++#define RR_TXRSV 0x5c ++#define RR_TXRSV_GAPK BIT(19) ++#define RR_BIAS 0x5e ++#define RR_BIAS_GAPK BIT(19) ++#define RR_BIASA 0x60 ++#define RR_BIASA_TXG GENMASK(15, 12) ++#define RR_BIASA_TXA GENMASK(19, 16) ++#define RR_BIASA_A GENMASK(2, 0) ++#define RR_BIASA2 0x63 ++#define RR_BIASA2_LB GENMASK(4, 2) ++#define RR_TXATANK 0x64 ++#define RR_TXATANK_LBSW GENMASK(16, 15) ++#define RR_TRXIQ 0x66 ++#define RR_RSV6 0x6d ++#define RR_TXPOW 0x7f ++#define RR_TXPOW_TXG BIT(1) ++#define RR_TXPOW_TXA BIT(8) ++#define RR_RXPOW 0x80 ++#define RR_RXPOW_IQK GENMASK(17, 16) ++#define RR_RXBB 0x83 ++#define RR_RXBB_C2G GENMASK(16, 10) ++#define RR_RXBB_C1G GENMASK(9, 8) ++#define RR_RXBB_ATTR GENMASK(7, 4) ++#define RR_RXBB_ATTC GENMASK(2, 0) ++#define RR_XGLNA2 0x85 ++#define RR_XGLNA2_SW GENMASK(1, 0) ++#define RR_RXA 0x8a ++#define RR_RXA_DPK GENMASK(9, 8) ++#define RR_RXA2 0x8c ++#define RR_RXA2_C2 GENMASK(9, 3) ++#define RR_RXA2_C1 GENMASK(12, 10) ++#define RR_RXIQGEN 0x8d ++#define RR_RXIQGEN_ATTL GENMASK(12, 8) ++#define RR_RXIQGEN_ATTH GENMASK(14, 13) ++#define RR_RXBB2 0x8f ++#define RR_EN_TIA_IDA GENMASK(11, 10) ++#define RR_RXBB2_DAC_EN BIT(13) ++#define RR_XALNA2 0x90 ++#define RR_XALNA2_SW GENMASK(1, 0) ++#define RR_DCK 0x92 ++#define RR_DCK_FINE BIT(1) ++#define RR_DCK_LV BIT(0) ++#define RR_DCK1 0x93 ++#define RR_DCK1_SEL BIT(3) ++#define RR_DCK2 0x94 ++#define RR_DCK2_CYCLE GENMASK(7, 2) ++#define RR_MIXER 0x9f ++#define RR_MIXER_GN GENMASK(4, 3) ++#define RR_XTALX2 0xb8 ++#define RR_MALSEL 0xbe ++#define RR_RCKD 0xde ++#define RR_RCKD_POW GENMASK(19, 13) ++#define RR_RCKD_BW BIT(2) ++#define RR_TXADBG 0xde ++#define RR_LUTDBG 0xdf ++#define RR_LUTDBG_LOK BIT(2) ++#define RR_LUTWE2 0xee ++#define RR_LUTWE 0xef ++#define RR_LUTWE_LOK BIT(2) ++#define RR_RFC 0xf0 ++#define RR_RFC_CKEN BIT(1) ++ ++#define R_UPD_P0 0x0000 ++#define R_RSTB_WATCH_DOG 0x000C ++#define B_P0_RSTB_WATCH_DOG BIT(0) ++#define B_P1_RSTB_WATCH_DOG BIT(1) ++#define B_UPD_P0_EN BIT(30) ++#define R_ANAPAR_PW15 0x030C ++#define B_ANAPAR_PW15 GENMASK(31, 24) ++#define B_ANAPAR_PW15_H GENMASK(27, 24) ++#define B_ANAPAR_PW15_H2 GENMASK(27, 26) ++#define R_ANAPAR 0x032C ++#define B_ANAPAR_15 GENMASK(31, 16) ++#define B_ANAPAR_ADCCLK BIT(30) ++#define B_ANAPAR_FLTRST BIT(22) ++#define B_ANAPAR_CRXBB GENMASK(18, 16) ++#define B_ANAPAR_14 GENMASK(15, 0) ++#define R_UPD_CLK_ADC 0x0700 ++#define B_UPD_CLK_ADC_ON BIT(24) ++#define B_UPD_CLK_ADC_VAL GENMASK(26, 25) ++#define R_RSTB_ASYNC 0x0704 ++#define B_RSTB_ASYNC_ALL BIT(1) ++#define R_PMAC_GNT 0x0980 ++#define B_PMAC_GNT_TXEN BIT(0) ++#define B_PMAC_GNT_RXEN BIT(16) ++#define B_PMAC_GNT_P1 GENMASK(20, 17) ++#define B_PMAC_GNT_P2 GENMASK(29, 26) ++#define R_PMAC_RX_CFG1 0x0988 ++#define B_PMAC_OPT1_MSK GENMASK(11, 0) ++#define R_PMAC_RXMOD 0x0994 ++#define B_PMAC_RXMOD_MSK GENMASK(7, 4) ++#define R_MAC_SEL 0x09A4 ++#define B_MAC_SEL_MOD GENMASK(4, 2) ++#define B_MAC_SEL_DPD_EN BIT(10) ++#define B_MAC_SEL_PWR_EN BIT(16) ++#define R_PMAC_TX_CTRL 0x09C0 ++#define B_PMAC_TXEN_DIS BIT(0) ++#define R_PMAC_TX_PRD 0x09C4 ++#define B_PMAC_TX_PRD_MSK GENMASK(31, 8) ++#define B_PMAC_CTX_EN BIT(0) ++#define B_PMAC_PTX_EN BIT(4) ++#define R_PMAC_TX_CNT 0x09C8 ++#define B_PMAC_TX_CNT_MSK GENMASK(31, 0) ++#define R_CCX 0x0C00 ++#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) ++#define B_MEASUREMENT_TRIG_MSK BIT(2) ++#define B_CCX_TRIG_OPT_MSK BIT(1) ++#define B_CCX_EN_MSK BIT(0) ++#define R_IFS_COUNTER 0x0C28 ++#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) ++#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) ++#define B_IFS_COUNTER_CLR_MSK BIT(13) ++#define B_IFS_COLLECT_EN BIT(12) ++#define R_IFS_T1 0x0C2C ++#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T1_EN_MSK BIT(15) ++#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T2 0x0C30 ++#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T2_EN_MSK BIT(15) ++#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T3 0x0C34 ++#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T3_EN_MSK BIT(15) ++#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T4 0x0C38 ++#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T4_EN_MSK BIT(15) ++#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) ++#define R_PD_CTRL 0x0C3C ++#define B_PD_HIT_DIS BIT(9) ++#define R_IOQ_IQK_DPK 0x0C60 ++#define B_IOQ_IQK_DPK_EN BIT(1) ++#define R_P0_EN_SOUND_WO_NDP 0x0D7C ++#define B_P0_EN_SOUND_WO_NDP BIT(1) ++#define R_SPOOF_ASYNC_RST 0x0D84 ++#define B_SPOOF_ASYNC_RST BIT(15) ++#define R_NDP_BRK0 0xDA0 ++#define R_NDP_BRK1 0xDA4 ++#define B_NDP_RU_BRK BIT(0) ++#define R_BRK_ASYNC_RST_EN_1 0x0DC0 ++#define R_BRK_ASYNC_RST_EN_2 0x0DC4 ++#define R_BRK_ASYNC_RST_EN_3 0x0DC8 ++#define R_P0_RXCK 0x12A0 ++#define B_P0_RXCK_VAL GENMASK(18, 16) ++#define B_P0_RXCK_ON BIT(19) ++#define B_P0_RXCK_BW3 BIT(30) ++#define R_P0_NRBW 0x12B8 ++#define B_P0_NRBW_DBG BIT(30) ++#define R_S0_RXDC 0x12D4 ++#define B_S0_RXDC_I GENMASK(25, 16) ++#define B_S0_RXDC_Q GENMASK(31, 26) ++#define R_S0_RXDC2 0x12D8 ++#define B_S0_RXDC2_SEL GENMASK(9, 8) ++#define B_S0_RXDC2_AVG GENMASK(7, 6) ++#define B_S0_RXDC2_MEN GENMASK(5, 4) ++#define B_S0_RXDC2_Q2 GENMASK(3, 0) ++#define R_CFO_COMP_SEG0_L 0x1384 ++#define R_CFO_COMP_SEG0_H 0x1388 ++#define R_CFO_COMP_SEG0_CTRL 0x138C ++#define R_DBG32_D 0x1730 ++#define R_TX_COUNTER 0x1A40 ++#define R_IFS_CLM_TX_CNT 0x1ACC ++#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) ++#define R_IFS_CLM_CCA 0x1AD0 ++#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) ++#define R_IFS_CLM_FA 0x1AD4 ++#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) ++#define R_IFS_HIS 0x1AD8 ++#define B_IFS_T4_HIS_MSK GENMASK(31, 24) ++#define B_IFS_T3_HIS_MSK GENMASK(23, 16) ++#define B_IFS_T2_HIS_MSK GENMASK(15, 8) ++#define B_IFS_T1_HIS_MSK GENMASK(7, 0) ++#define R_IFS_AVG_L 0x1ADC ++#define B_IFS_T2_AVG_MSK GENMASK(31, 16) ++#define B_IFS_T1_AVG_MSK GENMASK(15, 0) ++#define R_IFS_AVG_H 0x1AE0 ++#define B_IFS_T4_AVG_MSK GENMASK(31, 16) ++#define B_IFS_T3_AVG_MSK GENMASK(15, 0) ++#define R_IFS_CCA_L 0x1AE4 ++#define B_IFS_T2_CCA_MSK GENMASK(31, 16) ++#define B_IFS_T1_CCA_MSK GENMASK(15, 0) ++#define R_IFS_CCA_H 0x1AE8 ++#define B_IFS_T4_CCA_MSK GENMASK(31, 16) ++#define B_IFS_T3_CCA_MSK GENMASK(15, 0) ++#define R_IFSCNT 0x1AEC ++#define B_IFSCNT_DONE_MSK BIT(16) ++#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) ++#define R_TXAGC_TP 0x1C04 ++#define B_TXAGC_TP GENMASK(2, 0) ++#define R_TSSI_THER 0x1C10 ++#define B_TSSI_THER GENMASK(29, 24) ++#define R_TXAGC_BB 0x1C60 ++#define R_S0_ADDCK 0x1E00 ++#define B_S0_ADDCK_I GENMASK(9, 0) ++#define B_S0_ADDCK_Q GENMASK(19, 10) ++#define R_ADC_FIFO 0x20fc ++#define B_ADC_FIFO_RST GENMASK(31, 24) ++#define R_TXFIR0 0x2300 ++#define B_TXFIR_C01 GENMASK(23, 0) ++#define R_TXFIR2 0x2304 ++#define B_TXFIR_C23 GENMASK(23, 0) ++#define R_TXFIR4 0x2308 ++#define B_TXFIR_C45 GENMASK(23, 0) ++#define R_TXFIR6 0x230c ++#define B_TXFIR_C67 GENMASK(23, 0) ++#define R_TXFIR8 0x2310 ++#define B_TXFIR_C89 GENMASK(23, 0) ++#define R_TXFIRA 0x2314 ++#define B_TXFIR_CAB GENMASK(23, 0) ++#define R_TXFIRC 0x2318 ++#define B_TXFIR_CCD GENMASK(23, 0) ++#define R_TXFIRE 0x231c ++#define B_TXFIR_CEF GENMASK(23, 0) ++#define R_RXCCA 0x2344 ++#define B_RXCCA_DIS BIT(31) ++#define R_RXSC 0x237C ++#define B_RXSC_EN BIT(0) ++#define R_RXSCOBC 0x23B0 ++#define B_RXSCOBC_TH GENMASK(18, 0) ++#define R_RXSCOCCK 0x23B4 ++#define B_RXSCOCCK_TH GENMASK(18, 0) ++#define R_P1_EN_SOUND_WO_NDP 0x2D7C ++#define B_P1_EN_SOUND_WO_NDP BIT(1) ++#define R_P1_DBGMOD 0x32B8 ++#define B_P1_DBGMOD_ON BIT(30) ++#define R_S1_RXDC 0x32D4 ++#define B_S1_RXDC_I GENMASK(25, 16) ++#define B_S1_RXDC_Q GENMASK(31, 26) ++#define R_S1_RXDC2 0x32D8 ++#define B_S1_RXDC2_EN GENMASK(5, 4) ++#define B_S1_RXDC2_SEL GENMASK(9, 8) ++#define B_S1_RXDC2_Q2 GENMASK(3, 0) ++#define R_TXAGC_BB_S1 0x3C60 ++#define R_S1_ADDCK 0x3E00 ++#define B_S1_ADDCK_I GENMASK(9, 0) ++#define B_S1_ADDCK_Q GENMASK(19, 10) ++#define R_DCFO 0x4264 ++#define B_DCFO GENMASK(1, 0) ++#define R_SEG0CSI 0x42AC ++#define B_SEG0CSI_IDX GENMASK(10, 0) ++#define R_SEG0CSI_EN 0x42C4 ++#define B_SEG0CSI_EN BIT(23) ++#define R_BSS_CLR_MAP 0x43ac ++#define B_BSS_CLR_MAP_VLD0 BIT(28) ++#define B_BSS_CLR_MAP_TGT GENMASK(27, 22) ++#define B_BSS_CLR_MAP_STAID GENMASK(21, 11) ++#define R_CFO_TRK0 0x4404 ++#define R_CFO_TRK1 0x440C ++#define B_CFO_TRK_MSK GENMASK(14, 10) ++#define R_DCFO_COMP_S0 0x448C ++#define B_DCFO_COMP_S0_MSK GENMASK(11, 0) ++#define R_DCFO_WEIGHT 0x4490 ++#define B_DCFO_WEIGHT_MSK GENMASK(27, 24) ++#define R_DCFO_OPT 0x4494 ++#define B_DCFO_OPT_EN BIT(29) ++#define R_BANDEDGE 0x4498 ++#define B_BANDEDGE_EN BIT(30) ++#define R_TXPATH_SEL 0x458C ++#define B_TXPATH_SEL_MSK GENMASK(31, 28) ++#define R_TXPWR 0x4594 ++#define B_TXPWR_MSK GENMASK(30, 22) ++#define R_TXNSS_MAP 0x45B4 ++#define B_TXNSS_MAP_MSK GENMASK(20, 17) ++#define R_PATH0_IB_PKPW 0x4628 ++#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR1 0x462C ++#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR2 0x4630 ++#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18) ++#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0) ++#define R_PATH0_LNA_ERR3 0x4634 ++#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18) ++#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6) ++#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0) ++#define R_PATH0_LNA_ERR4 0x4638 ++#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR5 0x463C ++#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0) ++#define R_PATH0_TIA_ERR_G0 0x4640 ++#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18) ++#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12) ++#define R_PATH0_TIA_ERR_G1 0x4644 ++#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30) ++#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6) ++#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0) ++#define R_PATH0_IB_PBK 0x4650 ++#define B_PATH0_IB_PBK_MSK GENMASK(14, 10) ++#define R_PATH0_RXB_INIT 0x4658 ++#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5) ++#define R_PATH0_LNA_INIT 0x4668 ++#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24) ++#define R_PATH0_BTG 0x466C ++#define B_PATH0_BTG_SHEN GENMASK(18, 17) ++#define R_PATH0_TIA_INIT 0x4674 ++#define B_PATH0_TIA_INIT_IDX_MSK BIT(17) ++#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0 ++#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4 ++#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_P0_NBIIDX 0x469C ++#define B_P0_NBIIDX_VAL GENMASK(11, 0) ++#define B_P0_NBIIDX_NOTCH_EN BIT(12) ++#define R_P1_MODE 0x4718 ++#define B_P1_MODE_SEL GENMASK(31, 30) ++#define R_PATH1_LNA_INIT 0x473C ++#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24) ++#define R_PATH1_TIA_INIT 0x4748 ++#define B_PATH1_TIA_INIT_IDX_MSK BIT(17) ++#define R_PATH1_BTG 0x4740 ++#define B_PATH1_BTG_SHEN GENMASK(18, 17) ++#define R_PATH1_RXB_INIT 0x472C ++#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5) ++#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774 ++#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778 ++#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_P1_NBIIDX 0x4770 ++#define B_P1_NBIIDX_VAL GENMASK(11, 0) ++#define B_P1_NBIIDX_NOTCH_EN BIT(12) ++#define R_SEG0R_PD 0x481C ++#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29) ++#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6) ++#define R_2P4G_BAND 0x4970 ++#define B_2P4G_BAND_SEL BIT(1) ++#define R_FC0_BW 0x4974 ++#define B_FC0_BW_INV GENMASK(6, 0) ++#define B_FC0_BW_SET GENMASK(31, 30) ++#define R_CHBW_MOD 0x4978 ++#define B_CHBW_MOD_PRICH GENMASK(11, 8) ++#define B_CHBW_MOD_SBW GENMASK(13, 12) ++#define R_CFO_COMP_SEG1_L 0x5384 ++#define R_CFO_COMP_SEG1_H 0x5388 ++#define R_CFO_COMP_SEG1_CTRL 0x538C ++#define B_CFO_COMP_VALID_BIT BIT(29) ++#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) ++#define B_CFO_COMP_VAL_MSK GENMASK(11, 0) ++#define R_DPD_OFT_EN 0x5800 ++#define B_DPD_OFT_EN BIT(28) ++#define R_DPD_OFT_ADDR 0x5804 ++#define B_DPD_OFT_ADDR GENMASK(31, 27) ++#define R_P0_TMETER 0x5810 ++#define B_P0_TMETER GENMASK(15, 10) ++#define B_P0_TMETER_DIS BIT(16) ++#define B_P0_TMETER_TRK BIT(24) ++#define R_P0_TSSI_TRK 0x5818 ++#define B_P0_TSSI_TRK_EN BIT(30) ++#define R_P0_RFCTM 0x5864 ++#define B_P0_RFCTM_VAL GENMASK(25, 20) ++#define R_P0_RFCTM_RDY BIT(26) ++#define R_P0_TXDPD 0x58D4 ++#define B_P0_TXDPD GENMASK(31, 28) ++#define R_P0_TXPW_RSTB 0x58DC ++#define B_P0_TXPW_RSTB_MANON BIT(30) ++#define B_P0_TXPW_RSTB_TSSI BIT(31) ++#define R_TXGAIN_SCALE 0x58F0 ++#define B_TXGAIN_SCALE_EN BIT(19) ++#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) ++#define R_P0_TSSI_BASE 0x5C00 ++#define R_S0_DACKI 0x5E00 ++#define B_S0_DACKI_AR GENMASK(31, 28) ++#define B_S0_DACKI_EN BIT(3) ++#define R_S0_DACKI2 0x5E30 ++#define B_S0_DACKI2_K GENMASK(21, 12) ++#define R_S0_DACKI7 0x5E44 ++#define B_S0_DACKI7_K GENMASK(15, 8) ++#define R_S0_DACKI8 0x5E48 ++#define B_S0_DACKI8_K GENMASK(15, 8) ++#define R_S0_DACKQ 0x5E50 ++#define B_S0_DACKQ_AR GENMASK(31, 28) ++#define B_S0_DACKQ_EN BIT(3) ++#define R_S0_DACKQ2 0x5E80 ++#define B_S0_DACKQ2_K GENMASK(21, 12) ++#define R_S0_DACKQ7 0x5E94 ++#define B_S0_DACKQ7_K GENMASK(15, 8) ++#define R_S0_DACKQ8 0x5E98 ++#define B_S0_DACKQ8_K GENMASK(15, 8) ++#define R_P1_TMETER 0x7810 ++#define B_P1_TMETER GENMASK(15, 10) ++#define B_P1_TMETER_DIS BIT(16) ++#define B_P1_TMETER_TRK BIT(24) ++#define R_P1_TSSI_TRK 0x7818 ++#define B_P1_TSSI_TRK_EN BIT(30) ++#define R_P1_RFCTM 0x7864 ++#define R_P1_RFCTM_RDY BIT(26) ++#define B_P1_RFCTM_VAL GENMASK(25, 20) ++#define R_P1_TXPW_RSTB 0x78DC ++#define B_P1_TXPW_RSTB_MANON BIT(30) ++#define B_P1_TXPW_RSTB_TSSI BIT(31) ++#define R_TSSI_THOF 0x7C00 ++#define R_S1_DACKI 0x7E00 ++#define B_S1_DACKI_AR GENMASK(31, 28) ++#define B_S1_DACKI_EN BIT(3) ++#define R_S1_DACKI2 0x7E30 ++#define B_S1_DACKI2_K GENMASK(21, 12) ++#define R_S1_DACKI7 0x7E44 ++#define B_S1_DACKI_K GENMASK(15, 8) ++#define R_S1_DACKI8 0x7E48 ++#define B_S1_DACKI8_K GENMASK(15, 8) ++#define R_S1_DACKQ 0x7E50 ++#define B_S1_DACKQ_AR GENMASK(31, 28) ++#define B_S1_DACKQ_EN BIT(3) ++#define R_S1_DACKQ2 0x7E80 ++#define B_S1_DACKQ2_K GENMASK(21, 12) ++#define R_S1_DACKQ7 0x7E94 ++#define B_S1_DACKQ7_K GENMASK(15, 8) ++#define R_S1_DACKQ8 0x7E98 ++#define B_S1_DACKQ8_K GENMASK(15, 8) ++#define R_NCTL_CFG 0x8000 ++#define B_NCTL_CFG_SPAGE GENMASK(2, 1) ++#define R_NCTL_RPT 0x8008 ++#define B_NCTL_RPT_FLG BIT(26) ++#define R_NCTL_N1 0x8010 ++#define B_NCTL_N1_CIP GENMASK(7, 0) ++#define R_NCTL_N2 0x8014 ++#define R_IQK_COM 0x8018 ++#define R_IQK_DIF 0x801C ++#define B_IQK_DIF_TRX GENMASK(1, 0) ++#define R_IQK_DIF1 0x8020 ++#define B_IQK_DIF1_TXPI GENMASK(19, 0) ++#define R_IQK_DIF2 0x8024 ++#define B_IQK_DIF2_RXPI GENMASK(19, 0) ++#define R_IQK_DIF4 0x802C ++#define B_IQK_DIF4_TXT GENMASK(11, 0) ++#define B_IQK_DIF4_RXT GENMASK(27, 16) ++#define R_IQK_CFG 0x8034 ++#define B_IQK_CFG_SET GENMASK(5, 4) ++#define R_TPG_MOD 0x806C ++#define B_TPG_MOD_F GENMASK(2, 1) ++#define R_MDPK_SYNC 0x8070 ++#define B_MDPK_SYNC_SEL BIT(31) ++#define B_MDPK_SYNC_MAN GENMASK(31, 28) ++#define R_MDPK_RX_DCK 0x8074 ++#define R_NCTL_RW 0x8080 ++#define R_KIP_SYSCFG 0x8088 ++#define R_KIP_CLK 0x808C ++#define R_LDL_NORM 0x80A0 ++#define B_LDL_NORM_PN GENMASK(12, 8) ++#define B_LDL_NORM_OP GENMASK(1, 0) ++#define R_DPK_CTL 0x80B0 ++#define B_DPK_CTL_EN BIT(28) ++#define R_DPK_CFG 0x80B8 ++#define B_DPK_CFG_IDX GENMASK(14, 12) ++#define R_DPK_CFG2 0x80BC ++#define B_DPK_CFG2_ST BIT(14) ++#define R_DPK_CFG3 0x80C0 ++#define R_KPATH_CFG 0x80D0 ++#define R_KIP_RPT1 0x80D4 ++#define B_KIP_RPT1_SEL GENMASK(21, 16) ++#define R_SRAM_IQRX 0x80D8 ++#define R_GAPK 0x80E0 ++#define B_GAPK_ADR BIT(0) ++#define R_SRAM_IQRX2 0x80E8 ++#define R_DPK_TRK 0x80f0 ++#define B_DPK_TRK_DIS BIT(31) ++#define R_RPT_COM 0x80FC ++#define B_PRT_COM_SYNERR BIT(30) ++#define B_PRT_COM_DCI GENMASK(27, 16) ++#define B_PRT_COM_CORV GENMASK(15, 8) ++#define B_PRT_COM_DCQ GENMASK(11, 0) ++#define B_PRT_COM_GL GENMASK(7, 4) ++#define B_PRT_COM_CORI GENMASK(7, 0) ++#define R_COEF_SEL 0x8104 ++#define B_COEF_SEL_IQC BIT(0) ++#define B_COEF_SEL_MDPD BIT(8) ++#define R_CFIR_SYS 0x8120 ++#define R_IQK_RES 0x8124 ++#define B_IQK_RES_TXCFIR GENMASK(11, 8) ++#define B_IQK_RES_RXCFIR GENMASK(3, 0) ++#define R_TXIQC 0x8138 ++#define R_RXIQC 0x813c ++#define B_RXIQC_BYPASS BIT(0) ++#define B_RXIQC_BYPASS2 BIT(2) ++#define B_RXIQC_NEWP GENMASK(19, 8) ++#define B_RXIQC_NEWX GENMASK(31, 20) ++#define R_KIP 0x8140 ++#define B_KIP_DBCC BIT(0) ++#define B_KIP_RFGAIN BIT(8) ++#define R_RFGAIN 0x8144 ++#define B_RFGAIN_PAD GENMASK(4, 0) ++#define B_RFGAIN_TXBB GENMASK(12, 8) ++#define R_RFGAIN_BND 0x8148 ++#define B_RFGAIN_BND GENMASK(4, 0) ++#define R_CFIR_MAP 0x8150 ++#define R_CFIR_LUT 0x8154 ++#define B_CFIR_LUT_SEL BIT(8) ++#define B_CFIR_LUT_G3 BIT(3) ++#define B_CFIR_LUT_G2 BIT(2) ++#define B_CFIR_LUT_GP GENMASK(1, 0) ++#define R_DPD_V1 0x81a0 ++#define R_DPD_CH0 0x81AC ++#define R_DPD_BND 0x81B4 ++#define R_DPD_CH0A 0x81BC ++#define R_TXAGC_RFK 0x81C4 ++#define B_TXAGC_RFK_CH0 GENMASK(5, 0) ++#define R_DPD_COM 0x81C8 ++#define R_KIP_IQP 0x81CC ++#define B_KIP_IQP_IQSW GENMASK(5, 0) ++#define R_KIP_RPT 0x81D4 ++#define B_KIP_RPT_SEL GENMASK(21, 16) ++#define R_W_COEF 0x81D8 ++#define R_LOAD_COEF 0x81DC ++#define B_LOAD_COEF_MDPD BIT(16) ++#define B_LOAD_COEF_CFIR GENMASK(1, 0) ++#define B_LOAD_COEF_AUTO BIT(0) ++#define R_RPT_PER 0x81FC ++#define R_RXCFIR_P0C0 0x8D40 ++#define R_RXCFIR_P0C1 0x8D84 ++#define R_RXCFIR_P0C2 0x8DC8 ++#define R_RXCFIR_P0C3 0x8E0C ++#define R_TXCFIR_P0C0 0x8F50 ++#define R_TXCFIR_P0C1 0x8F84 ++#define R_TXCFIR_P0C2 0x8FB8 ++#define R_TXCFIR_P0C3 0x8FEC ++#define R_RXCFIR_P1C0 0x9140 ++#define R_RXCFIR_P1C1 0x9184 ++#define R_RXCFIR_P1C2 0x91C8 ++#define R_RXCFIR_P1C3 0x920C ++#define R_TXCFIR_P1C0 0x9350 ++#define R_TXCFIR_P1C1 0x9384 ++#define R_TXCFIR_P1C2 0x93B8 ++#define R_TXCFIR_P1C3 0x93EC ++#define R_IQKINF 0x9FE0 ++#define B_IQKINF_VER GENMASK(31, 24) ++#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16) ++#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8) ++#define B_IQKINF_FAIL GENMASK(3, 0) ++#define B_IQKINF_F_RX BIT(3) ++#define B_IQKINF_FTX BIT(2) ++#define B_IQKINF_FFIN BIT(1) ++#define B_IQKINF_FCOR BIT(0) ++#define R_IQKCH 0x9FE4 ++#define B_IQKCH_CH GENMASK(15, 8) ++#define B_IQKCH_BW GENMASK(7, 4) ++#define B_IQKCH_BAND GENMASK(3, 0) ++#define R_IQKINF2 0x9FE8 ++#define B_IQKINF2_FCNT GENMASK(23, 16) ++#define B_IQKINF2_KCNT GENMASK(15, 8) ++#define B_IQKINF2_NCTLV GENMAKS(7, 0) ++#endif + +From patchwork Fri Aug 20 04:35:26 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448381 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, + USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 5A521C4320A + for ; + Fri, 20 Aug 2021 04:37:21 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 3C83460F91 + for ; + Fri, 20 Aug 2021 04:37:21 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233245AbhHTEh5 (ORCPT + ); + Fri, 20 Aug 2021 00:37:57 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39256 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233148AbhHTEhw (ORCPT + ); + Fri, 20 Aug 2021 00:37:52 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bBXP1004033, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bBXP1004033 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:11 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:11 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:10 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 12/24] rtw89: add regulatory support +Date: Fri, 20 Aug 2021 12:35:26 +0800 +Message-ID: <20210820043538.12424-13-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Interact with regulatory hints by below rules: +For a non-PGed chip, I assume that it is world-roaming, so accepts every +notifications except the following condition. +For a non-PGed chip and the current domain is set by userspace, the +country ie notification will be disabled. The reason is that the current +setting might come from the system of a distro, and I assume that they +do not expect the domain will be changed by connecting to an AP. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/regd.c | 353 ++++++++++++++++++++++ + 1 file changed, 353 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/regd.c + +diff --git a/drivers/net/wireless/realtek/rtw89/regd.c b/drivers/net/wireless/realtek/rtw89/regd.c +new file mode 100644 +index 000000000000..f00b94ecfff4 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/regd.c +@@ -0,0 +1,353 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "ps.h" ++ ++#define COUNTRY_REGD(_alpha2, _txpwr_regd_2g, _txpwr_regd_5g) \ ++ {.alpha2 = (_alpha2), \ ++ .txpwr_regd[RTW89_BAND_2G] = (_txpwr_regd_2g), \ ++ .txpwr_regd[RTW89_BAND_5G] = (_txpwr_regd_5g) \ ++ } ++ ++static const struct rtw89_regulatory rtw89_ww_regd = ++ COUNTRY_REGD("00", RTW89_WW, RTW89_WW); ++ ++static const struct rtw89_regulatory rtw89_regd_map[] = { ++ COUNTRY_REGD("AR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BO", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("BR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CL", RTW89_WW, RTW89_CHILE), ++ COUNTRY_REGD("CO", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("EC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SV", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("HN", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("MX", RTW89_FCC, RTW89_MEXICO), ++ COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("UY", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("VE", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("PR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("DO", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ES", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("JO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("OM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("QA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ME", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("UA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("YE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC), ++ COUNTRY_REGD("MY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AU", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("NZ", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("PG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CA", RTW89_IC, RTW89_IC), ++ COUNTRY_REGD("JP", RTW89_MKK, RTW89_MKK), ++ COUNTRY_REGD("JM", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AG", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BB", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BZ", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KY", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CX", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("CC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ER", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ET", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FJ", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GP", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GY", RTW89_FCC, RTW89_NCC), ++ COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("HM", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("VA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("JE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ML", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MH", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("YT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NP", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NU", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("NF", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("MP", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("RE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KN", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("LC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MF", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SX", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("WS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ST", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TK", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("TO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TV", RTW89_ETSI, RTW89_NA), ++ COUNTRY_REGD("UG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VI", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("UZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("WF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IR", RTW89_WW, RTW89_ETSI), ++}; ++ ++static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2) ++{ ++ u32 i; ++ ++ for (i = 0; i < ARRAY_SIZE(rtw89_regd_map); i++) { ++ if (!memcmp(rtw89_regd_map[i].alpha2, alpha2, 2)) ++ return &rtw89_regd_map[i]; ++ } ++ ++ return &rtw89_ww_regd; ++} ++ ++static bool rtw89_regd_is_ww(const struct rtw89_regulatory *regd) ++{ ++ return regd == &rtw89_ww_regd; ++} ++ ++int rtw89_regd_init(struct rtw89_dev *rtwdev, ++ void (*reg_notifier)(struct wiphy *wiphy, ++ struct regulatory_request *request)) ++{ ++ const struct rtw89_regulatory *chip_regd; ++ struct wiphy *wiphy = rtwdev->hw->wiphy; ++ int ret; ++ ++ if (!wiphy) ++ return -EINVAL; ++ ++ chip_regd = rtw89_regd_find_reg_by_name(rtwdev->efuse.country_code); ++ if (!rtw89_regd_is_ww(chip_regd)) { ++ rtwdev->regd = chip_regd; ++ /* Ignore country ie if there is a country domain programmed in chip */ ++ wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE; ++ wiphy->regulatory_flags |= REGULATORY_STRICT_REG; ++ ++ ret = regulatory_hint(rtwdev->hw->wiphy, rtwdev->regd->alpha2); ++ if (ret) ++ rtw89_warn(rtwdev, "failed to hint regulatory:%d\n", ret); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "efuse country code %c%c, mapping to 2g txregd %d, 5g txregd %d\n", ++ rtwdev->efuse.country_code[0], rtwdev->efuse.country_code[1], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ return 0; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "worldwide roaming chip, follow the setting of stack(%c%c), mapping to 2g txregd %d, 5g txregd %d\n", ++ rtwdev->regd->alpha2[0], rtwdev->regd->alpha2[1], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ return 0; ++} ++ ++static void rtw89_regd_notifier_apply(struct rtw89_dev *rtwdev, ++ struct wiphy *wiphy, ++ struct regulatory_request *request) ++{ ++ rtwdev->regd = rtw89_regd_find_reg_by_name(request->alpha2); ++ /* This notification might be set from the system of distros, ++ * and it does not expect the regulatory will be modified by ++ * connecting to an AP (i.e. country ie). ++ */ ++ if (request->initiator == NL80211_REGDOM_SET_BY_USER && ++ !rtw89_regd_is_ww(rtwdev->regd)) ++ wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE; ++ else ++ wiphy->regulatory_flags &= ~REGULATORY_COUNTRY_IE_IGNORE; ++} ++ ++void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request) ++{ ++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if (wiphy->regd) { ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "There is a country domain programmed in chip, ignore notifications\n"); ++ goto exit; ++ } ++ rtw89_regd_notifier_apply(rtwdev, wiphy, request); ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "get alpha2 %c%c from initiator %d, mapping to 2g txregd %d, 5g txregd %d\n", ++ request->alpha2[0], request->alpha2[1], request->initiator, ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ rtw89_chip_set_txpwr(rtwdev); ++ ++exit: ++ mutex_unlock(&rtwdev->mutex); ++} + +From patchwork Fri Aug 20 04:35:27 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448385 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 6C462C432BE + for ; + Fri, 20 Aug 2021 04:37:24 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 4540960EB5 + for ; + Fri, 20 Aug 2021 04:37:24 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233581AbhHTEiA (ORCPT + ); + Fri, 20 Aug 2021 00:38:00 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39260 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S234483AbhHTEh4 (ORCPT + ); + Fri, 20 Aug 2021 00:37:56 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bF1C1004041, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bF1C1004041 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:15 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:14 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:14 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 13/24] rtw89: 8852a: add 8852a specific files +Date: Fri, 20 Aug 2021 12:35:27 +0800 +Message-ID: <20210820043538.12424-14-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_all_Bitcoin, bb} +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +The 8852A specific chip info and ops are written in this file. The chip +info describes the chip specific capabilities, and chip ops are specific +efuse parser, FEM setup, set channel, RFK trigger, set TX power, and +WL/BT grant controlled by coex. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 2030 +++++++++++++++++ + drivers/net/wireless/realtek/rtw89/rtw8852a.h | 109 + + 2 files changed, 2139 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a.h + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +new file mode 100644 +index 000000000000..1533cc80de19 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -0,0 +1,2030 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a.h" ++#include "rtw8852a_rfk.h" ++#include "rtw8852a_table.h" ++#include "txrx.h" ++ ++static struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { ++ {128, 1896, grp_0}, /* ACH 0 */ ++ {128, 1896, grp_0}, /* ACH 1 */ ++ {128, 1896, grp_0}, /* ACH 2 */ ++ {128, 1896, grp_0}, /* ACH 3 */ ++ {128, 1896, grp_1}, /* ACH 4 */ ++ {128, 1896, grp_1}, /* ACH 5 */ ++ {128, 1896, grp_1}, /* ACH 6 */ ++ {128, 1896, grp_1}, /* ACH 7 */ ++ {32, 1896, grp_0}, /* B0MGQ */ ++ {128, 1896, grp_0}, /* B0HIQ */ ++ {32, 1896, grp_1}, /* B1MGQ */ ++ {128, 1896, grp_1}, /* B1HIQ */ ++ {40, 0, 0} /* FWCMDQ */ ++}; ++ ++static struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { ++ 1896, /* Group 0 */ ++ 1896, /* Group 1 */ ++ 3792, /* Public Max */ ++ 0 /* WP threshold */ ++}; ++ ++static struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { ++ [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, ++ &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, ++ [RTW89_QTA_DLFW] = {NULL, NULL, &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, ++ [RTW89_QTA_INVALID] = {NULL}, ++}; ++ ++static struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { ++ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &wde_size0, &ple_size0, &wde_qt0, ++ &wde_qt0, &ple_qt4, &ple_qt5}, ++ [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &wde_size4, &ple_size4, ++ &wde_qt4, &wde_qt4, &ple_qt13, &ple_qt13}, ++ [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, ++ NULL}, ++}; ++ ++static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { ++ {0x44AC, 0x00000000}, ++ {0x44B0, 0x00000000}, ++ {0x44B4, 0x00000000}, ++ {0x44B8, 0x00000000}, ++ {0x44BC, 0x00000000}, ++ {0x44C0, 0x00000000}, ++ {0x44C4, 0x00000000}, ++ {0x44C8, 0x00000000}, ++ {0x44CC, 0x00000000}, ++ {0x44D0, 0x00000000}, ++ {0x44D4, 0x00000000}, ++ {0x44D8, 0x00000000}, ++ {0x44DC, 0x00000000}, ++ {0x44E0, 0x00000000}, ++ {0x44E4, 0x00000000}, ++ {0x44E8, 0x00000000}, ++ {0x44EC, 0x00000000}, ++ {0x44F0, 0x00000000}, ++ {0x44F4, 0x00000000}, ++ {0x44F8, 0x00000000}, ++ {0x44FC, 0x00000000}, ++ {0x4500, 0x00000000}, ++ {0x4504, 0x00000000}, ++ {0x4508, 0x00000000}, ++ {0x450C, 0x00000000}, ++ {0x4510, 0x00000000}, ++ {0x4514, 0x00000000}, ++ {0x4518, 0x00000000}, ++ {0x451C, 0x00000000}, ++ {0x4520, 0x00000000}, ++ {0x4524, 0x00000000}, ++ {0x4528, 0x00000000}, ++ {0x452C, 0x00000000}, ++ {0x4530, 0x4E1F3E81}, ++ {0x4534, 0x00000000}, ++ {0x4538, 0x0000005A}, ++ {0x453C, 0x00000000}, ++ {0x4540, 0x00000000}, ++ {0x4544, 0x00000000}, ++ {0x4548, 0x00000000}, ++ {0x454C, 0x00000000}, ++ {0x4550, 0x00000000}, ++ {0x4554, 0x00000000}, ++ {0x4558, 0x00000000}, ++ {0x455C, 0x00000000}, ++ {0x4560, 0x4060001A}, ++ {0x4564, 0x40000000}, ++ {0x4568, 0x00000000}, ++ {0x456C, 0x00000000}, ++ {0x4570, 0x04000007}, ++ {0x4574, 0x0000DC87}, ++ {0x4578, 0x00000BAB}, ++ {0x457C, 0x03E00000}, ++ {0x4580, 0x00000048}, ++ {0x4584, 0x00000000}, ++ {0x4588, 0x000003E8}, ++ {0x458C, 0x30000000}, ++ {0x4590, 0x00000000}, ++ {0x4594, 0x10000000}, ++ {0x4598, 0x00000001}, ++ {0x459C, 0x00030000}, ++ {0x45A0, 0x01000000}, ++ {0x45A4, 0x03000200}, ++ {0x45A8, 0xC00001C0}, ++ {0x45AC, 0x78018000}, ++ {0x45B0, 0x80000000}, ++ {0x45B4, 0x01C80600}, ++ {0x45B8, 0x00000002}, ++ {0x4594, 0x10000000} ++}; ++ ++static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { ++ {0x4624, GENMASK(20, 14), 0x40}, ++ {0x46f8, GENMASK(20, 14), 0x40}, ++ {0x4674, GENMASK(20, 19), 0x2}, ++ {0x4748, GENMASK(20, 19), 0x2}, ++ {0x4650, GENMASK(14, 10), 0x18}, ++ {0x4724, GENMASK(14, 10), 0x18}, ++ {0x4688, GENMASK(1, 0), 0x3}, ++ {0x475c, GENMASK(1, 0), 0x3}, ++}; ++ ++static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); ++ ++static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { ++ {0x4624, GENMASK(20, 14), 0x1a}, ++ {0x46f8, GENMASK(20, 14), 0x1a}, ++ {0x4674, GENMASK(20, 19), 0x1}, ++ {0x4748, GENMASK(20, 19), 0x1}, ++ {0x4650, GENMASK(14, 10), 0x12}, ++ {0x4724, GENMASK(14, 10), 0x12}, ++ {0x4688, GENMASK(1, 0), 0x0}, ++ {0x475c, GENMASK(1, 0), 0x0}, ++}; ++ ++static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); ++ ++static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { ++ {0x00C6, ++ PWR_CV_MSK_B, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), BIT(6)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), BIT(1)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), 0}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), BIT(1)}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(0), 0}, ++ {0x106D, ++ PWR_CV_MSK_B | PWR_CV_MSK_C, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0083, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), 0}, ++ {0x0080, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(5), BIT(5)}, ++ {0x0024, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, ++ {0x02A0, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1), BIT(1)}, ++ {0x02A2, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, ++ {0x0071, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4), 0}, ++ {0x0010, ++ PWR_CV_MSK_A, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), BIT(2)}, ++ {0x02A0, ++ PWR_CV_MSK_A, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, ++ {0xFFFF, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ 0, ++ PWR_CMD_END, 0, 0}, ++}; ++ ++static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { ++ {0x02F0, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, 0xFF, 0}, ++ {0x02F1, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, 0xFF, 0}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0002, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, ++ {0x0082, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, ++ {0x106D, ++ PWR_CV_MSK_B | PWR_CV_MSK_C, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), BIT(6)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1), BIT(1)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), 0}, ++ {0x0091, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), BIT(2)}, ++ {0x0007, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4), 0}, ++ {0x0007, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, ++ {0x0005, ++ PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | ++ PWR_CV_MSK_G, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), 0}, ++ {0xFFFF, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ 0, ++ PWR_CMD_END, 0, 0}, ++}; ++ ++static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { ++ rtw8852a_pwron, NULL ++}; ++ ++static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { ++ rtw8852a_pwroff, NULL ++}; ++ ++static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, ++ struct rtw8852a_efuse *map) ++{ ++ ether_addr_copy(efuse->addr, map->e.mac_addr); ++ efuse->rfe_type = map->rfe_type; ++ efuse->xtal_cap = map->xtal_k; ++} ++ ++static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, ++ struct rtw8852a_efuse *map) ++{ ++ struct rtw89_tssi_info *tssi = &rtwdev->tssi; ++ struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; ++ u8 i, j; ++ ++ tssi->thermal[RF_PATH_A] = map->path_a_therm; ++ tssi->thermal[RF_PATH_B] = map->path_b_therm; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, ++ sizeof(ofst[i]->cck_tssi)); ++ ++ for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", ++ i, j, tssi->tssi_cck[i][j]); ++ ++ memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, ++ sizeof(ofst[i]->bw40_tssi)); ++ memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, ++ ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); ++ ++ for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", ++ i, j, tssi->tssi_mcs[i][j]); ++ } ++} ++ ++static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) ++{ ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ struct rtw8852a_efuse *map; ++ ++ map = (struct rtw8852a_efuse *)log_map; ++ ++ efuse->country_code[0] = map->country_code[0]; ++ efuse->country_code[1] = map->country_code[1]; ++ rtw8852a_efuse_parsing_tssi(rtwdev, map); ++ ++ switch (rtwdev->hci.type) { ++ case RTW89_HCI_TYPE_PCIE: ++ rtw8852ae_efuse_parsing(efuse, map); ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); ++ ++ return 0; ++} ++ ++static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) ++{ ++ struct rtw89_tssi_info *tssi = &rtwdev->tssi; ++ static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ bool pg = false; ++ u32 ofst; ++ u8 i, j; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { ++ /* addrs are in decreasing order */ ++ ofst = tssi_trim_addr[i] - addr - j; ++ tssi->tssi_trim[i][j] = phycap_map[ofst]; ++ ++ if (phycap_map[ofst] != 0xff) ++ pg = true; ++ } ++ } ++ ++ if (!pg) { ++ memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM] no PG, set all trim info to 0\n"); ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", ++ i, j, tssi->tssi_trim[i][j], ++ tssi_trim_addr[i] - j); ++} ++ ++static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, ++ u8 *phycap_map) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", ++ i, info->thermal_trim[i]); ++ ++ if (info->thermal_trim[i] != 0xff) ++ info->pg_thermal_trim = true; ++ } ++} ++ ++static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) ++{ ++#define __thm_setting(raw) \ ++({ \ ++ u8 __v = (raw); \ ++ ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ ++}) ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ u8 i, val; ++ ++ if (!info->pg_thermal_trim) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] no PG, do nothing\n"); ++ ++ return; ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ val = __thm_setting(info->thermal_trim[i]); ++ rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", ++ i, val); ++ } ++#undef __thm_setting ++} ++ ++static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, ++ u8 *phycap_map) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", ++ i, info->pa_bias_trim[i]); ++ ++ if (info->pa_bias_trim[i] != 0xff) ++ info->pg_pa_bias_trim = true; ++ } ++} ++ ++static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ u8 pabias_2g, pabias_5g; ++ u8 i; ++ ++ if (!info->pg_pa_bias_trim) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] no PG, do nothing\n"); ++ ++ return; ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); ++ pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", ++ i, pabias_2g, pabias_5g); ++ ++ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); ++ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); ++ } ++} ++ ++static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) ++{ ++ rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); ++ rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); ++ rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); ++ ++ return 0; ++} ++ ++static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_thermal_trim(rtwdev); ++ rtw8852a_pa_bias_trim(rtwdev); ++} ++ ++static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ u8 mac_idx) ++{ ++ u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); ++ u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, ++ mac_idx); ++ u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); ++ u8 txsc20 = 0, txsc40 = 0; ++ ++ switch (param->bandwidth) { ++ case RTW89_CHANNEL_WIDTH_80: ++ txsc40 = rtw89_phy_get_txsc(rtwdev, param, ++ RTW89_CHANNEL_WIDTH_40); ++ fallthrough; ++ case RTW89_CHANNEL_WIDTH_40: ++ txsc20 = rtw89_phy_get_txsc(rtwdev, param, ++ RTW89_CHANNEL_WIDTH_20); ++ break; ++ default: ++ break; ++ } ++ ++ switch (param->bandwidth) { ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); ++ rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); ++ rtw89_write32(rtwdev, sub_carr, txsc20); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); ++ rtw89_write32(rtwdev, sub_carr, 0); ++ break; ++ default: ++ break; ++ } ++ ++ if (param->center_chan > 14) ++ rtw89_write8_set(rtwdev, chk_rate, ++ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); ++ else ++ rtw89_write8_clr(rtwdev, chk_rate, ++ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); ++} ++ ++static const u32 rtw8852a_sco_barker_threshold[14] = { ++ 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, ++ 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 ++}; ++ ++static const u32 rtw8852a_sco_cck_threshold[14] = { ++ 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, ++ 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed ++}; ++ ++static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, ++ u8 primary_ch, enum rtw89_bandwidth bw) ++{ ++ u8 ch_element; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_20) { ++ ch_element = central_ch - 1; ++ } else if (bw == RTW89_CHANNEL_WIDTH_40) { ++ if (primary_ch == 1) ++ ch_element = central_ch - 1 + 2; ++ else ++ ch_element = central_ch - 1 - 2; ++ } else { ++ rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); ++ return -EINVAL; ++ } ++ rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, ++ rtw8852a_sco_barker_threshold[ch_element]); ++ rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, ++ rtw8852a_sco_cck_threshold[ch_element]); ++ ++ return 0; ++} ++ ++static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, ++ u8 path) ++{ ++ u32 val; ++ ++ val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ if (val == INV_RF_DATA) { ++ rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); ++ return; ++ } ++ val &= ~0x303ff; ++ val |= central_ch; ++ if (central_ch > 14) ++ val |= (BIT(16) | BIT(8)); ++ rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); ++} ++ ++static u8 rtw8852a_sco_mapping(u8 central_ch) ++{ ++ if (central_ch == 1) ++ return 109; ++ else if (central_ch >= 2 && central_ch <= 6) ++ return 108; ++ else if (central_ch >= 7 && central_ch <= 10) ++ return 107; ++ else if (central_ch >= 11 && central_ch <= 14) ++ return 106; ++ else if (central_ch == 36 || central_ch == 38) ++ return 51; ++ else if (central_ch >= 40 && central_ch <= 58) ++ return 50; ++ else if (central_ch >= 60 && central_ch <= 64) ++ return 49; ++ else if (central_ch == 100 || central_ch == 102) ++ return 48; ++ else if (central_ch >= 104 && central_ch <= 126) ++ return 47; ++ else if (central_ch >= 128 && central_ch <= 151) ++ return 46; ++ else if (central_ch >= 153 && central_ch <= 177) ++ return 45; ++ else ++ return 0; ++} ++ ++static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u8 sco_comp; ++ bool is_2g = central_ch <= 14; ++ ++ if (phy_idx == RTW89_PHY_0) { ++ /* Path A */ ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, ++ B_PATH0_TIA_ERR_G1_SEL, 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, ++ B_PATH0_TIA_ERR_G1_SEL, 0, ++ phy_idx); ++ ++ /* Path B */ ++ if (!rtwdev->dbcc_en) { ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 0, phy_idx); ++ } else { ++ if (is_2g) ++ rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, ++ B_2P4G_BAND_SEL); ++ else ++ rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, ++ B_2P4G_BAND_SEL); ++ } ++ /* SCO compensate FC setting */ ++ sco_comp = rtw8852a_sco_mapping(central_ch); ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, ++ sco_comp, phy_idx); ++ } else { ++ /* Path B */ ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ /* SCO compensate FC setting */ ++ sco_comp = rtw8852a_sco_mapping(central_ch); ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, ++ sco_comp, phy_idx); ++ } ++ ++ /* Band edge */ ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, ++ phy_idx); ++ ++ /* CCK parameters */ ++ if (central_ch == 14) { ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, ++ 0x3b13ff); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, ++ 0x1c42de); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, ++ 0xfdb0ad); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, ++ 0xf60f6e); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, ++ 0xfd8f92); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, ++ 0xfff00a); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, ++ 0x3d23ff); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, ++ 0x29b354); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, ++ 0xfdb053); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, ++ 0xf86f9a); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, ++ 0xfaef92); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, ++ 0xfe5fcc); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, ++ 0xffdff5); ++ } ++} ++ ++static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) ++{ ++ u32 val = 0; ++ u32 adc_sel[2] = {0x12d0, 0x32d0}; ++ u32 wbadc_sel[2] = {0x12ec, 0x32ec}; ++ ++ val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ if (val == INV_RF_DATA) { ++ rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); ++ return; ++ } ++ val &= ~(BIT(11) | BIT(10)); ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_5: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= BIT(11); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= BIT(10); ++ break; ++ default: ++ rtw89_warn(rtwdev, "Fail to set ADC\n"); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); ++} ++ ++static void ++rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, ++ enum rtw89_phy_idx phy_idx) ++{ ++ /* Switch bandwidth */ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_5: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ pri_ch, ++ phy_idx); ++ if (pri_ch == RTW89_SC_20_UPPER) ++ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ pri_ch, ++ phy_idx); ++ break; ++ default: ++ rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, ++ pri_ch); ++ } ++ ++ if (phy_idx == RTW89_PHY_0) { ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); ++ if (!rtwdev->dbcc_en) ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); ++ } else { ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); ++ } ++} ++ ++static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) ++{ ++ if (central_ch == 153) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else if (central_ch == 151) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else if (central_ch == 155) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x2d0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x2d0); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x0); ++ } ++} ++ ++static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, ++ phy_idx); ++} ++ ++static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, ++ 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, ++ 0, ++ phy_idx); ++} ++ ++static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++} ++ ++static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u32 addr; ++ ++ for (addr = R_AX_PWR_MACID_LMT_TABLE0; ++ addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); ++} ++ ++static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); ++ rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); ++ ++ if (rtwdev->hal.cv <= CHIP_CCV) { ++ rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); ++ rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); ++ rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ } ++ rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); ++ rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); ++ rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); ++ rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); ++ ++ rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ udelay(1); ++} ++ ++static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_phy_idx phy_idx) ++{ ++ bool cck_en = param->center_chan > 14 ? false : true; ++ u8 pri_ch_idx = param->pri_ch_idx; ++ ++ if (param->center_chan <= 14) ++ rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, ++ param->primary_chan, param->bandwidth); ++ ++ rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx); ++ rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); ++ if (cck_en) { ++ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); ++ rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); ++ } ++ rtw8852a_spur_elimination(rtwdev, param->center_chan); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++} ++ ++static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *params) ++{ ++ rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0); ++ rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0); ++} ++ ++static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); ++} ++ ++static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, ++ enum rtw89_rf_path path) ++{ ++ static const u32 tssi_trk[2] = {0x5818, 0x7818}; ++ static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; ++ ++ if (en) { ++ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); ++ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); ++ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); ++ } ++} ++ ++static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, ++ u8 phy_idx) ++{ ++ if (!rtwdev->dbcc_en) { ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); ++ } else { ++ if (phy_idx == RTW89_PHY_0) ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); ++ else ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); ++ } ++} ++ ++static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, ++ 0x0); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, ++ 0xf); ++} ++ ++static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, ++ struct rtw89_channel_help_params *p) ++{ ++ u8 phy_idx = RTW89_PHY_0; ++ ++ if (enter) { ++ rtw89_mac_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); ++ rtw8852a_dfs_en(rtwdev, false); ++ rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); ++ rtw8852a_adc_en(rtwdev, false); ++ fsleep(40); ++ rtw8852a_bb_reset_en(rtwdev, phy_idx, false); ++ } else { ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); ++ rtw8852a_adc_en(rtwdev, true); ++ rtw8852a_dfs_en(rtwdev, true); ++ rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); ++ rtw8852a_bb_reset_en(rtwdev, phy_idx, true); ++ rtw89_mac_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); ++ } ++} ++ ++static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ ++ switch (efuse->rfe_type) { ++ case 11: ++ case 12: ++ case 17: ++ case 18: ++ case 51: ++ case 53: ++ rtwdev->fem.epa_2g = true; ++ rtwdev->fem.elna_2g = true; ++ fallthrough; ++ case 9: ++ case 10: ++ case 15: ++ case 16: ++ rtwdev->fem.epa_5g = true; ++ rtwdev->fem.elna_5g = true; ++ break; ++ default: ++ break; ++ } ++} ++ ++static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->is_tssi_mode[RF_PATH_A] = false; ++ rtwdev->is_tssi_mode[RF_PATH_B] = false; ++ ++ rtw8852a_rck(rtwdev); ++ rtw8852a_dack(rtwdev); ++ rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); ++} ++ ++static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_phy_idx phy_idx = RTW89_PHY_0; ++ ++ rtw8852a_rx_dck(rtwdev, phy_idx, true); ++ rtw8852a_iqk(rtwdev, phy_idx); ++ rtw8852a_tssi(rtwdev, phy_idx); ++ rtw8852a_dpk(rtwdev, phy_idx); ++} ++ ++static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_dpk_track(rtwdev); ++ rtw8852a_iqk_track(rtwdev); ++ rtw8852a_tssi_track(rtwdev); ++} ++ ++static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, s16 ref) ++{ ++ s8 ofst_int = 0; ++ u8 base_cw_0db = 0x27; ++ u16 tssi_16dbm_cw = 0x12c; ++ s16 pwr_s10_3 = 0; ++ s16 rf_pwr_cw = 0; ++ u16 bb_pwr_cw = 0; ++ u32 pwr_cw = 0; ++ u32 tssi_ofst_cw = 0; ++ ++ pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); ++ bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); ++ rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); ++ rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); ++ pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; ++ ++ tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", ++ tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); ++ ++ return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); ++} ++ ++static ++void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, ++ s16 pw_ofst, enum rtw89_mac_idx mac_idx) ++{ ++ s32 val_1t = 0; ++ s32 val_2t = 0; ++ u32 reg; ++ ++ if (pw_ofst < -16 || pw_ofst > 15) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", ++ pw_ofst); ++ return; ++ } ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); ++ val_1t = (s32)pw_ofst; ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); ++ val_2t = max(val_1t - 3, -16); ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", ++ val_1t, val_2t); ++} ++ ++static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; ++ const u32 mask = 0x7FFFFFF; ++ const u8 ofst_ofdm = 0x4; ++ const u8 ofst_cck = 0x8; ++ s16 ref_ofdm = 0; ++ s16 ref_cck = 0; ++ u32 val; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); ++ ++ rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, ++ GENMASK(27, 10), 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); ++ val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, ++ phy_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); ++ val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, ++ phy_idx); ++} ++ ++static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ static const u8 rs[] = { ++ RTW89_RS_CCK, ++ RTW89_RS_OFDM, ++ RTW89_RS_MCS, ++ RTW89_RS_HEDCM, ++ }; ++ s8 tmp; ++ u8 i, j; ++ u32 val, shf, addr = R_AX_PWR_BY_RATE; ++ struct rtw89_rate_desc cur; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr byrate with ch=%d\n", ch); ++ ++ for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { ++ for (i = 0; i < ARRAY_SIZE(rs); i++) { ++ if (cur.nss >= rtw89_rs_nss_max[rs[i]]) ++ continue; ++ ++ val = 0; ++ cur.rs = rs[i]; ++ ++ for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { ++ cur.idx = j; ++ shf = (j % 4) * 8; ++ tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur); ++ val |= (tmp << shf); ++ ++ if ((j + 1) % 4) ++ continue; ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ val = 0; ++ addr += 4; ++ } ++ } ++ } ++} ++ ++static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ struct rtw89_rate_desc desc = { ++ .nss = RTW89_NSS_1, ++ .rs = RTW89_RS_OFFSET, ++ }; ++ u32 val = 0; ++ s8 v; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); ++ ++ for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { ++ v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc); ++ val |= ((v & 0xf) << (4 * desc.idx)); ++ } ++ ++ rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, ++ GENMASK(19, 0), val); ++} ++ ++static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++#define __MAC_TXPWR_LMT_PAGE_SIZE 40 ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; ++ u32 addr, val; ++ const s8 *ptr; ++ u8 i, j, k; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); ++ ++ for (i = 0; i < NTX_NUM_8852A; i++) { ++ rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i); ++ ++ for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { ++ addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; ++ ptr = (s8 *)&lmt[i] + j; ++ val = 0; ++ ++ for (k = 0; k < 4; k++) ++ val |= (ptr[k] << (8 * k)); ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ } ++ } ++#undef __MAC_TXPWR_LMT_PAGE_SIZE ++} ++ ++static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; ++ u32 addr, val; ++ const s8 *ptr; ++ u8 i, j, k; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); ++ ++ for (i = 0; i < NTX_NUM_8852A; i++) { ++ rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i); ++ ++ for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { ++ addr = R_AX_PWR_RU_LMT + j + ++ __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; ++ ptr = (s8 *)&lmt_ru[i] + j; ++ val = 0; ++ ++ for (k = 0; k < 4; k++) ++ val |= (ptr[k] << (8 * k)); ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ } ++ } ++ ++#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE ++} ++ ++static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0); ++} ++ ++static int ++rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ int ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) ++{ ++ u8 i = 0; ++ u32 addr, val; ++ ++ for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { ++ addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; ++ val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; ++ rtw89_phy_write32(rtwdev, addr, val); ++ } ++} ++ ++static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); ++ if (tx_info->mode == CONT_TX) ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, ++ idx); ++ else if (tx_info->mode == PKTS_TX) ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, ++ idx); ++} ++ ++static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ enum rtw8852a_pmac_mode mode = tx_info->mode; ++ u32 pkt_cnt = tx_info->tx_cnt; ++ u16 period = tx_info->period; ++ ++ if (mode == CONT_TX && !tx_info->is_cck) { ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, ++ idx); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); ++ } else if (mode == PKTS_TX) { ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, ++ idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, ++ B_PMAC_TX_PRD_MSK, period, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, ++ pkt_cnt, idx); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); ++ } ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); ++} ++ ++void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ if (!tx_info->en_pmac_tx) { ++ rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); ++ if (rtwdev->hal.current_band_type == RTW89_BAND_2G) ++ rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ return; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, ++ idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); ++ rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); ++} ++ ++void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, ++ u16 tx_cnt, u16 period, u16 tx_time, ++ enum rtw89_phy_idx idx) ++{ ++ struct rtw8852a_bb_pmac_info tx_info = {0}; ++ ++ tx_info.en_pmac_tx = enable; ++ tx_info.is_cck = 0; ++ tx_info.mode = PKTS_TX; ++ tx_info.tx_cnt = tx_cnt; ++ tx_info.period = period; ++ tx_info.tx_time = tx_time; ++ rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); ++} ++ ++void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, ++ enum rtw89_phy_idx idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); ++} ++ ++void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) ++{ ++ u32 rst_mask0 = 0; ++ u32 rst_mask1 = 0; ++ ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); ++ if (!rtwdev->dbcc_en) { ++ if (tx_path == RF_PATH_A) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 1); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 0); ++ } else if (tx_path == RF_PATH_B) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 2); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 0); ++ } else if (tx_path == RF_PATH_AB) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 3); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 4); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); ++ } ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, ++ 1); ++ rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, ++ RTW89_PHY_1); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, ++ 0); ++ rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, ++ RTW89_PHY_1); ++ } ++ rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; ++ rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; ++ if (tx_path == RF_PATH_A) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); ++ } ++} ++ ++void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx idx, u8 mode) ++{ ++ if (mode != 0) ++ return; ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); ++} ++ ++static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) ++{ ++ rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : ++ &rtw8852a_btc_preagc_dis_defs_tbl); ++} ++ ++static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) ++{ ++ if (rtwdev->is_tssi_mode[rf_path]) { ++ u32 addr = 0x1c10 + (rf_path << 13); ++ ++ return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); ++ } ++ ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); ++ ++ fsleep(200); ++ ++ return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); ++} ++ ++static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ ++ module->rfe_type = rtwdev->efuse.rfe_type; ++ module->cv = rtwdev->hal.cv; ++ module->bt_solo = 0; ++ module->switch_type = BTC_SWITCH_INTERNAL; ++ ++ if (module->rfe_type > 0) ++ module->ant.num = (module->rfe_type % 2 ? 2 : 3); ++ else ++ module->ant.num = 2; ++ ++ module->ant.diversity = 0; ++ module->ant.isolation = 10; ++ ++ if (module->ant.num == 3) { ++ module->ant.type = BTC_ANT_DEDICATED; ++ module->bt_pos = BTC_BT_ALONE; ++ } else { ++ module->ant.type = BTC_ANT_SHARED; ++ module->bt_pos = BTC_BT_BTG; ++ } ++} ++ ++static ++void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) ++{ ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); ++} ++ ++static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) ++{ ++ if (btg) { ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); ++ } ++} ++ ++static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_mac_ax_coex coex_params = { ++ .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, ++ .direction = RTW89_MAC_AX_COEX_INNER, ++ }; ++ ++ /* PTA init */ ++ rtw89_mac_coex_init(rtwdev, &coex_params); ++ ++ /* set WL Tx response = Hi-Pri */ ++ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); ++ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); ++ ++ /* set rf gnt debug off */ ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); ++ ++ /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ ++ if (module->ant.type == BTC_ANT_SHARED) { ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); ++ } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); ++ } ++ ++ /* set PTA break table */ ++ rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); ++ ++ /* enable BT counter 0xda40[16,2] = 2b'11 */ ++ rtw89_write32_set(rtwdev, ++ R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); ++ btc->cx.wl.status.map.init_ok = true; ++} ++ ++static ++void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) ++{ ++ u32 bitmap = 0; ++ u32 reg = 0; ++ ++ switch (map) { ++ case BTC_PRI_MASK_TX_RESP: ++ reg = R_BTC_BT_COEX_MSK_TABLE; ++ bitmap = B_BTC_PRI_MASK_TX_RESP_V1; ++ break; ++ case BTC_PRI_MASK_BEACON: ++ reg = R_AX_WL_PRI_MSK; ++ bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; ++ break; ++ default: ++ return; ++ } ++ ++ if (state) ++ rtw89_write32_set(rtwdev, reg, bitmap); ++ else ++ rtw89_write32_clr(rtwdev, reg, bitmap); ++} ++ ++static inline u32 __btc_ctrl_val_all_time(u32 ctrl) ++{ ++ return FIELD_GET(GENMASK(15, 0), ctrl); ++} ++ ++static inline u32 __btc_ctrl_rst_all_time(u32 cur) ++{ ++ return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; ++} ++ ++static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) ++{ ++ u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; ++ u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; ++ ++ return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; ++} ++ ++static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) ++{ ++ return FIELD_GET(GENMASK(31, 16), ctrl); ++} ++ ++static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) ++{ ++ return cur & ~B_AX_TXAGC_BT_EN; ++} ++ ++static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) ++{ ++ u32 ov = cur & ~B_AX_TXAGC_BT_MASK; ++ u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); ++ ++ return ov | iv | B_AX_TXAGC_BT_EN; ++} ++ ++static void ++rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) ++{ ++ const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; ++ const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; ++ ++#define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) ++#define __handle(_case) \ ++ do { \ ++ const u32 _reg = __btc_cr_ ## _case; \ ++ u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ ++ u32 _cur, _wrt; \ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl %s: 0x%x\n", #_case, _val); \ ++ rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ ++ _wrt = __do_clr(_val) ? \ ++ __btc_ctrl_rst_ ## _case(_cur) : \ ++ __btc_ctrl_gen_ ## _case(_cur, _val); \ ++ rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ ++ } while (0) ++ ++ __handle(all_time); ++ __handle(gnt_bt); ++ ++#undef __handle ++#undef __do_clr ++} ++ ++static ++s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) ++{ ++ return clamp_t(s8, val, -100, 0) + 100; ++} ++ ++static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { ++ {255, 0, 0, 7}, /* 0 -> original */ ++ {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ ++ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ ++ {6, 1, 0, 7}, ++ {13, 1, 0, 7}, ++ {13, 1, 0, 7} ++}; ++ ++static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { ++ {255, 0, 0, 7}, /* 0 -> original */ ++ {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ ++ {255, 1, 0, 7}, ++ {255, 1, 0, 7}, ++ {255, 1, 0, 7} ++}; ++ ++static const ++u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; ++static const ++u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; ++ ++static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), ++ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), ++ RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), ++}; ++ ++static ++void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ ++ /* fix LNA2 = level-5 for BT ACI issue at BTG */ ++ if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ++ dm->trx_para_level = 1; ++} ++ ++static ++void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); ++ cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); ++ ++ val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); ++ cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); ++ ++ /* clock-gate off before reset counter*/ ++ rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); ++ rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); ++ rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); ++ rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); ++} ++ ++static ++void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) ++{ ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); ++ ++ /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ ++ if (state) ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, ++ RFREG_MASK, 0xa2d7c); ++ else ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, ++ RFREG_MASK, 0xa2020); ++ ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); ++} ++ ++static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status) ++{ ++ u8 path; ++ s8 *rx_power = phy_ppdu->rssi; ++ ++ status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); ++ for (path = 0; path < rtwdev->chip->rf_path_num; path++) { ++ status->chains |= BIT(path); ++ status->chain_signal[path] = rx_power[path]; ++ } ++} ++ ++static const struct rtw89_chip_ops rtw8852a_chip_ops = { ++ .bb_reset = rtw8852a_bb_reset, ++ .bb_sethw = rtw8852a_bb_sethw, ++ .read_rf = rtw89_phy_read_rf, ++ .write_rf = rtw89_phy_write_rf, ++ .set_channel = rtw8852a_set_channel, ++ .set_channel_help = rtw8852a_set_channel_help, ++ .read_efuse = rtw8852a_read_efuse, ++ .read_phycap = rtw8852a_read_phycap, ++ .fem_setup = rtw8852a_fem_setup, ++ .rfk_init = rtw8852a_rfk_init, ++ .rfk_channel = rtw8852a_rfk_channel, ++ .rfk_band_changed = rtw8852a_rfk_band_changed, ++ .rfk_track = rtw8852a_rfk_track, ++ .power_trim = rtw8852a_power_trim, ++ .set_txpwr = rtw8852a_set_txpwr, ++ .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, ++ .init_txpwr_unit = rtw8852a_init_txpwr_unit, ++ .get_thermal = rtw8852a_get_thermal, ++ .ctrl_btg = rtw8852a_ctrl_btg, ++ .query_ppdu = rtw8852a_query_ppdu, ++ .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, ++ .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, ++ ++ .btc_set_rfe = rtw8852a_btc_set_rfe, ++ .btc_init_cfg = rtw8852a_btc_init_cfg, ++ .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, ++ .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, ++ .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, ++ .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, ++ .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, ++ .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, ++}; ++ ++const struct rtw89_chip_info rtw8852a_chip_info = { ++ .chip_id = RTL8852A, ++ .ops = &rtw8852a_chip_ops, ++ .fw_name = "rtw89/rtw8852a_fw.bin", ++ .fifo_size = 458752, ++ .max_amsdu_limit = 3500, ++ .dis_2g_40m_ul_ofdma = true, ++ .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, ++ .dle_mem = rtw8852a_dle_mem_pcie, ++ .rf_base_addr = {0xc000, 0xd000}, ++ .pwr_on_seq = pwr_on_seq_8852a, ++ .pwr_off_seq = pwr_off_seq_8852a, ++ .bb_table = &rtw89_8852a_phy_bb_table, ++ .rf_table = {&rtw89_8852a_phy_radioa_table, ++ &rtw89_8852a_phy_radiob_table,}, ++ .nctl_table = &rtw89_8852a_phy_nctl_table, ++ .byr_table = &rtw89_8852a_byr_table, ++ .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, ++ .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, ++ .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, ++ .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, ++ .txpwr_factor_rf = 2, ++ .txpwr_factor_mac = 1, ++ .dig_table = &rtw89_8852a_phy_dig_table, ++ .rf_path_num = 2, ++ .tx_nss = 2, ++ .rx_nss = 2, ++ .acam_num = 128, ++ .bcam_num = 10, ++ .scam_num = 128, ++ .sec_ctrl_efuse_size = 4, ++ .physical_efuse_size = 1216, ++ .logical_efuse_size = 1536, ++ .limit_efuse_size = 1152, ++ .phycap_addr = 0x580, ++ .phycap_size = 128, ++ .para_ver = 0x05050764, ++ .wlcx_desired = 0x05050000, ++ .btcx_desired = 0x5, ++ .scbd = 0x1, ++ .mailbox = 0x1, ++ .afh_guard_ch = 6, ++ .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, ++ .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, ++ .rssi_tol = 2, ++ .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), ++ .mon_reg = rtw89_btc_8852a_mon_reg, ++ .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), ++ .rf_para_ulink = rtw89_btc_8852a_rf_ul, ++ .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), ++ .rf_para_dlink = rtw89_btc_8852a_rf_dl, ++ .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | ++ BIT(RTW89_PS_MODE_CLK_GATED) | ++ BIT(RTW89_PS_MODE_PWR_GATED), ++}; ++EXPORT_SYMBOL(rtw8852a_chip_info); ++ ++MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.h b/drivers/net/wireless/realtek/rtw89/rtw8852a.h +new file mode 100644 +index 000000000000..633384374de0 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.h +@@ -0,0 +1,109 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_H__ ++#define __RTW89_8852A_H__ ++ ++#include "core.h" ++ ++#define RF_PATH_NUM_8852A 2 ++#define NTX_NUM_8852A 2 ++ ++enum rtw8852a_pmac_mode { ++ NONE_TEST, ++ PKTS_TX, ++ PKTS_RX, ++ CONT_TX ++}; ++ ++struct rtw8852au_efuse { ++ u8 rsvd[0x38]; ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++struct rtw8852ae_efuse { ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++struct rtw8852a_tssi_offset { ++ u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; ++ u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; ++ u8 rsvd[7]; ++ u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; ++} __packed; ++ ++struct rtw8852a_efuse { ++ u8 rsvd[0x210]; ++ struct rtw8852a_tssi_offset path_a_tssi; ++ u8 rsvd1[10]; ++ struct rtw8852a_tssi_offset path_b_tssi; ++ u8 rsvd2[94]; ++ u8 channel_plan; ++ u8 xtal_k; ++ u8 rsvd3; ++ u8 iqk_lck; ++ u8 rsvd4[5]; ++ u8 reg_setting:2; ++ u8 tx_diversity:1; ++ u8 rx_diversity:2; ++ u8 ac_mode:1; ++ u8 module_type:2; ++ u8 rsvd5; ++ u8 shared_ant:1; ++ u8 coex_type:3; ++ u8 ant_iso:1; ++ u8 radio_on_off:1; ++ u8 rsvd6:2; ++ u8 eeprom_version; ++ u8 customer_id; ++ u8 tx_bb_swing_2g; ++ u8 tx_bb_swing_5g; ++ u8 tx_cali_pwr_trk_mode; ++ u8 trx_path_selection; ++ u8 rfe_type; ++ u8 country_code[2]; ++ u8 rsvd7[3]; ++ u8 path_a_therm; ++ u8 path_b_therm; ++ u8 rsvd8[46]; ++ u8 path_a_cck_pwr_idx[6]; ++ u8 path_a_bw40_1tx_pwr_idx[5]; ++ u8 path_a_ofdm_1tx_pwr_idx_diff:4; ++ u8 path_a_bw20_1tx_pwr_idx_diff:4; ++ u8 path_a_bw20_2tx_pwr_idx_diff:4; ++ u8 path_a_bw40_2tx_pwr_idx_diff:4; ++ u8 path_a_cck_2tx_pwr_idx_diff:4; ++ u8 path_a_ofdm_2tx_pwr_idx_diff:4; ++ u8 rsvd9[0xf2]; ++ union { ++ struct rtw8852au_efuse u; ++ struct rtw8852ae_efuse e; ++ }; ++} __packed; ++ ++struct rtw8852a_bb_pmac_info { ++ u8 en_pmac_tx:1; ++ u8 is_cck:1; ++ u8 mode:3; ++ u8 rsvd:3; ++ u16 tx_cnt; ++ u16 period; ++ u16 tx_time; ++ u8 duty_cycle; ++}; ++ ++void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev); ++void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, ++ u16 tx_cnt, u16 period, u16 tx_time, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path); ++void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx idx, u8 mode); ++ ++#endif + +From patchwork Fri Aug 20 04:35:28 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448387 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 02571C4338F + for ; + Fri, 20 Aug 2021 04:37:26 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id CA88060EB5 + for ; + Fri, 20 Aug 2021 04:37:25 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233925AbhHTEiB (ORCPT + ); + Fri, 20 Aug 2021 00:38:01 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39268 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233544AbhHTEiA (ORCPT + ); + Fri, 20 Aug 2021 00:38:00 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bJNP1004049, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bJNP1004049 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:19 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:18 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:17 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 14/24] rtw89: 8852a: add 8852a RFK files +Date: Fri, 20 Aug 2021 12:35:28 +0800 +Message-ID: <20210820043538.12424-15-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +RFK contains DACK, IQK, LOK, RCK, RX DCK, DPK and TSSI. They are called by +rfk_init, rfk_channel and rfk_track at the occasions of initialization, +channel switch and periodic track respectively. + +Signed-off-by: Ping-Ke Shih +--- + .../net/wireless/realtek/rtw89/rtw8852a_rfk.c | 3801 +++++++++++++++++ + .../net/wireless/realtek/rtw89/rtw8852a_rfk.h | 22 + + 2 files changed, 3823 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c +new file mode 100644 +index 000000000000..eba31fa88d61 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c +@@ -0,0 +1,3801 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a.h" ++#include "rtw8852a_rfk.h" ++#include "rtw8852a_rfk_table.h" ++#include "rtw8852a_table.h" ++ ++static void ++_rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); ++} ++ ++static void ++_rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); ++} ++ ++static void ++_rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_set(rtwdev, def->addr, def->mask); ++} ++ ++static void ++_rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); ++} ++ ++static void ++_rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ udelay(def->data); ++} ++ ++static void ++(*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { ++ [RTW89_RFK_F_WRF] = _rfk_write_rf, ++ [RTW89_RFK_F_WM] = _rfk_write32_mask, ++ [RTW89_RFK_F_WS] = _rfk_write32_set, ++ [RTW89_RFK_F_WC] = _rfk_write32_clr, ++ [RTW89_RFK_F_DELAY] = _rfk_delay, ++}; ++ ++static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); ++ ++static void ++rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) ++{ ++ const struct rtw89_reg5_def *p = tbl->defs; ++ const struct rtw89_reg5_def *end = tbl->defs + tbl->size; ++ ++ for (; p < end; p++) ++ _rfk_handler[p->flag](rtwdev, p); ++} ++ ++#define rtw89_rfk_parser_by_cond(rtwdev, cond, tbl_t, tbl_f) \ ++ do { \ ++ typeof(rtwdev) _dev = (rtwdev); \ ++ if (cond) \ ++ rtw89_rfk_parser(_dev, (tbl_t)); \ ++ else \ ++ rtw89_rfk_parser(_dev, (tbl_f)); \ ++ } while (0) ++ ++static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n", ++ rtwdev->dbcc_en, phy_idx); ++ ++ if (!rtwdev->dbcc_en) ++ return RF_AB; ++ ++ if (phy_idx == RTW89_PHY_0) ++ return RF_A; ++ else ++ return RF_B; ++} ++ ++static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0}; ++static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5}; ++#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852a_backup_bb_regs) ++#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852a_backup_rf_regs) ++ ++static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[]) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_BB_REGS_NR; i++) { ++ backup_bb_reg_val[i] = ++ rtw89_phy_read32_mask(rtwdev, rtw8852a_backup_bb_regs[i], ++ MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]backup bb reg : %x, value =%x\n", ++ rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]); ++ } ++} ++ ++static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[], ++ u8 rf_path) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_RF_REGS_NR; i++) { ++ backup_rf_reg_val[i] = ++ rtw89_read_rf(rtwdev, rf_path, ++ rtw8852a_backup_rf_regs[i], RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path, ++ rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]); ++ } ++} ++ ++static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev, ++ u32 backup_bb_reg_val[]) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_BB_REGS_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, rtw8852a_backup_bb_regs[i], ++ MASKDWORD, backup_bb_reg_val[i]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]restore bb reg : %x, value =%x\n", ++ rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]); ++ } ++} ++ ++static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev, ++ u32 backup_rf_reg_val[], u8 rf_path) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_RF_REGS_NR; i++) { ++ rtw89_write_rf(rtwdev, rf_path, rtw8852a_backup_rf_regs[i], ++ RFREG_MASK, backup_rf_reg_val[i]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path, ++ rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]); ++ } ++} ++ ++static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath) ++{ ++ u8 path; ++ u32 rf_mode; ++ int ret; ++ ++ for (path = 0; path < RF_PATH_MAX; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2, ++ 2, 5000, false, rtwdev, path, 0x00, ++ RR_MOD_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", ++ path, ret); ++ } ++} ++ ++static void _dack_dump(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ u8 t; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->addck_d[0][0], dack->addck_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->addck_d[1][0], dack->addck_d[1][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->dadck_d[0][0], dack->dadck_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->dadck_d[1][0], dack->dadck_d[1][1]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", ++ dack->biask_d[0][0], dack->biask_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", ++ dack->biask_d[1][0], dack->biask_d[1][1]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[0][0][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[0][1][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[1][0][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[1][1][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++} ++ ++static void _afe_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_afe_init_defs_tbl); ++} ++ ++static void _addck_backup(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ ++ rtw89_phy_write32_clr(rtwdev, R_S0_RXDC2, B_S0_RXDC2_SEL); ++ dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, ++ B_S0_ADDCK_Q); ++ dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, ++ B_S0_ADDCK_I); ++ ++ rtw89_phy_write32_clr(rtwdev, R_S1_RXDC2, B_S1_RXDC2_SEL); ++ dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK, ++ B_S1_ADDCK_Q); ++ dack->addck_d[1][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK, ++ B_S1_ADDCK_I); ++} ++ ++static void _addck_reload(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2, B_S0_RXDC2_Q2, ++ (dack->addck_d[0][1] >> 6)); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_Q, ++ (dack->addck_d[0][1] & 0x3f)); ++ rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC2, B_S1_RXDC2_Q2, ++ (dack->addck_d[1][1] >> 6)); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_Q, ++ (dack->addck_d[1][1] & 0x3f)); ++ rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN); ++} ++ ++static void _dack_backup_s0(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ ++ rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN); ++ rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN); ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG); ++ ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_S0_DACKI, B_S0_DACKI_AR, i); ++ dack->msbk_d[0][0][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI7, B_S0_DACKI7_K); ++ rtw89_phy_write32_mask(rtwdev, R_S0_DACKQ, B_S0_DACKQ_AR, i); ++ dack->msbk_d[0][1][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ7, B_S0_DACKQ7_K); ++ } ++ dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2, ++ B_S0_DACKI2_K); ++ dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2, ++ B_S0_DACKQ2_K); ++ dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8, ++ B_S0_DACKI8_K) - 8; ++ dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8, ++ B_S0_DACKQ8_K) - 8; ++} ++ ++static void _dack_backup_s1(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ ++ rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN); ++ rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON); ++ ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_S1_DACKI, B_S1_DACKI_AR, i); ++ dack->msbk_d[1][0][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI7, B_S1_DACKI_K); ++ rtw89_phy_write32_mask(rtwdev, R_S1_DACKQ, B_S1_DACKQ_AR, i); ++ dack->msbk_d[1][1][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ7, B_S1_DACKQ7_K); ++ } ++ dack->biask_d[1][0] = ++ (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI2, B_S1_DACKI2_K); ++ dack->biask_d[1][1] = ++ (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ2, B_S1_DACKQ2_K); ++ dack->dadck_d[1][0] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI8, B_S1_DACKI8_K) - 8; ++ dack->dadck_d[1][1] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ8, B_S1_DACKQ8_K) - 8; ++} ++ ++static void _dack_reload_by_path(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 index) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 tmp = 0, tmp_offset, tmp_reg; ++ u8 i; ++ u32 idx_offset, path_offset; ++ ++ if (index == 0) ++ idx_offset = 0; ++ else ++ idx_offset = 0x50; ++ ++ if (path == RF_PATH_A) ++ path_offset = 0; ++ else ++ path_offset = 0x2000; ++ ++ tmp_offset = idx_offset + path_offset; ++ /* msbk_d: 15/14/13/12 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 12] << (i * 8); ++ tmp_reg = 0x5e14 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 11/10/9/8 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 8] << (i * 8); ++ tmp_reg = 0x5e18 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 7/6/5/4 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 4] << (i * 8); ++ tmp_reg = 0x5e1c + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 3/2/1/0 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i] << (i * 8); ++ tmp_reg = 0x5e20 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* dadak_d/biask_d */ ++ tmp = 0x0; ++ tmp = (dack->biask_d[path][index] << 22) | ++ (dack->dadck_d[path][index] << 14); ++ tmp_reg = 0x5e24 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++} ++ ++static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ u8 i; ++ ++ for (i = 0; i < 2; i++) ++ _dack_reload_by_path(rtwdev, path, i); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_dack_reload_defs_a_tbl, ++ &rtw8852a_rfk_dack_reload_defs_b_tbl); ++} ++ ++#define ADDC_T_AVG 100 ++static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ s32 dc_re = 0, dc_im = 0; ++ u32 tmp; ++ u32 i; ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_addc_defs_a_tbl, ++ &rtw8852a_rfk_check_addc_defs_b_tbl); ++ ++ for (i = 0; i < ADDC_T_AVG; i++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD); ++ dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); ++ dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); ++ } ++ ++ dc_re /= ADDC_T_AVG; ++ dc_im /= ADDC_T_AVG; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); ++} ++ ++static void _addck(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ /* S0 */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_a_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_A); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x1e00, BIT(0)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n"); ++ dack->addck_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_A); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_a_tbl); ++ ++ /* S1 */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_b_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_B); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x3e00, BIT(0)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n"); ++ dack->addck_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_B); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_b_tbl); ++} ++ ++static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_dadc_defs_f_a_tbl, ++ &rtw8852a_rfk_check_dadc_defs_f_b_tbl); ++ ++ _check_addc(rtwdev, path); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_dadc_defs_r_a_tbl, ++ &rtw8852a_rfk_check_dadc_defs_r_b_tbl); ++} ++ ++static void _dack_s0(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e28, BIT(15)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e78, BIT(15)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n"); ++ dack->msbk_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e48, BIT(17)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e98, BIT(17)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADACK timeout\n"); ++ dack->dadck_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_a_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n"); ++ _check_dadc(rtwdev, RF_PATH_A); ++ ++ _dack_backup_s0(rtwdev); ++ _dack_reload(rtwdev, RF_PATH_A); ++ ++ rtw89_phy_write32_clr(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG); ++} ++ ++static void _dack_s1(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e28, BIT(15)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e78, BIT(15)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n"); ++ dack->msbk_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e48, BIT(17)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e98, BIT(17)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n"); ++ dack->dadck_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_b_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n"); ++ _check_dadc(rtwdev, RF_PATH_B); ++ ++ _dack_backup_s1(rtwdev); ++ _dack_reload(rtwdev, RF_PATH_B); ++ ++ rtw89_phy_write32_clr(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON); ++} ++ ++static void _dack(struct rtw89_dev *rtwdev) ++{ ++ _dack_s0(rtwdev); ++ _dack_s1(rtwdev); ++} ++ ++static void _dac_cal(struct rtw89_dev *rtwdev, bool force) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 rf0_0, rf1_0; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB); ++ ++ dack->dack_done = false; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n"); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n"); ++ rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK); ++ rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK); ++ _afe_init(rtwdev); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); ++ _addck(rtwdev); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); ++ _addck_backup(rtwdev); ++ _addck_reload(rtwdev); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); ++ _dack(rtwdev); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); ++ _dack_dump(rtwdev); ++ dack->dack_done = true; ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); ++ dack->dack_cnt++; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n"); ++} ++ ++#define RTW8852A_NCTL_VER 0xd ++#define RTW8852A_IQK_VER 0x2a ++#define RTW8852A_IQK_SS 2 ++#define RTW8852A_IQK_THR_REK 8 ++#define RTW8852A_IQK_CFIR_GROUP_NR 4 ++ ++enum rtw8852a_iqk_type { ++ ID_TXAGC, ++ ID_FLOK_COARSE, ++ ID_FLOK_FINE, ++ ID_TXK, ++ ID_RXAGC, ++ ID_RXK, ++ ID_NBTXK, ++ ID_NBRXK, ++}; ++ ++static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u8 i = 0x0; ++ u32 fft[6] = {0x0}; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000); ++ fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000); ++ fft[1] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000); ++ fft[2] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000); ++ fft[3] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000); ++ fft[4] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000); ++ fft[5] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ for (i = 0; i < 6; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x,fft[%x]= %x\n", ++ path, i, fft[i]); ++} ++ ++static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u8 i = 0x0; ++ u32 tmp = 0x0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1); ++ ++ for (i = 0x0; i < 0x18; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N2, MASKDWORD); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n", ++ path, BIT(path), tmp); ++ udelay(1); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX); ++ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100); ++ udelay(1); ++} ++ ++static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, ++ u8 group) ++{ ++ static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = { ++ {0x8f20, 0x8f54, 0x8f88, 0x8fbc}, ++ {0x9320, 0x9354, 0x9388, 0x93bc}, ++ }; ++ u8 idx = 0x0; ++ u32 tmp = 0x0; ++ u32 base_addr; ++ ++ if (path >= RTW8852A_IQK_SS) { ++ rtw89_warn(rtwdev, "cfir path %d out of range\n", path); ++ return; ++ } ++ if (group >= RTW8852A_IQK_CFIR_GROUP_NR) { ++ rtw89_warn(rtwdev, "cfir group %d out of range\n", group); ++ return; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); ++ ++ base_addr = base_addrs[path][group]; ++ ++ for (idx = 0; idx < 0x0d; idx++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK] %x = %x\n", ++ base_addr + (idx << 2), tmp); ++ } ++ ++ if (path == 0x0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc); ++ udelay(1); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, ++ BIT(path), tmp); ++} ++ ++static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, ++ u8 group) ++{ ++ static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = { ++ {0x8d00, 0x8d44, 0x8d88, 0x8dcc}, ++ {0x9100, 0x9144, 0x9188, 0x91cc}, ++ }; ++ u8 idx = 0x0; ++ u32 tmp = 0x0; ++ u32 base_addr; ++ ++ if (path >= RTW8852A_IQK_SS) { ++ rtw89_warn(rtwdev, "cfir path %d out of range\n", path); ++ return; ++ } ++ if (group >= RTW8852A_IQK_CFIR_GROUP_NR) { ++ rtw89_warn(rtwdev, "cfir group %d out of range\n", group); ++ return; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); ++ ++ base_addr = base_addrs[path][group]; ++ for (idx = 0; idx < 0x10; idx++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]%x = %x\n", ++ base_addr + (idx << 2), tmp); ++ } ++ ++ if (path == 0x0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, ++ BIT(path), tmp); ++} ++ ++static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u32 tmp = 0x0; ++ u32 i = 0x0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000); ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ ++ for (i = 0; i <= 0x9f; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); ++ } ++ ++ for (i = 0; i <= 0x9f; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX2, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX, MASKDWORD); ++} ++ ++static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 tmp = 0x0; ++ ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); ++ break; ++ default: ++ break; ++ } ++ tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); ++ fsleep(128); ++} ++ ++static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) ++{ ++ u32 tmp; ++ u32 val; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200, ++ false, rtwdev, 0xbff8, MASKBYTE0); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n"); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); ++ ++ return false; ++} ++ ++static bool _iqk_one_shot(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path, u8 ktype) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool fail = false; ++ u32 iqk_cmd = 0x0; ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path); ++ u32 addr_rfc_ctl = 0x0; ++ ++ if (path == RF_PATH_A) ++ addr_rfc_ctl = 0x5864; ++ else ++ addr_rfc_ctl = 0x7864; ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START); ++ switch (ktype) { ++ case ID_TXAGC: ++ iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); ++ break; ++ case ID_FLOK_COARSE: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ iqk_cmd = 0x108 | (1 << (4 + path)); ++ break; ++ case ID_FLOK_FINE: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ iqk_cmd = 0x208 | (1 << (4 + path)); ++ break; ++ case ID_TXK: ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); ++ iqk_cmd = 0x008 | (1 << (path + 4)) | ++ (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); ++ break; ++ case ID_RXAGC: ++ iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); ++ break; ++ case ID_RXK: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); ++ iqk_cmd = 0x008 | (1 << (path + 4)) | ++ (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); ++ break; ++ case ID_NBTXK: ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); ++ iqk_cmd = 0x308 | (1 << (4 + path)); ++ break; ++ case ID_NBRXK: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); ++ iqk_cmd = 0x608 | (1 << (4 + path)); ++ break; ++ default: ++ return false; ++ } ++ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1); ++ rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN); ++ udelay(1); ++ fail = _iqk_check_cal(rtwdev, path, ktype); ++ if (iqk_info->iqk_xym_en) ++ _iqk_read_xym_dbcc0(rtwdev, path); ++ if (iqk_info->iqk_fft_en) ++ _iqk_read_fft_dbcc0(rtwdev, path); ++ if (iqk_info->iqk_sram_en) ++ _iqk_sram(rtwdev, path); ++ if (iqk_info->iqk_cfir_en) { ++ if (ktype == ID_TXK) { ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3); ++ } else { ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3); ++ } ++ } ++ ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP); ++ ++ return fail; ++} ++ ++static bool _rxk_group_sel(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0}; ++ static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30}; ++ static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1}; ++ static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0}; ++ static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a}; ++ static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0}; ++ u8 gp = 0x0; ++ bool fail = false; ++ u32 rf0 = 0x0; ++ ++ for (gp = 0; gp < 0x4; gp++) { ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); ++ rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); ++ } ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); ++ break; ++ default: ++ break; ++ } ++ iqk_info->nb_rxcfir[path] = 0x40000000; ++ rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), ++ B_IQK_RES_RXCFIR, 0x5); ++ iqk_info->is_wb_rxiqk[path] = true; ++ return false; ++} ++ ++static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 group = 0x0; ++ u32 rf0 = 0x0, tmp = 0x0; ++ u32 idxrxgain_a = 0x1a0; ++ u32 idxattc2_a = 0x00; ++ u32 idxattc1_a = 0x5; ++ u32 idxrxgain_g = 0x1E0; ++ u32 idxattc2_g = 0x15; ++ u32 idxattc1_g = 0x0; ++ bool fail = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_GP, group); ++ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); ++ break; ++ default: ++ break; ++ } ++ if (!fail) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); ++ iqk_info->nb_rxcfir[path] = tmp | 0x2; ++ } else { ++ iqk_info->nb_rxcfir[path] = 0x40000002; ++ } ++ return fail; ++} ++ ++static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), ++ MASKDWORD, 0x4d000a08); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x2); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON); ++ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), ++ MASKDWORD, 0x44000a08); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x1); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON); ++ rtw89_phy_write32_clr(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL); ++ } ++} ++ ++static bool _txk_group_sel(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ static const u32 a_txgain[4] = {0xE466, 0x646D, 0xE4E2, 0x64ED}; ++ static const u32 g_txgain[4] = {0x60e8, 0x60f0, 0x61e8, 0x61ED}; ++ static const u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b}; ++ static const u32 g_itqt[4] = {0x09, 0x12, 0x12, 0x12}; ++ static const u32 g_attsmxr[4] = {0x0, 0x1, 0x1, 0x1}; ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool fail = false; ++ u8 gp = 0x0; ++ u32 tmp = 0x0; ++ ++ for (gp = 0x0; gp < 0x4; gp++) { ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x08); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, ++ g_txgain[gp]); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, ++ g_attsmxr[gp]); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, ++ g_attsmxr[gp]); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), ++ MASKDWORD, g_itqt[gp]); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x04); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, ++ a_txgain[gp]); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), ++ MASKDWORD, a_itqt[gp]); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_GP, gp); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail); ++ } ++ ++ iqk_info->nb_txcfir[path] = 0x40000000; ++ rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), ++ B_IQK_RES_TXCFIR, 0x5); ++ iqk_info->is_wb_txiqk[path] = true; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, ++ BIT(path), tmp); ++ return false; ++} ++ ++static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 group = 0x2; ++ u32 a_mode_txgain = 0x64e2; ++ u32 g_mode_txgain = 0x61e8; ++ u32 attsmxr = 0x1; ++ u32 itqt = 0x12; ++ u32 tmp = 0x0; ++ bool fail = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x08); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x04); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); ++ if (!fail) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ iqk_info->nb_txcfir[path] = tmp | 0x2; ++ } else { ++ iqk_info->nb_txcfir[path] = 0x40000002; ++ } ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, ++ BIT(path), tmp); ++ return fail; ++} ++ ++static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); ++ if (iqk_info->iqk_band[path] == RTW89_BAND_2G) ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); ++ else ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); ++} ++ ++static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) ++{ ++ bool is_fail = false; ++ u32 tmp = 0x0; ++ u32 core_i = 0x0; ++ u32 core_q = 0x0; ++ ++ tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK][FineLOK] S%x, 0x58 = 0x%x\n", ++ path, tmp); ++ core_i = FIELD_GET(RR_TXMO_COI, tmp); ++ core_q = FIELD_GET(RR_TXMO_COQ, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q); ++ ++ if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) ++ is_fail = true; ++ return is_fail; ++} ++ ++static bool _iqk_lok(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 rf0 = 0x0; ++ u8 itqt = 0x12; ++ bool fail = false; ++ bool tmp = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0); ++ itqt = 0x09; ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0); ++ itqt = 0x12; ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF1, B_IQK_DIF1_TXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0); ++ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE); ++ iqk_info->lok_cor_fail[0][path] = tmp; ++ fsleep(10); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE); ++ iqk_info->lok_fin_fail[0][path] = tmp; ++ fail = _lok_finetune_check(rtwdev, path); ++ return fail; ++} ++ ++static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000); ++ rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, ++ 0x403e0 | iqk_info->syn1to2); ++ udelay(1); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7); ++ rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100); ++ rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, ++ 0x403e0 | iqk_info->syn1to2); ++ udelay(1); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); ++} ++ ++static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 tmp = 0x0; ++ bool flag = 0x0; ++ ++ iqk_info->thermal[path] = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ iqk_info->thermal_rek_en = false; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path, ++ iqk_info->thermal[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path, ++ iqk_info->lok_cor_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, ++ iqk_info->lok_fin_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path, ++ iqk_info->iqk_tx_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path, ++ iqk_info->iqk_rx_fail[0][path]); ++ flag = iqk_info->lok_cor_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag); ++ flag = iqk_info->lok_fin_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag); ++ flag = iqk_info->iqk_tx_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag); ++ flag = iqk_info->iqk_rx_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag); ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); ++ iqk_info->bp_iqkenable[path] = tmp; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ iqk_info->bp_txkresult[path] = tmp; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); ++ iqk_info->bp_rxkresult[path] = tmp; ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, ++ (u8)iqk_info->iqk_times); ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4)); ++ if (tmp != 0x0) ++ iqk_info->iqk_fail_cnt++; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4), ++ iqk_info->iqk_fail_cnt); ++} ++ ++static ++void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool lok_is_fail = false; ++ u8 ibias = 0x1; ++ u8 i = 0; ++ ++ _iqk_txclk_setting(rtwdev, path); ++ ++ for (i = 0; i < 3; i++) { ++ _lok_res_table(rtwdev, path, ibias++); ++ _iqk_txk_setting(rtwdev, path); ++ lok_is_fail = _iqk_lok(rtwdev, phy_idx, path); ++ if (!lok_is_fail) ++ break; ++ } ++ if (iqk_info->is_nbiqk) ++ iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); ++ else ++ iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); ++ ++ _iqk_rxclk_setting(rtwdev, path); ++ _iqk_rxk_setting(rtwdev, path); ++ if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G) ++ iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); ++ else ++ iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); ++ ++ _iqk_info_iqk(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u32 reg_rf18 = 0x0, reg_35c = 0x0; ++ u8 idx = 0; ++ u8 get_empty_table = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { ++ if (iqk_info->iqk_mcc_ch[idx][path] == 0) { ++ get_empty_table = true; ++ break; ++ } ++ } ++ if (!get_empty_table) { ++ idx = iqk_info->iqk_table_idx[path] + 1; ++ if (idx > RTW89_IQK_CHS_NR - 1) ++ idx = 0; ++ } ++ reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]cfg ch = %d\n", reg_rf18); ++ reg_35c = rtw89_phy_read32_mask(rtwdev, 0x35c, 0x00000c00); ++ ++ iqk_info->iqk_band[path] = hal->current_band_type; ++ iqk_info->iqk_bw[path] = hal->current_band_width; ++ iqk_info->iqk_ch[path] = hal->current_channel; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, ++ iqk_info->iqk_band[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", ++ path, iqk_info->iqk_bw[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", ++ path, iqk_info->iqk_ch[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy, ++ rtwdev->dbcc_en ? "on" : "off", ++ iqk_info->iqk_band[path] == 0 ? "2G" : ++ iqk_info->iqk_band[path] == 1 ? "5G" : "6G", ++ iqk_info->iqk_ch[path], ++ iqk_info->iqk_bw[path] == 0 ? "20M" : ++ iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"); ++ if (reg_35c == 0x01) ++ iqk_info->syn1to2 = 0x1; ++ else ++ iqk_info->syn1to2 = 0x0; ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852A_IQK_VER); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16), ++ (u8)iqk_info->iqk_band[path]); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16), ++ (u8)iqk_info->iqk_bw[path]); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16), ++ (u8)iqk_info->iqk_ch[path]); ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x000000ff, RTW8852A_NCTL_VER); ++} ++ ++static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ u8 path) ++{ ++ _iqk_by_path(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, ++ iqk_info->nb_txcfir[path]); ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, ++ iqk_info->nb_rxcfir[path]); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_RX_DCK, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_clr(rtwdev, R_KPATH_CFG, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_GAPK, B_GAPK_ADR); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); ++ rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW); ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); ++} ++ ++static void _iqk_afebb_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ const struct rtw89_rfk_tbl *tbl; ++ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl; ++ break; ++ case RF_B: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl; ++ break; ++ default: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl; ++ break; ++ } ++ ++ rtw89_rfk_parser(rtwdev, tbl); ++} ++ ++static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 idx = iqk_info->iqk_table_idx[path]; ++ ++ if (rtwdev->dbcc_en) { ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_IQC, path & 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_G2, path & 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_IQC, idx); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_G2, idx); ++ } ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RW, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); ++ rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, MASKDWORD, 0x00200000); ++ rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD); ++} ++ ++static void _iqk_macbb_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ const struct rtw89_rfk_tbl *tbl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===> %s\n", __func__); ++ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl; ++ break; ++ case RF_B: ++ tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl; ++ break; ++ default: ++ tbl = &rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl; ++ break; ++ } ++ ++ rtw89_rfk_parser(rtwdev, tbl); ++} ++ ++static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 phy_idx = 0x0; ++ ++ iqk_info->iqk_times++; ++ ++ if (path == 0x0) ++ phy_idx = RTW89_PHY_0; ++ else ++ phy_idx = RTW89_PHY_1; ++ ++ _iqk_get_ch_info(rtwdev, phy_idx, path); ++ _iqk_macbb_setting(rtwdev, phy_idx, path); ++ _iqk_preset(rtwdev, path); ++ _iqk_start_iqk(rtwdev, phy_idx, path); ++ _iqk_restore(rtwdev, path); ++ _iqk_afebb_restore(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_iqk_info *iqk = &rtwdev->iqk; ++ u8 path = 0x0; ++ u8 cur_ther; ++ ++ if (iqk->iqk_band[0] == RTW89_BAND_2G) ++ return; ++ if (iqk->iqk_bw[0] < RTW89_CHANNEL_WIDTH_80) ++ return; ++ ++ /* only check path 0 */ ++ for (path = 0; path < 1; path++) { ++ cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ if (abs(cur_ther - iqk->thermal[path]) > RTW8852A_IQK_THR_REK) ++ iqk->thermal_rek_en = true; ++ else ++ iqk->thermal_rek_en = false; ++ } ++} ++ ++static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ u32 rf_reg5, rck_val = 0; ++ u32 val; ++ int ret; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); ++ ++ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); ++ ++ /* RCK trigger */ ++ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); ++ ++ ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 20, ++ false, rtwdev, path, 0x1c, BIT(3)); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n"); ++ ++ rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); ++ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); ++ ++ /* RCK_ADC_OFFSET */ ++ rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4); ++ ++ rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0); ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RCK] RF 0x1b / 0x1c / 0x1d = 0x%x / 0x%x / 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK)); ++} ++ ++static void _iqk_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 ch, path; ++ ++ rtw89_phy_write32_clr(rtwdev, R_IQKINF, MASKDWORD); ++ if (iqk_info->is_iqk_init) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ iqk_info->is_iqk_init = true; ++ iqk_info->is_nbiqk = false; ++ iqk_info->iqk_fft_en = false; ++ iqk_info->iqk_sram_en = false; ++ iqk_info->iqk_cfir_en = false; ++ iqk_info->iqk_xym_en = false; ++ iqk_info->thermal_rek_en = false; ++ iqk_info->iqk_times = 0x0; ++ ++ for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) { ++ iqk_info->iqk_channel[ch] = 0x0; ++ for (path = 0; path < RTW8852A_IQK_SS; path++) { ++ iqk_info->lok_cor_fail[ch][path] = false; ++ iqk_info->lok_fin_fail[ch][path] = false; ++ iqk_info->iqk_tx_fail[ch][path] = false; ++ iqk_info->iqk_rx_fail[ch][path] = false; ++ iqk_info->iqk_mcc_ch[ch][path] = 0x0; ++ iqk_info->iqk_table_idx[path] = 0x0; ++ } ++ } ++} ++ ++static void _doiqk(struct rtw89_dev *rtwdev, bool force, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 backup_bb_val[BACKUP_BB_REGS_NR]; ++ u32 backup_rf_val[RTW8852A_IQK_SS][BACKUP_RF_REGS_NR]; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]==========IQK strat!!!!!==========\n"); ++ iqk_info->iqk_times++; ++ iqk_info->kcount = 0; ++ iqk_info->version = RTW8852A_IQK_VER; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); ++ _iqk_get_ch_info(rtwdev, phy_idx, path); ++ _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); ++ _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ _iqk_macbb_setting(rtwdev, phy_idx, path); ++ _iqk_preset(rtwdev, path); ++ _iqk_start_iqk(rtwdev, phy_idx, path); ++ _iqk_restore(rtwdev, path); ++ _iqk_afebb_restore(rtwdev, phy_idx, path); ++ _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); ++ _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP); ++} ++ ++static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force) ++{ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_A); ++ break; ++ case RF_B: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_B); ++ break; ++ case RF_AB: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_A); ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_B); ++ break; ++ default: ++ break; ++ } ++} ++ ++#define RXDCK_VER_8852A 0xe ++ ++static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, bool is_afe) ++{ ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); ++ u32 ori_val; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RX_DCK] ==== S%d RX DCK (by %s)====\n", ++ path, is_afe ? "AFE" : "RFC"); ++ ++ ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD); ++ ++ if (is_afe) { ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x3); ++ rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13), ++ B_S0_RXDC2_AVG, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); ++ rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK); ++ rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST); ++ rtw89_phy_write32_set(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_CRXBB, 0x1); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); ++ ++ fsleep(600); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_STOP); ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); ++ ++ if (is_afe) { ++ rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ MASKDWORD, ori_val); ++ } ++} ++ ++static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ bool is_afe) ++{ ++ u8 path, kpath, dck_tune; ++ u32 rf_reg5; ++ u32 addr; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n", ++ RXDCK_VER_8852A, rtwdev->hal.cv); ++ ++ kpath = _kpath(rtwdev, phy); ++ ++ for (path = 0; path < 2; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); ++ dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ addr = 0x5818 + (path << 13); ++ /* TSSI pause */ ++ rtw89_phy_write32_set(rtwdev, addr, BIT(30)); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ _set_rx_dck(rtwdev, phy, path, is_afe); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ addr = 0x5818 + (path << 13); ++ /* TSSI resume */ ++ rtw89_phy_write32_clr(rtwdev, addr, BIT(30)); ++ } ++ } ++} ++ ++#define RTW8852A_RF_REL_VERSION 34 ++#define RTW8852A_DPK_VER 0x10 ++#define RTW8852A_DPK_TH_AVG_NUM 4 ++#define RTW8852A_DPK_RF_PATH 2 ++#define RTW8852A_DPK_KIP_REG_NUM 2 ++ ++enum rtw8852a_dpk_id { ++ LBK_RXIQK = 0x06, ++ SYNC = 0x10, ++ MDPK_IDL = 0x11, ++ MDPK_MPA = 0x12, ++ GAIN_LOSS = 0x13, ++ GAIN_CAL = 0x14, ++}; ++ ++static void _rf_direct_cntrl(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_bybb) ++{ ++ if (is_bybb) ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++} ++ ++static void _dpk_onoff(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool off); ++ ++static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, u32 *reg, ++ u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], ++ u8 path) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { ++ reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev, ++ reg[i] + (path << 8), ++ MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", ++ reg[i] + (path << 8), reg_bkup[path][i]); ++ } ++} ++ ++static void _dpk_reload_kip(struct rtw89_dev *rtwdev, u32 *reg, ++ u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { ++ rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), ++ MASKDWORD, reg_bkup[path][i]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n", ++ reg[i] + (path << 8), reg_bkup[path][i]); ++ } ++} ++ ++static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, enum rtw8852a_dpk_id id) ++{ ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); ++ u16 dpk_cmd = 0x0; ++ u32 val; ++ int ret; ++ ++ dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd); ++ rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, ++ 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0); ++ ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_STOP); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] one-shot for %s = 0x%x (ret=%d)\n", ++ id == 0x06 ? "LBK_RXIQK" : ++ id == 0x10 ? "SYNC" : ++ id == 0x11 ? "MDPK_IDL" : ++ id == 0x12 ? "MDPK_MPA" : ++ id == 0x13 ? "GAIN_LOSS" : "PWR_CAL", ++ dpk_cmd, ret); ++ ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] one-shot over 20ms!!!!\n"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void _dpk_rx_dck(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); ++ _set_rx_dck(rtwdev, phy, path, false); ++} ++ ++static void _dpk_information(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ u8 kidx = dpk->cur_idx[path]; ++ ++ dpk->bp[path][kidx].band = hal->current_band_type; ++ dpk->bp[path][kidx].ch = hal->current_channel; ++ dpk->bp[path][kidx].bw = hal->current_band_width; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n", ++ path, dpk->cur_idx[path], phy, ++ rtwdev->is_tssi_mode[path] ? "on" : "off", ++ rtwdev->dbcc_en ? "on" : "off", ++ dpk->bp[path][kidx].band == 0 ? "2G" : ++ dpk->bp[path][kidx].band == 1 ? "5G" : "6G", ++ dpk->bp[path][kidx].ch, ++ dpk->bp[path][kidx].bw == 0 ? "20M" : ++ dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); ++} ++ ++static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kpath) ++{ ++ switch (kpath) { ++ case RF_A: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x0) ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl); ++ break; ++ case RF_B: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x1) ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl); ++ break; ++ case RF_AB: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl); ++ break; ++ default: ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Set BB/AFE for PHY%d (kpath=%d)\n", phy, kpath); ++} ++ ++static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kpath) ++{ ++ switch (kpath) { ++ case RF_A: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl); ++ break; ++ case RF_B: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl); ++ break; ++ case RF_AB: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl); ++ break; ++ default: ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Restore BB/AFE for PHY%d (kpath=%d)\n", phy, kpath); ++} ++ ++static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_pause) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), ++ B_P0_TSSI_TRK_EN, is_pause); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, ++ is_pause ? "pause" : "resume"); ++} ++ ++static void _dpk_kip_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x00093f3f); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG, B_DPK_CFG_IDX, 0x2); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x003f2e2e); ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x005b5b5b); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP setting for S%d[%d]!!\n", ++ path, kidx); ++} ++ ++static void _dpk_kip_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path) ++{ ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); ++ rtw89_phy_write32_clr(rtwdev, R_KIP_CLK, MASKDWORD); ++ ++ if (rtwdev->hal.cv > CHIP_CBV) ++ rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); ++} ++ ++static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ u8 cur_rxbb; ++ ++ cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl); ++ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2); ++ rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, ++ rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK)); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); ++ ++ fsleep(70); ++ ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f); ++ ++ if (cur_rxbb <= 0xa) ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3); ++ else if (cur_rxbb <= 0x10 && cur_rxbb >= 0xb) ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0); ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); ++ ++ _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD)); ++ ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl); ++} ++ ++static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ dpk->bp[path][kidx].ther_dpk = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n", ++ dpk->bp[path][kidx].ther_dpk); ++} ++ ++static u8 _dpk_set_tx_pwr(struct rtw89_dev *rtwdev, u8 gain, ++ enum rtw89_rf_path path) ++{ ++ u8 txagc_ori = 0x38; ++ ++ rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori); ++ ++ return txagc_ori; ++} ++ ++static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); ++ rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0); ++ } else { ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e); ++ rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7); ++ rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3); ++ rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3); ++ } ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); ++ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] RF 0x0/0x1/0x1a = 0x%x/ 0x%x/ 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); ++} ++ ++static void _dpk_manual_txcfir(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_manual) ++{ ++ u8 tmp_pad, tmp_txbb; ++ ++ if (is_manual) { ++ rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1); ++ tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD); ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), ++ B_RFGAIN_PAD, tmp_pad); ++ ++ tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB); ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), ++ B_RFGAIN_TXBB, tmp_txbb); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), ++ B_LOAD_COEF_CFIR, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), ++ B_LOAD_COEF_CFIR); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", tmp_pad, ++ tmp_txbb); ++ } else { ++ rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] disable manual switch TXCFIR\n"); ++ } ++} ++ ++static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_bypass) ++{ ++ if (is_bypass) { ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), ++ B_RXIQC_BYPASS2, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), ++ B_RXIQC_BYPASS, 0x1); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), ++ MASKDWORD)); ++ } else { ++ rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); ++ rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), ++ MASKDWORD)); ++ } ++} ++ ++static ++void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) ++ rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F); ++ else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) ++ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n", ++ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : ++ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); ++} ++ ++static void _dpk_table_select(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx, u8 gain) ++{ ++ u8 val; ++ ++ val = 0x80 + kidx * 0x20 + gain * 0x10; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx, ++ gain, val); ++} ++ ++static bool _dpk_sync_check(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path) ++{ ++#define DPK_SYNC_TH_DC_I 200 ++#define DPK_SYNC_TH_DC_Q 200 ++#define DPK_SYNC_TH_CORR 170 ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u16 dc_i, dc_q; ++ u8 corr_val, corr_idx; ++ ++ rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL); ++ ++ corr_idx = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI); ++ corr_val = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx, ++ corr_val); ++ ++ dpk->corr_idx[path] = corr_idx; ++ dpk->corr_val[path] = corr_val; ++ ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); ++ ++ dc_i = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ dc_q = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ); ++ ++ dc_i = abs(sign_extend32(dc_i, 11)); ++ dc_q = abs(sign_extend32(dc_q, 11)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n", ++ path, dc_i, dc_q); ++ ++ dpk->dc_i[path] = dc_i; ++ dpk->dc_q[path] = dc_q; ++ ++ if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q || ++ corr_val < DPK_SYNC_TH_CORR) ++ return true; ++ else ++ return false; ++} ++ ++static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ _dpk_tpg_sel(rtwdev, path, kidx); ++ _dpk_one_shot(rtwdev, phy, path, SYNC); ++ return _dpk_sync_check(rtwdev, path); /*1= fail*/ ++} ++ ++static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev) ++{ ++ u16 dgain = 0x0; ++ ++ rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL); ++ ++ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_SYNERR); ++ ++ dgain = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain, ++ dgain); ++ ++ return dgain; ++} ++ ++static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain) ++{ ++ s8 offset; ++ ++ if (dgain >= 0x783) ++ offset = 0x6; ++ else if (dgain <= 0x782 && dgain >= 0x551) ++ offset = 0x3; ++ else if (dgain <= 0x550 && dgain >= 0x3c4) ++ offset = 0x0; ++ else if (dgain <= 0x3c3 && dgain >= 0x2aa) ++ offset = -3; ++ else if (dgain <= 0x2a9 && dgain >= 0x1e3) ++ offset = -6; ++ else if (dgain <= 0x1e2 && dgain >= 0x156) ++ offset = -9; ++ else if (dgain <= 0x155) ++ offset = -12; ++ else ++ offset = 0x0; ++ ++ return offset; ++} ++ ++static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); ++ return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL); ++} ++ ++static void _dpk_gainloss(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, enum rtw89_rf_path path, ++ u8 kidx) ++{ ++ _dpk_table_select(rtwdev, path, kidx, 1); ++ _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); ++} ++ ++#define DPK_TXAGC_LOWER 0x2e ++#define DPK_TXAGC_UPPER 0x3f ++#define DPK_TXAGC_INVAL 0xff ++ ++static u8 _dpk_set_offset(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, s8 gain_offset) ++{ ++ u8 txagc; ++ ++ txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK); ++ ++ if (txagc - gain_offset < DPK_TXAGC_LOWER) ++ txagc = DPK_TXAGC_LOWER; ++ else if (txagc - gain_offset > DPK_TXAGC_UPPER) ++ txagc = DPK_TXAGC_UPPER; ++ else ++ txagc = txagc - gain_offset; ++ ++ rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n", ++ gain_offset, txagc); ++ return txagc; ++} ++ ++enum dpk_agc_step { ++ DPK_AGC_STEP_SYNC_DGAIN, ++ DPK_AGC_STEP_GAIN_ADJ, ++ DPK_AGC_STEP_GAIN_LOSS_IDX, ++ DPK_AGC_STEP_GL_GT_CRITERION, ++ DPK_AGC_STEP_GL_LT_CRITERION, ++ DPK_AGC_STEP_SET_TX_GAIN, ++}; ++ ++static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check) ++{ ++ u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; ++ u8 i; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_pas_read_defs_tbl); ++ ++ if (is_check) { ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); ++ val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); ++ val1_i = abs(sign_extend32(val1_i, 11)); ++ val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); ++ val1_q = abs(sign_extend32(val1_q, 11)); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); ++ val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); ++ val2_i = abs(sign_extend32(val2_i, 11)); ++ val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); ++ val2_q = abs(sign_extend32(val2_q, 11)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", ++ (val1_i * val1_i + val1_q * val1_q) / ++ (val2_i * val2_i + val2_q * val2_q)); ++ ++ } else { ++ for (i = 0; i < 32; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] PAS_Read[%02d]= 0x%08x\n", i, ++ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD)); ++ } ++ } ++ if ((val1_i * val1_i + val1_q * val1_q) >= ++ ((val2_i * val2_i + val2_q * val2_q) * 8 / 5)) ++ return 1; ++ else ++ return 0; ++} ++ ++static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx, u8 init_txagc, ++ bool loss_only) ++{ ++#define DPK_AGC_ADJ_LMT 6 ++#define DPK_DGAIN_UPPER 1922 ++#define DPK_DGAIN_LOWER 342 ++#define DPK_RXBB_UPPER 0x1f ++#define DPK_RXBB_LOWER 0 ++#define DPK_GL_CRIT 7 ++ u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0; ++ u8 agc_cnt = 0; ++ bool limited_rxbb = false; ++ s8 offset = 0; ++ u16 dgain = 0; ++ u8 step = DPK_AGC_STEP_SYNC_DGAIN; ++ bool goout = false; ++ ++ tmp_txagc = init_txagc; ++ ++ do { ++ switch (step) { ++ case DPK_AGC_STEP_SYNC_DGAIN: ++ if (_dpk_sync(rtwdev, phy, path, kidx)) { ++ tmp_txagc = DPK_TXAGC_INVAL; ++ goout = true; ++ break; ++ } ++ ++ dgain = _dpk_dgain_read(rtwdev); ++ ++ if (loss_only || limited_rxbb) ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ else ++ step = DPK_AGC_STEP_GAIN_ADJ; ++ break; ++ ++ case DPK_AGC_STEP_GAIN_ADJ: ++ tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); ++ offset = _dpk_dgain_mapping(rtwdev, dgain); ++ ++ if (tmp_rxbb + offset > DPK_RXBB_UPPER) { ++ tmp_rxbb = DPK_RXBB_UPPER; ++ limited_rxbb = true; ++ } else if (tmp_rxbb + offset < DPK_RXBB_LOWER) { ++ tmp_rxbb = DPK_RXBB_LOWER; ++ limited_rxbb = true; ++ } else { ++ tmp_rxbb = tmp_rxbb + offset; ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, ++ tmp_rxbb); ++ if (offset != 0 || agc_cnt == 0) { ++ if (rtwdev->hal.current_band_width < RTW89_CHANNEL_WIDTH_80) ++ _dpk_bypass_rxcfir(rtwdev, path, true); ++ else ++ _dpk_lbk_rxiqk(rtwdev, phy, path); ++ } ++ if (dgain > DPK_DGAIN_UPPER || dgain < DPK_DGAIN_LOWER) ++ step = DPK_AGC_STEP_SYNC_DGAIN; ++ else ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_GAIN_LOSS_IDX: ++ _dpk_gainloss(rtwdev, phy, path, kidx); ++ tmp_gl_idx = _dpk_gainloss_read(rtwdev); ++ ++ if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) || ++ tmp_gl_idx > DPK_GL_CRIT) ++ step = DPK_AGC_STEP_GL_GT_CRITERION; ++ else if (tmp_gl_idx == 0) ++ step = DPK_AGC_STEP_GL_LT_CRITERION; ++ else ++ step = DPK_AGC_STEP_SET_TX_GAIN; ++ break; ++ ++ case DPK_AGC_STEP_GL_GT_CRITERION: ++ if (tmp_txagc == DPK_TXAGC_LOWER) { ++ goout = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc@lower bound!!\n"); ++ } else { ++ tmp_txagc = _dpk_set_offset(rtwdev, path, 3); ++ } ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_GL_LT_CRITERION: ++ if (tmp_txagc == DPK_TXAGC_UPPER) { ++ goout = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc@upper bound!!\n"); ++ } else { ++ tmp_txagc = _dpk_set_offset(rtwdev, path, -2); ++ } ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_SET_TX_GAIN: ++ tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx); ++ goout = true; ++ agc_cnt++; ++ break; ++ ++ default: ++ goout = true; ++ break; ++ } ++ } while (!goout && (agc_cnt < DPK_AGC_ADJ_LMT)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc, ++ tmp_rxbb); ++ ++ return tmp_txagc; ++} ++ ++static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order) ++{ ++ switch (order) { ++ case 0: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1); ++ break; ++ case 1: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN); ++ break; ++ case 2: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Wrong MDPD order!!(0x%x)\n", order); ++ break; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Set MDPD order to 0x%x for IDL\n", order); ++} ++ ++static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx, u8 gain) ++{ ++ _dpk_set_mdpd_para(rtwdev, 0x0); ++ _dpk_table_select(rtwdev, path, kidx, 1); ++ _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); ++} ++ ++static void _dpk_fill_result(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx, u8 gain, ++ u8 txagc) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ u16 pwsf = 0x78; ++ u8 gs = 0x5b; ++ ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc, ++ pwsf, gs); ++ ++ dpk->bp[path][kidx].txagc_dpk = txagc; ++ rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), ++ 0x3F << ((gain << 3) + (kidx << 4)), txagc); ++ ++ dpk->bp[path][kidx].pwsf = pwsf; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x1FF << (gain << 4), pwsf); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD); ++ ++ dpk->bp[path][kidx].gs = gs; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x065b5b5b); ++ ++ rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD); ++ ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL); ++} ++ ++static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ bool is_reload = false; ++ u8 idx, cur_band, cur_ch; ++ ++ cur_band = rtwdev->hal.current_band_type; ++ cur_ch = rtwdev->hal.current_channel; ++ ++ for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { ++ if (cur_band != dpk->bp[path][idx].band || ++ cur_ch != dpk->bp[path][idx].ch) ++ continue; ++ ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_MDPD, idx); ++ dpk->cur_idx[path] = idx; ++ is_reload = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] reload S%d[%d] success\n", path, idx); ++ } ++ ++ return is_reload; ++} ++ ++static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 gain) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u8 txagc = 0, kidx = dpk->cur_idx[path]; ++ bool is_fail = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] ========= S%d[%d] DPK Start =========\n", path, ++ kidx); ++ ++ _rf_direct_cntrl(rtwdev, path, false); ++ txagc = _dpk_set_tx_pwr(rtwdev, gain, path); ++ _dpk_rf_setting(rtwdev, gain, path, kidx); ++ _dpk_rx_dck(rtwdev, phy, path); ++ ++ _dpk_kip_setting(rtwdev, path, kidx); ++ _dpk_manual_txcfir(rtwdev, path, true); ++ txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false); ++ if (txagc == DPK_TXAGC_INVAL) ++ is_fail = true; ++ _dpk_get_thermal(rtwdev, kidx, path); ++ ++ _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ _dpk_fill_result(rtwdev, path, kidx, gain, txagc); ++ _dpk_manual_txcfir(rtwdev, path, false); ++ ++ if (!is_fail) ++ dpk->bp[path][kidx].path_ok = true; ++ else ++ dpk->bp[path][kidx].path_ok = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, ++ is_fail ? "Check" : "Success"); ++ ++ return is_fail; ++} ++ ++static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force, ++ enum rtw89_phy_idx phy, u8 kpath) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u32 backup_bb_val[BACKUP_BB_REGS_NR]; ++ u32 backup_rf_val[RTW8852A_DPK_RF_PATH][BACKUP_RF_REGS_NR]; ++ u32 kip_bkup[RTW8852A_DPK_RF_PATH][RTW8852A_DPK_KIP_REG_NUM] = {{0}}; ++ u32 kip_reg[] = {R_RXIQC, R_IQK_RES}; ++ u8 path; ++ bool is_fail = true, reloaded[RTW8852A_DPK_RF_PATH] = {false}; ++ ++ if (dpk->is_dpk_reload_en) { ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ reloaded[path] = _dpk_reload_check(rtwdev, phy, path); ++ if (!reloaded[path] && dpk->bp[path][0].ch != 0) ++ dpk->cur_idx[path] = !dpk->cur_idx[path]; ++ else ++ _dpk_onoff(rtwdev, path, false); ++ } ++ } else { ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) ++ dpk->cur_idx[path] = 0; ++ } ++ ++ if ((kpath == RF_A && reloaded[RF_PATH_A]) || ++ (kpath == RF_B && reloaded[RF_PATH_B]) || ++ (kpath == RF_AB && reloaded[RF_PATH_A] && reloaded[RF_PATH_B])) ++ return; ++ ++ _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ if (rtwdev->is_tssi_mode[path]) ++ _dpk_tssi_pause(rtwdev, path, true); ++ _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); ++ _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ _dpk_information(rtwdev, phy, path); ++ } ++ ++ _dpk_bb_afe_setting(rtwdev, phy, path, kpath); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ ++ is_fail = _dpk_main(rtwdev, phy, path, 1); ++ _dpk_onoff(rtwdev, path, is_fail); ++ } ++ ++ _dpk_bb_afe_restore(rtwdev, phy, path, kpath); ++ _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ ++ _dpk_kip_restore(rtwdev, path); ++ _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); ++ _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ if (rtwdev->is_tssi_mode[path]) ++ _dpk_tssi_pause(rtwdev, path, false); ++ } ++} ++ ++static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_fem_info *fem = &rtwdev->fem; ++ ++ if (fem->epa_2g && rtwdev->hal.current_band_type == RTW89_BAND_2G) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Skip DPK due to 2G_ext_PA exist!!\n"); ++ return true; ++ } else if (fem->epa_5g && rtwdev->hal.current_band_type == RTW89_BAND_5G) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Skip DPK due to 5G_ext_PA exist!!\n"); ++ return true; ++ } ++ ++ return false; ++} ++ ++static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 path, kpath; ++ ++ kpath = _kpath(rtwdev, phy); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (kpath & BIT(path)) ++ _dpk_onoff(rtwdev, path, true); ++ } ++} ++ ++static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", ++ RTW8852A_DPK_VER, rtwdev->hal.cv, ++ RTW8852A_RF_REL_VERSION); ++ ++ if (_dpk_bypass_check(rtwdev, phy)) ++ _dpk_force_bypass(rtwdev, phy); ++ else ++ _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy)); ++} ++ ++static void _dpk_onoff(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool off) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u8 val, kidx = dpk->cur_idx[path]; ++ ++ val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKBYTE3, 0x6 | val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, ++ kidx, dpk->is_dpk_enable && !off ? "enable" : "disable"); ++} ++ ++static void _dpk_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 path, kidx; ++ u8 trk_idx = 0, txagc_rf = 0; ++ s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0; ++ u16 pwsf[2]; ++ u8 cur_ther; ++ s8 delta_ther[2] = {0}; ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ kidx = dpk->cur_idx[path]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n", ++ path, kidx, dpk->bp[path][kidx].ch); ++ ++ cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] thermal now = %d\n", cur_ther); ++ ++ if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) ++ delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; ++ ++ if (dpk->bp[path][kidx].band == RTW89_BAND_2G) ++ delta_ther[path] = delta_ther[path] * 3 / 2; ++ else ++ delta_ther[path] = delta_ther[path] * 5 / 2; ++ ++ txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), ++ RR_MODOPT_M_TXPWR); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", ++ txagc_rf, trk_idx); ++ ++ txagc_bb = ++ (s8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_BB + (path << 13), ++ MASKBYTE2); ++ txagc_bb_tp = ++ (u8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_TP + (path << 13), ++ B_TXAGC_TP); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", ++ txagc_bb_tp, txagc_bb); ++ ++ txagc_ofst = ++ (s8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_BB + (path << 13), ++ MASKBYTE3); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n", ++ txagc_ofst, delta_ther[path]); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), ++ BIT(15)) == 0x1) ++ txagc_ofst = 0; ++ ++ if (txagc_rf != 0 && cur_ther != 0) ++ ini_diff = txagc_ofst + delta_ther[path]; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13), ++ B_P0_TXDPD) == 0x0) { ++ pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - ++ txagc_bb + ini_diff + ++ tssi_info->extra_ofst[path]; ++ pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - ++ txagc_bb + ini_diff + ++ tssi_info->extra_ofst[path]; ++ } else { ++ pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff + ++ tssi_info->extra_ofst[path]; ++ pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff + ++ tssi_info->extra_ofst[path]; ++ } ++ ++ } else { ++ pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; ++ pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; ++ } ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS) == 0x0 && ++ txagc_rf != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", ++ pwsf[0], pwsf[1]); ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x000001FF, pwsf[0]); ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x01FF0000, pwsf[1]); ++ } ++ } ++} ++ ++static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ if (band == RTW89_BAND_2G) ++ rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); ++} ++ ++static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_sys_defs_tbl); ++ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, ++ &rtw8852a_tssi_sys_defs_2g_tbl, ++ &rtw8852a_tssi_sys_defs_5g_tbl); ++} ++ ++static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl); ++ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_2g_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_5g_tbl); ++} ++ ++static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl); ++} ++ ++static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_dck_defs_a_tbl, ++ &rtw8852a_tssi_dck_defs_b_tbl); ++} ++ ++static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++#define __get_val(ptr, idx) \ ++({ \ ++ s8 *__ptr = (ptr); \ ++ u8 __idx = (idx), __i, __v; \ ++ u32 __val = 0; \ ++ for (__i = 0; __i < 4; __i++) { \ ++ __v = (__ptr[__idx + __i]); \ ++ __val |= (__v << (8 * __i)); \ ++ } \ ++ __val; \ ++}) ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u8 subband = rtwdev->hal.current_subband; ++ const u8 *thm_up_a = NULL; ++ const u8 *thm_down_a = NULL; ++ const u8 *thm_up_b = NULL; ++ const u8 *thm_down_b = NULL; ++ u8 thermal = 0xff; ++ s8 thm_ofst[64] = {0}; ++ u32 tmp = 0; ++ u8 i, j; ++ ++ switch (subband) { ++ case RTW89_CH_2G: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_p; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_n; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_p; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_n; ++ break; ++ case RTW89_CH_5G_BAND_1: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0]; ++ break; ++ case RTW89_CH_5G_BAND_3: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[1]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[1]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[1]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[1]; ++ break; ++ case RTW89_CH_5G_BAND_4: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[2]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[2]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[2]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[2]; ++ break; ++ } ++ ++ if (path == RF_PATH_A) { ++ thermal = tssi_info->thermal[RF_PATH_A]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); ++ ++ if (thermal == 0xff) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32); ++ ++ for (i = 0; i < 64; i += 4) { ++ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x5c00 + i, 0x0); ++ } ++ ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, ++ thermal); ++ ++ i = 0; ++ for (j = 0; j < 32; j++) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ -thm_down_a[i++] : ++ -thm_down_a[DELTA_SWINGIDX_SIZE - 1]; ++ ++ i = 1; ++ for (j = 63; j >= 32; j--) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ thm_up_a[i++] : ++ thm_up_a[DELTA_SWINGIDX_SIZE - 1]; ++ ++ for (i = 0; i < 64; i += 4) { ++ tmp = __get_val(thm_ofst, i); ++ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x5c00 + i, tmp); ++ } ++ } ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); ++ ++ } else { ++ thermal = tssi_info->thermal[RF_PATH_B]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); ++ ++ if (thermal == 0xff) { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32); ++ ++ for (i = 0; i < 64; i += 4) { ++ rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x7c00 + i, 0x0); ++ } ++ ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, ++ thermal); ++ ++ i = 0; ++ for (j = 0; j < 32; j++) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ -thm_down_b[i++] : ++ -thm_down_b[DELTA_SWINGIDX_SIZE - 1]; ++ ++ i = 1; ++ for (j = 63; j >= 32; j--) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ thm_up_b[i++] : ++ thm_up_b[DELTA_SWINGIDX_SIZE - 1]; ++ ++ for (i = 0; i < 64; i += 4) { ++ tmp = __get_val(thm_ofst, i); ++ rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x7c00 + i, tmp); ++ } ++ } ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); ++ } ++#undef __get_val ++} ++ ++static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_dac_gain_tbl_defs_a_tbl, ++ &rtw8852a_tssi_dac_gain_tbl_defs_b_tbl); ++} ++ ++static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_slope_cal_org_defs_a_tbl, ++ &rtw8852a_tssi_slope_cal_org_defs_b_tbl); ++} ++ ++static void _tssi_set_rf_gap_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_rf_gap_tbl_defs_a_tbl, ++ &rtw8852a_tssi_rf_gap_tbl_defs_b_tbl); ++} ++ ++static void _tssi_set_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_slope_defs_a_tbl, ++ &rtw8852a_tssi_slope_defs_b_tbl); ++} ++ ++static void _tssi_set_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_track_defs_a_tbl, ++ &rtw8852a_tssi_track_defs_b_tbl); ++} ++ ++static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl, ++ &rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl); ++} ++ ++static void _tssi_pak(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ u8 subband = rtwdev->hal.current_subband; ++ ++ switch (subband) { ++ case RTW89_CH_2G: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_2g_tbl, ++ &rtw8852a_tssi_pak_defs_b_2g_tbl); ++ break; ++ case RTW89_CH_5G_BAND_1: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_1_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_1_tbl); ++ break; ++ case RTW89_CH_5G_BAND_3: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_3_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_3_tbl); ++ break; ++ case RTW89_CH_5G_BAND_4: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_4_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_4_tbl); ++ break; ++ } ++} ++ ++static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_set_track(rtwdev, phy, i); ++ _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, i == RF_PATH_A, ++ &rtw8852a_tssi_enable_defs_a_tbl, ++ &rtw8852a_tssi_enable_defs_b_tbl); ++ ++ tssi_info->base_thermal[i] = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[i]); ++ rtwdev->is_tssi_mode[i] = true; ++ } ++} ++ ++static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl); ++ ++ rtwdev->is_tssi_mode[RF_PATH_A] = false; ++ rtwdev->is_tssi_mode[RF_PATH_B] = false; ++} ++ ++static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 2: ++ return 0; ++ case 3 ... 5: ++ return 1; ++ case 6 ... 8: ++ return 2; ++ case 9 ... 11: ++ return 3; ++ case 12 ... 13: ++ return 4; ++ case 14: ++ return 5; ++ } ++ ++ return 0; ++} ++ ++#define TSSI_EXTRA_GROUP_BIT (BIT(31)) ++#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx)) ++#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT) ++#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT) ++#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) ++ ++static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 2: ++ return 0; ++ case 3 ... 5: ++ return 1; ++ case 6 ... 8: ++ return 2; ++ case 9 ... 11: ++ return 3; ++ case 12 ... 14: ++ return 4; ++ case 36 ... 40: ++ return 5; ++ case 41 ... 43: ++ return TSSI_EXTRA_GROUP(5); ++ case 44 ... 48: ++ return 6; ++ case 49 ... 51: ++ return TSSI_EXTRA_GROUP(6); ++ case 52 ... 56: ++ return 7; ++ case 57 ... 59: ++ return TSSI_EXTRA_GROUP(7); ++ case 60 ... 64: ++ return 8; ++ case 100 ... 104: ++ return 9; ++ case 105 ... 107: ++ return TSSI_EXTRA_GROUP(9); ++ case 108 ... 112: ++ return 10; ++ case 113 ... 115: ++ return TSSI_EXTRA_GROUP(10); ++ case 116 ... 120: ++ return 11; ++ case 121 ... 123: ++ return TSSI_EXTRA_GROUP(11); ++ case 124 ... 128: ++ return 12; ++ case 129 ... 131: ++ return TSSI_EXTRA_GROUP(12); ++ case 132 ... 136: ++ return 13; ++ case 137 ... 139: ++ return TSSI_EXTRA_GROUP(13); ++ case 140 ... 144: ++ return 14; ++ case 149 ... 153: ++ return 15; ++ case 154 ... 156: ++ return TSSI_EXTRA_GROUP(15); ++ case 157 ... 161: ++ return 16; ++ case 162 ... 164: ++ return TSSI_EXTRA_GROUP(16); ++ case 165 ... 169: ++ return 17; ++ case 170 ... 172: ++ return TSSI_EXTRA_GROUP(17); ++ case 173 ... 177: ++ return 18; ++ } ++ ++ return 0; ++} ++ ++static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 8: ++ return 0; ++ case 9 ... 14: ++ return 1; ++ case 36 ... 48: ++ return 2; ++ case 52 ... 64: ++ return 3; ++ case 100 ... 112: ++ return 4; ++ case 116 ... 128: ++ return 5; ++ case 132 ... 144: ++ return 6; ++ case 149 ... 177: ++ return 7; ++ } ++ ++ return 0; ++} ++ ++static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u32 gidx, gidx_1st, gidx_2nd; ++ s8 de_1st = 0; ++ s8 de_2nd = 0; ++ s8 val; ++ ++ gidx = _tssi_get_ofdm_group(rtwdev, ch); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", ++ path, gidx); ++ ++ if (IS_TSSI_EXTRA_GROUP(gidx)) { ++ gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx); ++ gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx); ++ de_1st = tssi_info->tssi_mcs[path][gidx_1st]; ++ de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; ++ val = (de_1st + de_2nd) / 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", ++ path, val, de_1st, de_2nd); ++ } else { ++ val = tssi_info->tssi_mcs[path][gidx]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); ++ } ++ ++ return val; ++} ++ ++static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u32 tgidx, tgidx_1st, tgidx_2nd; ++ s8 tde_1st = 0; ++ s8 tde_2nd = 0; ++ s8 val; ++ ++ tgidx = _tssi_get_trim_group(rtwdev, ch); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", ++ path, tgidx); ++ ++ if (IS_TSSI_EXTRA_GROUP(tgidx)) { ++ tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx); ++ tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx); ++ tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; ++ tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; ++ val = (tde_1st + tde_2nd) / 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", ++ path, val, tde_1st, tde_2nd); ++ } else { ++ val = tssi_info->tssi_trim[path][tgidx]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", ++ path, val); ++ } ++ ++ return val; ++} ++ ++static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy) ++{ ++#define __DE_MASK 0x003ff000 ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ static const u32 r_cck_long[RF_PATH_NUM_8852A] = {0x5858, 0x7858}; ++ static const u32 r_cck_short[RF_PATH_NUM_8852A] = {0x5860, 0x7860}; ++ static const u32 r_mcs_20m[RF_PATH_NUM_8852A] = {0x5838, 0x7838}; ++ static const u32 r_mcs_40m[RF_PATH_NUM_8852A] = {0x5840, 0x7840}; ++ static const u32 r_mcs_80m[RF_PATH_NUM_8852A] = {0x5848, 0x7848}; ++ static const u32 r_mcs_80m_80m[RF_PATH_NUM_8852A] = {0x5850, 0x7850}; ++ static const u32 r_mcs_5m[RF_PATH_NUM_8852A] = {0x5828, 0x7828}; ++ static const u32 r_mcs_10m[RF_PATH_NUM_8852A] = {0x5830, 0x7830}; ++ u8 ch = rtwdev->hal.current_channel; ++ u8 i, gidx; ++ s8 ofdm_de; ++ s8 trim_de; ++ s32 val; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", ++ phy, ch); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ gidx = _tssi_get_cck_group(rtwdev, ch); ++ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); ++ val = tssi_info->tssi_cck[i][gidx] + trim_de; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", ++ i, gidx, tssi_info->tssi_cck[i][gidx], trim_de); ++ ++ rtw89_phy_write32_mask(rtwdev, r_cck_long[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_cck_short[i], __DE_MASK, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", ++ r_cck_long[i], ++ rtw89_phy_read32_mask(rtwdev, r_cck_long[i], ++ __DE_MASK)); ++ ++ ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i); ++ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); ++ val = ofdm_de + trim_de; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", ++ i, ofdm_de, trim_de); ++ ++ rtw89_phy_write32_mask(rtwdev, r_mcs_20m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_40m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_80m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_80m_80m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_5m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_10m[i], __DE_MASK, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", ++ r_mcs_20m[i], ++ rtw89_phy_read32_mask(rtwdev, r_mcs_20m[i], ++ __DE_MASK)); ++ } ++#undef __DE_MASK ++} ++ ++static void _tssi_track(struct rtw89_dev *rtwdev) ++{ ++ static const u32 tx_gain_scale_table[] = { ++ 0x400, 0x40e, 0x41d, 0x427, 0x43c, 0x44c, 0x45c, 0x46c, ++ 0x400, 0x39d, 0x3ab, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f1 ++ }; ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 path; ++ u8 cur_ther; ++ s32 delta_ther = 0, gain_offset_int, gain_offset_float; ++ s8 gain_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] %s:\n", ++ __func__); ++ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A]) ++ return; ++ if (!rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) { ++ if (!tssi_info->tssi_tracking_check[path]) { ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] return!!!\n"); ++ continue; ++ } ++ ++ cur_ther = (u8)rtw89_phy_read32_mask(rtwdev, ++ R_TSSI_THER + (path << 13), ++ B_TSSI_THER); ++ ++ if (cur_ther == 0 || tssi_info->base_thermal[path] == 0) ++ continue; ++ ++ delta_ther = cur_ther - tssi_info->base_thermal[path]; ++ ++ gain_offset = (s8)delta_ther * 15 / 10; ++ ++ tssi_info->extra_ofst[path] = gain_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n", ++ tssi_info->base_thermal[path], gain_offset, path); ++ ++ gain_offset_int = gain_offset >> 3; ++ gain_offset_float = gain_offset & 7; ++ ++ if (gain_offset_int > 15) ++ gain_offset_int = 15; ++ else if (gain_offset_int < -16) ++ gain_offset_int = -16; ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13), ++ B_DPD_OFT_EN, 0x1); ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), ++ B_TXGAIN_SCALE_EN, 0x1); ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13), ++ B_DPD_OFT_ADDR, gain_offset_int); ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), ++ B_TXGAIN_SCALE_OFT, ++ tx_gain_scale_table[gain_offset_float]); ++ } ++} ++ ++static void _tssi_high_power(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel, ch_tmp; ++ u8 bw = rtwdev->hal.current_band_width; ++ u8 subband = rtwdev->hal.current_subband; ++ s8 power; ++ s32 xdbm; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_40) ++ ch_tmp = ch - 2; ++ else if (bw == RTW89_CHANNEL_WIDTH_80) ++ ch_tmp = ch - 6; ++ else ++ ch_tmp = ch; ++ ++ power = rtw89_phy_read_txpwr_limit(rtwdev, bw, RTW89_1TX, ++ RTW89_RS_MCS, RTW89_NONBF, ch_tmp); ++ ++ xdbm = power * 100 / 4; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d xdbm=%d\n", ++ __func__, phy, xdbm); ++ ++ if (xdbm > 1800 && subband == RTW89_CH_2G) { ++ tssi_info->tssi_tracking_check[RF_PATH_A] = true; ++ tssi_info->tssi_tracking_check[RF_PATH_B] = true; ++ } else { ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_tracking_defs_tbl); ++ tssi_info->extra_ofst[RF_PATH_A] = 0; ++ tssi_info->extra_ofst[RF_PATH_B] = 0; ++ tssi_info->tssi_tracking_check[RF_PATH_A] = false; ++ tssi_info->tssi_tracking_check[RF_PATH_B] = false; ++ } ++} ++ ++static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ u8 path, s16 pwr_dbm, u8 enable) ++{ ++ rtw8852a_bb_set_plcp_tx(rtwdev); ++ rtw8852a_bb_cfg_tx_path(rtwdev, path); ++ rtw8852a_bb_set_power(rtwdev, pwr_dbm, phy); ++ rtw8852a_bb_set_pmac_pkt_tx(rtwdev, enable, 20, 5000, 0, phy); ++} ++ ++static void _tssi_pre_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ const struct rtw89_chip_info *mac_reg = rtwdev->chip; ++ u8 ch = rtwdev->hal.current_channel, ch_tmp; ++ u8 bw = rtwdev->hal.current_band_width; ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy, 0); ++ s8 power; ++ s16 xdbm; ++ u32 i, tx_counter = 0; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_40) ++ ch_tmp = ch - 2; ++ else if (bw == RTW89_CHANNEL_WIDTH_80) ++ ch_tmp = ch - 6; ++ else ++ ch_tmp = ch; ++ ++ power = rtw89_phy_read_txpwr_limit(rtwdev, RTW89_CHANNEL_WIDTH_20, RTW89_1TX, ++ RTW89_RS_OFDM, RTW89_NONBF, ch_tmp); ++ ++ xdbm = (power * 100) >> mac_reg->txpwr_factor_mac; ++ ++ if (xdbm > 1800) ++ xdbm = 68; ++ else ++ xdbm = power * 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] %s: phy=%d org_power=%d xdbm=%d\n", ++ __func__, phy, power, xdbm); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy)); ++ tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD); ++ ++ _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, true); ++ mdelay(15); ++ _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, false); ++ ++ tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD) - ++ tx_counter; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_A] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, ++ MASKBYTE3); ++ ++ if (tssi_info->default_txagc_offset[RF_PATH_A] != 0x0) ++ break; ++ } ++ } ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_B] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, ++ MASKBYTE3); ++ ++ if (tssi_info->default_txagc_offset[RF_PATH_B] != 0x0) ++ break; ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] %s: tx counter=%d\n", ++ __func__, tx_counter); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Backup R_TXAGC_BB=0x%x R_TXAGC_BB_S1=0x%x\n", ++ tssi_info->default_txagc_offset[RF_PATH_A], ++ tssi_info->default_txagc_offset[RF_PATH_B]); ++ ++ rtw8852a_bb_tx_mode_switch(rtwdev, phy, 0); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_rck(struct rtw89_dev *rtwdev) ++{ ++ u8 path; ++ ++ for (path = 0; path < 2; path++) ++ _rck(rtwdev, path); ++} ++ ++void rtw8852a_dack(struct rtw89_dev *rtwdev) ++{ ++ u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START); ++ _dac_cal(rtwdev, false); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ _iqk_init(rtwdev); ++ if (rtwdev->dbcc_en) ++ _iqk_dbcc(rtwdev, phy_idx); ++ else ++ _iqk(rtwdev, phy_idx, false); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_iqk_track(struct rtw89_dev *rtwdev) ++{ ++ _iqk_track(rtwdev); ++} ++ ++void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ bool is_afe) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ _rx_dck(rtwdev, phy_idx, is_afe); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ rtwdev->dpk.is_dpk_enable = true; ++ rtwdev->dpk.is_dpk_reload_en = false; ++ _dpk(rtwdev, phy_idx, false); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_dpk_track(struct rtw89_dev *rtwdev) ++{ ++ _dpk_track(rtwdev); ++} ++ ++void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", ++ __func__, phy); ++ ++ _tssi_disable(rtwdev, phy); ++ ++ for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_rf_setting(rtwdev, phy, i); ++ _tssi_set_sys(rtwdev, phy); ++ _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i); ++ _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i); ++ _tssi_set_dck(rtwdev, phy, i); ++ _tssi_set_tmeter_tbl(rtwdev, phy, i); ++ _tssi_set_dac_gain_tbl(rtwdev, phy, i); ++ _tssi_slope_cal_org(rtwdev, phy, i); ++ _tssi_set_rf_gap_tbl(rtwdev, phy, i); ++ _tssi_set_slope(rtwdev, phy, i); ++ _tssi_pak(rtwdev, phy, i); ++ } ++ ++ _tssi_enable(rtwdev, phy); ++ _tssi_set_efuse_to_de(rtwdev, phy); ++ _tssi_high_power(rtwdev, phy); ++ _tssi_pre_tx(rtwdev, phy); ++} ++ ++void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", ++ __func__, phy); ++ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A]) ++ return; ++ if (!rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ _tssi_disable(rtwdev, phy); ++ ++ for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_rf_setting(rtwdev, phy, i); ++ _tssi_set_sys(rtwdev, phy); ++ _tssi_set_tmeter_tbl(rtwdev, phy, i); ++ _tssi_pak(rtwdev, phy, i); ++ } ++ ++ _tssi_enable(rtwdev, phy); ++ _tssi_set_efuse_to_de(rtwdev, phy); ++} ++ ++void rtw8852a_tssi_track(struct rtw89_dev *rtwdev) ++{ ++ _tssi_track(rtwdev); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h +new file mode 100644 +index 000000000000..a6da27fd6eb9 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_RFK_H__ ++#define __RTW89_8852A_RFK_H__ ++ ++#include "core.h" ++ ++void rtw8852a_rck(struct rtw89_dev *rtwdev); ++void rtw8852a_dack(struct rtw89_dev *rtwdev); ++void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); ++void rtw8852a_iqk_track(struct rtw89_dev *rtwdev); ++void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ bool is_afe); ++void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_dpk_track(struct rtw89_dev *rtwdev); ++void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_tssi_track(struct rtw89_dev *rtwdev); ++ ++#endif + +From patchwork Fri Aug 20 04:35:29 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448389 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 361B9C4320E + for ; + Fri, 20 Aug 2021 04:37:28 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 0C7F860F91 + for ; + Fri, 20 Aug 2021 04:37:28 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233148AbhHTEiE (ORCPT + ); + Fri, 20 Aug 2021 00:38:04 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39270 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232848AbhHTEiD (ORCPT + ); + Fri, 20 Aug 2021 00:38:03 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bLfF5004140, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bLfF5004140 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:21 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:21 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:20 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 15/24] rtw89: 8852a: add 8852a RFK tables +Date: Fri, 20 Aug 2021 12:35:29 +0800 +Message-ID: <20210820043538.12424-16-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +RFK tables are used by RFK functions implemented by rtw8852a_rfk.c. + +Signed-off-by: Ping-Ke Shih +--- + .../realtek/rtw89/rtw8852a_rfk_table.c | 1596 +++++++++++++++++ + .../realtek/rtw89/rtw8852a_rfk_table.h | 132 ++ + 2 files changed, 1728 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c +new file mode 100644 +index 000000000000..91c0fadef76c +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c +@@ -0,0 +1,1596 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "rtw8852a_rfk_table.h" ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs[] = { ++ DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), ++ DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), ++ DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x32bc, 0x000000f0, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x00000f00, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x000f0000, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x0000f000, 0x00000005), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x0300, 0xff000000, 0x00000019), ++ DECL_RFK_WM(0x0304, 0x000000ff, 0x00000019), ++ DECL_RFK_WM(0x0304, 0x0000ff00, 0x0000001d), ++ DECL_RFK_WM(0x0314, 0xffff0000, 0x00002044), ++ DECL_RFK_WM(0x0318, 0x0000ffff, 0x00002042), ++ DECL_RFK_WM(0x0318, 0xffff0000, 0x00002002), ++ DECL_RFK_WM(0x0020, 0x00006000, 0x00000003), ++ DECL_RFK_WM(0x0024, 0x00006000, 0x00000003), ++ DECL_RFK_WM(0x0704, 0xffff0000, 0x0000601e), ++ DECL_RFK_WM(0x2704, 0xffff0000, 0x0000601e), ++ DECL_RFK_WM(0x0700, 0xf0000000, 0x00000004), ++ DECL_RFK_WM(0x2700, 0xf0000000, 0x00000004), ++ DECL_RFK_WM(0x0650, 0x3c000000, 0x00000000), ++ DECL_RFK_WM(0x2650, 0x3c000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_2g[] = { ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_5g[] = { ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000044), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000044), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000044), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000044), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_5g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_a[] = { ++ DECL_RFK_WM(0x5800, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x5800, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x5800, 0x003f0000, 0x0000003f), ++ DECL_RFK_WM(0x5800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5800, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5800, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x5804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x580c, 0x0000007f, 0x00000040), ++ DECL_RFK_WM(0x580c, 0x00007f00, 0x00000040), ++ DECL_RFK_WM(0x580c, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x0000fc00, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x00010000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x00fe0000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x06000000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x38000000, 0x00000003), ++ DECL_RFK_WM(0x5810, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000c00, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00002000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x5814, 0x003c0000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x01c00000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0xe0000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x0001ff00, 0x00000018), ++ DECL_RFK_WM(0x5818, 0x03fe0000, 0x00000016), ++ DECL_RFK_WM(0x5818, 0xfc000000, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x01e00000, 0x00000008), ++ DECL_RFK_WM(0x581c, 0x01e00000, 0x0000000e), ++ DECL_RFK_WM(0x581c, 0x1e000000, 0x00000008), ++ DECL_RFK_WM(0x581c, 0x1e000000, 0x0000000e), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x5820, 0x0000f000, 0x0000000f), ++ DECL_RFK_WM(0x5820, 0x001f0000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0xffe00000, 0x00000000), ++ DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x5864, 0x03f00000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58a0, 0x000000ff, 0x000000fd), ++ DECL_RFK_WM(0x58a0, 0x0000ff00, 0x000000e5), ++ DECL_RFK_WM(0x58a0, 0x00ff0000, 0x000000cd), ++ DECL_RFK_WM(0x58a0, 0xff000000, 0x000000b5), ++ DECL_RFK_WM(0x58a4, 0x000000ff, 0x00000016), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x0000001f, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x00000020, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x000001c0, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x0000f000, 0x00000002), ++ DECL_RFK_WM(0x58b4, 0x00ff0000, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x58bc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x58bc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x58bc, 0x00030000, 0x00000003), ++ DECL_RFK_WM(0x58bc, 0x000c0000, 0x00000001), ++ DECL_RFK_WM(0x58bc, 0x00300000, 0x00000002), ++ DECL_RFK_WM(0x58bc, 0x00c00000, 0x00000002), ++ DECL_RFK_WM(0x58bc, 0x07000000, 0x00000007), ++ DECL_RFK_WM(0x58c0, 0x00fe0000, 0x0000003f), ++ DECL_RFK_WM(0x58c0, 0xff000000, 0x00000000), ++ DECL_RFK_WM(0x58c4, 0x0003ffff, 0x0003ffff), ++ DECL_RFK_WM(0x58c4, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x58c4, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x00ffffff, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0xf0000000, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58d0, 0x00001fff, 0x00000101), ++ DECL_RFK_WM(0x58d0, 0x0001e000, 0x00000004), ++ DECL_RFK_WM(0x58d0, 0x03fe0000, 0x00000100), ++ DECL_RFK_WM(0x58d0, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x58d4, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x58d4, 0x0003fe00, 0x000000ff), ++ DECL_RFK_WM(0x58d4, 0x07fc0000, 0x00000100), ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x58d8, 0x0003fe00, 0x0000005c), ++ DECL_RFK_WM(0x58d8, 0x000c0000, 0x00000002), ++ DECL_RFK_WM(0x58d8, 0xfff00000, 0x00000800), ++ DECL_RFK_WM(0x58dc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x58dc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x58dc, 0x00010000, 0x00000000), ++ DECL_RFK_WM(0x58dc, 0x3ff00000, 0x00000000), ++ DECL_RFK_WM(0x58dc, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x58f0, 0x000001ff, 0x000001ff), ++ DECL_RFK_WM(0x58f0, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_b[] = { ++ DECL_RFK_WM(0x7800, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x7800, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x7800, 0x003f0000, 0x0000003f), ++ DECL_RFK_WM(0x7800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7800, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7800, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x7804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x780c, 0x0000007f, 0x00000040), ++ DECL_RFK_WM(0x780c, 0x00007f00, 0x00000040), ++ DECL_RFK_WM(0x780c, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x0000fc00, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x00010000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x00fe0000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x06000000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x38000000, 0x00000003), ++ DECL_RFK_WM(0x7810, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000c00, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00002000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x7814, 0x003c0000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x01c00000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0xe0000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x0001ff00, 0x00000018), ++ DECL_RFK_WM(0x7818, 0x03fe0000, 0x00000016), ++ DECL_RFK_WM(0x7818, 0xfc000000, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x01e00000, 0x00000008), ++ DECL_RFK_WM(0x781c, 0x01e00000, 0x0000000e), ++ DECL_RFK_WM(0x781c, 0x1e000000, 0x00000008), ++ DECL_RFK_WM(0x781c, 0x1e000000, 0x0000000e), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x7820, 0x0000f000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x001f0000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0xffe00000, 0x00000000), ++ DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x7864, 0x03f00000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78a0, 0x000000ff, 0x000000fd), ++ DECL_RFK_WM(0x78a0, 0x0000ff00, 0x000000e5), ++ DECL_RFK_WM(0x78a0, 0x00ff0000, 0x000000cd), ++ DECL_RFK_WM(0x78a0, 0xff000000, 0x000000b5), ++ DECL_RFK_WM(0x78a4, 0x000000ff, 0x00000016), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x0000001f, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x00000020, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x000001c0, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x0000f000, 0x00000002), ++ DECL_RFK_WM(0x78b4, 0x00ff0000, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x78bc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x78bc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x78bc, 0x00030000, 0x00000003), ++ DECL_RFK_WM(0x78bc, 0x000c0000, 0x00000001), ++ DECL_RFK_WM(0x78bc, 0x00300000, 0x00000002), ++ DECL_RFK_WM(0x78bc, 0x00c00000, 0x00000002), ++ DECL_RFK_WM(0x78bc, 0x07000000, 0x00000007), ++ DECL_RFK_WM(0x78c0, 0x00fe0000, 0x0000003f), ++ DECL_RFK_WM(0x78c0, 0xff000000, 0x00000000), ++ DECL_RFK_WM(0x78c4, 0x0003ffff, 0x0003ffff), ++ DECL_RFK_WM(0x78c4, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x78c4, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x00ffffff, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0xf0000000, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78d0, 0x00001fff, 0x00000101), ++ DECL_RFK_WM(0x78d0, 0x0001e000, 0x00000004), ++ DECL_RFK_WM(0x78d0, 0x03fe0000, 0x00000100), ++ DECL_RFK_WM(0x78d0, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x78d4, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x78d4, 0x0003fe00, 0x000000ff), ++ DECL_RFK_WM(0x78d4, 0x07fc0000, 0x00000100), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x78d8, 0x0003fe00, 0x0000005c), ++ DECL_RFK_WM(0x78d8, 0x000c0000, 0x00000002), ++ DECL_RFK_WM(0x78d8, 0xfff00000, 0x00000800), ++ DECL_RFK_WM(0x78dc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x78dc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x78dc, 0x00010000, 0x00000000), ++ DECL_RFK_WM(0x78dc, 0x3ff00000, 0x00000000), ++ DECL_RFK_WM(0x78dc, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x78f0, 0x000001ff, 0x000001ff), ++ DECL_RFK_WM(0x78f0, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_2g[] = { ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000013c), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000013c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_5g[] = { ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000016c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_5g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a[] = { ++ DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fc), ++ DECL_RFK_WM(0x58e4, 0x0000007f, 0x00000020), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b[] = { ++ DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fc), ++ DECL_RFK_WM(0x78e4, 0x0000007f, 0x00000020), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_a[] = { ++ DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00002000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x5814, 0x003c0000, 0x00000003), ++ DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_b[] = { ++ DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00002000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x7814, 0x003c0000, 0x00000003), ++ DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_a[] = { ++ DECL_RFK_WM(0x58b0, 0x00000fff, 0x00000000), ++ DECL_RFK_WM(0x58b0, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_b[] = { ++ DECL_RFK_WM(0x78b0, 0x00000fff, 0x00000000), ++ DECL_RFK_WM(0x78b0, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_a[] = { ++ DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x58cc, 0x00000007, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0x00000038, 0x00000001), ++ DECL_RFK_WM(0x58cc, 0x000001c0, 0x00000002), ++ DECL_RFK_WM(0x58cc, 0x00000e00, 0x00000003), ++ DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0xff000000, 0x00000040), ++ DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0xff000000, 0x00000040), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_b[] = { ++ DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x78cc, 0x00000007, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0x00000038, 0x00000001), ++ DECL_RFK_WM(0x78cc, 0x000001c0, 0x00000002), ++ DECL_RFK_WM(0x78cc, 0x00000e00, 0x00000003), ++ DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0xff000000, 0x00000040), ++ DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x7878, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0xff000000, 0x00000040), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_a[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_b[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_a[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x5820, 0x0000f000, 0x00000001), ++ DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x5810, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x580c, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x580c, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_b[] = { ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x0000f000, 0x00000001), ++ DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x7810, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x780c, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x780c, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_a[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000800, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x5814, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_b[] = { ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000800, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x7814, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_a[] = { ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x000f0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_b[] = { ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x000f0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_2g[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d0), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001e8), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x0000000b), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000088), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_1[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d7), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fb), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000005), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x0000007c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_1); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_3[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d8), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fc), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000006), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000078), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_3); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_4[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001e5), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x0000000a), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000011), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000075), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_4); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_2g[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001cc), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001e2), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000005), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000089), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_1[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001d5), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001fc), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000005), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000079), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_1); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_3[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001dc), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000002), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000000b), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000076), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_3); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_4[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001f0), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000016), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000001f), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000072), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_4); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_a[] = { ++ DECL_RFK_WRF(0x0, 0x55, 0x00080, 0x00001), ++ DECL_RFK_WM(0x5818, 0x000000ff, 0x000000c0), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_b[] = { ++ DECL_RFK_WRF(0x1, 0x55, 0x00080, 0x00001), ++ DECL_RFK_WM(0x7818, 0x000000ff, 0x000000c0), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_disable_defs[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_disable_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_tracking_defs[] = { ++ DECL_RFK_WM(0x5800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x5804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x58f0, 0xfff00000, 0x00000400), ++ DECL_RFK_WM(0x7800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x7804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0xfff00000, 0x00000400), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_tracking_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_afe_init_defs[] = { ++ DECL_RFK_WC(0x12ec, 0x00008000), ++ DECL_RFK_WS(0x12ec, 0x00008000), ++ DECL_RFK_WC(0x5e00, 0x00000001), ++ DECL_RFK_WS(0x5e00, 0x00000001), ++ DECL_RFK_WC(0x32ec, 0x00008000), ++ DECL_RFK_WS(0x32ec, 0x00008000), ++ DECL_RFK_WC(0x7e00, 0x00000001), ++ DECL_RFK_WS(0x7e00, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_afe_init_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_a[] = { ++ DECL_RFK_WS(0x5e00, 0x00000008), ++ DECL_RFK_WS(0x5e50, 0x00000008), ++ DECL_RFK_WS(0x5e10, 0x80000000), ++ DECL_RFK_WS(0x5e60, 0x80000000), ++ DECL_RFK_WC(0x5e00, 0x00000008), ++ DECL_RFK_WC(0x5e50, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_b[] = { ++ DECL_RFK_WS(0x7e00, 0x00000008), ++ DECL_RFK_WS(0x7e50, 0x00000008), ++ DECL_RFK_WS(0x7e10, 0x80000000), ++ DECL_RFK_WS(0x7e60, 0x80000000), ++ DECL_RFK_WC(0x7e00, 0x00000008), ++ DECL_RFK_WC(0x7e50, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_a[] = { ++ DECL_RFK_WC(0x20f4, 0x01000000), ++ DECL_RFK_WS(0x20f8, 0x80000000), ++ DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), ++ DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), ++ DECL_RFK_WC(0x20f0, 0x0000000f), ++ DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000002), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_b[] = { ++ DECL_RFK_WC(0x20f4, 0x01000000), ++ DECL_RFK_WS(0x20f8, 0x80000000), ++ DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), ++ DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), ++ DECL_RFK_WC(0x20f0, 0x0000000f), ++ DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_a[] = { ++ DECL_RFK_WC(0x12d8, 0x00000030), ++ DECL_RFK_WC(0x32d8, 0x00000030), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x00400000), ++ DECL_RFK_WS(0x032c, 0x00400000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x12dc, 0x00000002), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_a[] = { ++ DECL_RFK_WS(0x12d8, 0x000000c0), ++ DECL_RFK_WS(0x12d8, 0x00000800), ++ DECL_RFK_WC(0x12d8, 0x00000800), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x12d8, 0x00000300, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_a[] = { ++ DECL_RFK_WC(0x12dc, 0x00000002), ++ DECL_RFK_WS(0x032c, 0x00010000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), ++ DECL_RFK_WS(0x032c, 0x40000000), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_b[] = { ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x00400000), ++ DECL_RFK_WS(0x032c, 0x00400000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x32dc, 0x00000002), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_b[] = { ++ DECL_RFK_WS(0x32d8, 0x000000c0), ++ DECL_RFK_WS(0x32d8, 0x00000800), ++ DECL_RFK_WC(0x32d8, 0x00000800), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x32d8, 0x00000300, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_b[] = { ++ DECL_RFK_WC(0x32dc, 0x00000002), ++ DECL_RFK_WS(0x032c, 0x00010000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), ++ DECL_RFK_WS(0x032c, 0x40000000), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_a[] = { ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x12dc, 0x00000001), ++ DECL_RFK_WS(0x12e8, 0x00000004), ++ DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_b[] = { ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x32dc, 0x00000001), ++ DECL_RFK_WS(0x32e8, 0x00000004), ++ DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_a[] = { ++ DECL_RFK_WC(0x12dc, 0x00000001), ++ DECL_RFK_WC(0x12e8, 0x00000004), ++ DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00000), ++ DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_b[] = { ++ DECL_RFK_WC(0x32dc, 0x00000001), ++ DECL_RFK_WC(0x32e8, 0x00000004), ++ DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00000), ++ DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_a[] = { ++ DECL_RFK_WS(0x5e00, 0x00000008), ++ DECL_RFK_WC(0x5e10, 0x80000000), ++ DECL_RFK_WS(0x5e50, 0x00000008), ++ DECL_RFK_WC(0x5e60, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000003), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x10000000), ++ DECL_RFK_WC(0x032c, 0x80000000), ++ DECL_RFK_WS(0x12e0, 0x00010000), ++ DECL_RFK_WS(0x12e4, 0x0c000000), ++ DECL_RFK_WM(0x5e00, 0x03ff0000, 0x00000030), ++ DECL_RFK_WM(0x5e50, 0x03ff0000, 0x00000030), ++ DECL_RFK_WC(0x5e00, 0x0c000000), ++ DECL_RFK_WC(0x5e50, 0x0c000000), ++ DECL_RFK_WC(0x5e0c, 0x00000008), ++ DECL_RFK_WC(0x5e5c, 0x00000008), ++ DECL_RFK_WS(0x5e0c, 0x00000001), ++ DECL_RFK_WS(0x5e5c, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_a[] = { ++ DECL_RFK_WC(0x12e4, 0x0c000000), ++ DECL_RFK_WS(0x5e0c, 0x00000008), ++ DECL_RFK_WS(0x5e5c, 0x00000008), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_a[] = { ++ DECL_RFK_WC(0x5e0c, 0x00000001), ++ DECL_RFK_WC(0x5e5c, 0x00000001), ++ DECL_RFK_WC(0x12e0, 0x00010000), ++ DECL_RFK_WC(0x12a0, 0x00008000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_b[] = { ++ DECL_RFK_WS(0x7e00, 0x00000008), ++ DECL_RFK_WC(0x7e10, 0x80000000), ++ DECL_RFK_WS(0x7e50, 0x00000008), ++ DECL_RFK_WC(0x7e60, 0x80000000), ++ DECL_RFK_WS(0x32a0, 0x00008000), ++ DECL_RFK_WM(0x32a0, 0x00007000, 0x00000003), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x10000000), ++ DECL_RFK_WC(0x032c, 0x80000000), ++ DECL_RFK_WS(0x32e0, 0x00010000), ++ DECL_RFK_WS(0x32e4, 0x0c000000), ++ DECL_RFK_WM(0x7e00, 0x03ff0000, 0x00000030), ++ DECL_RFK_WM(0x7e50, 0x03ff0000, 0x00000030), ++ DECL_RFK_WC(0x7e00, 0x0c000000), ++ DECL_RFK_WC(0x7e50, 0x0c000000), ++ DECL_RFK_WC(0x7e0c, 0x00000008), ++ DECL_RFK_WC(0x7e5c, 0x00000008), ++ DECL_RFK_WS(0x7e0c, 0x00000001), ++ DECL_RFK_WS(0x7e5c, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_b[] = { ++ DECL_RFK_WC(0x32e4, 0x0c000000), ++ DECL_RFK_WM(0x7e0c, 0x00000008, 0x00000001), ++ DECL_RFK_WM(0x7e5c, 0x00000008, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_b[] = { ++ DECL_RFK_WC(0x7e0c, 0x00000001), ++ DECL_RFK_WC(0x7e5c, 0x00000001), ++ DECL_RFK_WC(0x32e0, 0x00010000), ++ DECL_RFK_WC(0x32a0, 0x00008000), ++ DECL_RFK_WS(0x32a0, 0x00007000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_a[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x12b8, 0x10000000), ++ DECL_RFK_WS(0x58c8, 0x01000000), ++ DECL_RFK_WS(0x5864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x0c1c, 0x00000004), ++ DECL_RFK_WS(0x0700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x58ac, 0x08000000), ++ DECL_RFK_WS(0x0c3c, 0x00000200), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_a[] = { ++ DECL_RFK_WS(0x4490, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x12a0, 0x00080000), ++ DECL_RFK_WS(0x0700, 0x01000000), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_b[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x32b8, 0x10000000), ++ DECL_RFK_WS(0x78c8, 0x01000000), ++ DECL_RFK_WS(0x7864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x2c1c, 0x00000004), ++ DECL_RFK_WS(0x2700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x78ac, 0x08000000), ++ DECL_RFK_WS(0x2c3c, 0x00000200), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_b[] = { ++ DECL_RFK_WS(0x6490, 0x80000000), ++ DECL_RFK_WS(0x32a0, 0x00007000), ++ DECL_RFK_WS(0x32a0, 0x00008000), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x32a0, 0x00080000), ++ DECL_RFK_WS(0x2700, 0x01000000), ++ DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_s_defs_ab[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x12b8, 0x10000000), ++ DECL_RFK_WS(0x58c8, 0x01000000), ++ DECL_RFK_WS(0x78c8, 0x01000000), ++ DECL_RFK_WS(0x5864, 0xc0000000), ++ DECL_RFK_WS(0x7864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x0c1c, 0x00000004), ++ DECL_RFK_WS(0x0700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x58ac, 0x08000000), ++ DECL_RFK_WS(0x78ac, 0x08000000), ++ DECL_RFK_WS(0x0c3c, 0x00000200), ++ DECL_RFK_WS(0x2344, 0x80000000), ++ DECL_RFK_WS(0x4490, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x12a0, 0x00080000), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x32a0, 0x00080000), ++ DECL_RFK_WS(0x0700, 0x01000000), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_s_defs_ab); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_a[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x5864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x0c1c, 0x00000004), ++ DECL_RFK_WC(0x0700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x12a0, 0x000ff000), ++ DECL_RFK_WC(0x0700, 0x07000000), ++ DECL_RFK_WC(0x5864, 0x20000000), ++ DECL_RFK_WC(0x0c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x58c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_b[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x7864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x2c1c, 0x00000004), ++ DECL_RFK_WC(0x2700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x32a0, 0x000ff000), ++ DECL_RFK_WC(0x2700, 0x07000000), ++ DECL_RFK_WC(0x7864, 0x20000000), ++ DECL_RFK_WC(0x2c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x78c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_ab[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x5864, 0xc0000000), ++ DECL_RFK_WC(0x7864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x0c1c, 0x00000004), ++ DECL_RFK_WC(0x0700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x12a0, 0x000ff000), ++ DECL_RFK_WC(0x32a0, 0x000ff000), ++ DECL_RFK_WC(0x0700, 0x07000000), ++ DECL_RFK_WC(0x5864, 0x20000000), ++ DECL_RFK_WC(0x7864, 0x20000000), ++ DECL_RFK_WC(0x0c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x58c8, 0x01000000), ++ DECL_RFK_WC(0x78c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_ab); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_f[] = { ++ DECL_RFK_WM(0x030c, 0xff000000, 0x0000000f), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000003), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a001), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a041), ++ DECL_RFK_WS(0x8074, 0x80000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_f); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_r[] = { ++ DECL_RFK_WC(0x8074, 0x80000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x0000001f), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_r); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_pas_read_defs[] = { ++ DECL_RFK_WM(0x80d4, 0x00ff0000, 0x00000006), ++ DECL_RFK_WC(0x80bc, 0x00004000), ++ DECL_RFK_WM(0x80c0, 0x00ff0000, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_pas_read_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_nondbcc_path01[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x2344, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_nondbcc_path01); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path0[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x2320, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path0); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path1[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x32b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x6490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x32a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path1); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_nondbcc_path01[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x2320, 0x00000001, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_nondbcc_path01); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path0[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path0); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path1[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x2700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x2700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path1); +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h +new file mode 100644 +index 000000000000..2a4ba5b39b30 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h +@@ -0,0 +1,132 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_RFK_TABLE_H__ ++#define __RTW89_8852A_RFK_TABLE_H__ ++ ++#include "core.h" ++ ++enum rtw89_rfk_flag { ++ RTW89_RFK_F_WRF = 0, ++ RTW89_RFK_F_WM = 1, ++ RTW89_RFK_F_WS = 2, ++ RTW89_RFK_F_WC = 3, ++ RTW89_RFK_F_DELAY = 4, ++ RTW89_RFK_F_NUM, ++}; ++ ++struct rtw89_rfk_tbl { ++ const struct rtw89_reg5_def *defs; ++ u32 size; ++}; ++ ++#define DECLARE_RFK_TBL(_name) \ ++const struct rtw89_rfk_tbl _name ## _tbl = { \ ++ .defs = _name, \ ++ .size = ARRAY_SIZE(_name), \ ++} ++ ++#define DECL_RFK_WRF(_path, _addr, _mask, _data) \ ++ {.flag = RTW89_RFK_F_WRF, \ ++ .path = _path, \ ++ .addr = _addr, \ ++ .mask = _mask, \ ++ .data = _data,} ++ ++#define DECL_RFK_WM(_addr, _mask, _data) \ ++ {.flag = RTW89_RFK_F_WM, \ ++ .addr = _addr, \ ++ .mask = _mask, \ ++ .data = _data,} ++ ++#define DECL_RFK_WS(_addr, _mask) \ ++ {.flag = RTW89_RFK_F_WS, \ ++ .addr = _addr, \ ++ .mask = _mask,} ++ ++#define DECL_RFK_WC(_addr, _mask) \ ++ {.flag = RTW89_RFK_F_WC, \ ++ .addr = _addr, \ ++ .mask = _mask,} ++ ++#define DECL_RFK_DELAY(_data) \ ++ {.flag = RTW89_RFK_F_DELAY, \ ++ .data = _data,} ++ ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_5g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_5g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_3_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_4_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_3_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_4_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_disable_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_tracking_defs_tbl; ++ ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_afe_init_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_pas_read_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl; ++ ++#endif + +From patchwork Fri Aug 20 04:35:30 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448391 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id BB339C4338F + for ; + Fri, 20 Aug 2021 04:37:35 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 8E40460EB5 + for ; + Fri, 20 Aug 2021 04:37:35 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233557AbhHTEiL (ORCPT + ); + Fri, 20 Aug 2021 00:38:11 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39277 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233877AbhHTEiI (ORCPT + ); + Fri, 20 Aug 2021 00:38:08 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bQxhD004208, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bQxhD004208 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:26 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:25 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:24 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 16/24] rtw89: 8852a: add 8852a tables (1 of 5) +Date: Fri, 20 Aug 2021 12:35:30 +0800 +Message-ID: <20210820043538.12424-17-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;127.0.0.199:7.1.2;realtek.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +PHY and RF parameters are used to set PHY and RF register initially. +Other tables are TX power by rate, limit and swing tables. + +Signed-off-by: Ping-Ke Shih +--- + .../wireless/realtek/rtw89/rtw8852a_table.c | 10000 ++++++++++++++++ + .../wireless/realtek/rtw89/rtw8852a_table.h | 28 + + 2 files changed, 10028 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_table.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_table.h + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +new file mode 100644 +index 000000000000..81188c6c5f7d +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -0,0 +1,10000 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a_table.h" ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_bb_regs[] = { ++ {0xF0FF0001, 0x00000000}, ++ {0xF03300FF, 0x00000001}, ++ {0xF03500FF, 0x00000002}, ++ {0xF03200FF, 0x00000003}, ++ {0xF03400FF, 0x00000004}, ++ {0xF03600FF, 0x00000005}, ++ {0x704, 0x601E0100}, ++ {0x714, 0x00000000}, ++ {0x718, 0x13332333}, ++ {0x714, 0x00010000}, ++ {0x720, 0x20000000}, ++ {0x980, 0x10002250}, ++ {0x994, 0x00000010}, ++ {0x644, 0x2314283C}, ++ {0x644, 0x3426283C}, ++ {0x994, 0x00000010}, ++ {0xC3C, 0x2840E1BF}, ++ {0xC40, 0x00000000}, ++ {0xC44, 0x00000007}, ++ {0xC48, 0x410E4000}, ++ {0xC54, 0x1001436E}, ++ {0xC58, 0x41000000}, ++ {0x730, 0x00000002}, ++ {0xC60, 0x017FFFF2}, ++ {0xC64, 0x0010A130}, ++ {0xC64, 0x0010A130}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0xA0000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0xB0000000, 0x00000000}, ++ {0xC64, 0x0010A130}, ++ {0xC54, 0x1EE1436E}, ++ {0xC6C, 0x00000020}, ++ {0x708, 0x00000000}, ++ {0xC6C, 0x00000020}, ++ {0x804, 0x0043F01D}, ++ {0x12D0, 0x00000000}, ++ {0x12EC, 0x888CA72B}, ++ {0x32D0, 0x00000000}, ++ {0x32EC, 0x888CA72B}, ++ {0xD40, 0xF64FA0F7}, ++ {0xD44, 0x0400063F}, ++ {0xD48, 0x0003FF7F}, ++ {0xD4C, 0x00000000}, ++ {0xD50, 0xF64FA0F7}, ++ {0xD54, 0x04100437}, ++ {0xD58, 0x0000FF7F}, ++ {0xD5C, 0x00000000}, ++ {0xD60, 0x00000000}, ++ {0xD64, 0x00000000}, ++ {0xD70, 0x0000001D}, ++ {0xD90, 0x000003FF}, ++ {0xD94, 0x00000000}, ++ {0xD98, 0x0000003F}, ++ {0xD9C, 0x00000000}, ++ {0xDA0, 0x000003FF}, ++ {0xDA4, 0x00000000}, ++ {0xDA8, 0x0000003F}, ++ {0xDAC, 0x00000000}, ++ {0xD00, 0x77777777}, ++ {0xD04, 0xBBBBBBBB}, ++ {0xD08, 0xBBBBBBBB}, ++ {0xD0C, 0x00000070}, ++ {0xD10, 0x20110900}, ++ {0xD10, 0x20110FFF}, ++ {0xD7C, 0x001D050C}, ++ {0xD84, 0x00006207}, ++ {0xD18, 0x50209900}, ++ {0xD80, 0x00804100}, ++ {0x714, 0x00010000}, ++ {0x704, 0x601E00FD}, ++ {0x710, 0xF3810000}, ++ {0x000, 0x0580801F}, ++ {0x000, 0x8580801F}, ++ {0x334, 0xFFFFFFFF}, ++ {0x33C, 0x55000000}, ++ {0x340, 0x00005555}, ++ {0x724, 0x00111200}, ++ {0x5868, 0xA9550000}, ++ {0x5870, 0x33221100}, ++ {0x5874, 0x77665544}, ++ {0x5878, 0xBBAA9988}, ++ {0x587C, 0xFFEEDDCC}, ++ {0x5880, 0x76543210}, ++ {0x5884, 0xFEDCBA98}, ++ {0x5888, 0x00000000}, ++ {0x588C, 0x00000000}, ++ {0x5894, 0x00000008}, ++ {0x7868, 0xA9550000}, ++ {0x7870, 0x33221100}, ++ {0x7874, 0x77665544}, ++ {0x7878, 0xBBAA9988}, ++ {0x787C, 0xFFEEDDCC}, ++ {0x7880, 0x76543210}, ++ {0x7884, 0xFEDCBA98}, ++ {0x7888, 0x00000000}, ++ {0x788C, 0x00000000}, ++ {0x7894, 0x00000008}, ++ {0x240C, 0x00000000}, ++ {0xC70, 0x00000400}, ++ {0x700, 0x00000030}, ++ {0x704, 0x601E00FF}, ++ {0x704, 0x601E00FD}, ++ {0x704, 0x601E00FF}, ++ {0x586C, 0x000000F0}, ++ {0x586C, 0x000000E0}, ++ {0x586C, 0x000000D0}, ++ {0x586C, 0x000000C0}, ++ {0x586C, 0x000000B0}, ++ {0x586C, 0x000000A0}, ++ {0x586C, 0x00000090}, ++ {0x586C, 0x00000080}, ++ {0x586C, 0x00000070}, ++ {0x586C, 0x00000060}, ++ {0x586C, 0x00000050}, ++ {0x586C, 0x00000040}, ++ {0x586C, 0x00000030}, ++ {0x586C, 0x00000020}, ++ {0x586C, 0x00000010}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0xA0000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0xB0000000, 0x00000000}, ++ {0x786C, 0x000000F0}, ++ {0x786C, 0x000000E0}, ++ {0x786C, 0x000000D0}, ++ {0x786C, 0x000000C0}, ++ {0x786C, 0x000000B0}, ++ {0x786C, 0x000000A0}, ++ {0x786C, 0x00000090}, ++ {0x786C, 0x00000080}, ++ {0x786C, 0x00000070}, ++ {0x786C, 0x00000060}, ++ {0x786C, 0x00000050}, ++ {0x786C, 0x00000040}, ++ {0x786C, 0x00000030}, ++ {0x786C, 0x00000020}, ++ {0x786C, 0x00000010}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0xA0000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0xB0000000, 0x00000000}, ++ {0x5864, 0x080801FF}, ++ {0x7864, 0x080801FF}, ++ {0xC60, 0x017FFFF3}, ++ {0xC6C, 0x00000021}, ++ {0x58AC, 0x08000000}, ++ {0x78AC, 0x08000000}, ++ {0x5864, 0x180801FF}, ++ {0x7864, 0x180801FF}, ++ {0xC60, 0x017FFFF3}, ++ {0xC60, 0x017FFFF3}, ++ {0x2C60, 0x013FFF0A}, ++ {0xC70, 0x00000600}, ++ {0xC70, 0x00000660}, ++ {0xC6C, 0x10001021}, ++ {0x58AC, 0x08000000}, ++ {0x78AC, 0x08000000}, ++ {0x5864, 0x100801FF}, ++ {0x7864, 0x100801FF}, ++ {0x5864, 0x180801FF}, ++ {0x7864, 0x180801FF}, ++ {0x704, 0x601C01FF}, ++ {0x58D4, 0x0401FE00}, ++ {0x78D4, 0x0401FE00}, ++ {0x58F0, 0x000401FF}, ++ {0x78F0, 0x000401FF}, ++ {0x58F0, 0x400401FF}, ++ {0x78F0, 0x400401FF}, ++ {0x12A8, 0x333378A5}, ++ {0x32A8, 0x333378A5}, ++ {0x2300, 0x02748790}, ++ {0x2304, 0x00558670}, ++ {0x2308, 0x002883F0}, ++ {0x230C, 0x00090120}, ++ {0x2310, 0x00000000}, ++ {0x2314, 0x06000000}, ++ {0x2318, 0x00000000}, ++ {0x231C, 0x00000000}, ++ {0x2320, 0x03020100}, ++ {0x2324, 0x07060504}, ++ {0x2328, 0x0B0A0908}, ++ {0x232C, 0x0F0E0D0C}, ++ {0x2330, 0x13121110}, ++ {0x2334, 0x17161514}, ++ {0x2338, 0x0C700022}, ++ {0x233C, 0x0A05298F}, ++ {0x2340, 0x0005298E}, ++ {0x2344, 0x0006318A}, ++ {0x2348, 0xB7E6318A}, ++ {0x234C, 0x80039CE7}, ++ {0x2350, 0x80039CE7}, ++ {0x2354, 0x0005298F}, ++ {0x2358, 0x0015296E}, ++ {0x235C, 0x0C07FC31}, ++ {0x2360, 0x0219A6AE}, ++ {0x2364, 0xE4F624C3}, ++ {0x2368, 0x53626F15}, ++ {0x236C, 0x48000000}, ++ {0x2370, 0x48000000}, ++ {0x2374, 0x074C0000}, ++ {0x2378, 0x202401B5}, ++ {0x237C, 0x00F7000E}, ++ {0x2380, 0x0F0A1111}, ++ {0x2384, 0x30D9000F}, ++ {0x2388, 0x0400EA02}, ++ {0x238C, 0x003CB061}, ++ {0x2390, 0x69C00000}, ++ {0x2394, 0x00000000}, ++ {0x2398, 0x000000F0}, ++ {0x239C, 0x0001FFFF}, ++ {0x23A0, 0x00C80064}, ++ {0x23A4, 0x0190012C}, ++ {0x23A8, 0x001917BE}, ++ {0x23AC, 0x0B308800}, ++ {0x23B0, 0x0001D5B0}, ++ {0x23B4, 0x000285D2}, ++ {0x23B8, 0x00000000}, ++ {0x23BC, 0x00000000}, ++ {0x23C0, 0x00000000}, ++ {0x23C4, 0x00000000}, ++ {0x23C8, 0x00000000}, ++ {0x23CC, 0x00000000}, ++ {0x23D0, 0x00000000}, ++ {0x23D4, 0x00000000}, ++ {0x23D8, 0x00000000}, ++ {0x23DC, 0x00000000}, ++ {0x23E0, 0x00000000}, ++ {0x23E4, 0x00000000}, ++ {0x23E8, 0x00000000}, ++ {0x23EC, 0x00000000}, ++ {0x23F0, 0x00000000}, ++ {0x23F4, 0x00000000}, ++ {0x23F8, 0x00000000}, ++ {0x23FC, 0x00000000}, ++ {0x804, 0x0043F01D}, ++ {0x300, 0xF30CE31C}, ++ {0x304, 0x13EF1F19}, ++ {0x308, 0x0C0CF3F3}, ++ {0x30C, 0x0C0C0C0C}, ++ {0x310, 0x80416000}, ++ {0x314, 0x0041E000}, ++ {0x318, 0x20022042}, ++ {0x31C, 0x20448001}, ++ {0x320, 0x00410040}, ++ {0x324, 0xE000E000}, ++ {0x328, 0xE000E000}, ++ {0x32C, 0xE000E000}, ++ {0x12BC, 0x10104041}, ++ {0x12C0, 0x14411111}, ++ {0x32BC, 0x10104041}, ++ {0x32C0, 0x14411111}, ++ {0x010, 0x0005FFFF}, ++ {0x604, 0x1E1E1E28}, ++ {0x650, 0x00200888}, ++ {0x620, 0x00141230}, ++ {0x35C, 0x000004C4}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0xA0000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0xB0000000, 0x00000000}, ++ {0x12A0, 0x24903156}, ++ {0x32A0, 0x24903156}, ++ {0x640, 0x1414141E}, ++ {0x12B8, 0x30020000}, ++ {0x12AC, 0x02333121}, ++ {0x9A4, 0x0000001C}, ++ {0x624, 0x01010301}, ++ {0x628, 0x00010101}, ++ {0x5800, 0x03FF807F}, ++ {0x7800, 0x03FF807F}, ++ {0x4000, 0x00000000}, ++ {0x4004, 0xCA014000}, ++ {0x4008, 0xC751D4F0}, ++ {0x400C, 0x44511475}, ++ {0x4010, 0x00000000}, ++ {0x4014, 0x00000000}, ++ {0x4018, 0x4F4C084B}, ++ {0x401C, 0x084A4E52}, ++ {0x4020, 0x4D504E4B}, ++ {0x4024, 0x4F4C0849}, ++ {0x4028, 0x08484C50}, ++ {0x402C, 0x4C50504C}, ++ {0x4030, 0x5454084A}, ++ {0x4034, 0x084B5654}, ++ {0x4038, 0x6A6C605A}, ++ {0x403C, 0x4C4C084C}, ++ {0x4040, 0x084B4E4D}, ++ {0x4044, 0x4E4C4B4B}, ++ {0x4048, 0x4B4B084A}, ++ {0x404C, 0x084A4E4C}, ++ {0x4050, 0x514F4C4A}, ++ {0x4054, 0x524E084A}, ++ {0x4058, 0x084A5154}, ++ {0x405C, 0x53555554}, ++ {0x4060, 0x45450845}, ++ {0x4064, 0x08454144}, ++ {0x4068, 0x40434445}, ++ {0x406C, 0x44450845}, ++ {0x4070, 0x08444043}, ++ {0x4074, 0x42434444}, ++ {0x4078, 0x46450844}, ++ {0x407C, 0x08444843}, ++ {0x4080, 0x4B4E4A47}, ++ {0x4084, 0x4F4C084B}, ++ {0x4088, 0x084A4E52}, ++ {0x408C, 0x4D504E4B}, ++ {0x4090, 0x4F4C0849}, ++ {0x4094, 0x08484C50}, ++ {0x4098, 0x4C50504C}, ++ {0x409C, 0x5454084A}, ++ {0x40A0, 0x084B5654}, ++ {0x40A4, 0x6A6C605A}, ++ {0x40A8, 0x4C4C084C}, ++ {0x40AC, 0x084B4E4D}, ++ {0x40B0, 0x4E4C4B4B}, ++ {0x40B4, 0x4B4B084A}, ++ {0x40B8, 0x084A4E4C}, ++ {0x40BC, 0x514F4C4A}, ++ {0x40C0, 0x524E084A}, ++ {0x40C4, 0x084A5154}, ++ {0x40C8, 0x53555554}, ++ {0x40CC, 0x45450845}, ++ {0x40D0, 0x08454144}, ++ {0x40D4, 0x40434445}, ++ {0x40D8, 0x44450845}, ++ {0x40DC, 0x08444043}, ++ {0x40E0, 0x42434444}, ++ {0x40E4, 0x46450844}, ++ {0x40E8, 0x08444843}, ++ {0x40EC, 0x4B4E4A47}, ++ {0x40F0, 0x00000000}, ++ {0x40F4, 0x00000006}, ++ {0x40F8, 0x00000001}, ++ {0x40FC, 0x8C30C30C}, ++ {0x4100, 0x4C30C30C}, ++ {0x4104, 0x0C30C30C}, ++ {0x4108, 0x0C30C30C}, ++ {0x410C, 0x0C30C30C}, ++ {0x4110, 0x0C30C30C}, ++ {0x4114, 0x28A28A28}, ++ {0x4118, 0x28A28A28}, ++ {0x411C, 0x28A28A28}, ++ {0x4120, 0x28A28A28}, ++ {0x4124, 0x28A28A28}, ++ {0x4128, 0x28A28A28}, ++ {0x412C, 0x06666666}, ++ {0x4130, 0x33333333}, ++ {0x4134, 0x33333333}, ++ {0x4138, 0x33333333}, ++ {0x413C, 0x00000031}, ++ {0x4140, 0x5100600A}, ++ {0x4144, 0x18363113}, ++ {0x4148, 0x1D976DDC}, ++ {0x414C, 0x1C072DD7}, ++ {0x4150, 0x1127CDF4}, ++ {0x4154, 0x1E37BDF1}, ++ {0x4158, 0x1FB7F1D6}, ++ {0x415C, 0x1EA7DDF9}, ++ {0x4160, 0x1FE445DD}, ++ {0x4164, 0x1F97F1FE}, ++ {0x4168, 0x1FF781ED}, ++ {0x416C, 0x1FA7F5FE}, ++ {0x4170, 0x1E07B913}, ++ {0x4174, 0x1FD7FDFF}, ++ {0x4178, 0x1E17B9FA}, ++ {0x417C, 0x19A66914}, ++ {0x4180, 0x10F65598}, ++ {0x4184, 0x14A5A111}, ++ {0x4188, 0x1D3765DB}, ++ {0x418C, 0x17C685CA}, ++ {0x4190, 0x1107C5F3}, ++ {0x4194, 0x1B5785EB}, ++ {0x4198, 0x1F97ED8F}, ++ {0x419C, 0x1BC7A5F3}, ++ {0x41A0, 0x1FE43595}, ++ {0x41A4, 0x1EB7D9FC}, ++ {0x41A8, 0x1FE65DBE}, ++ {0x41AC, 0x1EC7D9FC}, ++ {0x41B0, 0x1976FCFF}, ++ {0x41B4, 0x1F77F5FF}, ++ {0x41B8, 0x1976FDEC}, ++ {0x41BC, 0x198664EF}, ++ {0x41C0, 0x11062D93}, ++ {0x41C4, 0x10C4E910}, ++ {0x41C8, 0x1CA759DB}, ++ {0x41CC, 0x1335A9B5}, ++ {0x41D0, 0x1097B9F3}, ++ {0x41D4, 0x17B72DE1}, ++ {0x41D8, 0x1F67ED42}, ++ {0x41DC, 0x18074DE9}, ++ {0x41E0, 0x1FD40547}, ++ {0x41E4, 0x1D57ADF9}, ++ {0x41E8, 0x1FE52182}, ++ {0x41EC, 0x1D67B1F9}, ++ {0x41F0, 0x14860CE1}, ++ {0x41F4, 0x1EC7E9FE}, ++ {0x41F8, 0x14860DD6}, ++ {0x41FC, 0x195664C7}, ++ {0x4200, 0x0005E58A}, ++ {0x4204, 0x00000000}, ++ {0x4208, 0x00000000}, ++ {0x420C, 0x7A000000}, ++ {0x4210, 0x0F9F3D7A}, ++ {0x4214, 0x0040817C}, ++ {0x4218, 0x00E10204}, ++ {0x421C, 0x227D94CD}, ++ {0x4220, 0x080238E3}, ++ {0x4224, 0x00000210}, ++ {0x4228, 0x04688000}, ++ {0x422C, 0x0060B002}, ++ {0x4230, 0x9A8249A8}, ++ {0x4234, 0x26A1469E}, ++ {0x4238, 0x2099A824}, ++ {0x423C, 0x2359461C}, ++ {0x4240, 0x1631A675}, ++ {0x4244, 0x2C6B1D63}, ++ {0x4248, 0x0000000E}, ++ {0x424C, 0x00000001}, ++ {0x4250, 0x00000001}, ++ {0x4254, 0x00000000}, ++ {0x4258, 0x00000000}, ++ {0x425C, 0x00000000}, ++ {0x4260, 0x0020000C}, ++ {0x4264, 0x00000000}, ++ {0x4268, 0x00000000}, ++ {0x426C, 0x0418317C}, ++ {0x4270, 0x00D6135C}, ++ {0x4274, 0x00000000}, ++ {0x4278, 0x00000000}, ++ {0x427C, 0x00000000}, ++ {0x4280, 0x00000000}, ++ {0x4284, 0x00000000}, ++ {0x4288, 0x00000000}, ++ {0x428C, 0x00000000}, ++ {0x4290, 0x00000000}, ++ {0x4294, 0x00000000}, ++ {0x4298, 0x84026000}, ++ {0x429C, 0x0051AC20}, ++ {0x42A0, 0x02024008}, ++ {0x42A4, 0x00000000}, ++ {0x42A8, 0x00000000}, ++ {0x42AC, 0x22CE803C}, ++ {0x42B0, 0x80000000}, ++ {0x42B4, 0x00E7D03D}, ++ {0x42B8, 0x3D67D67D}, ++ {0x42BC, 0x7D67D65B}, ++ {0x42C0, 0x2802AF59}, ++ {0x42C4, 0x00280280}, ++ {0x42C8, 0x00000000}, ++ {0x42CC, 0x00000000}, ++ {0x42D0, 0x00000003}, ++ {0x42D4, 0x00000001}, ++ {0x42D8, 0x61861800}, ++ {0x42DC, 0x830C30C3}, ++ {0x42E0, 0xC30C30C3}, ++ {0x42E4, 0x830C30C3}, ++ {0x42E8, 0x451450C3}, ++ {0x42EC, 0x05145145}, ++ {0x42F0, 0x05145145}, ++ {0x42F4, 0x05145145}, ++ {0x42F8, 0x0F0C3145}, ++ {0x42FC, 0x030C30CF}, ++ {0x4300, 0x030C30C3}, ++ {0x4304, 0x030CF3C3}, ++ {0x4308, 0x030C30C3}, ++ {0x430C, 0x0F3CF3C3}, ++ {0x4310, 0x0F3CF3CF}, ++ {0x4314, 0x0F3CF3CF}, ++ {0x4318, 0x0F3CF3CF}, ++ {0x431C, 0x0F3CF3CF}, ++ {0x4320, 0x030C10C3}, ++ {0x4324, 0x051430C3}, ++ {0x4328, 0x051490CB}, ++ {0x432C, 0x030CD151}, ++ {0x4330, 0x050C50C7}, ++ {0x4334, 0x051492CB}, ++ {0x4338, 0x05145145}, ++ {0x433C, 0x05145145}, ++ {0x4340, 0x05145145}, ++ {0x4344, 0x05145145}, ++ {0x4348, 0x090CD3CF}, ++ {0x434C, 0x071491C5}, ++ {0x4350, 0x073CF143}, ++ {0x4354, 0x071431C3}, ++ {0x4358, 0x0F3CF1C5}, ++ {0x435C, 0x0F3CF3CF}, ++ {0x4360, 0x0F3CF3CF}, ++ {0x4364, 0x0F3CF3CF}, ++ {0x4368, 0x0F3CF3CF}, ++ {0x436C, 0x090C91CF}, ++ {0x4370, 0x11243143}, ++ {0x4374, 0x9777A777}, ++ {0x4378, 0xBB7BAC95}, ++ {0x437C, 0xB667B889}, ++ {0x4380, 0x7B9B8899}, ++ {0x4384, 0x7A5567C8}, ++ {0x4388, 0x2278CCCC}, ++ {0x438C, 0x7C222222}, ++ {0x4390, 0x0000069B}, ++ {0x4394, 0x001CCCCC}, ++ {0x4398, 0x00000000}, ++ {0x439C, 0x00000008}, ++ {0x49A4, 0x00000000}, ++ {0x43A0, 0x00000000}, ++ {0x43A4, 0x00000000}, ++ {0x43A8, 0x00000000}, ++ {0x43AC, 0x10000800}, ++ {0x43B0, 0x00401802}, ++ {0x43B4, 0x00061004}, ++ {0x43B8, 0x000024D8}, ++ {0x43BC, 0x00000000}, ++ {0x43C0, 0x10000020}, ++ {0x43C4, 0x20000200}, ++ {0x43C8, 0x00000000}, ++ {0x43CC, 0x04000000}, ++ {0x43D0, 0x44000100}, ++ {0x43D4, 0x60804060}, ++ {0x43D8, 0x44204210}, ++ {0x43DC, 0x82108082}, ++ {0x43E0, 0x82108402}, ++ {0x43E4, 0xC8082108}, ++ {0x43E8, 0xC8202084}, ++ {0x43EC, 0x44208208}, ++ {0x43F0, 0x84108204}, ++ {0x43F4, 0xD0108104}, ++ {0x43F8, 0xF8210108}, ++ {0x43FC, 0x6431E930}, ++ {0x4400, 0x02109468}, ++ {0x4404, 0x10C61C22}, ++ {0x4408, 0x02109469}, ++ {0x440C, 0x10C61C22}, ++ {0x4410, 0x00041049}, ++ {0x4414, 0x00000000}, ++ {0x4418, 0x00000000}, ++ {0x441C, 0x6C000000}, ++ {0x4420, 0xB0200020}, ++ {0x4424, 0x00001FF0}, ++ {0x4428, 0x00000000}, ++ {0x442C, 0x00000000}, ++ {0x4430, 0x00000000}, ++ {0x4434, 0x00000000}, ++ {0x4438, 0x65F962F8}, ++ {0x443C, 0x280668A0}, ++ {0x4440, 0x64100820}, ++ {0x4444, 0x4A146304}, ++ {0x4448, 0x0C59008F}, ++ {0x444C, 0x6E30498A}, ++ {0x4450, 0x656E371B}, ++ {0x4454, 0x00000F52}, ++ {0x4458, 0x00000000}, ++ {0x445C, 0x4801442E}, ++ {0x4460, 0x0041A0B8}, ++ {0x4464, 0x00000000}, ++ {0x4468, 0x00000000}, ++ {0x446C, 0x00000000}, ++ {0x4470, 0x00000000}, ++ {0x4474, 0x00000000}, ++ {0x4478, 0x00000000}, ++ {0x447C, 0x00000000}, ++ {0x4480, 0x2A0A6040}, ++ {0x4484, 0x0A0A6829}, ++ {0x4488, 0x00000004}, ++ {0x448C, 0x00000000}, ++ {0x4490, 0x80000000}, ++ {0x4494, 0x10000000}, ++ {0x4498, 0xA0000000}, ++ {0x449C, 0x0000001E}, ++ {0x44A0, 0x02B29397}, ++ {0x44A4, 0x00000400}, ++ {0x44A8, 0x00000001}, ++ {0x44AC, 0x00000000}, ++ {0x44B0, 0x00000000}, ++ {0x44B4, 0x00000000}, ++ {0x44B8, 0x00000000}, ++ {0x44BC, 0x00000000}, ++ {0x44C0, 0x00000000}, ++ {0x44C4, 0x00000000}, ++ {0x44C8, 0x00000000}, ++ {0x44CC, 0x00000000}, ++ {0x44D0, 0x00000000}, ++ {0x44D4, 0x00000000}, ++ {0x44D8, 0x00000000}, ++ {0x44DC, 0x00000000}, ++ {0x44E0, 0x00000000}, ++ {0x44E4, 0x00000000}, ++ {0x44E8, 0x00000000}, ++ {0x44EC, 0x00000000}, ++ {0x44F0, 0x00000000}, ++ {0x44F4, 0x00000000}, ++ {0x44F8, 0x00000000}, ++ {0x44FC, 0x00000000}, ++ {0x4500, 0x00000000}, ++ {0x4504, 0x00000000}, ++ {0x4508, 0x00000000}, ++ {0x450C, 0x00000000}, ++ {0x4510, 0x00000000}, ++ {0x4514, 0x00000000}, ++ {0x4518, 0x00000000}, ++ {0x451C, 0x00000000}, ++ {0x4520, 0x00000000}, ++ {0x4524, 0x00000000}, ++ {0x4528, 0x00000000}, ++ {0x452C, 0x00000000}, ++ {0x4530, 0x4EA20631}, ++ {0x4534, 0x000005C8}, ++ {0x4538, 0x000000FF}, ++ {0x453C, 0x00000000}, ++ {0x4540, 0x00000000}, ++ {0x4544, 0x00000000}, ++ {0x4548, 0x00000000}, ++ {0x454C, 0x00000000}, ++ {0x4550, 0x00000000}, ++ {0x4554, 0x00000000}, ++ {0x4558, 0x00000000}, ++ {0x455C, 0x00000000}, ++ {0x4560, 0x4060001A}, ++ {0x4564, 0x40000000}, ++ {0x4568, 0x00000000}, ++ {0x456C, 0x20000000}, ++ {0x4570, 0x04800406}, ++ {0x4574, 0x00022270}, ++ {0x4578, 0x0002024B}, ++ {0x457C, 0x00200000}, ++ {0x4580, 0x00009B40}, ++ {0x4584, 0x00000000}, ++ {0x4588, 0x00000063}, ++ {0x458C, 0x30000000}, ++ {0x4590, 0x00000000}, ++ {0x4594, 0x05000000}, ++ {0x4598, 0x00000001}, ++ {0x459C, 0x0003FE00}, ++ {0x45A0, 0x00000000}, ++ {0x45A4, 0x00000000}, ++ {0x45A8, 0xC00001C0}, ++ {0x45AC, 0x78028000}, ++ {0x45B0, 0x80000048}, ++ {0x45B4, 0x01C90800}, ++ {0x45B8, 0x00000002}, ++ {0x45BC, 0x06748790}, ++ {0x45C0, 0x80000000}, ++ {0x45C4, 0x00000000}, ++ {0x45C8, 0x00000000}, ++ {0x45CC, 0x00558670}, ++ {0x45D0, 0x002883F0}, ++ {0x45D4, 0x00090120}, ++ {0x45D8, 0x00000000}, ++ {0x45DC, 0xA3A6D3C4}, ++ {0x49A8, 0xAB27B126}, ++ {0x49AC, 0x00006778}, ++ {0x49FC, 0x000001B5}, ++ {0x49B0, 0x11110F0A}, ++ {0x49B4, 0x00000007}, ++ {0x49B8, 0x0000000A}, ++ {0x49BC, 0x0058BC3F}, ++ {0x49C0, 0x00000003}, ++ {0x49C4, 0x000003D9}, ++ {0x49C8, 0x002B1CB0}, ++ {0x4A00, 0x00000000}, ++ {0x49CC, 0x00000001}, ++ {0x49D0, 0x00000010}, ++ {0x49D4, 0x00000001}, ++ {0x49D8, 0x85298FBF}, ++ {0x49DC, 0x18A5296E}, ++ {0x49E0, 0x18C6298C}, ++ {0x49E4, 0x0A739CA7}, ++ {0x49E8, 0x001A50E7}, ++ {0x49EC, 0x00000001}, ++ {0x49F0, 0x00005924}, ++ {0x49F4, 0x0003AAA6}, ++ {0x49F8, 0x0000C4C3}, ++ {0x45E0, 0x00000000}, ++ {0x45E4, 0x00000000}, ++ {0x45E8, 0x00E2E100}, ++ {0x45EC, 0xCB00B6B6}, ++ {0x45F0, 0x59100FCA}, ++ {0x45F4, 0x08882550}, ++ {0x45F8, 0x08CC2660}, ++ {0x45FC, 0x09102660}, ++ {0x4600, 0x00000154}, ++ {0x4604, 0x00000800}, ++ {0x4608, 0x31BF0400}, ++ {0x460C, 0x00E0C0A0}, ++ {0x4610, 0x30604020}, ++ {0x4614, 0x2F346D50}, ++ {0x4618, 0x2E36B6E2}, ++ {0x461C, 0x3E7EF86B}, ++ {0x4620, 0x001FC004}, ++ {0x4624, 0xA8068010}, ++ {0x4628, 0x4602CA80}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0xA0000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0xB0000000, 0x00000000}, ++ {0x4648, 0x64204FB2}, ++ {0x464C, 0x4C823404}, ++ {0x4650, 0x9084C800}, ++ {0x4654, 0x9889314F}, ++ {0x4658, 0x5ECC3FF4}, ++ {0x465C, 0xFEECAECE}, ++ {0x4660, 0x47806638}, ++ {0x4664, 0x0F5AF843}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0xA0000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0xB0000000, 0x00000000}, ++ {0x4670, 0xE8DF38D8}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0xA0000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0xB0000000, 0x00000000}, ++ {0x4678, 0x00000000}, ++ {0x467C, 0x00000000}, ++ {0x4680, 0x00000219}, ++ {0x4684, 0x00000000}, ++ {0x4688, 0x00000000}, ++ {0x468C, 0x00000001}, ++ {0x4690, 0x00000001}, ++ {0x4694, 0x00000000}, ++ {0x4698, 0x00000000}, ++ {0x469C, 0x00000151}, ++ {0x46A0, 0x00000498}, ++ {0x46A4, 0x00000498}, ++ {0x46A8, 0x00000000}, ++ {0x46AC, 0x00000000}, ++ {0x46B0, 0x00001146}, ++ {0x46B4, 0x00000000}, ++ {0x46B8, 0x00000000}, ++ {0x46BC, 0x00E2E100}, ++ {0x46C0, 0xCB00B6B6}, ++ {0x46C4, 0x59100FCA}, ++ {0x46C8, 0x08882550}, ++ {0x46CC, 0x08CC2660}, ++ {0x46D0, 0x09102660}, ++ {0x46D4, 0x00000154}, ++ {0x46D8, 0x00000800}, ++ {0x46DC, 0x31BF0400}, ++ {0x46E0, 0x00E0C0A0}, ++ {0x46E4, 0x30604020}, ++ {0x46E8, 0x4F346D50}, ++ {0x46EC, 0x2E36B6E2}, ++ {0x46F0, 0x3E7EF86B}, ++ {0x46F4, 0x001FC004}, ++ {0x46F8, 0xA8068010}, ++ {0x46FC, 0x4602CA80}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0xA0000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0xB0000000, 0x00000000}, ++ {0x471C, 0x64204FB2}, ++ {0x4720, 0x4C823404}, ++ {0x4724, 0x9084C800}, ++ {0x4728, 0x9889314F}, ++ {0x472C, 0x5ECC3FF4}, ++ {0x4730, 0xFEECAECE}, ++ {0x4734, 0x47806638}, ++ {0x4738, 0x0F4A7843}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0xA0000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0xB0000000, 0x00000000}, ++ {0x4744, 0xE8DF38D8}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0xA0000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0xB0000000, 0x00000000}, ++ {0x474C, 0x00000000}, ++ {0x4750, 0x00000000}, ++ {0x4754, 0x00000219}, ++ {0x4758, 0x00000000}, ++ {0x475C, 0x00000000}, ++ {0x4760, 0x00000001}, ++ {0x4764, 0x00000001}, ++ {0x4768, 0x00000000}, ++ {0x476C, 0x00000000}, ++ {0x4770, 0x00000151}, ++ {0x4774, 0x00000498}, ++ {0x4778, 0x00000498}, ++ {0x477C, 0x00000000}, ++ {0x4780, 0x00000000}, ++ {0x4784, 0x00001147}, ++ {0x4788, 0x00000000}, ++ {0x478C, 0xA32103FE}, ++ {0x4790, 0x320A7B28}, ++ {0x4794, 0xC6A7B14F}, ++ {0x4798, 0x000006D7}, ++ {0x479C, 0x009B902A}, ++ {0x47A0, 0x009B902A}, ++ {0x47A4, 0x98682C18}, ++ {0x47A8, 0x6308C4C1}, ++ {0x47AC, 0x6248C631}, ++ {0x47B0, 0x922A8253}, ++ {0x47B4, 0x00000005}, ++ {0x47B8, 0x00001759}, ++ {0x47BC, 0x4B802000}, ++ {0x47C0, 0x831408BE}, ++ {0x47C4, 0x9ABBCACB}, ++ {0x47C8, 0x56767578}, ++ {0x47CC, 0xBBCCBBB3}, ++ {0x47D0, 0x57889989}, ++ {0x47D4, 0x00000F45}, ++ {0x47D8, 0x27039CE9}, ++ {0x47DC, 0x31413432}, ++ {0x47E0, 0x26058342}, ++ {0x47E4, 0x00000006}, ++ {0x47E8, 0x00000005}, ++ {0x47EC, 0x00000005}, ++ {0x47F0, 0xC7013016}, ++ {0x47F4, 0x84413016}, ++ {0x47F8, 0x84413016}, ++ {0x47FC, 0x8C413016}, ++ {0x4800, 0x8C40B028}, ++ {0x4804, 0x3140B028}, ++ {0x4808, 0x2940B028}, ++ {0x480C, 0x8440B028}, ++ {0x4810, 0x2318C610}, ++ {0x4814, 0x45334753}, ++ {0x4818, 0x236A6A88}, ++ {0x481C, 0x576DF814}, ++ {0x4820, 0xA08877AC}, ++ {0x4824, 0x0000087A}, ++ {0x4828, 0xBCEB4A14}, ++ {0x482C, 0x000A3A4A}, ++ {0x4830, 0xBCEB4A14}, ++ {0x4834, 0x000A3A4A}, ++ {0x4838, 0xBCBDBD85}, ++ {0x483C, 0x0CABB99A}, ++ {0x4840, 0x38384242}, ++ {0x4844, 0x8086102E}, ++ {0x4848, 0xCA24C82A}, ++ {0x484C, 0x00008A62}, ++ {0x4850, 0x00000008}, ++ {0x4854, 0x009B902A}, ++ {0x4858, 0x009B902A}, ++ {0x485C, 0x98682C18}, ++ {0x4860, 0x6308C4C1}, ++ {0x4864, 0x6248C631}, ++ {0x4868, 0x922A8253}, ++ {0x486C, 0x00000005}, ++ {0x4870, 0x00001759}, ++ {0x4874, 0x4B802000}, ++ {0x4878, 0x831408BE}, ++ {0x487C, 0x9898A8BB}, ++ {0x4880, 0x54535368}, ++ {0x4884, 0x999999B3}, ++ {0x4888, 0x35555589}, ++ {0x488C, 0x00000745}, ++ {0x4890, 0x27039CE9}, ++ {0x4894, 0x31413432}, ++ {0x4898, 0x26058342}, ++ {0x489C, 0x00000006}, ++ {0x48A0, 0x00000005}, ++ {0x48A4, 0x00000005}, ++ {0x48A8, 0xC7013016}, ++ {0x48AC, 0x84413016}, ++ {0x48B0, 0x84413016}, ++ {0x48B4, 0x8C413016}, ++ {0x48B8, 0x8C40B028}, ++ {0x48BC, 0x3140B028}, ++ {0x48C0, 0x2940B028}, ++ {0x48C4, 0x8440B028}, ++ {0x48C8, 0x2318C610}, ++ {0x48CC, 0x45334753}, ++ {0x48D0, 0x236A6A88}, ++ {0x48D4, 0x576DF814}, ++ {0x48D8, 0xA08877AC}, ++ {0x48DC, 0x0000007A}, ++ {0x48E0, 0xBCEB4A14}, ++ {0x48E4, 0x000A3A4A}, ++ {0x48E8, 0xBCEB4A14}, ++ {0x48EC, 0x000A3A4A}, ++ {0x48F0, 0x9A8A8A85}, ++ {0x48F4, 0x0CA3B99A}, ++ {0x48F8, 0x38384242}, ++ {0x48FC, 0x8086102E}, ++ {0x4900, 0xCA24C82A}, ++ {0x4904, 0x00008A62}, ++ {0x4908, 0x00000008}, ++ {0x490C, 0x80040000}, ++ {0x4910, 0x80040000}, ++ {0x4914, 0xFE800000}, ++ {0x4918, 0x834C0000}, ++ {0x491C, 0x00000000}, ++ {0x4920, 0x00000000}, ++ {0x4924, 0x00000000}, ++ {0x4928, 0x00000000}, ++ {0x492C, 0x00000000}, ++ {0x4930, 0x00000000}, ++ {0x4934, 0x40000000}, ++ {0x4938, 0x00000000}, ++ {0x493C, 0x00000000}, ++ {0x4940, 0x00000000}, ++ {0x4944, 0x00000000}, ++ {0x4948, 0x04065800}, ++ {0x494C, 0x32004080}, ++ {0x4950, 0x0E1E3E05}, ++ {0x4954, 0x0A163068}, ++ {0x4958, 0x00206040}, ++ {0x495C, 0x02020202}, ++ {0x4960, 0x00A16020}, ++ {0x4964, 0x031F4284}, ++ {0x4968, 0x00A10285}, ++ {0x496C, 0x00000005}, ++ {0x4970, 0x00000000}, ++ {0x4974, 0x800CD62D}, ++ {0x4978, 0x00000103}, ++ {0x497C, 0x00000000}, ++ {0x4980, 0x00000000}, ++ {0x4984, 0x00000000}, ++ {0x4988, 0x00000000}, ++ {0x498C, 0x00000000}, ++ {0x4990, 0x00000000}, ++ {0x4994, 0x00000000}, ++ {0x4998, 0x00000000}, ++ {0x499C, 0x00000000}, ++ {0x49A0, 0x00000000}, ++ {0x2404, 0x00000001}, ++ {0xC7C, 0x0000BFE0}, ++ {0x020, 0x0000F381}, ++ {0x024, 0x0000F381}, ++ {0x028, 0x0000F381}, ++ {0x02C, 0x0000F381}, ++ {0xD78, 0x00000005}, ++ {0x12CC, 0x00000CC1}, ++ {0x12D0, 0x00000000}, ++ {0x12D4, 0x00000000}, ++ {0x12D8, 0x00000040}, ++ {0x12DC, 0x4486888C}, ++ {0x12E0, 0xC43A10E1}, ++ {0x12E4, 0x30D52A68}, ++ {0x12E8, 0x02024128}, ++ {0x12EC, 0x888C272B}, ++ {0x12EC, 0x888CA72B}, ++ {0x32CC, 0x00000CC1}, ++ {0x32D0, 0x00000000}, ++ {0x32D4, 0x00000000}, ++ {0x32D8, 0x00000040}, ++ {0x32DC, 0x4486888C}, ++ {0x32E0, 0xC43A10E1}, ++ {0x32E4, 0x30D52A68}, ++ {0x32E8, 0x02024128}, ++ {0x32EC, 0x888C272B}, ++ {0x32EC, 0x888CA72B}, ++ {0x12AC, 0x12333121}, ++ {0x32AC, 0x12333121}, ++ {0x738, 0x004100CC}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0xC0001080}, ++ {0x7820, 0xC0001080}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0xC0001080}, ++ {0x7820, 0xC0001080}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0xA0000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0xB0000000, 0x00000000}, ++ {0x2000, 0x18BBBF84}, ++ {0x0F0, 0x00000002}, ++ {0x0F4, 0x00000016}, ++ {0x0F8, 0x20201013}, ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_radioa_regs[] = { ++ {0xF0010000, 0x00000000}, ++ {0xF0010001, 0x00000001}, ++ {0xF0020001, 0x00000002}, ++ {0xF0030001, 0x00000003}, ++ {0xF0250001, 0x00000004}, ++ {0xF0260001, 0x00000005}, ++ {0xF0320001, 0x00000006}, ++ {0xF0330001, 0x00000007}, ++ {0xF0340001, 0x00000008}, ++ {0xF0350001, 0x00000009}, ++ {0xF0360001, 0x0000000A}, ++ {0xF0010002, 0x0000000B}, ++ {0xF0020002, 0x0000000C}, ++ {0xF0030002, 0x0000000D}, ++ {0xF0250002, 0x0000000E}, ++ {0xF0260002, 0x0000000F}, ++ {0xF0320002, 0x00000010}, ++ {0xF0330002, 0x00000011}, ++ {0xF0340002, 0x00000012}, ++ {0xF0350002, 0x00000013}, ++ {0xF0360002, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x000, 0x00030000}, ++ {0x018, 0x00011124}, ++ {0x000, 0x00033C00}, ++ {0x01A, 0x00040004}, ++ {0x0FE, 0x00000000}, ++ {0x055, 0x00080000}, ++ {0x056, 0x0008FFF0}, ++ {0x057, 0x0000C485}, ++ {0x058, 0x000A4164}, ++ {0x059, 0x00010000}, ++ {0x05A, 0x00060000}, ++ {0x05B, 0x0000A000}, ++ {0x05C, 0x00000000}, ++ {0x05D, 0x0001C013}, ++ {0x05E, 0x00000000}, ++ {0x05F, 0x00001FF0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0xA0000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0xB0000000, 0x00000000}, ++ {0x061, 0x0009F338}, ++ {0x062, 0x0009233A}, ++ {0x063, 0x000D6002}, ++ {0x064, 0x000A0CB0}, ++ {0x065, 0x00030EFE}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xA0000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xB0000000, 0x00000000}, ++ {0x068, 0x00000000}, ++ {0x069, 0x00030F0A}, ++ {0x06A, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0009BC24}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0xA0000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0009BC24}, ++ {0xB0000000, 0x00000000}, ++ {0x0D3, 0x00000143}, ++ {0x043, 0x00005000}, ++ {0x0DD, 0x000003A0}, ++ {0x0B0, 0x000E6700}, ++ {0x0AF, 0x0001F82E}, ++ {0x0B2, 0x000210A7}, ++ {0x0B1, 0x00065FFF}, ++ {0x0BB, 0x000F7A00}, ++ {0x0B3, 0x00013F7A}, ++ {0x0D4, 0x0000000E}, ++ {0x0B7, 0x00001E0C}, ++ {0x0A0, 0x0000004F}, ++ {0x0B4, 0x0007C03E}, ++ {0x0B5, 0x0007E301}, ++ {0x0B6, 0x00080800}, ++ {0x0CA, 0x00002000}, ++ {0x0DD, 0x000003A0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0xA0000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0xB0000000, 0x00000000}, ++ {0x0A1, 0x0006F300}, ++ {0x0A2, 0x00080500}, ++ {0x0A3, 0x0008050B}, ++ {0x0A4, 0x0006DB12}, ++ {0x0A5, 0x00000000}, ++ {0x0A6, 0x00000000}, ++ {0x0A7, 0x00000000}, ++ {0x0A8, 0x00000000}, ++ {0x0A9, 0x00000000}, ++ {0x0AA, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E1333}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E7333}, ++ {0x033, 0x00000002}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000FA000}, ++ {0x033, 0x00000003}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000FA400}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000F5000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x00004001}, ++ {0x03F, 0x00029400}, ++ {0x033, 0x00000006}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00041999}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00034444}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x0004D555}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000A}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000B}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x0008C555}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00081EB8}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00071EB8}, ++ {0x033, 0x0000000E}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00090000}, ++ {0x033, 0x0000000F}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x000DB999}, ++ {0x0ED, 0x00000000}, ++ {0x0ED, 0x00002000}, ++ {0x033, 0x00000002}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x033, 0x00000006}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x0ED, 0x00000000}, ++ {0x018, 0x00001001}, ++ {0x002, 0x0000000D}, ++ {0x0EE, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0xA0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x08F, 0x000D0F7A}, ++ {0x08C, 0x00084584}, ++ {0x0EF, 0x00004000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00001000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000017}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00008000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x0000007C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000100}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x00003338}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000040}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000004BA}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000010}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000080}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EE, 0x00002000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h +new file mode 100644 +index 000000000000..913796506286 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_TABLE_H__ ++#define __RTW89_8852A_TABLE_H__ ++ ++#include "core.h" ++ ++extern const struct rtw89_phy_table rtw89_8852a_phy_bb_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_radioa_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_radiob_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_nctl_table; ++extern const struct rtw89_txpwr_table rtw89_8852a_byr_table; ++extern const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table; ++extern const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg; ++extern const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ ++#endif + +From patchwork Fri Aug 20 04:35:31 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448393 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 43123C432BE + for ; + Fri, 20 Aug 2021 04:37:39 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 130F260F91 + for ; + Fri, 20 Aug 2021 04:37:39 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233877AbhHTEiP (ORCPT + ); + Fri, 20 Aug 2021 00:38:15 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39281 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S236436AbhHTEiL (ORCPT + ); + Fri, 20 Aug 2021 00:38:11 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bTexD004223, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bTexD004223 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:29 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:28 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:27 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 17/24] rtw89: 8852a: add 8852a tables (2 of 5) +Date: Fri, 20 Aug 2021 12:35:31 +0800 +Message-ID: <20210820043538.12424-18-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +PHY and RF parameters are used to set PHY and RF register initially. +Other tables are TX power by rate, limit and swing tables. + +Signed-off-by: Ping-Ke Shih +--- + .../wireless/realtek/rtw89/rtw8852a_table.c | 10000 ++++++++++++++++ + 1 file changed, 10000 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index 81188c6c5f7d..4283c252dd3d 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -9998,3 +9998,10003 @@ static const struct rtw89_reg2_def rtw89_8852a_phy_radioa_regs[] = { + {0x03F, 0x00000057}, + {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, + {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000042}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000047}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000053}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000054}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000059}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000065}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000066}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000077}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000078}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x0EE, 0x00004000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003BEF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00003BE9}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00003BE3}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00003BDD}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003BD7}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x00003BD1}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000035}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000036}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000037}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000038}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000039}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x0000003A}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x0000003B}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000042}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000047}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000053}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000054}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000059}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000065}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000066}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000006B}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000077}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000078}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000007D}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000088}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000089}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000008A}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000008B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008C}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000008D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008E}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000008F}, ++ {0x03F, 0x00000807}, ++ {0x0EE, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00020F3C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x000305BC}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x03C, 0x00000020}, ++ {0x03D, 0x00000078}, ++ {0x03E, 0x00080000}, ++ {0x03F, 0x00001999}, ++ {0x0EC, 0x00000000}, ++ {0x02F, 0x0002260D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000002}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000002}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000002}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000400}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, + +From patchwork Fri Aug 20 04:35:32 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448401 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id CBB86C4320E + for ; + Fri, 20 Aug 2021 04:37:44 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 98D8060F91 + for ; + Fri, 20 Aug 2021 04:37:44 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S235425AbhHTEiU (ORCPT + ); + Fri, 20 Aug 2021 00:38:20 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39284 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232904AbhHTEiS (ORCPT + ); + Fri, 20 Aug 2021 00:38:18 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bZzA5004242, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bZzA5004242 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:35 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:34 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:33 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 18/24] rtw89: 8852a: add 8852a tables (3 of 5) +Date: Fri, 20 Aug 2021 12:35:32 +0800 +Message-ID: <20210820043538.12424-19-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +PHY and RF parameters are used to set PHY and RF register initially. +Other tables are TX power by rate, limit and swing tables. + +Signed-off-by: Ping-Ke Shih +--- + .../wireless/realtek/rtw89/rtw8852a_table.c | 10000 ++++++++++++++++ + 1 file changed, 10000 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index 4283c252dd3d..9b1d9e9dfb26 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -19998,3 +19998,10003 @@ static const struct rtw89_reg2_def rtw89_8852a_phy_radioa_regs[] = { + {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, + {0x03F, 0x000000FB}, + {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000200}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000018}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x06D, 0x00000C31}, ++ {0x0EF, 0x00020000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000005FF}, ++ {0x0EF, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00022020}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0xA0000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0xB0000000, 0x00000000}, ++ {0x002, 0x00000000}, ++ {0x067, 0x00000052}, ++ ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_radiob_regs[] = { ++ {0xF0010000, 0x00000000}, ++ {0xF0010001, 0x00000001}, ++ {0xF0020001, 0x00000002}, ++ {0xF0030001, 0x00000003}, ++ {0xF0250001, 0x00000004}, ++ {0xF0260001, 0x00000005}, ++ {0xF0320001, 0x00000006}, ++ {0xF0330001, 0x00000007}, ++ {0xF0340001, 0x00000008}, ++ {0xF0350001, 0x00000009}, ++ {0xF0360001, 0x0000000A}, ++ {0xF0010002, 0x0000000B}, ++ {0xF0020002, 0x0000000C}, ++ {0xF0030002, 0x0000000D}, ++ {0xF0250002, 0x0000000E}, ++ {0xF0260002, 0x0000000F}, ++ {0xF0320002, 0x00000010}, ++ {0xF0330002, 0x00000011}, ++ {0xF0340002, 0x00000012}, ++ {0xF0350002, 0x00000013}, ++ {0xF0360002, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x000, 0x00030000}, ++ {0x018, 0x00011124}, ++ {0x000, 0x00033C00}, ++ {0x01A, 0x00040004}, ++ {0x0FE, 0x00000000}, ++ {0x055, 0x00080000}, ++ {0x056, 0x0008FFF0}, ++ {0x057, 0x0000C485}, ++ {0x058, 0x000A4164}, ++ {0x059, 0x00010000}, ++ {0x05A, 0x00060000}, ++ {0x05B, 0x0000A000}, ++ {0x05C, 0x00000000}, ++ {0x05D, 0x0001C013}, ++ {0x05E, 0x00000000}, ++ {0x05F, 0x00001FF0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0xA0000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0xB0000000, 0x00000000}, ++ {0x061, 0x0009F338}, ++ {0x062, 0x0009233A}, ++ {0x063, 0x000D6002}, ++ {0x064, 0x000A0CB0}, ++ {0x065, 0x00030EFE}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xA0000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0xB0000000, 0x00000000}, ++ {0x068, 0x00000000}, ++ {0x069, 0x00030F0A}, ++ {0x06A, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0007BC24}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0xA0000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0007BC24}, ++ {0xB0000000, 0x00000000}, ++ {0x0D3, 0x00000143}, ++ {0x043, 0x00005000}, ++ {0x0DD, 0x000003A0}, ++ {0x0B0, 0x000E6700}, ++ {0x0AF, 0x0001F82E}, ++ {0x0B2, 0x000210A7}, ++ {0x0B1, 0x00065FFF}, ++ {0x0BB, 0x000F7A00}, ++ {0x0B3, 0x00013F7A}, ++ {0x0D4, 0x0000000E}, ++ {0x0B7, 0x00001E0C}, ++ {0x0A0, 0x0000004F}, ++ {0x0B4, 0x0007C03E}, ++ {0x0B5, 0x0007E301}, ++ {0x0B6, 0x00080800}, ++ {0x0CA, 0x00002000}, ++ {0x0DD, 0x000003A0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0xA0000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0xB0000000, 0x00000000}, ++ {0x0A1, 0x0006F300}, ++ {0x0A2, 0x00080500}, ++ {0x0A3, 0x0008050B}, ++ {0x0A4, 0x0006DB12}, ++ {0x0A5, 0x00000000}, ++ {0x0A6, 0x00000000}, ++ {0x0A7, 0x00000000}, ++ {0x0A8, 0x00000000}, ++ {0x0A9, 0x00000000}, ++ {0x0AA, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E1333}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E7333}, ++ {0x033, 0x00000002}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000FA000}, ++ {0x033, 0x00000003}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000FA400}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000F5000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x00004001}, ++ {0x03F, 0x00029400}, ++ {0x033, 0x00000006}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00041999}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00034444}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x0004D555}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000A}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000B}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x0008C555}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00081EB8}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00071EB8}, ++ {0x033, 0x0000000E}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00090000}, ++ {0x033, 0x0000000F}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x000DB999}, ++ {0x0ED, 0x00000000}, ++ {0x0ED, 0x00002000}, ++ {0x033, 0x00000002}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x033, 0x00000006}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x0ED, 0x00000000}, ++ {0x018, 0x00001001}, ++ {0x002, 0x0000000D}, ++ {0x0EE, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0xA0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x08F, 0x000D0F7A}, ++ {0x08C, 0x00084584}, ++ {0x0EF, 0x00004000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00001000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000017}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000017}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00008000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x0000007C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000100}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x00003338}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000040}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000004BA}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000010}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000080}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F258}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F258}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EE, 0x00002000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, + +From patchwork Fri Aug 20 04:35:33 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448407 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 33DDEC43214 + for ; + Fri, 20 Aug 2021 04:37:49 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 018EB60F91 + for ; + Fri, 20 Aug 2021 04:37:48 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S235342AbhHTEiZ (ORCPT + ); + Fri, 20 Aug 2021 00:38:25 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39288 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S232524AbhHTEiY (ORCPT + ); + Fri, 20 Aug 2021 00:38:24 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bfT43004246, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bfT43004246 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:41 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:41 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:39 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 19/24] rtw89: 8852a: add 8852a tables (4 of 5) +Date: Fri, 20 Aug 2021 12:35:33 +0800 +Message-ID: <20210820043538.12424-20-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +PHY and RF parameters are used to set PHY and RF register initially. +Other tables are TX power by rate, limit and swing tables. + +Signed-off-by: Ping-Ke Shih +--- + .../wireless/realtek/rtw89/rtw8852a_table.c | 10000 ++++++++++++++++ + 1 file changed, 10000 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index 9b1d9e9dfb26..b75aa6a8159f 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -29998,3 +29998,10003 @@ static const struct rtw89_reg2_def rtw89_8852a_phy_radiob_regs[] = { + {0x03F, 0x000000DD}, + {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, + {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000042}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000047}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000053}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000054}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000059}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000065}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000066}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000077}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000078}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x0EE, 0x00004000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003BEF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00003BE9}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00003BE3}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00003BDD}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003BD7}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x00003BD1}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000035}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000036}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000037}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000038}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000039}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x0000003A}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x0000003B}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000042}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000047}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000053}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000054}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000059}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000065}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000066}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000006B}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000077}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000078}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000007D}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000088}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000089}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000008A}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000008B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008C}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000008D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008E}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000008F}, ++ {0x03F, 0x00000807}, ++ {0x0EE, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00020F3C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x000305BC}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x03C, 0x00000020}, ++ {0x03D, 0x00000078}, ++ {0x03E, 0x00080000}, ++ {0x03F, 0x00001999}, ++ {0x0EC, 0x00000000}, ++ {0x02F, 0x0002260D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000002}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000002}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000002}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000400}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, + +From patchwork Fri Aug 20 04:35:34 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448403 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 504F4C4338F + for ; + Fri, 20 Aug 2021 04:37:58 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 2124E60EB5 + for ; + Fri, 20 Aug 2021 04:37:58 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S233691AbhHTEid (ORCPT + ); + Fri, 20 Aug 2021 00:38:33 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39293 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S235243AbhHTEia (ORCPT + ); + Fri, 20 Aug 2021 00:38:30 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4bmd57004262, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4bmd57004262 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:48 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:47 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:46 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 20/24] rtw89: 8852a: add 8852a tables (5 of 5) +Date: Fri, 20 Aug 2021 12:35:34 +0800 +Message-ID: <20210820043538.12424-21-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +PHY and RF parameters are used to set PHY and RF register initially. +Other tables are TX power by rate, limit and swing tables. + +Signed-off-by: Ping-Ke Shih +--- + .../wireless/realtek/rtw89/rtw8852a_table.c | 8725 +++++++++++++++++ + 1 file changed, 8725 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index b75aa6a8159f..60e1df4e7310 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -39998,3 +39998,8728 @@ static const struct rtw89_reg2_def rtw89_8852a_phy_radiob_regs[] = { + {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, + {0x03F, 0x0000013F}, + {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000200}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000018}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x06D, 0x00000C31}, ++ {0x0EF, 0x00020000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000005FF}, ++ {0x0EF, 0x00000000}, ++ {0x0A0, 0x00000043}, ++ {0x005, 0x00000001}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00022020}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0xA0000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0xB0000000, 0x00000000}, ++ {0x002, 0x00000000}, ++ {0x067, 0x00000052}, ++ ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_nctl_regs[] = { ++ {0x8000, 0x00000008}, ++ {0x8008, 0x00000000}, ++ {0x8004, 0xf0862966}, ++ {0x800c, 0x78000000}, ++ {0x8010, 0x88015000}, ++ {0x8014, 0x80010100}, ++ {0x8018, 0x10010100}, ++ {0x801c, 0xa210bc00}, ++ {0x8020, 0x000403e0}, ++ {0x8024, 0x00072160}, ++ {0x8028, 0x00180e00}, ++ {0x8030, 0x400000c0}, ++ {0x8034, 0x56000800}, ++ {0x8038, 0x00000009}, ++ {0x803c, 0x00000008}, ++ {0x8040, 0x00000046}, ++ {0x8044, 0x0010001f}, ++ {0x8048, 0xf0000003}, ++ {0x804c, 0x62ac6162}, ++ {0x8050, 0xf2acf162}, ++ {0x8054, 0x62ac6162}, ++ {0x8058, 0xf2acf162}, ++ {0x805c, 0x150c0b02}, ++ {0x8060, 0x150c0b02}, ++ {0x8064, 0x2aa00047}, ++ {0x8074, 0x80000000}, ++ {0x807c, 0x000000ee}, ++ {0x8088, 0x80000000}, ++ {0x8098, 0x0000ff00}, ++ {0x809c, 0x0000001f}, ++ {0x80a0, 0x00010300}, ++ {0x80b0, 0x00000000}, ++ {0x80d0, 0x00000000}, ++ {0x8114, 0x00000000}, ++ {0x8120, 0x10010000}, ++ {0x8124, 0x00000000}, ++ {0x812c, 0x0000c000}, ++ {0x8138, 0x40000002}, ++ {0x813c, 0x40000002}, ++ {0x8140, 0x00000000}, ++ {0x8144, 0x0b040b03}, ++ {0x8148, 0x0b040b04}, ++ {0x814c, 0x0b040b03}, ++ {0x8150, 0x00000000}, ++ {0x8158, 0xffffffff}, ++ {0x815c, 0xffffffff}, ++ {0x8160, 0xffffffff}, ++ {0x8164, 0xffffffff}, ++ {0x8168, 0xffffffff}, ++ {0x816c, 0x1fffffff}, ++ {0x81ac, 0x003f1a00}, ++ {0x81b0, 0x003f1a00}, ++ {0x81bc, 0x005b5b5b}, ++ {0x81c0, 0x005b5b5b}, ++ {0x81b4, 0x00600060}, ++ {0x81b8, 0x00600060}, ++ {0x81cc, 0x00000000}, ++ {0x81dc, 0x00000002}, ++ {0x8214, 0x00000000}, ++ {0x8220, 0x10010000}, ++ {0x8224, 0x00000000}, ++ {0x822c, 0x0000d000}, ++ {0x8238, 0x40000002}, ++ {0x823c, 0x40000002}, ++ {0x8240, 0x00000000}, ++ {0x8244, 0x0b040b03}, ++ {0x8248, 0x0b040b03}, ++ {0x824c, 0x0b030b03}, ++ {0x8250, 0x00000000}, ++ {0x8258, 0xffffffff}, ++ {0x825c, 0xffffffff}, ++ {0x8260, 0xffffffff}, ++ {0x8264, 0xffffffff}, ++ {0x8268, 0xffffffff}, ++ {0x826c, 0x1fffffff}, ++ {0x82ac, 0x003f1a00}, ++ {0x82b0, 0x003f1a00}, ++ {0x82bc, 0x005b5b5b}, ++ {0x82c0, 0x005b5b5b}, ++ {0x82b4, 0x00600060}, ++ {0x82b8, 0x00600060}, ++ {0x82cc, 0x00000000}, ++ {0x82dc, 0x00000002}, ++ {0x81d8, 0x00000001}, ++ {0x82d8, 0x00000001}, ++ {0x8d00, 0x00000000}, ++ {0x8d04, 0x00000000}, ++ {0x8d08, 0x00000000}, ++ {0x8d0c, 0x00000000}, ++ {0x8d10, 0x00000000}, ++ {0x8d14, 0x00000000}, ++ {0x8d18, 0x00000000}, ++ {0x8d1c, 0x00000000}, ++ {0x8d20, 0x00000000}, ++ {0x8d24, 0x00000000}, ++ {0x8d28, 0x00000000}, ++ {0x8d2c, 0x00000000}, ++ {0x8d30, 0x00000000}, ++ {0x8d34, 0x00000000}, ++ {0x8d38, 0x00000000}, ++ {0x8d3c, 0x00000000}, ++ {0x8d40, 0x00000000}, ++ {0x8d44, 0x00000000}, ++ {0x8d48, 0x00000000}, ++ {0x8d4c, 0x00000000}, ++ {0x8d50, 0x00000000}, ++ {0x8d54, 0x00000000}, ++ {0x8d58, 0x00000000}, ++ {0x8d5c, 0x00000000}, ++ {0x8d60, 0x00000000}, ++ {0x8d64, 0x00000000}, ++ {0x8d68, 0x00000000}, ++ {0x8d6c, 0x00000000}, ++ {0x8d70, 0x00000000}, ++ {0x8d74, 0x00000000}, ++ {0x8d78, 0x00000000}, ++ {0x8d7c, 0x00000000}, ++ {0x8d80, 0x00000000}, ++ {0x8d84, 0x00000000}, ++ {0x8d88, 0x00000000}, ++ {0x8d8c, 0x00000000}, ++ {0x8d90, 0x00000000}, ++ {0x8d94, 0x00000000}, ++ {0x8d98, 0x00000000}, ++ {0x8d9c, 0x00000000}, ++ {0x8da0, 0x00000000}, ++ {0x8da4, 0x00000000}, ++ {0x8da8, 0x00000000}, ++ {0x8dac, 0x00000000}, ++ {0x8db0, 0x00000000}, ++ {0x8db4, 0x00000000}, ++ {0x8db8, 0x00000000}, ++ {0x8dbc, 0x00000000}, ++ {0x8dc0, 0x00000000}, ++ {0x8dc4, 0x00000000}, ++ {0x8dc8, 0x00000000}, ++ {0x8dcc, 0x00000000}, ++ {0x8dd0, 0x00000000}, ++ {0x8dd4, 0x00000000}, ++ {0x8dd8, 0x00000000}, ++ {0x8ddc, 0x00000000}, ++ {0x8de0, 0x00000000}, ++ {0x8de4, 0x00000000}, ++ {0x8de8, 0x00000000}, ++ {0x8dec, 0x00000000}, ++ {0x8df0, 0x00000000}, ++ {0x8df4, 0x00000000}, ++ {0x8df8, 0x00000000}, ++ {0x8dfc, 0x00000000}, ++ {0x8e00, 0x00000000}, ++ {0x8e04, 0x00000000}, ++ {0x8e08, 0x00000000}, ++ {0x8e0c, 0x00000000}, ++ {0x8e10, 0x00000000}, ++ {0x8e14, 0x00000000}, ++ {0x8e18, 0x00000000}, ++ {0x8e1c, 0x00000000}, ++ {0x8e20, 0x00000000}, ++ {0x8e24, 0x00000000}, ++ {0x8e28, 0x00000000}, ++ {0x8e2c, 0x00000000}, ++ {0x8e30, 0x00000000}, ++ {0x8e34, 0x00000000}, ++ {0x8e38, 0x00000000}, ++ {0x8e3c, 0x00000000}, ++ {0x8e40, 0x00000000}, ++ {0x8e44, 0x00000000}, ++ {0x8e48, 0x00000000}, ++ {0x8e4c, 0x00000000}, ++ {0x8e50, 0x00000000}, ++ {0x8e54, 0x00000000}, ++ {0x8e58, 0x00000000}, ++ {0x8e5c, 0x00000000}, ++ {0x8e60, 0x00000000}, ++ {0x8e64, 0x00000000}, ++ {0x8e68, 0x00000000}, ++ {0x8e6c, 0x00000000}, ++ {0x8e70, 0x00000000}, ++ {0x8e74, 0x00000000}, ++ {0x8e78, 0x00000000}, ++ {0x8e7c, 0x00000000}, ++ {0x8e80, 0x00000000}, ++ {0x8e84, 0x00000000}, ++ {0x8e88, 0x00000000}, ++ {0x8e8c, 0x00000000}, ++ {0x8e90, 0x00000000}, ++ {0x8e94, 0x00000000}, ++ {0x8e98, 0x00000000}, ++ {0x8e9c, 0x00000000}, ++ {0x8ea0, 0x00000000}, ++ {0x8ea4, 0x00000000}, ++ {0x8ea8, 0x00000000}, ++ {0x8eac, 0x00000000}, ++ {0x8eb0, 0x00000000}, ++ {0x8eb4, 0x00000000}, ++ {0x8eb8, 0x00000000}, ++ {0x8ebc, 0x00000000}, ++ {0x8ec0, 0x00000000}, ++ {0x8ec4, 0x00000000}, ++ {0x8ec8, 0x00000000}, ++ {0x8ecc, 0x00000000}, ++ {0x8ed0, 0x00000000}, ++ {0x8ed4, 0x00000000}, ++ {0x8ed8, 0x00000000}, ++ {0x8edc, 0x00000000}, ++ {0x8ee0, 0x00000000}, ++ {0x8ee4, 0x00000000}, ++ {0x8ee8, 0x00000000}, ++ {0x8eec, 0x00000000}, ++ {0x8ef0, 0x00000000}, ++ {0x8ef4, 0x00000000}, ++ {0x8ef8, 0x00000000}, ++ {0x8efc, 0x00000000}, ++ {0x8f00, 0x00000000}, ++ {0x8f04, 0x00000000}, ++ {0x8f08, 0x00000000}, ++ {0x8f0c, 0x00000000}, ++ {0x8f10, 0x00000000}, ++ {0x8f14, 0x00000000}, ++ {0x8f18, 0x00000000}, ++ {0x8f1c, 0x00000000}, ++ {0x8f20, 0x00000000}, ++ {0x8f24, 0x00000000}, ++ {0x8f28, 0x00000000}, ++ {0x8f2c, 0x00000000}, ++ {0x8f30, 0x00000000}, ++ {0x8f34, 0x00000000}, ++ {0x8f38, 0x00000000}, ++ {0x8f3c, 0x00000000}, ++ {0x8f40, 0x00000000}, ++ {0x8f44, 0x00000000}, ++ {0x8f48, 0x00000000}, ++ {0x8f4c, 0x00000000}, ++ {0x8f50, 0x00000000}, ++ {0x8f54, 0x00000000}, ++ {0x8f58, 0x00000000}, ++ {0x8f5c, 0x00000000}, ++ {0x8f60, 0x00000000}, ++ {0x8f64, 0x00000000}, ++ {0x8f68, 0x00000000}, ++ {0x8f6c, 0x00000000}, ++ {0x8f70, 0x00000000}, ++ {0x8f74, 0x00000000}, ++ {0x8f78, 0x00000000}, ++ {0x8f7c, 0x00000000}, ++ {0x8f80, 0x00000000}, ++ {0x8f84, 0x00000000}, ++ {0x8f88, 0x00000000}, ++ {0x8f8c, 0x00000000}, ++ {0x8f90, 0x00000000}, ++ {0x8f94, 0x00000000}, ++ {0x8f98, 0x00000000}, ++ {0x8f9c, 0x00000000}, ++ {0x8fa0, 0x00000000}, ++ {0x8fa4, 0x00000000}, ++ {0x8fa8, 0x00000000}, ++ {0x8fac, 0x00000000}, ++ {0x8fb0, 0x00000000}, ++ {0x8fb4, 0x00000000}, ++ {0x8fb8, 0x00000000}, ++ {0x8fbc, 0x00000000}, ++ {0x8fc0, 0x00000000}, ++ {0x8fc4, 0x00000000}, ++ {0x8fc8, 0x00000000}, ++ {0x8fcc, 0x00000000}, ++ {0x8fd0, 0x00000000}, ++ {0x8fd4, 0x00000000}, ++ {0x8fd8, 0x00000000}, ++ {0x8fdc, 0x00000000}, ++ {0x8fe0, 0x00000000}, ++ {0x8fe4, 0x00000000}, ++ {0x8fe8, 0x00000000}, ++ {0x8fec, 0x00000000}, ++ {0x8ff0, 0x00000000}, ++ {0x8ff4, 0x00000000}, ++ {0x8ff8, 0x00000000}, ++ {0x8ffc, 0x00000000}, ++ {0x9000, 0x00000000}, ++ {0x9004, 0x00000000}, ++ {0x9008, 0x00000000}, ++ {0x900c, 0x00000000}, ++ {0x9010, 0x00000000}, ++ {0x9014, 0x00000000}, ++ {0x9018, 0x00000000}, ++ {0x901c, 0x00000000}, ++ {0x9020, 0x00000000}, ++ {0x9024, 0x00000000}, ++ {0x9028, 0x00000000}, ++ {0x902c, 0x00000000}, ++ {0x9030, 0x00000000}, ++ {0x9034, 0x00000000}, ++ {0x9038, 0x00000000}, ++ {0x903c, 0x00000000}, ++ {0x9040, 0x00000000}, ++ {0x9044, 0x00000000}, ++ {0x9048, 0x00000000}, ++ {0x904c, 0x00000000}, ++ {0x9050, 0x00000000}, ++ {0x9054, 0x00000000}, ++ {0x9058, 0x00000000}, ++ {0x905c, 0x00000000}, ++ {0x9060, 0x00000000}, ++ {0x9064, 0x00000000}, ++ {0x9068, 0x00000000}, ++ {0x906c, 0x00000000}, ++ {0x9070, 0x00000000}, ++ {0x9074, 0x00000000}, ++ {0x9078, 0x00000000}, ++ {0x907c, 0x00000000}, ++ {0x9080, 0x00000000}, ++ {0x9084, 0x00000000}, ++ {0x9088, 0x00000000}, ++ {0x908c, 0x00000000}, ++ {0x9090, 0x00000000}, ++ {0x9094, 0x00000000}, ++ {0x9098, 0x00000000}, ++ {0x909c, 0x00000000}, ++ {0x90a0, 0x00000000}, ++ {0x90a4, 0x00000000}, ++ {0x90a8, 0x00000000}, ++ {0x90ac, 0x00000000}, ++ {0x90b0, 0x00000000}, ++ {0x90b4, 0x00000000}, ++ {0x90b8, 0x00000000}, ++ {0x90bc, 0x00000000}, ++ {0x9100, 0x00000000}, ++ {0x9104, 0x00000000}, ++ {0x9108, 0x00000000}, ++ {0x910c, 0x00000000}, ++ {0x9110, 0x00000000}, ++ {0x9114, 0x00000000}, ++ {0x9118, 0x00000000}, ++ {0x911c, 0x00000000}, ++ {0x9120, 0x00000000}, ++ {0x9124, 0x00000000}, ++ {0x9128, 0x00000000}, ++ {0x912c, 0x00000000}, ++ {0x9130, 0x00000000}, ++ {0x9134, 0x00000000}, ++ {0x9138, 0x00000000}, ++ {0x913c, 0x00000000}, ++ {0x9140, 0x00000000}, ++ {0x9144, 0x00000000}, ++ {0x9148, 0x00000000}, ++ {0x914c, 0x00000000}, ++ {0x9150, 0x00000000}, ++ {0x9154, 0x00000000}, ++ {0x9158, 0x00000000}, ++ {0x915c, 0x00000000}, ++ {0x9160, 0x00000000}, ++ {0x9164, 0x00000000}, ++ {0x9168, 0x00000000}, ++ {0x916c, 0x00000000}, ++ {0x9170, 0x00000000}, ++ {0x9174, 0x00000000}, ++ {0x9178, 0x00000000}, ++ {0x917c, 0x00000000}, ++ {0x9180, 0x00000000}, ++ {0x9184, 0x00000000}, ++ {0x9188, 0x00000000}, ++ {0x918c, 0x00000000}, ++ {0x9190, 0x00000000}, ++ {0x9194, 0x00000000}, ++ {0x9198, 0x00000000}, ++ {0x919c, 0x00000000}, ++ {0x91a0, 0x00000000}, ++ {0x91a4, 0x00000000}, ++ {0x91a8, 0x00000000}, ++ {0x91ac, 0x00000000}, ++ {0x91b0, 0x00000000}, ++ {0x91b4, 0x00000000}, ++ {0x91b8, 0x00000000}, ++ {0x91bc, 0x00000000}, ++ {0x91c0, 0x00000000}, ++ {0x91c4, 0x00000000}, ++ {0x91c8, 0x00000000}, ++ {0x91cc, 0x00000000}, ++ {0x91d0, 0x00000000}, ++ {0x91d4, 0x00000000}, ++ {0x91d8, 0x00000000}, ++ {0x91dc, 0x00000000}, ++ {0x91e0, 0x00000000}, ++ {0x91e4, 0x00000000}, ++ {0x91e8, 0x00000000}, ++ {0x91ec, 0x00000000}, ++ {0x91f0, 0x00000000}, ++ {0x91f4, 0x00000000}, ++ {0x91f8, 0x00000000}, ++ {0x91fc, 0x00000000}, ++ {0x9200, 0x00000000}, ++ {0x9204, 0x00000000}, ++ {0x9208, 0x00000000}, ++ {0x920c, 0x00000000}, ++ {0x9210, 0x00000000}, ++ {0x9214, 0x00000000}, ++ {0x9218, 0x00000000}, ++ {0x921c, 0x00000000}, ++ {0x9220, 0x00000000}, ++ {0x9224, 0x00000000}, ++ {0x9228, 0x00000000}, ++ {0x922c, 0x00000000}, ++ {0x9230, 0x00000000}, ++ {0x9234, 0x00000000}, ++ {0x9238, 0x00000000}, ++ {0x923c, 0x00000000}, ++ {0x9240, 0x00000000}, ++ {0x9244, 0x00000000}, ++ {0x9248, 0x00000000}, ++ {0x924c, 0x00000000}, ++ {0x9250, 0x00000000}, ++ {0x9254, 0x00000000}, ++ {0x9258, 0x00000000}, ++ {0x925c, 0x00000000}, ++ {0x9260, 0x00000000}, ++ {0x9264, 0x00000000}, ++ {0x9268, 0x00000000}, ++ {0x926c, 0x00000000}, ++ {0x9270, 0x00000000}, ++ {0x9274, 0x00000000}, ++ {0x9278, 0x00000000}, ++ {0x927c, 0x00000000}, ++ {0x9280, 0x00000000}, ++ {0x9284, 0x00000000}, ++ {0x9288, 0x00000000}, ++ {0x928c, 0x00000000}, ++ {0x9290, 0x00000000}, ++ {0x9294, 0x00000000}, ++ {0x9298, 0x00000000}, ++ {0x929c, 0x00000000}, ++ {0x92a0, 0x00000000}, ++ {0x92a4, 0x00000000}, ++ {0x92a8, 0x00000000}, ++ {0x92ac, 0x00000000}, ++ {0x92b0, 0x00000000}, ++ {0x92b4, 0x00000000}, ++ {0x92b8, 0x00000000}, ++ {0x92bc, 0x00000000}, ++ {0x92c0, 0x00000000}, ++ {0x92c4, 0x00000000}, ++ {0x92c8, 0x00000000}, ++ {0x92cc, 0x00000000}, ++ {0x92d0, 0x00000000}, ++ {0x92d4, 0x00000000}, ++ {0x92d8, 0x00000000}, ++ {0x92dc, 0x00000000}, ++ {0x92e0, 0x00000000}, ++ {0x92e4, 0x00000000}, ++ {0x92e8, 0x00000000}, ++ {0x92ec, 0x00000000}, ++ {0x92f0, 0x00000000}, ++ {0x92f4, 0x00000000}, ++ {0x92f8, 0x00000000}, ++ {0x92fc, 0x00000000}, ++ {0x9300, 0x00000000}, ++ {0x9304, 0x00000000}, ++ {0x9308, 0x00000000}, ++ {0x930c, 0x00000000}, ++ {0x9310, 0x00000000}, ++ {0x9314, 0x00000000}, ++ {0x9318, 0x00000000}, ++ {0x931c, 0x00000000}, ++ {0x9320, 0x00000000}, ++ {0x9324, 0x00000000}, ++ {0x9328, 0x00000000}, ++ {0x932c, 0x00000000}, ++ {0x9330, 0x00000000}, ++ {0x9334, 0x00000000}, ++ {0x9338, 0x00000000}, ++ {0x933c, 0x00000000}, ++ {0x9340, 0x00000000}, ++ {0x9344, 0x00000000}, ++ {0x9348, 0x00000000}, ++ {0x934c, 0x00000000}, ++ {0x9350, 0x00000000}, ++ {0x9354, 0x00000000}, ++ {0x9358, 0x00000000}, ++ {0x935c, 0x00000000}, ++ {0x9360, 0x00000000}, ++ {0x9364, 0x00000000}, ++ {0x9368, 0x00000000}, ++ {0x936c, 0x00000000}, ++ {0x9370, 0x00000000}, ++ {0x9374, 0x00000000}, ++ {0x9378, 0x00000000}, ++ {0x937c, 0x00000000}, ++ {0x9380, 0x00000000}, ++ {0x9384, 0x00000000}, ++ {0x9388, 0x00000000}, ++ {0x938c, 0x00000000}, ++ {0x9390, 0x00000000}, ++ {0x9394, 0x00000000}, ++ {0x9398, 0x00000000}, ++ {0x939c, 0x00000000}, ++ {0x93a0, 0x00000000}, ++ {0x93a4, 0x00000000}, ++ {0x93a8, 0x00000000}, ++ {0x93ac, 0x00000000}, ++ {0x93b0, 0x00000000}, ++ {0x93b4, 0x00000000}, ++ {0x93b8, 0x00000000}, ++ {0x93bc, 0x00000000}, ++ {0x93c0, 0x00000000}, ++ {0x93c4, 0x00000000}, ++ {0x93c8, 0x00000000}, ++ {0x93cc, 0x00000000}, ++ {0x93d0, 0x00000000}, ++ {0x93d4, 0x00000000}, ++ {0x93d8, 0x00000000}, ++ {0x93dc, 0x00000000}, ++ {0x93e0, 0x00000000}, ++ {0x93e4, 0x00000000}, ++ {0x93e8, 0x00000000}, ++ {0x93ec, 0x00000000}, ++ {0x93f0, 0x00000000}, ++ {0x93f4, 0x00000000}, ++ {0x93f8, 0x00000000}, ++ {0x93fc, 0x00000000}, ++ {0x9400, 0x00000000}, ++ {0x9404, 0x00000000}, ++ {0x9408, 0x00000000}, ++ {0x940c, 0x00000000}, ++ {0x9410, 0x00000000}, ++ {0x9414, 0x00000000}, ++ {0x9418, 0x00000000}, ++ {0x941c, 0x00000000}, ++ {0x9420, 0x00000000}, ++ {0x9424, 0x00000000}, ++ {0x9428, 0x00000000}, ++ {0x942c, 0x00000000}, ++ {0x9430, 0x00000000}, ++ {0x9434, 0x00000000}, ++ {0x9438, 0x00000000}, ++ {0x943c, 0x00000000}, ++ {0x9440, 0x00000000}, ++ {0x9444, 0x00000000}, ++ {0x9448, 0x00000000}, ++ {0x944c, 0x00000000}, ++ {0x9450, 0x00000000}, ++ {0x9454, 0x00000000}, ++ {0x9458, 0x00000000}, ++ {0x945c, 0x00000000}, ++ {0x9460, 0x00000000}, ++ {0x9464, 0x00000000}, ++ {0x9468, 0x00000000}, ++ {0x946c, 0x00000000}, ++ {0x9470, 0x00000000}, ++ {0x9474, 0x00000000}, ++ {0x9478, 0x00000000}, ++ {0x947c, 0x00000000}, ++ {0x9480, 0x00000000}, ++ {0x9484, 0x00000000}, ++ {0x9488, 0x00000000}, ++ {0x948c, 0x00000000}, ++ {0x9490, 0x00000000}, ++ {0x9494, 0x00000000}, ++ {0x9498, 0x00000000}, ++ {0x949c, 0x00000000}, ++ {0x94a0, 0x00000000}, ++ {0x94a4, 0x00000000}, ++ {0x94a8, 0x00000000}, ++ {0x94ac, 0x00000000}, ++ {0x94b0, 0x00000000}, ++ {0x94b4, 0x00000000}, ++ {0x94b8, 0x00000000}, ++ {0x94bc, 0x00000000}, ++ {0x81d8, 0x00000000}, ++ {0x82d8, 0x00000000}, ++ {0x9f04, 0x2b251f19}, ++ {0x9f08, 0x433d3731}, ++ {0x9f0c, 0x5b554f49}, ++ {0x9f10, 0x736d6761}, ++ {0x9f14, 0x7f7f7f79}, ++ {0x9f18, 0x120f7f7f}, ++ {0x9f1c, 0x1e1b1815}, ++ {0x9f20, 0x2a272421}, ++ {0x9f24, 0x3633302d}, ++ {0x9f28, 0x3f3f3c39}, ++ {0x9f2c, 0x3f3f3f3f}, ++ {0x8088, 0x00000110}, ++ {0x8000, 0x00000008}, ++ {0x8080, 0x00000005}, ++ {0x8500, 0x00060009}, ++ {0x8504, 0x000418b0}, ++ {0x8508, 0x00089c00}, ++ {0x850c, 0x43000004}, ++ {0x8510, 0x4b044a00}, ++ {0x8514, 0x40098603}, ++ {0x8518, 0x4b05e01f}, ++ {0x851c, 0x400b8703}, ++ {0x8520, 0x4b00e01f}, ++ {0x8524, 0x43800004}, ++ {0x8528, 0x4c000007}, ++ {0x852c, 0x43000004}, ++ {0x8530, 0x57007430}, ++ {0x8534, 0x73000006}, ++ {0x8538, 0x50550004}, ++ {0x853c, 0xb4163000}, ++ {0x8540, 0xe37ea510}, ++ {0x8544, 0xf117f017}, ++ {0x8548, 0xf317f217}, ++ {0x854c, 0xf517f417}, ++ {0x8550, 0xf717f617}, ++ {0x8554, 0xf917f817}, ++ {0x8558, 0xfb17fa17}, ++ {0x855c, 0xfd17fc17}, ++ {0x8560, 0xf117f017}, ++ {0x8564, 0xf317f217}, ++ {0x8568, 0xa503f417}, ++ {0x856c, 0xf116f016}, ++ {0x8570, 0x304e0001}, ++ {0x8574, 0x30873053}, ++ {0x8578, 0x30ab30a8}, ++ {0x857c, 0x30b330ae}, ++ {0x8580, 0x30ba30b6}, ++ {0x8584, 0x30d430c7}, ++ {0x8588, 0x310d3100}, ++ {0x858c, 0x31ed3112}, ++ {0x8590, 0x320a31f1}, ++ {0x8594, 0x3243320b}, ++ {0x8598, 0x31e631b1}, ++ {0x859c, 0x5b00e283}, ++ {0x85a0, 0xe2d15500}, ++ {0x85a4, 0xe2830001}, ++ {0x85a8, 0x5b10e2e3}, ++ {0x85ac, 0x20987410}, ++ {0x85b0, 0xe3750200}, ++ {0x85b4, 0x00002080}, ++ {0x85b8, 0x23f0e375}, ++ {0x85bc, 0xe3750001}, ++ {0x85c0, 0x000023f0}, ++ {0x85c4, 0x5507e375}, ++ {0x85c8, 0xe2d5e2d5}, ++ {0x85cc, 0x20887410}, ++ {0x85d0, 0xe3750200}, ++ {0x85d4, 0x000123f0}, ++ {0x85d8, 0x23f0e375}, ++ {0x85dc, 0xe3750000}, ++ {0x85e0, 0xe2d55517}, ++ {0x85e4, 0x4e004f02}, ++ {0x85e8, 0x52015302}, ++ {0x85ec, 0x7508e2d9}, ++ {0x85f0, 0x74207900}, ++ {0x85f4, 0x57005710}, ++ {0x85f8, 0x75fbe375}, ++ {0x85fc, 0x23f07410}, ++ {0x8600, 0xe3750001}, ++ {0x8604, 0x000023f0}, ++ {0x8608, 0x7430e375}, ++ {0x860c, 0x5b100001}, ++ {0x8610, 0x20907410}, ++ {0x8614, 0xe3750000}, ++ {0x8618, 0x000123f0}, ++ {0x861c, 0x23f0e375}, ++ {0x8620, 0xe3750000}, ++ {0x8624, 0xe2d55507}, ++ {0x8628, 0x7410e2d5}, ++ {0x862c, 0x02002098}, ++ {0x8630, 0x23f0e375}, ++ {0x8634, 0xe3750001}, ++ {0x8638, 0x000023f0}, ++ {0x863c, 0x5517e375}, ++ {0x8640, 0x4f02e2d5}, ++ {0x8644, 0x53024e00}, ++ {0x8648, 0xe2d95201}, ++ {0x864c, 0x30787509}, ++ {0x8650, 0xe2e3e283}, ++ {0x8654, 0xe27b0001}, ++ {0x8658, 0x0001e2e3}, ++ {0x865c, 0x5b30e28f}, ++ {0x8660, 0xe2d15500}, ++ {0x8664, 0xe28f0001}, ++ {0x8668, 0x0001e312}, ++ {0x866c, 0x4380e287}, ++ {0x8670, 0x0001e312}, ++ {0x8674, 0x30e2e283}, ++ {0x8678, 0xe3600023}, ++ {0x867c, 0x54ed0002}, ++ {0x8680, 0x00230baa}, ++ {0x8684, 0x0002e360}, ++ {0x8688, 0xe27be330}, ++ {0x868c, 0xe2830001}, ++ {0x8690, 0x002230dd}, ++ {0x8694, 0x0002e360}, ++ {0x8698, 0x0baa54ec}, ++ {0x869c, 0xe3600022}, ++ {0x86a0, 0xe3300002}, ++ {0x86a4, 0x0001e27b}, ++ {0x86a8, 0x0baae283}, ++ {0x86ac, 0x6d0f6c67}, ++ {0x86b0, 0xe360e2e3}, ++ {0x86b4, 0xe2e36c8b}, ++ {0x86b8, 0x0bace360}, ++ {0x86bc, 0x6d0f6cb3}, ++ {0x86c0, 0xe360e2e3}, ++ {0x86c4, 0x6cdb0bad}, ++ {0x86c8, 0xe2e36d0f}, ++ {0x86cc, 0x6cf7e360}, ++ {0x86d0, 0xe2e36d0f}, ++ {0x86d4, 0x6c09e360}, ++ {0x86d8, 0xe2e36d00}, ++ {0x86dc, 0x6c25e360}, ++ {0x86e0, 0xe360e2e3}, ++ {0x86e4, 0x6c4df8ca}, ++ {0x86e8, 0xe360e2e3}, ++ {0x86ec, 0x6c75f9d3}, ++ {0x86f0, 0xe360e2e3}, ++ {0x86f4, 0xe2e36c99}, ++ {0x86f8, 0xe330e360}, ++ {0x86fc, 0x0001e27b}, ++ {0x8700, 0x314de28f}, ++ {0x8704, 0xe3650022}, ++ {0x8708, 0x54ec0002}, ++ {0x870c, 0x00220baa}, ++ {0x8710, 0x0002e365}, ++ {0x8714, 0xe287e330}, ++ {0x8718, 0xe28f0001}, ++ {0x871c, 0xe3303139}, ++ {0x8720, 0x0001e287}, ++ {0x8724, 0x0ba6e28f}, ++ {0x8728, 0x21e07410}, ++ {0x872c, 0x21e80009}, ++ {0x8730, 0x6e670009}, ++ {0x8734, 0xe32b6f0f}, ++ {0x8738, 0xe365e312}, ++ {0x873c, 0x21e07410}, ++ {0x8740, 0x21e8000a}, ++ {0x8744, 0x6e77000a}, ++ {0x8748, 0xe312e32b}, ++ {0x874c, 0x7410e365}, ++ {0x8750, 0x000b21e0}, ++ {0x8754, 0x000b21e8}, ++ {0x8758, 0xe32b6e8b}, ++ {0x875c, 0xe365e312}, ++ {0x8760, 0x21e07410}, ++ {0x8764, 0x21e8000c}, ++ {0x8768, 0x6e9f000c}, ++ {0x876c, 0xe312e32b}, ++ {0x8770, 0x0baae365}, ++ {0x8774, 0x21e07410}, ++ {0x8778, 0x21e8000d}, ++ {0x877c, 0x6eb3000d}, ++ {0x8780, 0xe32b6f0f}, ++ {0x8784, 0xe365e312}, ++ {0x8788, 0x21e07410}, ++ {0x878c, 0x21e8000e}, ++ {0x8790, 0x6ec7000e}, ++ {0x8794, 0xe312e32b}, ++ {0x8798, 0x0bace365}, ++ {0x879c, 0x21e07410}, ++ {0x87a0, 0x21e8000f}, ++ {0x87a4, 0x6edb000f}, ++ {0x87a8, 0xe32b6f0f}, ++ {0x87ac, 0xe365e312}, ++ {0x87b0, 0x21e07410}, ++ {0x87b4, 0x21e80010}, ++ {0x87b8, 0x6eef0010}, ++ {0x87bc, 0xe312e32b}, ++ {0x87c0, 0xe365e365}, ++ {0x87c4, 0x21e07410}, ++ {0x87c8, 0x21e80013}, ++ {0x87cc, 0x6e110013}, ++ {0x87d0, 0xe32b6f00}, ++ {0x87d4, 0xe365e312}, ++ {0x87d8, 0x7410e365}, ++ {0x87dc, 0x001421e0}, ++ {0x87e0, 0x001421e8}, ++ {0x87e4, 0xe32b6e25}, ++ {0x87e8, 0xe365e312}, ++ {0x87ec, 0x7410fb8c}, ++ {0x87f0, 0x001521e0}, ++ {0x87f4, 0x001521e8}, ++ {0x87f8, 0xe32b6e39}, ++ {0x87fc, 0xe365e312}, ++ {0x8800, 0x21e07410}, ++ {0x8804, 0x21e80016}, ++ {0x8808, 0x6e4d0016}, ++ {0x880c, 0xe312e32b}, ++ {0x8810, 0xfc86e365}, ++ {0x8814, 0x21e07410}, ++ {0x8818, 0x21e80017}, ++ {0x881c, 0x6e610017}, ++ {0x8820, 0xe312e32b}, ++ {0x8824, 0x7410e365}, ++ {0x8828, 0x001821e0}, ++ {0x882c, 0x001821e8}, ++ {0x8830, 0xe32b6e75}, ++ {0x8834, 0xe365e312}, ++ {0x8838, 0x21e07410}, ++ {0x883c, 0x21e80019}, ++ {0x8840, 0x6e890019}, ++ {0x8844, 0xe312e32b}, ++ {0x8848, 0x7410e365}, ++ {0x884c, 0x001a21e0}, ++ {0x8850, 0x001a21e8}, ++ {0x8854, 0xe32b6e99}, ++ {0x8858, 0xe365e312}, ++ {0x885c, 0xe287e330}, ++ {0x8860, 0x00040001}, ++ {0x8864, 0x0007775c}, ++ {0x8868, 0x62006220}, ++ {0x886c, 0x55010004}, ++ {0x8870, 0xe2d15b00}, ++ {0x8874, 0x66055b40}, ++ {0x8878, 0x62000007}, ++ {0x887c, 0xe3506300}, ++ {0x8880, 0xe2d10004}, ++ {0x8884, 0x0a010900}, ++ {0x8888, 0x0d000b40}, ++ {0x888c, 0x00320e01}, ++ {0x8890, 0x95060004}, ++ {0x8894, 0x00074380}, ++ {0x8898, 0x00044d01}, ++ {0x889c, 0x00074300}, ++ {0x88a0, 0x05a30562}, ++ {0x88a4, 0xe3509617}, ++ {0x88a8, 0xe2d10004}, ++ {0x88ac, 0x06a20007}, ++ {0x88b0, 0xe35007a3}, ++ {0x88b4, 0xe2d10004}, ++ {0x88b8, 0x0002e340}, ++ {0x88bc, 0x4380e348}, ++ {0x88c0, 0x4d000007}, ++ {0x88c4, 0x43000004}, ++ {0x88c8, 0x00017900}, ++ {0x88cc, 0x775e0004}, ++ {0x88d0, 0x000731b3}, ++ {0x88d4, 0x07a306a2}, ++ {0x88d8, 0xe29331dd}, ++ {0x88dc, 0x73000005}, ++ {0x88e0, 0xe2930001}, ++ {0x88e4, 0x5d000006}, ++ {0x88e8, 0x42f70004}, ++ {0x88ec, 0x6c000005}, ++ {0x88f0, 0x42000004}, ++ {0x88f4, 0x0004e2ab}, ++ {0x88f8, 0x00074380}, ++ {0x88fc, 0x4a004e00}, ++ {0x8900, 0x00064c00}, ++ {0x8904, 0x60007f00}, ++ {0x8908, 0x00046f00}, ++ {0x890c, 0x00054300}, ++ {0x8910, 0x00017300}, ++ {0x8914, 0xe2930001}, ++ {0x8918, 0x5d010006}, ++ {0x891c, 0x61006002}, ++ {0x8920, 0x00055601}, ++ {0x8924, 0xe2ab7710}, ++ {0x8928, 0x73000005}, ++ {0x892c, 0x43800004}, ++ {0x8930, 0x5e010007}, ++ {0x8934, 0x4d205e00}, ++ {0x8938, 0x4a084e20}, ++ {0x893c, 0x4c3f4960}, ++ {0x8940, 0x00064301}, ++ {0x8944, 0x63807f01}, ++ {0x8948, 0x00046010}, ++ {0x894c, 0x00064300}, ++ {0x8950, 0x00077402}, ++ {0x8954, 0x40004001}, ++ {0x8958, 0x0006ab00}, ++ {0x895c, 0x00077404}, ++ {0x8960, 0x40004001}, ++ {0x8964, 0x0004ab00}, ++ {0x8968, 0x00074380}, ++ {0x896c, 0x4e004d00}, ++ {0x8970, 0x4c004a00}, ++ {0x8974, 0x00064300}, ++ {0x8978, 0x63007f00}, ++ {0x897c, 0x6f006000}, ++ {0x8980, 0x43000004}, ++ {0x8984, 0x00040001}, ++ {0x8988, 0x42bf4380}, ++ {0x898c, 0x48400007}, ++ {0x8990, 0x42ef0004}, ++ {0x8994, 0x4d100007}, ++ {0x8998, 0x42000004}, ++ {0x899c, 0x5f800006}, ++ {0x89a0, 0x5a010007}, ++ {0x89a4, 0x00044a08}, ++ {0x89a8, 0x00054300}, ++ {0x89ac, 0x73807381}, ++ {0x89b0, 0x003f9300}, ++ {0x89b4, 0x00000000}, ++ {0x89b8, 0x00000000}, ++ {0x89bc, 0x00020000}, ++ {0x89c0, 0x5f800006}, ++ {0x89c4, 0x99005f00}, ++ {0x89c8, 0x43800004}, ++ {0x89cc, 0x00074280}, ++ {0x89d0, 0x00044800}, ++ {0x89d4, 0x000742ef}, ++ {0x89d8, 0x00044d00}, ++ {0x89dc, 0x00064200}, ++ {0x89e0, 0x60005f00}, ++ {0x89e4, 0x5a000007}, ++ {0x89e8, 0x48004a00}, ++ {0x89ec, 0x43000004}, ++ {0x89f0, 0x73000005}, ++ {0x89f4, 0x43800001}, ++ {0x89f8, 0x78006505}, ++ {0x89fc, 0x7a007900}, ++ {0x8a00, 0x43007b00}, ++ {0x8a04, 0x43800001}, ++ {0x8a08, 0x43006500}, ++ {0x8a0c, 0x43800001}, ++ {0x8a10, 0x7c006405}, ++ {0x8a14, 0x7e007d00}, ++ {0x8a18, 0x43007f00}, ++ {0x8a1c, 0x43800001}, ++ {0x8a20, 0x43006400}, ++ {0x8a24, 0x00060001}, ++ {0x8a28, 0x55025601}, ++ {0x8a2c, 0x00055400}, ++ {0x8a30, 0x7e127f00}, ++ {0x8a34, 0x76007710}, ++ {0x8a38, 0x74007500}, ++ {0x8a3c, 0x42700004}, ++ {0x8a40, 0x73810005}, ++ {0x8a44, 0x00047380}, ++ {0x8a48, 0x93004200}, ++ {0x8a4c, 0x77000005}, ++ {0x8a50, 0x56000006}, ++ {0x8a54, 0x00060001}, ++ {0x8a58, 0x5f005f80}, ++ {0x8a5c, 0x00059900}, ++ {0x8a60, 0x00067300}, ++ {0x8a64, 0x63006380}, ++ {0x8a68, 0x00019800}, ++ {0x8a6c, 0x7b484380}, ++ {0x8a70, 0x79007a90}, ++ {0x8a74, 0x43007802}, ++ {0x8a78, 0x32cd5503}, ++ {0x8a7c, 0x7b384380}, ++ {0x8a80, 0x79007a80}, ++ {0x8a84, 0x43007802}, ++ {0x8a88, 0x32cd5513}, ++ {0x8a8c, 0x7b404380}, ++ {0x8a90, 0x79007a00}, ++ {0x8a94, 0x43007802}, ++ {0x8a98, 0x74315523}, ++ {0x8a9c, 0x8e007430}, ++ {0x8aa0, 0x74010001}, ++ {0x8aa4, 0x8e007400}, ++ {0x8aa8, 0x74310001}, ++ {0x8aac, 0x8e007430}, ++ {0x8ab0, 0x57020001}, ++ {0x8ab4, 0x97005700}, ++ {0x8ab8, 0x42ef0001}, ++ {0x8abc, 0x56005610}, ++ {0x8ac0, 0x8c004200}, ++ {0x8ac4, 0x4f780001}, ++ {0x8ac8, 0x53884e00}, ++ {0x8acc, 0x5b205201}, ++ {0x8ad0, 0x5480e2f2}, ++ {0x8ad4, 0x54815400}, ++ {0x8ad8, 0x54825400}, ++ {0x8adc, 0xe2fd5400}, ++ {0x8ae0, 0x3012bf1d}, ++ {0x8ae4, 0xe2bee2b6}, ++ {0x8ae8, 0xe2d9e2c6}, ++ {0x8aec, 0x5523e359}, ++ {0x8af0, 0x5525e2cd}, ++ {0x8af4, 0xe359e2d9}, ++ {0x8af8, 0x54bf0001}, ++ {0x8afc, 0x54a354c0}, ++ {0x8b00, 0x54a454c1}, ++ {0x8b04, 0xbf074c18}, ++ {0x8b08, 0x54a454c2}, ++ {0x8b0c, 0x54c1bf04}, ++ {0x8b10, 0xbf0154a3}, ++ {0x8b14, 0x54dfe36a}, ++ {0x8b18, 0x54bf0001}, ++ {0x8b1c, 0x050a54e5}, ++ {0x8b20, 0x000154df}, ++ {0x8b24, 0x43807b80}, ++ {0x8b28, 0x7e007f40}, ++ {0x8b2c, 0x7c027d00}, ++ {0x8b30, 0x5b404300}, ++ {0x8b34, 0x5c015501}, ++ {0x8b38, 0x5480e2dd}, ++ {0x8b3c, 0x54815400}, ++ {0x8b40, 0x54825400}, ++ {0x8b44, 0x7b005400}, ++ {0x8b48, 0xbfe8e2fd}, ++ {0x8b4c, 0x56103012}, ++ {0x8b50, 0x8c005600}, ++ {0x8b54, 0xe36d0001}, ++ {0x8b58, 0xe36de36d}, ++ {0x8b5c, 0x0001e36d}, ++ {0x8b60, 0x57005704}, ++ {0x8b64, 0x57089700}, ++ {0x8b68, 0x97005700}, ++ {0x8b6c, 0x57805781}, ++ {0x8b70, 0x43809700}, ++ {0x8b74, 0x5c010007}, ++ {0x8b78, 0x00045c00}, ++ {0x8b7c, 0x00014300}, ++ {0x8b80, 0x0007427f}, ++ {0x8b84, 0x62006280}, ++ {0x8b88, 0x00049200}, ++ {0x8b8c, 0x00014200}, ++ {0x8b90, 0x0007427f}, ++ {0x8b94, 0x63146394}, ++ {0x8b98, 0x00049100}, ++ {0x8b9c, 0x00014200}, ++ {0x8ba0, 0x79010004}, ++ {0x8ba4, 0xe3757420}, ++ {0x8ba8, 0x57005710}, ++ {0x8bac, 0xe375e375}, ++ {0x8bb0, 0x549f0001}, ++ {0x8bb4, 0x5c015400}, ++ {0x8bb8, 0x540054df}, ++ {0x8bbc, 0x00015c02}, ++ {0x8bc0, 0x07145c01}, ++ {0x8bc4, 0x5c025400}, ++ {0x8bc8, 0x5c020001}, ++ {0x8bcc, 0x54000714}, ++ {0x8bd0, 0x00015c01}, ++ {0x8bd4, 0x4c184c98}, ++ {0x8bd8, 0x003f0001}, ++ {0x8bdc, 0x00000000}, ++ {0x8be0, 0x00000000}, ++ {0x8be4, 0x00020000}, ++ {0x8be8, 0x00000001}, ++ {0x8bec, 0x00000000}, ++ {0x8bf0, 0x00000000}, ++ {0x8bf4, 0x00000000}, ++ {0x8bf8, 0x00010000}, ++ {0x8bfc, 0x5c020004}, ++ {0x8c00, 0x66076204}, ++ {0x8c04, 0x743070c0}, ++ {0x8c08, 0x0c010901}, ++ {0x8c0c, 0x00010ba6}, ++ {0x8080, 0x00000004}, ++ {0x8080, 0x00000000}, ++ {0x8088, 0x00000000}, ++}; ++ ++static const struct rtw89_txpwr_byrate_cfg rtw89_8852a_txpwr_byrate[] = { ++ { 0, 0, 0, 0, 4, 0x50505050, }, ++ { 0, 0, 1, 0, 4, 0x50505050, }, ++ { 0, 0, 1, 4, 4, 0x484c5050, }, ++ { 0, 0, 2, 0, 4, 0x50505050, }, ++ { 0, 0, 2, 4, 4, 0x44484c50, }, ++ { 0, 0, 2, 8, 4, 0x34383c40, }, ++ { 0, 0, 3, 0, 4, 0x50505050, }, ++ { 0, 1, 2, 0, 4, 0x50505050, }, ++ { 0, 1, 2, 4, 4, 0x44484c50, }, ++ { 0, 1, 2, 8, 4, 0x34383c40, }, ++ { 0, 1, 3, 0, 4, 0x50505050, }, ++ { 0, 0, 4, 1, 4, 0x00000000, }, ++ { 0, 0, 4, 0, 1, 0x00000000, }, ++ { 1, 0, 1, 0, 4, 0x50505050, }, ++ { 1, 0, 1, 4, 4, 0x484c5050, }, ++ { 1, 0, 2, 0, 4, 0x50505050, }, ++ { 1, 0, 2, 4, 4, 0x44484c50, }, ++ { 1, 0, 2, 8, 4, 0x34383c40, }, ++ { 1, 0, 3, 0, 4, 0x50505050, }, ++ { 1, 1, 2, 0, 4, 0x50505050, }, ++ { 1, 1, 2, 4, 4, 0x44484c50, }, ++ { 1, 1, 2, 8, 4, 0x34383c40, }, ++ { 1, 1, 3, 0, 4, 0x50505050, }, ++ { 1, 0, 4, 0, 4, 0x00000000, }, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5gb_n[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, ++ 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5gb_p[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, ++ 6, 7, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5ga_n[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, ++ 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5ga_p[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, ++ 6, 7, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_2gb_n[] = { ++ 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, ++ 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7}; ++ ++static const u8 _txpwr_track_delta_swingidx_2gb_p[] = { ++ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, ++ 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3}; ++ ++static const u8 _txpwr_track_delta_swingidx_2ga_n[] = { ++ 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, ++ 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5}; ++ ++static const u8 _txpwr_track_delta_swingidx_2ga_p[] = { ++ 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, ++ 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_b_n[] = { ++ 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, ++ 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_b_p[] = { ++ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, ++ 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_a_n[] = { ++ 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, ++ 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = { ++ 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, ++ 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10}; ++ ++const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { ++ [0][0][0][0][0][0] = 56, ++ [0][0][0][0][0][1] = 56, ++ [0][0][0][0][0][2] = 56, ++ [0][0][0][0][0][3] = 56, ++ [0][0][0][0][0][4] = 56, ++ [0][0][0][0][0][5] = 56, ++ [0][0][0][0][0][6] = 56, ++ [0][0][0][0][0][7] = 56, ++ [0][0][0][0][0][8] = 56, ++ [0][0][0][0][0][9] = 56, ++ [0][0][0][0][0][10] = 56, ++ [0][0][0][0][0][11] = 56, ++ [0][0][0][0][0][12] = 48, ++ [0][0][0][0][0][13] = 76, ++ [0][1][0][0][0][0] = 44, ++ [0][1][0][0][0][1] = 44, ++ [0][1][0][0][0][2] = 44, ++ [0][1][0][0][0][3] = 44, ++ [0][1][0][0][0][4] = 44, ++ [0][1][0][0][0][5] = 44, ++ [0][1][0][0][0][6] = 44, ++ [0][1][0][0][0][7] = 44, ++ [0][1][0][0][0][8] = 44, ++ [0][1][0][0][0][9] = 44, ++ [0][1][0][0][0][10] = 44, ++ [0][1][0][0][0][11] = 44, ++ [0][1][0][0][0][12] = 38, ++ [0][1][0][0][0][13] = 64, ++ [1][0][0][0][0][0] = 0, ++ [1][0][0][0][0][1] = 0, ++ [1][0][0][0][0][2] = 58, ++ [1][0][0][0][0][3] = 58, ++ [1][0][0][0][0][4] = 58, ++ [1][0][0][0][0][5] = 58, ++ [1][0][0][0][0][6] = 46, ++ [1][0][0][0][0][7] = 46, ++ [1][0][0][0][0][8] = 46, ++ [1][0][0][0][0][9] = 32, ++ [1][0][0][0][0][10] = 32, ++ [1][0][0][0][0][11] = 0, ++ [1][0][0][0][0][12] = 0, ++ [1][0][0][0][0][13] = 0, ++ [1][1][0][0][0][0] = 0, ++ [1][1][0][0][0][1] = 0, ++ [1][1][0][0][0][2] = 46, ++ [1][1][0][0][0][3] = 46, ++ [1][1][0][0][0][4] = 46, ++ [1][1][0][0][0][5] = 46, ++ [1][1][0][0][0][6] = 46, ++ [1][1][0][0][0][7] = 46, ++ [1][1][0][0][0][8] = 46, ++ [1][1][0][0][0][9] = 24, ++ [1][1][0][0][0][10] = 24, ++ [1][1][0][0][0][11] = 0, ++ [1][1][0][0][0][12] = 0, ++ [1][1][0][0][0][13] = 0, ++ [0][0][1][0][0][0] = 58, ++ [0][0][1][0][0][1] = 58, ++ [0][0][1][0][0][2] = 58, ++ [0][0][1][0][0][3] = 58, ++ [0][0][1][0][0][4] = 58, ++ [0][0][1][0][0][5] = 58, ++ [0][0][1][0][0][6] = 58, ++ [0][0][1][0][0][7] = 58, ++ [0][0][1][0][0][8] = 58, ++ [0][0][1][0][0][9] = 58, ++ [0][0][1][0][0][10] = 58, ++ [0][0][1][0][0][11] = 56, ++ [0][0][1][0][0][12] = 52, ++ [0][0][1][0][0][13] = 0, ++ [0][1][1][0][0][0] = 46, ++ [0][1][1][0][0][1] = 46, ++ [0][1][1][0][0][2] = 46, ++ [0][1][1][0][0][3] = 46, ++ [0][1][1][0][0][4] = 46, ++ [0][1][1][0][0][5] = 46, ++ [0][1][1][0][0][6] = 46, ++ [0][1][1][0][0][7] = 46, ++ [0][1][1][0][0][8] = 46, ++ [0][1][1][0][0][9] = 46, ++ [0][1][1][0][0][10] = 46, ++ [0][1][1][0][0][11] = 42, ++ [0][1][1][0][0][12] = 40, ++ [0][1][1][0][0][13] = 0, ++ [0][0][2][0][0][0] = 58, ++ [0][0][2][0][0][1] = 58, ++ [0][0][2][0][0][2] = 58, ++ [0][0][2][0][0][3] = 58, ++ [0][0][2][0][0][4] = 58, ++ [0][0][2][0][0][5] = 58, ++ [0][0][2][0][0][6] = 58, ++ [0][0][2][0][0][7] = 58, ++ [0][0][2][0][0][8] = 58, ++ [0][0][2][0][0][9] = 58, ++ [0][0][2][0][0][10] = 58, ++ [0][0][2][0][0][11] = 54, ++ [0][0][2][0][0][12] = 50, ++ [0][0][2][0][0][13] = 0, ++ [0][1][2][0][0][0] = 46, ++ [0][1][2][0][0][1] = 46, ++ [0][1][2][0][0][2] = 46, ++ [0][1][2][0][0][3] = 46, ++ [0][1][2][0][0][4] = 46, ++ [0][1][2][0][0][5] = 46, ++ [0][1][2][0][0][6] = 46, ++ [0][1][2][0][0][7] = 46, ++ [0][1][2][0][0][8] = 46, ++ [0][1][2][0][0][9] = 46, ++ [0][1][2][0][0][10] = 46, ++ [0][1][2][0][0][11] = 42, ++ [0][1][2][0][0][12] = 40, ++ [0][1][2][0][0][13] = 0, ++ [0][1][2][1][0][0] = 34, ++ [0][1][2][1][0][1] = 34, ++ [0][1][2][1][0][2] = 34, ++ [0][1][2][1][0][3] = 34, ++ [0][1][2][1][0][4] = 34, ++ [0][1][2][1][0][5] = 34, ++ [0][1][2][1][0][6] = 34, ++ [0][1][2][1][0][7] = 34, ++ [0][1][2][1][0][8] = 34, ++ [0][1][2][1][0][9] = 34, ++ [0][1][2][1][0][10] = 34, ++ [0][1][2][1][0][11] = 34, ++ [0][1][2][1][0][12] = 34, ++ [0][1][2][1][0][13] = 0, ++ [1][0][2][0][0][0] = 0, ++ [1][0][2][0][0][1] = 0, ++ [1][0][2][0][0][2] = 56, ++ [1][0][2][0][0][3] = 56, ++ [1][0][2][0][0][4] = 58, ++ [1][0][2][0][0][5] = 58, ++ [1][0][2][0][0][6] = 54, ++ [1][0][2][0][0][7] = 50, ++ [1][0][2][0][0][8] = 50, ++ [1][0][2][0][0][9] = 42, ++ [1][0][2][0][0][10] = 40, ++ [1][0][2][0][0][11] = 0, ++ [1][0][2][0][0][12] = 0, ++ [1][0][2][0][0][13] = 0, ++ [1][1][2][0][0][0] = 0, ++ [1][1][2][0][0][1] = 0, ++ [1][1][2][0][0][2] = 46, ++ [1][1][2][0][0][3] = 46, ++ [1][1][2][0][0][4] = 46, ++ [1][1][2][0][0][5] = 46, ++ [1][1][2][0][0][6] = 46, ++ [1][1][2][0][0][7] = 46, ++ [1][1][2][0][0][8] = 46, ++ [1][1][2][0][0][9] = 38, ++ [1][1][2][0][0][10] = 36, ++ [1][1][2][0][0][11] = 0, ++ [1][1][2][0][0][12] = 0, ++ [1][1][2][0][0][13] = 0, ++ [1][1][2][1][0][0] = 0, ++ [1][1][2][1][0][1] = 0, ++ [1][1][2][1][0][2] = 34, ++ [1][1][2][1][0][3] = 34, ++ [1][1][2][1][0][4] = 34, ++ [1][1][2][1][0][5] = 34, ++ [1][1][2][1][0][6] = 34, ++ [1][1][2][1][0][7] = 34, ++ [1][1][2][1][0][8] = 34, ++ [1][1][2][1][0][9] = 34, ++ [1][1][2][1][0][10] = 34, ++ [1][1][2][1][0][11] = 0, ++ [1][1][2][1][0][12] = 0, ++ [1][1][2][1][0][13] = 0, ++ [0][0][0][0][2][0] = 76, ++ [0][0][0][0][1][0] = 56, ++ [0][0][0][0][3][0] = 68, ++ [0][0][0][0][5][0] = 76, ++ [0][0][0][0][6][0] = 56, ++ [0][0][0][0][9][0] = 56, ++ [0][0][0][0][8][0] = 60, ++ [0][0][0][0][11][0] = 56, ++ [0][0][0][0][2][1] = 76, ++ [0][0][0][0][1][1] = 56, ++ [0][0][0][0][3][1] = 68, ++ [0][0][0][0][5][1] = 76, ++ [0][0][0][0][6][1] = 56, ++ [0][0][0][0][9][1] = 56, ++ [0][0][0][0][8][1] = 60, ++ [0][0][0][0][11][1] = 56, ++ [0][0][0][0][2][2] = 76, ++ [0][0][0][0][1][2] = 56, ++ [0][0][0][0][3][2] = 68, ++ [0][0][0][0][5][2] = 76, ++ [0][0][0][0][6][2] = 56, ++ [0][0][0][0][9][2] = 56, ++ [0][0][0][0][8][2] = 60, ++ [0][0][0][0][11][2] = 56, ++ [0][0][0][0][2][3] = 76, ++ [0][0][0][0][1][3] = 56, ++ [0][0][0][0][3][3] = 68, ++ [0][0][0][0][5][3] = 76, ++ [0][0][0][0][6][3] = 56, ++ [0][0][0][0][9][3] = 56, ++ [0][0][0][0][8][3] = 60, ++ [0][0][0][0][11][3] = 56, ++ [0][0][0][0][2][4] = 76, ++ [0][0][0][0][1][4] = 56, ++ [0][0][0][0][3][4] = 68, ++ [0][0][0][0][5][4] = 76, ++ [0][0][0][0][6][4] = 56, ++ [0][0][0][0][9][4] = 56, ++ [0][0][0][0][8][4] = 60, ++ [0][0][0][0][11][4] = 56, ++ [0][0][0][0][2][5] = 76, ++ [0][0][0][0][1][5] = 56, ++ [0][0][0][0][3][5] = 68, ++ [0][0][0][0][5][5] = 76, ++ [0][0][0][0][6][5] = 56, ++ [0][0][0][0][9][5] = 56, ++ [0][0][0][0][8][5] = 60, ++ [0][0][0][0][11][5] = 56, ++ [0][0][0][0][2][6] = 76, ++ [0][0][0][0][1][6] = 56, ++ [0][0][0][0][3][6] = 68, ++ [0][0][0][0][5][6] = 76, ++ [0][0][0][0][6][6] = 56, ++ [0][0][0][0][9][6] = 56, ++ [0][0][0][0][8][6] = 60, ++ [0][0][0][0][11][6] = 56, ++ [0][0][0][0][2][7] = 76, ++ [0][0][0][0][1][7] = 56, ++ [0][0][0][0][3][7] = 68, ++ [0][0][0][0][5][7] = 76, ++ [0][0][0][0][6][7] = 56, ++ [0][0][0][0][9][7] = 56, ++ [0][0][0][0][8][7] = 60, ++ [0][0][0][0][11][7] = 56, ++ [0][0][0][0][2][8] = 76, ++ [0][0][0][0][1][8] = 56, ++ [0][0][0][0][3][8] = 68, ++ [0][0][0][0][5][8] = 76, ++ [0][0][0][0][6][8] = 56, ++ [0][0][0][0][9][8] = 56, ++ [0][0][0][0][8][8] = 60, ++ [0][0][0][0][11][8] = 56, ++ [0][0][0][0][2][9] = 76, ++ [0][0][0][0][1][9] = 56, ++ [0][0][0][0][3][9] = 68, ++ [0][0][0][0][5][9] = 76, ++ [0][0][0][0][6][9] = 56, ++ [0][0][0][0][9][9] = 56, ++ [0][0][0][0][8][9] = 60, ++ [0][0][0][0][11][9] = 56, ++ [0][0][0][0][2][10] = 76, ++ [0][0][0][0][1][10] = 56, ++ [0][0][0][0][3][10] = 68, ++ [0][0][0][0][5][10] = 76, ++ [0][0][0][0][6][10] = 56, ++ [0][0][0][0][9][10] = 56, ++ [0][0][0][0][8][10] = 60, ++ [0][0][0][0][11][10] = 56, ++ [0][0][0][0][2][11] = 68, ++ [0][0][0][0][1][11] = 56, ++ [0][0][0][0][3][11] = 68, ++ [0][0][0][0][5][11] = 68, ++ [0][0][0][0][6][11] = 56, ++ [0][0][0][0][9][11] = 56, ++ [0][0][0][0][8][11] = 60, ++ [0][0][0][0][11][11] = 56, ++ [0][0][0][0][2][12] = 48, ++ [0][0][0][0][1][12] = 56, ++ [0][0][0][0][3][12] = 68, ++ [0][0][0][0][5][12] = 48, ++ [0][0][0][0][6][12] = 56, ++ [0][0][0][0][9][12] = 56, ++ [0][0][0][0][8][12] = 60, ++ [0][0][0][0][11][12] = 56, ++ [0][0][0][0][2][13] = 127, ++ [0][0][0][0][1][13] = 127, ++ [0][0][0][0][3][13] = 76, ++ [0][0][0][0][5][13] = 127, ++ [0][0][0][0][6][13] = 127, ++ [0][0][0][0][9][13] = 127, ++ [0][0][0][0][8][13] = 127, ++ [0][0][0][0][11][13] = 127, ++ [0][1][0][0][2][0] = 74, ++ [0][1][0][0][1][0] = 44, ++ [0][1][0][0][3][0] = 56, ++ [0][1][0][0][5][0] = 74, ++ [0][1][0][0][6][0] = 44, ++ [0][1][0][0][9][0] = 44, ++ [0][1][0][0][8][0] = 48, ++ [0][1][0][0][11][0] = 44, ++ [0][1][0][0][2][1] = 76, ++ [0][1][0][0][1][1] = 44, ++ [0][1][0][0][3][1] = 56, ++ [0][1][0][0][5][1] = 76, ++ [0][1][0][0][6][1] = 44, ++ [0][1][0][0][9][1] = 44, ++ [0][1][0][0][8][1] = 48, ++ [0][1][0][0][11][1] = 44, ++ [0][1][0][0][2][2] = 76, ++ [0][1][0][0][1][2] = 44, ++ [0][1][0][0][3][2] = 56, ++ [0][1][0][0][5][2] = 76, ++ [0][1][0][0][6][2] = 44, ++ [0][1][0][0][9][2] = 44, ++ [0][1][0][0][8][2] = 48, ++ [0][1][0][0][11][2] = 44, ++ [0][1][0][0][2][3] = 76, ++ [0][1][0][0][1][3] = 44, ++ [0][1][0][0][3][3] = 56, ++ [0][1][0][0][5][3] = 76, ++ [0][1][0][0][6][3] = 44, ++ [0][1][0][0][9][3] = 44, ++ [0][1][0][0][8][3] = 48, ++ [0][1][0][0][11][3] = 44, ++ [0][1][0][0][2][4] = 76, ++ [0][1][0][0][1][4] = 44, ++ [0][1][0][0][3][4] = 56, ++ [0][1][0][0][5][4] = 76, ++ [0][1][0][0][6][4] = 44, ++ [0][1][0][0][9][4] = 44, ++ [0][1][0][0][8][4] = 48, ++ [0][1][0][0][11][4] = 44, ++ [0][1][0][0][2][5] = 76, ++ [0][1][0][0][1][5] = 44, ++ [0][1][0][0][3][5] = 56, ++ [0][1][0][0][5][5] = 76, ++ [0][1][0][0][6][5] = 44, ++ [0][1][0][0][9][5] = 44, ++ [0][1][0][0][8][5] = 48, ++ [0][1][0][0][11][5] = 44, ++ [0][1][0][0][2][6] = 76, ++ [0][1][0][0][1][6] = 44, ++ [0][1][0][0][3][6] = 56, ++ [0][1][0][0][5][6] = 76, ++ [0][1][0][0][6][6] = 44, ++ [0][1][0][0][9][6] = 44, ++ [0][1][0][0][8][6] = 48, ++ [0][1][0][0][11][6] = 44, ++ [0][1][0][0][2][7] = 76, ++ [0][1][0][0][1][7] = 44, ++ [0][1][0][0][3][7] = 56, ++ [0][1][0][0][5][7] = 76, ++ [0][1][0][0][6][7] = 44, ++ [0][1][0][0][9][7] = 44, ++ [0][1][0][0][8][7] = 48, ++ [0][1][0][0][11][7] = 44, ++ [0][1][0][0][2][8] = 76, ++ [0][1][0][0][1][8] = 44, ++ [0][1][0][0][3][8] = 56, ++ [0][1][0][0][5][8] = 76, ++ [0][1][0][0][6][8] = 44, ++ [0][1][0][0][9][8] = 44, ++ [0][1][0][0][8][8] = 48, ++ [0][1][0][0][11][8] = 44, ++ [0][1][0][0][2][9] = 76, ++ [0][1][0][0][1][9] = 44, ++ [0][1][0][0][3][9] = 56, ++ [0][1][0][0][5][9] = 76, ++ [0][1][0][0][6][9] = 44, ++ [0][1][0][0][9][9] = 44, ++ [0][1][0][0][8][9] = 48, ++ [0][1][0][0][11][9] = 44, ++ [0][1][0][0][2][10] = 62, ++ [0][1][0][0][1][10] = 44, ++ [0][1][0][0][3][10] = 56, ++ [0][1][0][0][5][10] = 62, ++ [0][1][0][0][6][10] = 44, ++ [0][1][0][0][9][10] = 44, ++ [0][1][0][0][8][10] = 48, ++ [0][1][0][0][11][10] = 44, ++ [0][1][0][0][2][11] = 52, ++ [0][1][0][0][1][11] = 44, ++ [0][1][0][0][3][11] = 56, ++ [0][1][0][0][5][11] = 52, ++ [0][1][0][0][6][11] = 44, ++ [0][1][0][0][9][11] = 44, ++ [0][1][0][0][8][11] = 48, ++ [0][1][0][0][11][11] = 44, ++ [0][1][0][0][2][12] = 38, ++ [0][1][0][0][1][12] = 44, ++ [0][1][0][0][3][12] = 56, ++ [0][1][0][0][5][12] = 38, ++ [0][1][0][0][6][12] = 44, ++ [0][1][0][0][9][12] = 44, ++ [0][1][0][0][8][12] = 48, ++ [0][1][0][0][11][12] = 44, ++ [0][1][0][0][2][13] = 127, ++ [0][1][0][0][1][13] = 127, ++ [0][1][0][0][3][13] = 64, ++ [0][1][0][0][5][13] = 127, ++ [0][1][0][0][6][13] = 127, ++ [0][1][0][0][9][13] = 127, ++ [0][1][0][0][8][13] = 127, ++ [0][1][0][0][11][13] = 127, ++ [1][0][0][0][2][0] = 127, ++ [1][0][0][0][1][0] = 127, ++ [1][0][0][0][3][0] = 127, ++ [1][0][0][0][5][0] = 127, ++ [1][0][0][0][6][0] = 127, ++ [1][0][0][0][9][0] = 127, ++ [1][0][0][0][8][0] = 127, ++ [1][0][0][0][11][0] = 127, ++ [1][0][0][0][2][1] = 127, ++ [1][0][0][0][1][1] = 127, ++ [1][0][0][0][3][1] = 127, ++ [1][0][0][0][5][1] = 127, ++ [1][0][0][0][6][1] = 127, ++ [1][0][0][0][9][1] = 127, ++ [1][0][0][0][8][1] = 127, ++ [1][0][0][0][11][1] = 127, ++ [1][0][0][0][2][2] = 60, ++ [1][0][0][0][1][2] = 58, ++ [1][0][0][0][3][2] = 68, ++ [1][0][0][0][5][2] = 60, ++ [1][0][0][0][6][2] = 58, ++ [1][0][0][0][9][2] = 58, ++ [1][0][0][0][8][2] = 60, ++ [1][0][0][0][11][2] = 58, ++ [1][0][0][0][2][3] = 60, ++ [1][0][0][0][1][3] = 58, ++ [1][0][0][0][3][3] = 68, ++ [1][0][0][0][5][3] = 60, ++ [1][0][0][0][6][3] = 58, ++ [1][0][0][0][9][3] = 58, ++ [1][0][0][0][8][3] = 60, ++ [1][0][0][0][11][3] = 58, ++ [1][0][0][0][2][4] = 60, ++ [1][0][0][0][1][4] = 58, ++ [1][0][0][0][3][4] = 68, ++ [1][0][0][0][5][4] = 60, ++ [1][0][0][0][6][4] = 58, ++ [1][0][0][0][9][4] = 58, ++ [1][0][0][0][8][4] = 60, ++ [1][0][0][0][11][4] = 58, ++ [1][0][0][0][2][5] = 60, ++ [1][0][0][0][1][5] = 58, ++ [1][0][0][0][3][5] = 68, ++ [1][0][0][0][5][5] = 60, ++ [1][0][0][0][6][5] = 58, ++ [1][0][0][0][9][5] = 58, ++ [1][0][0][0][8][5] = 60, ++ [1][0][0][0][11][5] = 58, ++ [1][0][0][0][2][6] = 46, ++ [1][0][0][0][1][6] = 58, ++ [1][0][0][0][3][6] = 68, ++ [1][0][0][0][5][6] = 46, ++ [1][0][0][0][6][6] = 58, ++ [1][0][0][0][9][6] = 58, ++ [1][0][0][0][8][6] = 60, ++ [1][0][0][0][11][6] = 58, ++ [1][0][0][0][2][7] = 46, ++ [1][0][0][0][1][7] = 58, ++ [1][0][0][0][3][7] = 68, ++ [1][0][0][0][5][7] = 46, ++ [1][0][0][0][6][7] = 58, ++ [1][0][0][0][9][7] = 58, ++ [1][0][0][0][8][7] = 60, ++ [1][0][0][0][11][7] = 58, ++ [1][0][0][0][2][8] = 46, ++ [1][0][0][0][1][8] = 58, ++ [1][0][0][0][3][8] = 68, ++ [1][0][0][0][5][8] = 46, ++ [1][0][0][0][6][8] = 58, ++ [1][0][0][0][9][8] = 58, ++ [1][0][0][0][8][8] = 60, ++ [1][0][0][0][11][8] = 58, ++ [1][0][0][0][2][9] = 32, ++ [1][0][0][0][1][9] = 58, ++ [1][0][0][0][3][9] = 68, ++ [1][0][0][0][5][9] = 32, ++ [1][0][0][0][6][9] = 58, ++ [1][0][0][0][9][9] = 58, ++ [1][0][0][0][8][9] = 60, ++ [1][0][0][0][11][9] = 58, ++ [1][0][0][0][2][10] = 32, ++ [1][0][0][0][1][10] = 58, ++ [1][0][0][0][3][10] = 68, ++ [1][0][0][0][5][10] = 32, ++ [1][0][0][0][6][10] = 58, ++ [1][0][0][0][9][10] = 58, ++ [1][0][0][0][8][10] = 60, ++ [1][0][0][0][11][10] = 58, ++ [1][0][0][0][2][11] = 127, ++ [1][0][0][0][1][11] = 127, ++ [1][0][0][0][3][11] = 127, ++ [1][0][0][0][5][11] = 127, ++ [1][0][0][0][6][11] = 127, ++ [1][0][0][0][9][11] = 127, ++ [1][0][0][0][8][11] = 127, ++ [1][0][0][0][11][11] = 127, ++ [1][0][0][0][2][12] = 127, ++ [1][0][0][0][1][12] = 127, ++ [1][0][0][0][3][12] = 127, ++ [1][0][0][0][5][12] = 127, ++ [1][0][0][0][6][12] = 127, ++ [1][0][0][0][9][12] = 127, ++ [1][0][0][0][8][12] = 127, ++ [1][0][0][0][11][12] = 127, ++ [1][0][0][0][2][13] = 127, ++ [1][0][0][0][1][13] = 127, ++ [1][0][0][0][3][13] = 127, ++ [1][0][0][0][5][13] = 127, ++ [1][0][0][0][6][13] = 127, ++ [1][0][0][0][9][13] = 127, ++ [1][0][0][0][8][13] = 127, ++ [1][0][0][0][11][13] = 127, ++ [1][1][0][0][2][0] = 127, ++ [1][1][0][0][1][0] = 127, ++ [1][1][0][0][3][0] = 127, ++ [1][1][0][0][5][0] = 127, ++ [1][1][0][0][6][0] = 127, ++ [1][1][0][0][9][0] = 127, ++ [1][1][0][0][8][0] = 127, ++ [1][1][0][0][11][0] = 127, ++ [1][1][0][0][2][1] = 127, ++ [1][1][0][0][1][1] = 127, ++ [1][1][0][0][3][1] = 127, ++ [1][1][0][0][5][1] = 127, ++ [1][1][0][0][6][1] = 127, ++ [1][1][0][0][9][1] = 127, ++ [1][1][0][0][8][1] = 127, ++ [1][1][0][0][11][1] = 127, ++ [1][1][0][0][2][2] = 48, ++ [1][1][0][0][1][2] = 46, ++ [1][1][0][0][3][2] = 56, ++ [1][1][0][0][5][2] = 48, ++ [1][1][0][0][6][2] = 46, ++ [1][1][0][0][9][2] = 46, ++ [1][1][0][0][8][2] = 48, ++ [1][1][0][0][11][2] = 46, ++ [1][1][0][0][2][3] = 48, ++ [1][1][0][0][1][3] = 46, ++ [1][1][0][0][3][3] = 56, ++ [1][1][0][0][5][3] = 48, ++ [1][1][0][0][6][3] = 46, ++ [1][1][0][0][9][3] = 46, ++ [1][1][0][0][8][3] = 48, ++ [1][1][0][0][11][3] = 46, ++ [1][1][0][0][2][4] = 48, ++ [1][1][0][0][1][4] = 46, ++ [1][1][0][0][3][4] = 56, ++ [1][1][0][0][5][4] = 48, ++ [1][1][0][0][6][4] = 46, ++ [1][1][0][0][9][4] = 46, ++ [1][1][0][0][8][4] = 48, ++ [1][1][0][0][11][4] = 46, ++ [1][1][0][0][2][5] = 58, ++ [1][1][0][0][1][5] = 46, ++ [1][1][0][0][3][5] = 56, ++ [1][1][0][0][5][5] = 58, ++ [1][1][0][0][6][5] = 46, ++ [1][1][0][0][9][5] = 46, ++ [1][1][0][0][8][5] = 48, ++ [1][1][0][0][11][5] = 46, ++ [1][1][0][0][2][6] = 46, ++ [1][1][0][0][1][6] = 46, ++ [1][1][0][0][3][6] = 56, ++ [1][1][0][0][5][6] = 46, ++ [1][1][0][0][6][6] = 46, ++ [1][1][0][0][9][6] = 46, ++ [1][1][0][0][8][6] = 48, ++ [1][1][0][0][11][6] = 46, ++ [1][1][0][0][2][7] = 46, ++ [1][1][0][0][1][7] = 46, ++ [1][1][0][0][3][7] = 56, ++ [1][1][0][0][5][7] = 46, ++ [1][1][0][0][6][7] = 46, ++ [1][1][0][0][9][7] = 46, ++ [1][1][0][0][8][7] = 48, ++ [1][1][0][0][11][7] = 46, ++ [1][1][0][0][2][8] = 46, ++ [1][1][0][0][1][8] = 46, ++ [1][1][0][0][3][8] = 56, ++ [1][1][0][0][5][8] = 46, ++ [1][1][0][0][6][8] = 46, ++ [1][1][0][0][9][8] = 46, ++ [1][1][0][0][8][8] = 48, ++ [1][1][0][0][11][8] = 46, ++ [1][1][0][0][2][9] = 24, ++ [1][1][0][0][1][9] = 46, ++ [1][1][0][0][3][9] = 56, ++ [1][1][0][0][5][9] = 24, ++ [1][1][0][0][6][9] = 46, ++ [1][1][0][0][9][9] = 46, ++ [1][1][0][0][8][9] = 48, ++ [1][1][0][0][11][9] = 46, ++ [1][1][0][0][2][10] = 24, ++ [1][1][0][0][1][10] = 46, ++ [1][1][0][0][3][10] = 56, ++ [1][1][0][0][5][10] = 24, ++ [1][1][0][0][6][10] = 46, ++ [1][1][0][0][9][10] = 46, ++ [1][1][0][0][8][10] = 48, ++ [1][1][0][0][11][10] = 46, ++ [1][1][0][0][2][11] = 127, ++ [1][1][0][0][1][11] = 127, ++ [1][1][0][0][3][11] = 127, ++ [1][1][0][0][5][11] = 127, ++ [1][1][0][0][6][11] = 127, ++ [1][1][0][0][9][11] = 127, ++ [1][1][0][0][8][11] = 127, ++ [1][1][0][0][11][11] = 127, ++ [1][1][0][0][2][12] = 127, ++ [1][1][0][0][1][12] = 127, ++ [1][1][0][0][3][12] = 127, ++ [1][1][0][0][5][12] = 127, ++ [1][1][0][0][6][12] = 127, ++ [1][1][0][0][9][12] = 127, ++ [1][1][0][0][8][12] = 127, ++ [1][1][0][0][11][12] = 127, ++ [1][1][0][0][2][13] = 127, ++ [1][1][0][0][1][13] = 127, ++ [1][1][0][0][3][13] = 127, ++ [1][1][0][0][5][13] = 127, ++ [1][1][0][0][6][13] = 127, ++ [1][1][0][0][9][13] = 127, ++ [1][1][0][0][8][13] = 127, ++ [1][1][0][0][11][13] = 127, ++ [0][0][1][0][2][0] = 66, ++ [0][0][1][0][1][0] = 58, ++ [0][0][1][0][3][0] = 76, ++ [0][0][1][0][5][0] = 66, ++ [0][0][1][0][6][0] = 58, ++ [0][0][1][0][9][0] = 58, ++ [0][0][1][0][8][0] = 60, ++ [0][0][1][0][11][0] = 58, ++ [0][0][1][0][2][1] = 66, ++ [0][0][1][0][1][1] = 58, ++ [0][0][1][0][3][1] = 76, ++ [0][0][1][0][5][1] = 66, ++ [0][0][1][0][6][1] = 58, ++ [0][0][1][0][9][1] = 58, ++ [0][0][1][0][8][1] = 60, ++ [0][0][1][0][11][1] = 58, ++ [0][0][1][0][2][2] = 70, ++ [0][0][1][0][1][2] = 58, ++ [0][0][1][0][3][2] = 76, ++ [0][0][1][0][5][2] = 70, ++ [0][0][1][0][6][2] = 58, ++ [0][0][1][0][9][2] = 58, ++ [0][0][1][0][8][2] = 60, ++ [0][0][1][0][11][2] = 58, ++ [0][0][1][0][2][3] = 74, ++ [0][0][1][0][1][3] = 58, ++ [0][0][1][0][3][3] = 76, ++ [0][0][1][0][5][3] = 74, ++ [0][0][1][0][6][3] = 58, ++ [0][0][1][0][9][3] = 58, ++ [0][0][1][0][8][3] = 60, ++ [0][0][1][0][11][3] = 58, ++ [0][0][1][0][2][4] = 78, ++ [0][0][1][0][1][4] = 58, ++ [0][0][1][0][3][4] = 76, ++ [0][0][1][0][5][4] = 78, ++ [0][0][1][0][6][4] = 58, ++ [0][0][1][0][9][4] = 58, ++ [0][0][1][0][8][4] = 60, ++ [0][0][1][0][11][4] = 58, ++ [0][0][1][0][2][5] = 78, ++ [0][0][1][0][1][5] = 58, ++ [0][0][1][0][3][5] = 76, ++ [0][0][1][0][5][5] = 78, ++ [0][0][1][0][6][5] = 58, ++ [0][0][1][0][9][5] = 58, ++ [0][0][1][0][8][5] = 60, ++ [0][0][1][0][11][5] = 58, ++ [0][0][1][0][2][6] = 78, ++ [0][0][1][0][1][6] = 58, ++ [0][0][1][0][3][6] = 76, ++ [0][0][1][0][5][6] = 78, ++ [0][0][1][0][6][6] = 58, ++ [0][0][1][0][9][6] = 58, ++ [0][0][1][0][8][6] = 60, ++ [0][0][1][0][11][6] = 58, ++ [0][0][1][0][2][7] = 74, ++ [0][0][1][0][1][7] = 58, ++ [0][0][1][0][3][7] = 76, ++ [0][0][1][0][5][7] = 74, ++ [0][0][1][0][6][7] = 58, ++ [0][0][1][0][9][7] = 58, ++ [0][0][1][0][8][7] = 60, ++ [0][0][1][0][11][7] = 58, ++ [0][0][1][0][2][8] = 70, ++ [0][0][1][0][1][8] = 58, ++ [0][0][1][0][3][8] = 76, ++ [0][0][1][0][5][8] = 70, ++ [0][0][1][0][6][8] = 58, ++ [0][0][1][0][9][8] = 58, ++ [0][0][1][0][8][8] = 60, ++ [0][0][1][0][11][8] = 58, ++ [0][0][1][0][2][9] = 66, ++ [0][0][1][0][1][9] = 58, ++ [0][0][1][0][3][9] = 76, ++ [0][0][1][0][5][9] = 66, ++ [0][0][1][0][6][9] = 58, ++ [0][0][1][0][9][9] = 58, ++ [0][0][1][0][8][9] = 60, ++ [0][0][1][0][11][9] = 58, ++ [0][0][1][0][2][10] = 66, ++ [0][0][1][0][1][10] = 58, ++ [0][0][1][0][3][10] = 76, ++ [0][0][1][0][5][10] = 66, ++ [0][0][1][0][6][10] = 58, ++ [0][0][1][0][9][10] = 58, ++ [0][0][1][0][8][10] = 60, ++ [0][0][1][0][11][10] = 58, ++ [0][0][1][0][2][11] = 56, ++ [0][0][1][0][1][11] = 58, ++ [0][0][1][0][3][11] = 76, ++ [0][0][1][0][5][11] = 56, ++ [0][0][1][0][6][11] = 58, ++ [0][0][1][0][9][11] = 58, ++ [0][0][1][0][8][11] = 60, ++ [0][0][1][0][11][11] = 58, ++ [0][0][1][0][2][12] = 52, ++ [0][0][1][0][1][12] = 58, ++ [0][0][1][0][3][12] = 76, ++ [0][0][1][0][5][12] = 52, ++ [0][0][1][0][6][12] = 58, ++ [0][0][1][0][9][12] = 58, ++ [0][0][1][0][8][12] = 60, ++ [0][0][1][0][11][12] = 58, ++ [0][0][1][0][2][13] = 127, ++ [0][0][1][0][1][13] = 127, ++ [0][0][1][0][3][13] = 127, ++ [0][0][1][0][5][13] = 127, ++ [0][0][1][0][6][13] = 127, ++ [0][0][1][0][9][13] = 127, ++ [0][0][1][0][8][13] = 127, ++ [0][0][1][0][11][13] = 127, ++ [0][1][1][0][2][0] = 62, ++ [0][1][1][0][1][0] = 46, ++ [0][1][1][0][3][0] = 64, ++ [0][1][1][0][5][0] = 62, ++ [0][1][1][0][6][0] = 46, ++ [0][1][1][0][9][0] = 46, ++ [0][1][1][0][8][0] = 48, ++ [0][1][1][0][11][0] = 46, ++ [0][1][1][0][2][1] = 62, ++ [0][1][1][0][1][1] = 46, ++ [0][1][1][0][3][1] = 64, ++ [0][1][1][0][5][1] = 62, ++ [0][1][1][0][6][1] = 46, ++ [0][1][1][0][9][1] = 46, ++ [0][1][1][0][8][1] = 48, ++ [0][1][1][0][11][1] = 46, ++ [0][1][1][0][2][2] = 66, ++ [0][1][1][0][1][2] = 46, ++ [0][1][1][0][3][2] = 64, ++ [0][1][1][0][5][2] = 66, ++ [0][1][1][0][6][2] = 46, ++ [0][1][1][0][9][2] = 46, ++ [0][1][1][0][8][2] = 48, ++ [0][1][1][0][11][2] = 46, ++ [0][1][1][0][2][3] = 70, ++ [0][1][1][0][1][3] = 46, ++ [0][1][1][0][3][3] = 64, ++ [0][1][1][0][5][3] = 70, ++ [0][1][1][0][6][3] = 46, ++ [0][1][1][0][9][3] = 46, ++ [0][1][1][0][8][3] = 48, ++ [0][1][1][0][11][3] = 46, ++ [0][1][1][0][2][4] = 78, ++ [0][1][1][0][1][4] = 46, ++ [0][1][1][0][3][4] = 64, ++ [0][1][1][0][5][4] = 78, ++ [0][1][1][0][6][4] = 46, ++ [0][1][1][0][9][4] = 46, ++ [0][1][1][0][8][4] = 48, ++ [0][1][1][0][11][4] = 46, ++ [0][1][1][0][2][5] = 78, ++ [0][1][1][0][1][5] = 46, ++ [0][1][1][0][3][5] = 64, ++ [0][1][1][0][5][5] = 78, ++ [0][1][1][0][6][5] = 46, ++ [0][1][1][0][9][5] = 46, ++ [0][1][1][0][8][5] = 48, ++ [0][1][1][0][11][5] = 46, ++ [0][1][1][0][2][6] = 78, ++ [0][1][1][0][1][6] = 46, ++ [0][1][1][0][3][6] = 64, ++ [0][1][1][0][5][6] = 78, ++ [0][1][1][0][6][6] = 46, ++ [0][1][1][0][9][6] = 46, ++ [0][1][1][0][8][6] = 48, ++ [0][1][1][0][11][6] = 46, ++ [0][1][1][0][2][7] = 70, ++ [0][1][1][0][1][7] = 46, ++ [0][1][1][0][3][7] = 64, ++ [0][1][1][0][5][7] = 70, ++ [0][1][1][0][6][7] = 46, ++ [0][1][1][0][9][7] = 46, ++ [0][1][1][0][8][7] = 48, ++ [0][1][1][0][11][7] = 46, ++ [0][1][1][0][2][8] = 66, ++ [0][1][1][0][1][8] = 46, ++ [0][1][1][0][3][8] = 64, ++ [0][1][1][0][5][8] = 66, ++ [0][1][1][0][6][8] = 46, ++ [0][1][1][0][9][8] = 46, ++ [0][1][1][0][8][8] = 48, ++ [0][1][1][0][11][8] = 46, ++ [0][1][1][0][2][9] = 62, ++ [0][1][1][0][1][9] = 46, ++ [0][1][1][0][3][9] = 64, ++ [0][1][1][0][5][9] = 62, ++ [0][1][1][0][6][9] = 46, ++ [0][1][1][0][9][9] = 46, ++ [0][1][1][0][8][9] = 48, ++ [0][1][1][0][11][9] = 46, ++ [0][1][1][0][2][10] = 62, ++ [0][1][1][0][1][10] = 46, ++ [0][1][1][0][3][10] = 64, ++ [0][1][1][0][5][10] = 62, ++ [0][1][1][0][6][10] = 46, ++ [0][1][1][0][9][10] = 46, ++ [0][1][1][0][8][10] = 48, ++ [0][1][1][0][11][10] = 46, ++ [0][1][1][0][2][11] = 42, ++ [0][1][1][0][1][11] = 46, ++ [0][1][1][0][3][11] = 64, ++ [0][1][1][0][5][11] = 42, ++ [0][1][1][0][6][11] = 46, ++ [0][1][1][0][9][11] = 46, ++ [0][1][1][0][8][11] = 48, ++ [0][1][1][0][11][11] = 46, ++ [0][1][1][0][2][12] = 40, ++ [0][1][1][0][1][12] = 46, ++ [0][1][1][0][3][12] = 64, ++ [0][1][1][0][5][12] = 40, ++ [0][1][1][0][6][12] = 46, ++ [0][1][1][0][9][12] = 46, ++ [0][1][1][0][8][12] = 48, ++ [0][1][1][0][11][12] = 46, ++ [0][1][1][0][2][13] = 127, ++ [0][1][1][0][1][13] = 127, ++ [0][1][1][0][3][13] = 127, ++ [0][1][1][0][5][13] = 127, ++ [0][1][1][0][6][13] = 127, ++ [0][1][1][0][9][13] = 127, ++ [0][1][1][0][8][13] = 127, ++ [0][1][1][0][11][13] = 127, ++ [0][0][2][0][2][0] = 66, ++ [0][0][2][0][1][0] = 58, ++ [0][0][2][0][3][0] = 76, ++ [0][0][2][0][5][0] = 66, ++ [0][0][2][0][6][0] = 58, ++ [0][0][2][0][9][0] = 58, ++ [0][0][2][0][8][0] = 60, ++ [0][0][2][0][11][0] = 58, ++ [0][0][2][0][2][1] = 66, ++ [0][0][2][0][1][1] = 58, ++ [0][0][2][0][3][1] = 76, ++ [0][0][2][0][5][1] = 66, ++ [0][0][2][0][6][1] = 58, ++ [0][0][2][0][9][1] = 58, ++ [0][0][2][0][8][1] = 60, ++ [0][0][2][0][11][1] = 58, ++ [0][0][2][0][2][2] = 70, ++ [0][0][2][0][1][2] = 58, ++ [0][0][2][0][3][2] = 76, ++ [0][0][2][0][5][2] = 70, ++ [0][0][2][0][6][2] = 58, ++ [0][0][2][0][9][2] = 58, ++ [0][0][2][0][8][2] = 60, ++ [0][0][2][0][11][2] = 58, ++ [0][0][2][0][2][3] = 74, ++ [0][0][2][0][1][3] = 58, ++ [0][0][2][0][3][3] = 76, ++ [0][0][2][0][5][3] = 74, ++ [0][0][2][0][6][3] = 58, ++ [0][0][2][0][9][3] = 58, ++ [0][0][2][0][8][3] = 60, ++ [0][0][2][0][11][3] = 58, ++ [0][0][2][0][2][4] = 76, ++ [0][0][2][0][1][4] = 58, ++ [0][0][2][0][3][4] = 76, ++ [0][0][2][0][5][4] = 76, ++ [0][0][2][0][6][4] = 58, ++ [0][0][2][0][9][4] = 58, ++ [0][0][2][0][8][4] = 60, ++ [0][0][2][0][11][4] = 58, ++ [0][0][2][0][2][5] = 76, ++ [0][0][2][0][1][5] = 58, ++ [0][0][2][0][3][5] = 76, ++ [0][0][2][0][5][5] = 76, ++ [0][0][2][0][6][5] = 58, ++ [0][0][2][0][9][5] = 58, ++ [0][0][2][0][8][5] = 60, ++ [0][0][2][0][11][5] = 58, ++ [0][0][2][0][2][6] = 76, ++ [0][0][2][0][1][6] = 58, ++ [0][0][2][0][3][6] = 76, ++ [0][0][2][0][5][6] = 76, ++ [0][0][2][0][6][6] = 58, ++ [0][0][2][0][9][6] = 58, ++ [0][0][2][0][8][6] = 60, ++ [0][0][2][0][11][6] = 58, ++ [0][0][2][0][2][7] = 74, ++ [0][0][2][0][1][7] = 58, ++ [0][0][2][0][3][7] = 76, ++ [0][0][2][0][5][7] = 74, ++ [0][0][2][0][6][7] = 58, ++ [0][0][2][0][9][7] = 58, ++ [0][0][2][0][8][7] = 60, ++ [0][0][2][0][11][7] = 58, ++ [0][0][2][0][2][8] = 70, ++ [0][0][2][0][1][8] = 58, ++ [0][0][2][0][3][8] = 76, ++ [0][0][2][0][5][8] = 70, ++ [0][0][2][0][6][8] = 58, ++ [0][0][2][0][9][8] = 58, ++ [0][0][2][0][8][8] = 60, ++ [0][0][2][0][11][8] = 58, ++ [0][0][2][0][2][9] = 66, ++ [0][0][2][0][1][9] = 58, ++ [0][0][2][0][3][9] = 76, ++ [0][0][2][0][5][9] = 66, ++ [0][0][2][0][6][9] = 58, ++ [0][0][2][0][9][9] = 58, ++ [0][0][2][0][8][9] = 60, ++ [0][0][2][0][11][9] = 58, ++ [0][0][2][0][2][10] = 66, ++ [0][0][2][0][1][10] = 58, ++ [0][0][2][0][3][10] = 76, ++ [0][0][2][0][5][10] = 66, ++ [0][0][2][0][6][10] = 58, ++ [0][0][2][0][9][10] = 58, ++ [0][0][2][0][8][10] = 60, ++ [0][0][2][0][11][10] = 58, ++ [0][0][2][0][2][11] = 54, ++ [0][0][2][0][1][11] = 58, ++ [0][0][2][0][3][11] = 76, ++ [0][0][2][0][5][11] = 54, ++ [0][0][2][0][6][11] = 58, ++ [0][0][2][0][9][11] = 58, ++ [0][0][2][0][8][11] = 60, ++ [0][0][2][0][11][11] = 58, ++ [0][0][2][0][2][12] = 50, ++ [0][0][2][0][1][12] = 58, ++ [0][0][2][0][3][12] = 76, ++ [0][0][2][0][5][12] = 50, ++ [0][0][2][0][6][12] = 58, ++ [0][0][2][0][9][12] = 58, ++ [0][0][2][0][8][12] = 60, ++ [0][0][2][0][11][12] = 58, ++ [0][0][2][0][2][13] = 127, ++ [0][0][2][0][1][13] = 127, ++ [0][0][2][0][3][13] = 127, ++ [0][0][2][0][5][13] = 127, ++ [0][0][2][0][6][13] = 127, ++ [0][0][2][0][9][13] = 127, ++ [0][0][2][0][8][13] = 127, ++ [0][0][2][0][11][13] = 127, ++ [0][1][2][0][2][0] = 62, ++ [0][1][2][0][1][0] = 46, ++ [0][1][2][0][3][0] = 64, ++ [0][1][2][0][5][0] = 62, ++ [0][1][2][0][6][0] = 46, ++ [0][1][2][0][9][0] = 46, ++ [0][1][2][0][8][0] = 48, ++ [0][1][2][0][11][0] = 46, ++ [0][1][2][0][2][1] = 62, ++ [0][1][2][0][1][1] = 46, ++ [0][1][2][0][3][1] = 64, ++ [0][1][2][0][5][1] = 62, ++ [0][1][2][0][6][1] = 46, ++ [0][1][2][0][9][1] = 46, ++ [0][1][2][0][8][1] = 48, ++ [0][1][2][0][11][1] = 46, ++ [0][1][2][0][2][2] = 66, ++ [0][1][2][0][1][2] = 46, ++ [0][1][2][0][3][2] = 64, ++ [0][1][2][0][5][2] = 66, ++ [0][1][2][0][6][2] = 46, ++ [0][1][2][0][9][2] = 46, ++ [0][1][2][0][8][2] = 48, ++ [0][1][2][0][11][2] = 46, ++ [0][1][2][0][2][3] = 70, ++ [0][1][2][0][1][3] = 46, ++ [0][1][2][0][3][3] = 64, ++ [0][1][2][0][5][3] = 70, ++ [0][1][2][0][6][3] = 46, ++ [0][1][2][0][9][3] = 46, ++ [0][1][2][0][8][3] = 48, ++ [0][1][2][0][11][3] = 46, ++ [0][1][2][0][2][4] = 76, ++ [0][1][2][0][1][4] = 46, ++ [0][1][2][0][3][4] = 64, ++ [0][1][2][0][5][4] = 76, ++ [0][1][2][0][6][4] = 46, ++ [0][1][2][0][9][4] = 46, ++ [0][1][2][0][8][4] = 48, ++ [0][1][2][0][11][4] = 46, ++ [0][1][2][0][2][5] = 76, ++ [0][1][2][0][1][5] = 46, ++ [0][1][2][0][3][5] = 64, ++ [0][1][2][0][5][5] = 76, ++ [0][1][2][0][6][5] = 46, ++ [0][1][2][0][9][5] = 46, ++ [0][1][2][0][8][5] = 48, ++ [0][1][2][0][11][5] = 46, ++ [0][1][2][0][2][6] = 76, ++ [0][1][2][0][1][6] = 46, ++ [0][1][2][0][3][6] = 64, ++ [0][1][2][0][5][6] = 76, ++ [0][1][2][0][6][6] = 46, ++ [0][1][2][0][9][6] = 46, ++ [0][1][2][0][8][6] = 48, ++ [0][1][2][0][11][6] = 46, ++ [0][1][2][0][2][7] = 68, ++ [0][1][2][0][1][7] = 46, ++ [0][1][2][0][3][7] = 64, ++ [0][1][2][0][5][7] = 68, ++ [0][1][2][0][6][7] = 46, ++ [0][1][2][0][9][7] = 46, ++ [0][1][2][0][8][7] = 48, ++ [0][1][2][0][11][7] = 46, ++ [0][1][2][0][2][8] = 64, ++ [0][1][2][0][1][8] = 46, ++ [0][1][2][0][3][8] = 64, ++ [0][1][2][0][5][8] = 64, ++ [0][1][2][0][6][8] = 46, ++ [0][1][2][0][9][8] = 46, ++ [0][1][2][0][8][8] = 48, ++ [0][1][2][0][11][8] = 46, ++ [0][1][2][0][2][9] = 60, ++ [0][1][2][0][1][9] = 46, ++ [0][1][2][0][3][9] = 64, ++ [0][1][2][0][5][9] = 60, ++ [0][1][2][0][6][9] = 46, ++ [0][1][2][0][9][9] = 46, ++ [0][1][2][0][8][9] = 48, ++ [0][1][2][0][11][9] = 46, ++ [0][1][2][0][2][10] = 60, ++ [0][1][2][0][1][10] = 46, ++ [0][1][2][0][3][10] = 64, ++ [0][1][2][0][5][10] = 60, ++ [0][1][2][0][6][10] = 46, ++ [0][1][2][0][9][10] = 46, ++ [0][1][2][0][8][10] = 48, ++ [0][1][2][0][11][10] = 46, ++ [0][1][2][0][2][11] = 42, ++ [0][1][2][0][1][11] = 46, ++ [0][1][2][0][3][11] = 64, ++ [0][1][2][0][5][11] = 42, ++ [0][1][2][0][6][11] = 46, ++ [0][1][2][0][9][11] = 46, ++ [0][1][2][0][8][11] = 48, ++ [0][1][2][0][11][11] = 46, ++ [0][1][2][0][2][12] = 40, ++ [0][1][2][0][1][12] = 46, ++ [0][1][2][0][3][12] = 64, ++ [0][1][2][0][5][12] = 40, ++ [0][1][2][0][6][12] = 46, ++ [0][1][2][0][9][12] = 46, ++ [0][1][2][0][8][12] = 48, ++ [0][1][2][0][11][12] = 46, ++ [0][1][2][0][2][13] = 127, ++ [0][1][2][0][1][13] = 127, ++ [0][1][2][0][3][13] = 127, ++ [0][1][2][0][5][13] = 127, ++ [0][1][2][0][6][13] = 127, ++ [0][1][2][0][9][13] = 127, ++ [0][1][2][0][8][13] = 127, ++ [0][1][2][0][11][13] = 127, ++ [0][1][2][1][2][0] = 62, ++ [0][1][2][1][1][0] = 34, ++ [0][1][2][1][3][0] = 64, ++ [0][1][2][1][5][0] = 62, ++ [0][1][2][1][6][0] = 34, ++ [0][1][2][1][9][0] = 34, ++ [0][1][2][1][8][0] = 36, ++ [0][1][2][1][11][0] = 34, ++ [0][1][2][1][2][1] = 62, ++ [0][1][2][1][1][1] = 34, ++ [0][1][2][1][3][1] = 64, ++ [0][1][2][1][5][1] = 62, ++ [0][1][2][1][6][1] = 34, ++ [0][1][2][1][9][1] = 34, ++ [0][1][2][1][8][1] = 36, ++ [0][1][2][1][11][1] = 34, ++ [0][1][2][1][2][2] = 66, ++ [0][1][2][1][1][2] = 34, ++ [0][1][2][1][3][2] = 64, ++ [0][1][2][1][5][2] = 66, ++ [0][1][2][1][6][2] = 34, ++ [0][1][2][1][9][2] = 34, ++ [0][1][2][1][8][2] = 36, ++ [0][1][2][1][11][2] = 34, ++ [0][1][2][1][2][3] = 70, ++ [0][1][2][1][1][3] = 34, ++ [0][1][2][1][3][3] = 64, ++ [0][1][2][1][5][3] = 70, ++ [0][1][2][1][6][3] = 34, ++ [0][1][2][1][9][3] = 34, ++ [0][1][2][1][8][3] = 36, ++ [0][1][2][1][11][3] = 34, ++ [0][1][2][1][2][4] = 76, ++ [0][1][2][1][1][4] = 34, ++ [0][1][2][1][3][4] = 64, ++ [0][1][2][1][5][4] = 76, ++ [0][1][2][1][6][4] = 34, ++ [0][1][2][1][9][4] = 34, ++ [0][1][2][1][8][4] = 36, ++ [0][1][2][1][11][4] = 34, ++ [0][1][2][1][2][5] = 76, ++ [0][1][2][1][1][5] = 34, ++ [0][1][2][1][3][5] = 64, ++ [0][1][2][1][5][5] = 76, ++ [0][1][2][1][6][5] = 34, ++ [0][1][2][1][9][5] = 34, ++ [0][1][2][1][8][5] = 36, ++ [0][1][2][1][11][5] = 34, ++ [0][1][2][1][2][6] = 76, ++ [0][1][2][1][1][6] = 34, ++ [0][1][2][1][3][6] = 64, ++ [0][1][2][1][5][6] = 76, ++ [0][1][2][1][6][6] = 34, ++ [0][1][2][1][9][6] = 34, ++ [0][1][2][1][8][6] = 36, ++ [0][1][2][1][11][6] = 34, ++ [0][1][2][1][2][7] = 68, ++ [0][1][2][1][1][7] = 34, ++ [0][1][2][1][3][7] = 64, ++ [0][1][2][1][5][7] = 68, ++ [0][1][2][1][6][7] = 34, ++ [0][1][2][1][9][7] = 34, ++ [0][1][2][1][8][7] = 36, ++ [0][1][2][1][11][7] = 34, ++ [0][1][2][1][2][8] = 64, ++ [0][1][2][1][1][8] = 34, ++ [0][1][2][1][3][8] = 64, ++ [0][1][2][1][5][8] = 64, ++ [0][1][2][1][6][8] = 34, ++ [0][1][2][1][9][8] = 34, ++ [0][1][2][1][8][8] = 36, ++ [0][1][2][1][11][8] = 34, ++ [0][1][2][1][2][9] = 60, ++ [0][1][2][1][1][9] = 34, ++ [0][1][2][1][3][9] = 64, ++ [0][1][2][1][5][9] = 60, ++ [0][1][2][1][6][9] = 34, ++ [0][1][2][1][9][9] = 34, ++ [0][1][2][1][8][9] = 36, ++ [0][1][2][1][11][9] = 34, ++ [0][1][2][1][2][10] = 60, ++ [0][1][2][1][1][10] = 34, ++ [0][1][2][1][3][10] = 64, ++ [0][1][2][1][5][10] = 60, ++ [0][1][2][1][6][10] = 34, ++ [0][1][2][1][9][10] = 34, ++ [0][1][2][1][8][10] = 36, ++ [0][1][2][1][11][10] = 34, ++ [0][1][2][1][2][11] = 42, ++ [0][1][2][1][1][11] = 34, ++ [0][1][2][1][3][11] = 64, ++ [0][1][2][1][5][11] = 42, ++ [0][1][2][1][6][11] = 34, ++ [0][1][2][1][9][11] = 34, ++ [0][1][2][1][8][11] = 36, ++ [0][1][2][1][11][11] = 34, ++ [0][1][2][1][2][12] = 40, ++ [0][1][2][1][1][12] = 34, ++ [0][1][2][1][3][12] = 64, ++ [0][1][2][1][5][12] = 40, ++ [0][1][2][1][6][12] = 34, ++ [0][1][2][1][9][12] = 34, ++ [0][1][2][1][8][12] = 36, ++ [0][1][2][1][11][12] = 34, ++ [0][1][2][1][2][13] = 127, ++ [0][1][2][1][1][13] = 127, ++ [0][1][2][1][3][13] = 127, ++ [0][1][2][1][5][13] = 127, ++ [0][1][2][1][6][13] = 127, ++ [0][1][2][1][9][13] = 127, ++ [0][1][2][1][8][13] = 127, ++ [0][1][2][1][11][13] = 127, ++ [1][0][2][0][2][0] = 127, ++ [1][0][2][0][1][0] = 127, ++ [1][0][2][0][3][0] = 127, ++ [1][0][2][0][5][0] = 127, ++ [1][0][2][0][6][0] = 127, ++ [1][0][2][0][9][0] = 127, ++ [1][0][2][0][8][0] = 127, ++ [1][0][2][0][11][0] = 127, ++ [1][0][2][0][2][1] = 127, ++ [1][0][2][0][1][1] = 127, ++ [1][0][2][0][3][1] = 127, ++ [1][0][2][0][5][1] = 127, ++ [1][0][2][0][6][1] = 127, ++ [1][0][2][0][9][1] = 127, ++ [1][0][2][0][8][1] = 127, ++ [1][0][2][0][11][1] = 127, ++ [1][0][2][0][2][2] = 56, ++ [1][0][2][0][1][2] = 58, ++ [1][0][2][0][3][2] = 76, ++ [1][0][2][0][5][2] = 56, ++ [1][0][2][0][6][2] = 58, ++ [1][0][2][0][9][2] = 58, ++ [1][0][2][0][8][2] = 60, ++ [1][0][2][0][11][2] = 58, ++ [1][0][2][0][2][3] = 56, ++ [1][0][2][0][1][3] = 58, ++ [1][0][2][0][3][3] = 76, ++ [1][0][2][0][5][3] = 56, ++ [1][0][2][0][6][3] = 58, ++ [1][0][2][0][9][3] = 58, ++ [1][0][2][0][8][3] = 60, ++ [1][0][2][0][11][3] = 58, ++ [1][0][2][0][2][4] = 60, ++ [1][0][2][0][1][4] = 58, ++ [1][0][2][0][3][4] = 76, ++ [1][0][2][0][5][4] = 60, ++ [1][0][2][0][6][4] = 58, ++ [1][0][2][0][9][4] = 58, ++ [1][0][2][0][8][4] = 60, ++ [1][0][2][0][11][4] = 58, ++ [1][0][2][0][2][5] = 64, ++ [1][0][2][0][1][5] = 58, ++ [1][0][2][0][3][5] = 76, ++ [1][0][2][0][5][5] = 64, ++ [1][0][2][0][6][5] = 58, ++ [1][0][2][0][9][5] = 58, ++ [1][0][2][0][8][5] = 60, ++ [1][0][2][0][11][5] = 58, ++ [1][0][2][0][2][6] = 54, ++ [1][0][2][0][1][6] = 58, ++ [1][0][2][0][3][6] = 76, ++ [1][0][2][0][5][6] = 54, ++ [1][0][2][0][6][6] = 58, ++ [1][0][2][0][9][6] = 58, ++ [1][0][2][0][8][6] = 60, ++ [1][0][2][0][11][6] = 58, ++ [1][0][2][0][2][7] = 50, ++ [1][0][2][0][1][7] = 58, ++ [1][0][2][0][3][7] = 76, ++ [1][0][2][0][5][7] = 50, ++ [1][0][2][0][6][7] = 58, ++ [1][0][2][0][9][7] = 58, ++ [1][0][2][0][8][7] = 60, ++ [1][0][2][0][11][7] = 58, ++ [1][0][2][0][2][8] = 50, ++ [1][0][2][0][1][8] = 58, ++ [1][0][2][0][3][8] = 76, ++ [1][0][2][0][5][8] = 50, ++ [1][0][2][0][6][8] = 58, ++ [1][0][2][0][9][8] = 58, ++ [1][0][2][0][8][8] = 60, ++ [1][0][2][0][11][8] = 58, ++ [1][0][2][0][2][9] = 42, ++ [1][0][2][0][1][9] = 58, ++ [1][0][2][0][3][9] = 76, ++ [1][0][2][0][5][9] = 42, ++ [1][0][2][0][6][9] = 58, ++ [1][0][2][0][9][9] = 58, ++ [1][0][2][0][8][9] = 60, ++ [1][0][2][0][11][9] = 58, ++ [1][0][2][0][2][10] = 40, ++ [1][0][2][0][1][10] = 58, ++ [1][0][2][0][3][10] = 76, ++ [1][0][2][0][5][10] = 40, ++ [1][0][2][0][6][10] = 58, ++ [1][0][2][0][9][10] = 58, ++ [1][0][2][0][8][10] = 60, ++ [1][0][2][0][11][10] = 58, ++ [1][0][2][0][2][11] = 127, ++ [1][0][2][0][1][11] = 127, ++ [1][0][2][0][3][11] = 127, ++ [1][0][2][0][5][11] = 127, ++ [1][0][2][0][6][11] = 127, ++ [1][0][2][0][9][11] = 127, ++ [1][0][2][0][8][11] = 127, ++ [1][0][2][0][11][11] = 127, ++ [1][0][2][0][2][12] = 127, ++ [1][0][2][0][1][12] = 127, ++ [1][0][2][0][3][12] = 127, ++ [1][0][2][0][5][12] = 127, ++ [1][0][2][0][6][12] = 127, ++ [1][0][2][0][9][12] = 127, ++ [1][0][2][0][8][12] = 127, ++ [1][0][2][0][11][12] = 127, ++ [1][0][2][0][2][13] = 127, ++ [1][0][2][0][1][13] = 127, ++ [1][0][2][0][3][13] = 127, ++ [1][0][2][0][5][13] = 127, ++ [1][0][2][0][6][13] = 127, ++ [1][0][2][0][9][13] = 127, ++ [1][0][2][0][8][13] = 127, ++ [1][0][2][0][11][13] = 127, ++ [1][1][2][0][2][0] = 127, ++ [1][1][2][0][1][0] = 127, ++ [1][1][2][0][3][0] = 127, ++ [1][1][2][0][5][0] = 127, ++ [1][1][2][0][6][0] = 127, ++ [1][1][2][0][9][0] = 127, ++ [1][1][2][0][8][0] = 127, ++ [1][1][2][0][11][0] = 127, ++ [1][1][2][0][2][1] = 127, ++ [1][1][2][0][1][1] = 127, ++ [1][1][2][0][3][1] = 127, ++ [1][1][2][0][5][1] = 127, ++ [1][1][2][0][6][1] = 127, ++ [1][1][2][0][9][1] = 127, ++ [1][1][2][0][8][1] = 127, ++ [1][1][2][0][11][1] = 127, ++ [1][1][2][0][2][2] = 52, ++ [1][1][2][0][1][2] = 46, ++ [1][1][2][0][3][2] = 64, ++ [1][1][2][0][5][2] = 52, ++ [1][1][2][0][6][2] = 46, ++ [1][1][2][0][9][2] = 46, ++ [1][1][2][0][8][2] = 48, ++ [1][1][2][0][11][2] = 46, ++ [1][1][2][0][2][3] = 52, ++ [1][1][2][0][1][3] = 46, ++ [1][1][2][0][3][3] = 64, ++ [1][1][2][0][5][3] = 52, ++ [1][1][2][0][6][3] = 46, ++ [1][1][2][0][9][3] = 46, ++ [1][1][2][0][8][3] = 48, ++ [1][1][2][0][11][3] = 46, ++ [1][1][2][0][2][4] = 56, ++ [1][1][2][0][1][4] = 46, ++ [1][1][2][0][3][4] = 64, ++ [1][1][2][0][5][4] = 56, ++ [1][1][2][0][6][4] = 46, ++ [1][1][2][0][9][4] = 46, ++ [1][1][2][0][8][4] = 48, ++ [1][1][2][0][11][4] = 46, ++ [1][1][2][0][2][5] = 60, ++ [1][1][2][0][1][5] = 46, ++ [1][1][2][0][3][5] = 64, ++ [1][1][2][0][5][5] = 60, ++ [1][1][2][0][6][5] = 46, ++ [1][1][2][0][9][5] = 46, ++ [1][1][2][0][8][5] = 48, ++ [1][1][2][0][11][5] = 46, ++ [1][1][2][0][2][6] = 54, ++ [1][1][2][0][1][6] = 46, ++ [1][1][2][0][3][6] = 64, ++ [1][1][2][0][5][6] = 52, ++ [1][1][2][0][6][6] = 46, ++ [1][1][2][0][9][6] = 46, ++ [1][1][2][0][8][6] = 48, ++ [1][1][2][0][11][6] = 46, ++ [1][1][2][0][2][7] = 50, ++ [1][1][2][0][1][7] = 46, ++ [1][1][2][0][3][7] = 64, ++ [1][1][2][0][5][7] = 48, ++ [1][1][2][0][6][7] = 46, ++ [1][1][2][0][9][7] = 46, ++ [1][1][2][0][8][7] = 48, ++ [1][1][2][0][11][7] = 46, ++ [1][1][2][0][2][8] = 50, ++ [1][1][2][0][1][8] = 46, ++ [1][1][2][0][3][8] = 64, ++ [1][1][2][0][5][8] = 48, ++ [1][1][2][0][6][8] = 46, ++ [1][1][2][0][9][8] = 46, ++ [1][1][2][0][8][8] = 48, ++ [1][1][2][0][11][8] = 46, ++ [1][1][2][0][2][9] = 38, ++ [1][1][2][0][1][9] = 46, ++ [1][1][2][0][3][9] = 64, ++ [1][1][2][0][5][9] = 38, ++ [1][1][2][0][6][9] = 46, ++ [1][1][2][0][9][9] = 46, ++ [1][1][2][0][8][9] = 48, ++ [1][1][2][0][11][9] = 46, ++ [1][1][2][0][2][10] = 36, ++ [1][1][2][0][1][10] = 46, ++ [1][1][2][0][3][10] = 64, ++ [1][1][2][0][5][10] = 36, ++ [1][1][2][0][6][10] = 46, ++ [1][1][2][0][9][10] = 46, ++ [1][1][2][0][8][10] = 48, ++ [1][1][2][0][11][10] = 46, ++ [1][1][2][0][2][11] = 127, ++ [1][1][2][0][1][11] = 127, ++ [1][1][2][0][3][11] = 127, ++ [1][1][2][0][5][11] = 127, ++ [1][1][2][0][6][11] = 127, ++ [1][1][2][0][9][11] = 127, ++ [1][1][2][0][8][11] = 127, ++ [1][1][2][0][11][11] = 127, ++ [1][1][2][0][2][12] = 127, ++ [1][1][2][0][1][12] = 127, ++ [1][1][2][0][3][12] = 127, ++ [1][1][2][0][5][12] = 127, ++ [1][1][2][0][6][12] = 127, ++ [1][1][2][0][9][12] = 127, ++ [1][1][2][0][8][12] = 127, ++ [1][1][2][0][11][12] = 127, ++ [1][1][2][0][2][13] = 127, ++ [1][1][2][0][1][13] = 127, ++ [1][1][2][0][3][13] = 127, ++ [1][1][2][0][5][13] = 127, ++ [1][1][2][0][6][13] = 127, ++ [1][1][2][0][9][13] = 127, ++ [1][1][2][0][8][13] = 127, ++ [1][1][2][0][11][13] = 127, ++ [1][1][2][1][2][0] = 127, ++ [1][1][2][1][1][0] = 127, ++ [1][1][2][1][3][0] = 127, ++ [1][1][2][1][5][0] = 127, ++ [1][1][2][1][6][0] = 127, ++ [1][1][2][1][9][0] = 127, ++ [1][1][2][1][8][0] = 127, ++ [1][1][2][1][11][0] = 127, ++ [1][1][2][1][2][1] = 127, ++ [1][1][2][1][1][1] = 127, ++ [1][1][2][1][3][1] = 127, ++ [1][1][2][1][5][1] = 127, ++ [1][1][2][1][6][1] = 127, ++ [1][1][2][1][9][1] = 127, ++ [1][1][2][1][8][1] = 127, ++ [1][1][2][1][11][1] = 127, ++ [1][1][2][1][2][2] = 52, ++ [1][1][2][1][1][2] = 34, ++ [1][1][2][1][3][2] = 64, ++ [1][1][2][1][5][2] = 52, ++ [1][1][2][1][6][2] = 34, ++ [1][1][2][1][9][2] = 34, ++ [1][1][2][1][8][2] = 36, ++ [1][1][2][1][11][2] = 34, ++ [1][1][2][1][2][3] = 52, ++ [1][1][2][1][1][3] = 34, ++ [1][1][2][1][3][3] = 64, ++ [1][1][2][1][5][3] = 52, ++ [1][1][2][1][6][3] = 34, ++ [1][1][2][1][9][3] = 34, ++ [1][1][2][1][8][3] = 36, ++ [1][1][2][1][11][3] = 34, ++ [1][1][2][1][2][4] = 56, ++ [1][1][2][1][1][4] = 34, ++ [1][1][2][1][3][4] = 64, ++ [1][1][2][1][5][4] = 56, ++ [1][1][2][1][6][4] = 34, ++ [1][1][2][1][9][4] = 34, ++ [1][1][2][1][8][4] = 36, ++ [1][1][2][1][11][4] = 34, ++ [1][1][2][1][2][5] = 60, ++ [1][1][2][1][1][5] = 34, ++ [1][1][2][1][3][5] = 64, ++ [1][1][2][1][5][5] = 60, ++ [1][1][2][1][6][5] = 34, ++ [1][1][2][1][9][5] = 34, ++ [1][1][2][1][8][5] = 36, ++ [1][1][2][1][11][5] = 34, ++ [1][1][2][1][2][6] = 54, ++ [1][1][2][1][1][6] = 34, ++ [1][1][2][1][3][6] = 64, ++ [1][1][2][1][5][6] = 52, ++ [1][1][2][1][6][6] = 34, ++ [1][1][2][1][9][6] = 34, ++ [1][1][2][1][8][6] = 36, ++ [1][1][2][1][11][6] = 34, ++ [1][1][2][1][2][7] = 50, ++ [1][1][2][1][1][7] = 34, ++ [1][1][2][1][3][7] = 64, ++ [1][1][2][1][5][7] = 48, ++ [1][1][2][1][6][7] = 34, ++ [1][1][2][1][9][7] = 34, ++ [1][1][2][1][8][7] = 36, ++ [1][1][2][1][11][7] = 34, ++ [1][1][2][1][2][8] = 50, ++ [1][1][2][1][1][8] = 34, ++ [1][1][2][1][3][8] = 64, ++ [1][1][2][1][5][8] = 48, ++ [1][1][2][1][6][8] = 34, ++ [1][1][2][1][9][8] = 34, ++ [1][1][2][1][8][8] = 36, ++ [1][1][2][1][11][8] = 34, ++ [1][1][2][1][2][9] = 38, ++ [1][1][2][1][1][9] = 34, ++ [1][1][2][1][3][9] = 64, ++ [1][1][2][1][5][9] = 38, ++ [1][1][2][1][6][9] = 34, ++ [1][1][2][1][9][9] = 34, ++ [1][1][2][1][8][9] = 36, ++ [1][1][2][1][11][9] = 34, ++ [1][1][2][1][2][10] = 36, ++ [1][1][2][1][1][10] = 34, ++ [1][1][2][1][3][10] = 64, ++ [1][1][2][1][5][10] = 36, ++ [1][1][2][1][6][10] = 34, ++ [1][1][2][1][9][10] = 34, ++ [1][1][2][1][8][10] = 36, ++ [1][1][2][1][11][10] = 34, ++ [1][1][2][1][2][11] = 127, ++ [1][1][2][1][1][11] = 127, ++ [1][1][2][1][3][11] = 127, ++ [1][1][2][1][5][11] = 127, ++ [1][1][2][1][6][11] = 127, ++ [1][1][2][1][9][11] = 127, ++ [1][1][2][1][8][11] = 127, ++ [1][1][2][1][11][11] = 127, ++ [1][1][2][1][2][12] = 127, ++ [1][1][2][1][1][12] = 127, ++ [1][1][2][1][3][12] = 127, ++ [1][1][2][1][5][12] = 127, ++ [1][1][2][1][6][12] = 127, ++ [1][1][2][1][9][12] = 127, ++ [1][1][2][1][8][12] = 127, ++ [1][1][2][1][11][12] = 127, ++ [1][1][2][1][2][13] = 127, ++ [1][1][2][1][1][13] = 127, ++ [1][1][2][1][3][13] = 127, ++ [1][1][2][1][5][13] = 127, ++ [1][1][2][1][6][13] = 127, ++ [1][1][2][1][9][13] = 127, ++ [1][1][2][1][8][13] = 127, ++ [1][1][2][1][11][13] = 127, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { ++ [0][0][1][0][0][0] = 30, ++ [0][0][1][0][0][2] = 30, ++ [0][0][1][0][0][4] = 30, ++ [0][0][1][0][0][6] = 30, ++ [0][0][1][0][0][8] = 52, ++ [0][0][1][0][0][10] = 52, ++ [0][0][1][0][0][12] = 52, ++ [0][0][1][0][0][14] = 52, ++ [0][0][1][0][0][15] = 52, ++ [0][0][1][0][0][17] = 52, ++ [0][0][1][0][0][19] = 52, ++ [0][0][1][0][0][21] = 52, ++ [0][0][1][0][0][23] = 52, ++ [0][0][1][0][0][25] = 52, ++ [0][0][1][0][0][27] = 52, ++ [0][0][1][0][0][29] = 52, ++ [0][0][1][0][0][31] = 52, ++ [0][0][1][0][0][33] = 52, ++ [0][0][1][0][0][35] = 52, ++ [0][0][1][0][0][37] = 54, ++ [0][0][1][0][0][38] = 28, ++ [0][0][1][0][0][40] = 28, ++ [0][0][1][0][0][42] = 28, ++ [0][0][1][0][0][44] = 28, ++ [0][0][1][0][0][46] = 28, ++ [0][1][1][0][0][0] = 18, ++ [0][1][1][0][0][2] = 18, ++ [0][1][1][0][0][4] = 18, ++ [0][1][1][0][0][6] = 18, ++ [0][1][1][0][0][8] = 40, ++ [0][1][1][0][0][10] = 40, ++ [0][1][1][0][0][12] = 40, ++ [0][1][1][0][0][14] = 40, ++ [0][1][1][0][0][15] = 40, ++ [0][1][1][0][0][17] = 40, ++ [0][1][1][0][0][19] = 40, ++ [0][1][1][0][0][21] = 40, ++ [0][1][1][0][0][23] = 40, ++ [0][1][1][0][0][25] = 40, ++ [0][1][1][0][0][27] = 40, ++ [0][1][1][0][0][29] = 40, ++ [0][1][1][0][0][31] = 40, ++ [0][1][1][0][0][33] = 40, ++ [0][1][1][0][0][35] = 40, ++ [0][1][1][0][0][37] = 42, ++ [0][1][1][0][0][38] = 16, ++ [0][1][1][0][0][40] = 16, ++ [0][1][1][0][0][42] = 16, ++ [0][1][1][0][0][44] = 16, ++ [0][1][1][0][0][46] = 16, ++ [0][0][2][0][0][0] = 30, ++ [0][0][2][0][0][2] = 30, ++ [0][0][2][0][0][4] = 30, ++ [0][0][2][0][0][6] = 30, ++ [0][0][2][0][0][8] = 52, ++ [0][0][2][0][0][10] = 52, ++ [0][0][2][0][0][12] = 52, ++ [0][0][2][0][0][14] = 52, ++ [0][0][2][0][0][15] = 52, ++ [0][0][2][0][0][17] = 52, ++ [0][0][2][0][0][19] = 52, ++ [0][0][2][0][0][21] = 52, ++ [0][0][2][0][0][23] = 52, ++ [0][0][2][0][0][25] = 52, ++ [0][0][2][0][0][27] = 52, ++ [0][0][2][0][0][29] = 52, ++ [0][0][2][0][0][31] = 52, ++ [0][0][2][0][0][33] = 52, ++ [0][0][2][0][0][35] = 52, ++ [0][0][2][0][0][37] = 54, ++ [0][0][2][0][0][38] = 28, ++ [0][0][2][0][0][40] = 28, ++ [0][0][2][0][0][42] = 28, ++ [0][0][2][0][0][44] = 28, ++ [0][0][2][0][0][46] = 28, ++ [0][1][2][0][0][0] = 18, ++ [0][1][2][0][0][2] = 18, ++ [0][1][2][0][0][4] = 18, ++ [0][1][2][0][0][6] = 18, ++ [0][1][2][0][0][8] = 40, ++ [0][1][2][0][0][10] = 40, ++ [0][1][2][0][0][12] = 40, ++ [0][1][2][0][0][14] = 40, ++ [0][1][2][0][0][15] = 40, ++ [0][1][2][0][0][17] = 40, ++ [0][1][2][0][0][19] = 40, ++ [0][1][2][0][0][21] = 40, ++ [0][1][2][0][0][23] = 40, ++ [0][1][2][0][0][25] = 40, ++ [0][1][2][0][0][27] = 40, ++ [0][1][2][0][0][29] = 40, ++ [0][1][2][0][0][31] = 40, ++ [0][1][2][0][0][33] = 40, ++ [0][1][2][0][0][35] = 40, ++ [0][1][2][0][0][37] = 42, ++ [0][1][2][0][0][38] = 16, ++ [0][1][2][0][0][40] = 16, ++ [0][1][2][0][0][42] = 16, ++ [0][1][2][0][0][44] = 16, ++ [0][1][2][0][0][46] = 16, ++ [0][1][2][1][0][0] = 6, ++ [0][1][2][1][0][2] = 6, ++ [0][1][2][1][0][4] = 6, ++ [0][1][2][1][0][6] = 6, ++ [0][1][2][1][0][8] = 28, ++ [0][1][2][1][0][10] = 28, ++ [0][1][2][1][0][12] = 28, ++ [0][1][2][1][0][14] = 28, ++ [0][1][2][1][0][15] = 28, ++ [0][1][2][1][0][17] = 28, ++ [0][1][2][1][0][19] = 28, ++ [0][1][2][1][0][21] = 28, ++ [0][1][2][1][0][23] = 28, ++ [0][1][2][1][0][25] = 28, ++ [0][1][2][1][0][27] = 28, ++ [0][1][2][1][0][29] = 28, ++ [0][1][2][1][0][31] = 28, ++ [0][1][2][1][0][33] = 28, ++ [0][1][2][1][0][35] = 28, ++ [0][1][2][1][0][37] = 30, ++ [0][1][2][1][0][38] = 4, ++ [0][1][2][1][0][40] = 4, ++ [0][1][2][1][0][42] = 4, ++ [0][1][2][1][0][44] = 4, ++ [0][1][2][1][0][46] = 4, ++ [1][0][2][0][0][1] = 30, ++ [1][0][2][0][0][5] = 30, ++ [1][0][2][0][0][9] = 52, ++ [1][0][2][0][0][13] = 52, ++ [1][0][2][0][0][16] = 52, ++ [1][0][2][0][0][20] = 52, ++ [1][0][2][0][0][24] = 52, ++ [1][0][2][0][0][28] = 52, ++ [1][0][2][0][0][32] = 52, ++ [1][0][2][0][0][36] = 54, ++ [1][0][2][0][0][39] = 28, ++ [1][0][2][0][0][43] = 28, ++ [1][1][2][0][0][1] = 18, ++ [1][1][2][0][0][5] = 18, ++ [1][1][2][0][0][9] = 40, ++ [1][1][2][0][0][13] = 40, ++ [1][1][2][0][0][16] = 40, ++ [1][1][2][0][0][20] = 40, ++ [1][1][2][0][0][24] = 40, ++ [1][1][2][0][0][28] = 40, ++ [1][1][2][0][0][32] = 40, ++ [1][1][2][0][0][36] = 42, ++ [1][1][2][0][0][39] = 16, ++ [1][1][2][0][0][43] = 16, ++ [1][1][2][1][0][1] = 6, ++ [1][1][2][1][0][5] = 6, ++ [1][1][2][1][0][9] = 28, ++ [1][1][2][1][0][13] = 28, ++ [1][1][2][1][0][16] = 28, ++ [1][1][2][1][0][20] = 28, ++ [1][1][2][1][0][24] = 28, ++ [1][1][2][1][0][28] = 28, ++ [1][1][2][1][0][32] = 28, ++ [1][1][2][1][0][36] = 30, ++ [1][1][2][1][0][39] = 4, ++ [1][1][2][1][0][43] = 4, ++ [2][0][2][0][0][3] = 30, ++ [2][0][2][0][0][11] = 52, ++ [2][0][2][0][0][18] = 52, ++ [2][0][2][0][0][26] = 52, ++ [2][0][2][0][0][34] = 54, ++ [2][0][2][0][0][41] = 28, ++ [2][1][2][0][0][3] = 18, ++ [2][1][2][0][0][11] = 40, ++ [2][1][2][0][0][18] = 40, ++ [2][1][2][0][0][26] = 40, ++ [2][1][2][0][0][34] = 42, ++ [2][1][2][0][0][41] = 16, ++ [2][1][2][1][0][3] = 6, ++ [2][1][2][1][0][11] = 28, ++ [2][1][2][1][0][18] = 28, ++ [2][1][2][1][0][26] = 28, ++ [2][1][2][1][0][34] = 30, ++ [2][1][2][1][0][41] = 4, ++ [0][0][1][0][2][0] = 76, ++ [0][0][1][0][1][0] = 58, ++ [0][0][1][0][3][0] = 62, ++ [0][0][1][0][5][0] = 62, ++ [0][0][1][0][6][0] = 58, ++ [0][0][1][0][9][0] = 58, ++ [0][0][1][0][8][0] = 30, ++ [0][0][1][0][11][0] = 52, ++ [0][0][1][0][2][2] = 76, ++ [0][0][1][0][1][2] = 58, ++ [0][0][1][0][3][2] = 62, ++ [0][0][1][0][5][2] = 62, ++ [0][0][1][0][6][2] = 58, ++ [0][0][1][0][9][2] = 58, ++ [0][0][1][0][8][2] = 30, ++ [0][0][1][0][11][2] = 52, ++ [0][0][1][0][2][4] = 76, ++ [0][0][1][0][1][4] = 58, ++ [0][0][1][0][3][4] = 62, ++ [0][0][1][0][5][4] = 62, ++ [0][0][1][0][6][4] = 58, ++ [0][0][1][0][9][4] = 58, ++ [0][0][1][0][8][4] = 30, ++ [0][0][1][0][11][4] = 52, ++ [0][0][1][0][2][6] = 76, ++ [0][0][1][0][1][6] = 58, ++ [0][0][1][0][3][6] = 62, ++ [0][0][1][0][5][6] = 62, ++ [0][0][1][0][6][6] = 54, ++ [0][0][1][0][9][6] = 58, ++ [0][0][1][0][8][6] = 30, ++ [0][0][1][0][11][6] = 52, ++ [0][0][1][0][2][8] = 76, ++ [0][0][1][0][1][8] = 58, ++ [0][0][1][0][3][8] = 62, ++ [0][0][1][0][5][8] = 64, ++ [0][0][1][0][6][8] = 58, ++ [0][0][1][0][9][8] = 58, ++ [0][0][1][0][8][8] = 54, ++ [0][0][1][0][11][8] = 52, ++ [0][0][1][0][2][10] = 76, ++ [0][0][1][0][1][10] = 58, ++ [0][0][1][0][3][10] = 62, ++ [0][0][1][0][5][10] = 64, ++ [0][0][1][0][6][10] = 58, ++ [0][0][1][0][9][10] = 58, ++ [0][0][1][0][8][10] = 54, ++ [0][0][1][0][11][10] = 52, ++ [0][0][1][0][2][12] = 76, ++ [0][0][1][0][1][12] = 58, ++ [0][0][1][0][3][12] = 62, ++ [0][0][1][0][5][12] = 64, ++ [0][0][1][0][6][12] = 58, ++ [0][0][1][0][9][12] = 58, ++ [0][0][1][0][8][12] = 54, ++ [0][0][1][0][11][12] = 52, ++ [0][0][1][0][2][14] = 76, ++ [0][0][1][0][1][14] = 58, ++ [0][0][1][0][3][14] = 62, ++ [0][0][1][0][5][14] = 64, ++ [0][0][1][0][6][14] = 58, ++ [0][0][1][0][9][14] = 58, ++ [0][0][1][0][8][14] = 54, ++ [0][0][1][0][11][14] = 52, ++ [0][0][1][0][2][15] = 76, ++ [0][0][1][0][1][15] = 58, ++ [0][0][1][0][3][15] = 76, ++ [0][0][1][0][5][15] = 76, ++ [0][0][1][0][6][15] = 58, ++ [0][0][1][0][9][15] = 58, ++ [0][0][1][0][8][15] = 54, ++ [0][0][1][0][11][15] = 52, ++ [0][0][1][0][2][17] = 76, ++ [0][0][1][0][1][17] = 58, ++ [0][0][1][0][3][17] = 76, ++ [0][0][1][0][5][17] = 76, ++ [0][0][1][0][6][17] = 58, ++ [0][0][1][0][9][17] = 58, ++ [0][0][1][0][8][17] = 54, ++ [0][0][1][0][11][17] = 52, ++ [0][0][1][0][2][19] = 76, ++ [0][0][1][0][1][19] = 58, ++ [0][0][1][0][3][19] = 76, ++ [0][0][1][0][5][19] = 76, ++ [0][0][1][0][6][19] = 58, ++ [0][0][1][0][9][19] = 58, ++ [0][0][1][0][8][19] = 54, ++ [0][0][1][0][11][19] = 52, ++ [0][0][1][0][2][21] = 76, ++ [0][0][1][0][1][21] = 58, ++ [0][0][1][0][3][21] = 76, ++ [0][0][1][0][5][21] = 76, ++ [0][0][1][0][6][21] = 58, ++ [0][0][1][0][9][21] = 58, ++ [0][0][1][0][8][21] = 54, ++ [0][0][1][0][11][21] = 52, ++ [0][0][1][0][2][23] = 76, ++ [0][0][1][0][1][23] = 58, ++ [0][0][1][0][3][23] = 76, ++ [0][0][1][0][5][23] = 76, ++ [0][0][1][0][6][23] = 58, ++ [0][0][1][0][9][23] = 58, ++ [0][0][1][0][8][23] = 54, ++ [0][0][1][0][11][23] = 52, ++ [0][0][1][0][2][25] = 76, ++ [0][0][1][0][1][25] = 58, ++ [0][0][1][0][3][25] = 76, ++ [0][0][1][0][5][25] = 127, ++ [0][0][1][0][6][25] = 58, ++ [0][0][1][0][9][25] = 127, ++ [0][0][1][0][8][25] = 54, ++ [0][0][1][0][11][25] = 52, ++ [0][0][1][0][2][27] = 76, ++ [0][0][1][0][1][27] = 58, ++ [0][0][1][0][3][27] = 76, ++ [0][0][1][0][5][27] = 127, ++ [0][0][1][0][6][27] = 58, ++ [0][0][1][0][9][27] = 127, ++ [0][0][1][0][8][27] = 54, ++ [0][0][1][0][11][27] = 52, ++ [0][0][1][0][2][29] = 76, ++ [0][0][1][0][1][29] = 58, ++ [0][0][1][0][3][29] = 76, ++ [0][0][1][0][5][29] = 127, ++ [0][0][1][0][6][29] = 58, ++ [0][0][1][0][9][29] = 127, ++ [0][0][1][0][8][29] = 54, ++ [0][0][1][0][11][29] = 52, ++ [0][0][1][0][2][31] = 76, ++ [0][0][1][0][1][31] = 58, ++ [0][0][1][0][3][31] = 76, ++ [0][0][1][0][5][31] = 76, ++ [0][0][1][0][6][31] = 58, ++ [0][0][1][0][9][31] = 58, ++ [0][0][1][0][8][31] = 54, ++ [0][0][1][0][11][31] = 52, ++ [0][0][1][0][2][33] = 76, ++ [0][0][1][0][1][33] = 58, ++ [0][0][1][0][3][33] = 76, ++ [0][0][1][0][5][33] = 76, ++ [0][0][1][0][6][33] = 58, ++ [0][0][1][0][9][33] = 58, ++ [0][0][1][0][8][33] = 54, ++ [0][0][1][0][11][33] = 52, ++ [0][0][1][0][2][35] = 74, ++ [0][0][1][0][1][35] = 58, ++ [0][0][1][0][3][35] = 76, ++ [0][0][1][0][5][35] = 74, ++ [0][0][1][0][6][35] = 58, ++ [0][0][1][0][9][35] = 58, ++ [0][0][1][0][8][35] = 54, ++ [0][0][1][0][11][35] = 52, ++ [0][0][1][0][2][37] = 76, ++ [0][0][1][0][1][37] = 127, ++ [0][0][1][0][3][37] = 76, ++ [0][0][1][0][5][37] = 76, ++ [0][0][1][0][6][37] = 58, ++ [0][0][1][0][9][37] = 76, ++ [0][0][1][0][8][37] = 54, ++ [0][0][1][0][11][37] = 127, ++ [0][0][1][0][2][38] = 76, ++ [0][0][1][0][1][38] = 28, ++ [0][0][1][0][3][38] = 127, ++ [0][0][1][0][5][38] = 76, ++ [0][0][1][0][6][38] = 28, ++ [0][0][1][0][9][38] = 76, ++ [0][0][1][0][8][38] = 54, ++ [0][0][1][0][11][38] = 52, ++ [0][0][1][0][2][40] = 76, ++ [0][0][1][0][1][40] = 28, ++ [0][0][1][0][3][40] = 127, ++ [0][0][1][0][5][40] = 76, ++ [0][0][1][0][6][40] = 28, ++ [0][0][1][0][9][40] = 76, ++ [0][0][1][0][8][40] = 54, ++ [0][0][1][0][11][40] = 52, ++ [0][0][1][0][2][42] = 76, ++ [0][0][1][0][1][42] = 28, ++ [0][0][1][0][3][42] = 127, ++ [0][0][1][0][5][42] = 76, ++ [0][0][1][0][6][42] = 28, ++ [0][0][1][0][9][42] = 76, ++ [0][0][1][0][8][42] = 54, ++ [0][0][1][0][11][42] = 52, ++ [0][0][1][0][2][44] = 76, ++ [0][0][1][0][1][44] = 28, ++ [0][0][1][0][3][44] = 127, ++ [0][0][1][0][5][44] = 76, ++ [0][0][1][0][6][44] = 28, ++ [0][0][1][0][9][44] = 76, ++ [0][0][1][0][8][44] = 54, ++ [0][0][1][0][11][44] = 52, ++ [0][0][1][0][2][46] = 76, ++ [0][0][1][0][1][46] = 28, ++ [0][0][1][0][3][46] = 127, ++ [0][0][1][0][5][46] = 76, ++ [0][0][1][0][6][46] = 28, ++ [0][0][1][0][9][46] = 76, ++ [0][0][1][0][8][46] = 54, ++ [0][0][1][0][11][46] = 52, ++ [0][1][1][0][2][0] = 68, ++ [0][1][1][0][1][0] = 46, ++ [0][1][1][0][3][0] = 50, ++ [0][1][1][0][5][0] = 40, ++ [0][1][1][0][6][0] = 46, ++ [0][1][1][0][9][0] = 46, ++ [0][1][1][0][8][0] = 18, ++ [0][1][1][0][11][0] = 40, ++ [0][1][1][0][2][2] = 68, ++ [0][1][1][0][1][2] = 46, ++ [0][1][1][0][3][2] = 50, ++ [0][1][1][0][5][2] = 40, ++ [0][1][1][0][6][2] = 46, ++ [0][1][1][0][9][2] = 46, ++ [0][1][1][0][8][2] = 18, ++ [0][1][1][0][11][2] = 40, ++ [0][1][1][0][2][4] = 68, ++ [0][1][1][0][1][4] = 46, ++ [0][1][1][0][3][4] = 50, ++ [0][1][1][0][5][4] = 40, ++ [0][1][1][0][6][4] = 46, ++ [0][1][1][0][9][4] = 46, ++ [0][1][1][0][8][4] = 18, ++ [0][1][1][0][11][4] = 40, ++ [0][1][1][0][2][6] = 68, ++ [0][1][1][0][1][6] = 46, ++ [0][1][1][0][3][6] = 50, ++ [0][1][1][0][5][6] = 40, ++ [0][1][1][0][6][6] = 36, ++ [0][1][1][0][9][6] = 46, ++ [0][1][1][0][8][6] = 18, ++ [0][1][1][0][11][6] = 40, ++ [0][1][1][0][2][8] = 68, ++ [0][1][1][0][1][8] = 46, ++ [0][1][1][0][3][8] = 50, ++ [0][1][1][0][5][8] = 52, ++ [0][1][1][0][6][8] = 46, ++ [0][1][1][0][9][8] = 46, ++ [0][1][1][0][8][8] = 42, ++ [0][1][1][0][11][8] = 40, ++ [0][1][1][0][2][10] = 68, ++ [0][1][1][0][1][10] = 46, ++ [0][1][1][0][3][10] = 50, ++ [0][1][1][0][5][10] = 52, ++ [0][1][1][0][6][10] = 46, ++ [0][1][1][0][9][10] = 46, ++ [0][1][1][0][8][10] = 42, ++ [0][1][1][0][11][10] = 40, ++ [0][1][1][0][2][12] = 68, ++ [0][1][1][0][1][12] = 46, ++ [0][1][1][0][3][12] = 50, ++ [0][1][1][0][5][12] = 52, ++ [0][1][1][0][6][12] = 46, ++ [0][1][1][0][9][12] = 46, ++ [0][1][1][0][8][12] = 42, ++ [0][1][1][0][11][12] = 40, ++ [0][1][1][0][2][14] = 68, ++ [0][1][1][0][1][14] = 46, ++ [0][1][1][0][3][14] = 50, ++ [0][1][1][0][5][14] = 52, ++ [0][1][1][0][6][14] = 46, ++ [0][1][1][0][9][14] = 46, ++ [0][1][1][0][8][14] = 42, ++ [0][1][1][0][11][14] = 40, ++ [0][1][1][0][2][15] = 68, ++ [0][1][1][0][1][15] = 46, ++ [0][1][1][0][3][15] = 70, ++ [0][1][1][0][5][15] = 68, ++ [0][1][1][0][6][15] = 46, ++ [0][1][1][0][9][15] = 46, ++ [0][1][1][0][8][15] = 42, ++ [0][1][1][0][11][15] = 40, ++ [0][1][1][0][2][17] = 68, ++ [0][1][1][0][1][17] = 46, ++ [0][1][1][0][3][17] = 70, ++ [0][1][1][0][5][17] = 68, ++ [0][1][1][0][6][17] = 46, ++ [0][1][1][0][9][17] = 46, ++ [0][1][1][0][8][17] = 42, ++ [0][1][1][0][11][17] = 40, ++ [0][1][1][0][2][19] = 68, ++ [0][1][1][0][1][19] = 46, ++ [0][1][1][0][3][19] = 70, ++ [0][1][1][0][5][19] = 68, ++ [0][1][1][0][6][19] = 46, ++ [0][1][1][0][9][19] = 46, ++ [0][1][1][0][8][19] = 42, ++ [0][1][1][0][11][19] = 40, ++ [0][1][1][0][2][21] = 68, ++ [0][1][1][0][1][21] = 46, ++ [0][1][1][0][3][21] = 70, ++ [0][1][1][0][5][21] = 68, ++ [0][1][1][0][6][21] = 46, ++ [0][1][1][0][9][21] = 46, ++ [0][1][1][0][8][21] = 42, ++ [0][1][1][0][11][21] = 40, ++ [0][1][1][0][2][23] = 68, ++ [0][1][1][0][1][23] = 46, ++ [0][1][1][0][3][23] = 70, ++ [0][1][1][0][5][23] = 68, ++ [0][1][1][0][6][23] = 46, ++ [0][1][1][0][9][23] = 46, ++ [0][1][1][0][8][23] = 42, ++ [0][1][1][0][11][23] = 40, ++ [0][1][1][0][2][25] = 68, ++ [0][1][1][0][1][25] = 46, ++ [0][1][1][0][3][25] = 70, ++ [0][1][1][0][5][25] = 127, ++ [0][1][1][0][6][25] = 46, ++ [0][1][1][0][9][25] = 127, ++ [0][1][1][0][8][25] = 42, ++ [0][1][1][0][11][25] = 40, ++ [0][1][1][0][2][27] = 68, ++ [0][1][1][0][1][27] = 46, ++ [0][1][1][0][3][27] = 70, ++ [0][1][1][0][5][27] = 127, ++ [0][1][1][0][6][27] = 46, ++ [0][1][1][0][9][27] = 127, ++ [0][1][1][0][8][27] = 42, ++ [0][1][1][0][11][27] = 40, ++ [0][1][1][0][2][29] = 68, ++ [0][1][1][0][1][29] = 46, ++ [0][1][1][0][3][29] = 70, ++ [0][1][1][0][5][29] = 127, ++ [0][1][1][0][6][29] = 46, ++ [0][1][1][0][9][29] = 127, ++ [0][1][1][0][8][29] = 42, ++ [0][1][1][0][11][29] = 40, ++ [0][1][1][0][2][31] = 68, ++ [0][1][1][0][1][31] = 46, ++ [0][1][1][0][3][31] = 70, ++ [0][1][1][0][5][31] = 68, ++ [0][1][1][0][6][31] = 46, ++ [0][1][1][0][9][31] = 46, ++ [0][1][1][0][8][31] = 42, ++ [0][1][1][0][11][31] = 40, ++ [0][1][1][0][2][33] = 68, ++ [0][1][1][0][1][33] = 46, ++ [0][1][1][0][3][33] = 70, ++ [0][1][1][0][5][33] = 68, ++ [0][1][1][0][6][33] = 46, ++ [0][1][1][0][9][33] = 46, ++ [0][1][1][0][8][33] = 42, ++ [0][1][1][0][11][33] = 40, ++ [0][1][1][0][2][35] = 66, ++ [0][1][1][0][1][35] = 46, ++ [0][1][1][0][3][35] = 70, ++ [0][1][1][0][5][35] = 66, ++ [0][1][1][0][6][35] = 46, ++ [0][1][1][0][9][35] = 46, ++ [0][1][1][0][8][35] = 42, ++ [0][1][1][0][11][35] = 40, ++ [0][1][1][0][2][37] = 68, ++ [0][1][1][0][1][37] = 127, ++ [0][1][1][0][3][37] = 70, ++ [0][1][1][0][5][37] = 68, ++ [0][1][1][0][6][37] = 46, ++ [0][1][1][0][9][37] = 68, ++ [0][1][1][0][8][37] = 42, ++ [0][1][1][0][11][37] = 127, ++ [0][1][1][0][2][38] = 76, ++ [0][1][1][0][1][38] = 16, ++ [0][1][1][0][3][38] = 127, ++ [0][1][1][0][5][38] = 76, ++ [0][1][1][0][6][38] = 16, ++ [0][1][1][0][9][38] = 76, ++ [0][1][1][0][8][38] = 42, ++ [0][1][1][0][11][38] = 40, ++ [0][1][1][0][2][40] = 76, ++ [0][1][1][0][1][40] = 16, ++ [0][1][1][0][3][40] = 127, ++ [0][1][1][0][5][40] = 76, ++ [0][1][1][0][6][40] = 16, ++ [0][1][1][0][9][40] = 76, ++ [0][1][1][0][8][40] = 42, ++ [0][1][1][0][11][40] = 40, ++ [0][1][1][0][2][42] = 76, ++ [0][1][1][0][1][42] = 16, ++ [0][1][1][0][3][42] = 127, ++ [0][1][1][0][5][42] = 76, ++ [0][1][1][0][6][42] = 16, ++ [0][1][1][0][9][42] = 76, ++ [0][1][1][0][8][42] = 42, ++ [0][1][1][0][11][42] = 40, ++ [0][1][1][0][2][44] = 76, ++ [0][1][1][0][1][44] = 16, ++ [0][1][1][0][3][44] = 127, ++ [0][1][1][0][5][44] = 76, ++ [0][1][1][0][6][44] = 16, ++ [0][1][1][0][9][44] = 76, ++ [0][1][1][0][8][44] = 42, ++ [0][1][1][0][11][44] = 40, ++ [0][1][1][0][2][46] = 76, ++ [0][1][1][0][1][46] = 16, ++ [0][1][1][0][3][46] = 127, ++ [0][1][1][0][5][46] = 76, ++ [0][1][1][0][6][46] = 16, ++ [0][1][1][0][9][46] = 76, ++ [0][1][1][0][8][46] = 42, ++ [0][1][1][0][11][46] = 40, ++ [0][0][2][0][2][0] = 76, ++ [0][0][2][0][1][0] = 58, ++ [0][0][2][0][3][0] = 62, ++ [0][0][2][0][5][0] = 62, ++ [0][0][2][0][6][0] = 58, ++ [0][0][2][0][9][0] = 58, ++ [0][0][2][0][8][0] = 30, ++ [0][0][2][0][11][0] = 52, ++ [0][0][2][0][2][2] = 76, ++ [0][0][2][0][1][2] = 58, ++ [0][0][2][0][3][2] = 62, ++ [0][0][2][0][5][2] = 62, ++ [0][0][2][0][6][2] = 58, ++ [0][0][2][0][9][2] = 58, ++ [0][0][2][0][8][2] = 30, ++ [0][0][2][0][11][2] = 52, ++ [0][0][2][0][2][4] = 76, ++ [0][0][2][0][1][4] = 58, ++ [0][0][2][0][3][4] = 62, ++ [0][0][2][0][5][4] = 62, ++ [0][0][2][0][6][4] = 58, ++ [0][0][2][0][9][4] = 58, ++ [0][0][2][0][8][4] = 30, ++ [0][0][2][0][11][4] = 52, ++ [0][0][2][0][2][6] = 76, ++ [0][0][2][0][1][6] = 58, ++ [0][0][2][0][3][6] = 62, ++ [0][0][2][0][5][6] = 62, ++ [0][0][2][0][6][6] = 54, ++ [0][0][2][0][9][6] = 58, ++ [0][0][2][0][8][6] = 30, ++ [0][0][2][0][11][6] = 52, ++ [0][0][2][0][2][8] = 76, ++ [0][0][2][0][1][8] = 58, ++ [0][0][2][0][3][8] = 62, ++ [0][0][2][0][5][8] = 64, ++ [0][0][2][0][6][8] = 58, ++ [0][0][2][0][9][8] = 58, ++ [0][0][2][0][8][8] = 54, ++ [0][0][2][0][11][8] = 52, ++ [0][0][2][0][2][10] = 76, ++ [0][0][2][0][1][10] = 58, ++ [0][0][2][0][3][10] = 62, ++ [0][0][2][0][5][10] = 64, ++ [0][0][2][0][6][10] = 58, ++ [0][0][2][0][9][10] = 58, ++ [0][0][2][0][8][10] = 54, ++ [0][0][2][0][11][10] = 52, ++ [0][0][2][0][2][12] = 76, ++ [0][0][2][0][1][12] = 58, ++ [0][0][2][0][3][12] = 62, ++ [0][0][2][0][5][12] = 64, ++ [0][0][2][0][6][12] = 58, ++ [0][0][2][0][9][12] = 58, ++ [0][0][2][0][8][12] = 54, ++ [0][0][2][0][11][12] = 52, ++ [0][0][2][0][2][14] = 76, ++ [0][0][2][0][1][14] = 58, ++ [0][0][2][0][3][14] = 62, ++ [0][0][2][0][5][14] = 64, ++ [0][0][2][0][6][14] = 58, ++ [0][0][2][0][9][14] = 58, ++ [0][0][2][0][8][14] = 54, ++ [0][0][2][0][11][14] = 52, ++ [0][0][2][0][2][15] = 74, ++ [0][0][2][0][1][15] = 58, ++ [0][0][2][0][3][15] = 76, ++ [0][0][2][0][5][15] = 74, ++ [0][0][2][0][6][15] = 58, ++ [0][0][2][0][9][15] = 58, ++ [0][0][2][0][8][15] = 54, ++ [0][0][2][0][11][15] = 52, ++ [0][0][2][0][2][17] = 76, ++ [0][0][2][0][1][17] = 58, ++ [0][0][2][0][3][17] = 76, ++ [0][0][2][0][5][17] = 76, ++ [0][0][2][0][6][17] = 58, ++ [0][0][2][0][9][17] = 58, ++ [0][0][2][0][8][17] = 54, ++ [0][0][2][0][11][17] = 52, ++ [0][0][2][0][2][19] = 76, ++ [0][0][2][0][1][19] = 58, ++ [0][0][2][0][3][19] = 76, ++ [0][0][2][0][5][19] = 76, ++ [0][0][2][0][6][19] = 58, ++ [0][0][2][0][9][19] = 58, ++ [0][0][2][0][8][19] = 54, ++ [0][0][2][0][11][19] = 52, ++ [0][0][2][0][2][21] = 76, ++ [0][0][2][0][1][21] = 58, ++ [0][0][2][0][3][21] = 76, ++ [0][0][2][0][5][21] = 76, ++ [0][0][2][0][6][21] = 58, ++ [0][0][2][0][9][21] = 58, ++ [0][0][2][0][8][21] = 54, ++ [0][0][2][0][11][21] = 52, ++ [0][0][2][0][2][23] = 76, ++ [0][0][2][0][1][23] = 58, ++ [0][0][2][0][3][23] = 76, ++ [0][0][2][0][5][23] = 76, ++ [0][0][2][0][6][23] = 58, ++ [0][0][2][0][9][23] = 58, ++ [0][0][2][0][8][23] = 54, ++ [0][0][2][0][11][23] = 52, ++ [0][0][2][0][2][25] = 76, ++ [0][0][2][0][1][25] = 58, ++ [0][0][2][0][3][25] = 76, ++ [0][0][2][0][5][25] = 127, ++ [0][0][2][0][6][25] = 58, ++ [0][0][2][0][9][25] = 127, ++ [0][0][2][0][8][25] = 54, ++ [0][0][2][0][11][25] = 52, ++ [0][0][2][0][2][27] = 76, ++ [0][0][2][0][1][27] = 58, ++ [0][0][2][0][3][27] = 76, ++ [0][0][2][0][5][27] = 127, ++ [0][0][2][0][6][27] = 58, ++ [0][0][2][0][9][27] = 127, ++ [0][0][2][0][8][27] = 54, ++ [0][0][2][0][11][27] = 52, ++ [0][0][2][0][2][29] = 76, ++ [0][0][2][0][1][29] = 58, ++ [0][0][2][0][3][29] = 76, ++ [0][0][2][0][5][29] = 127, ++ [0][0][2][0][6][29] = 58, ++ [0][0][2][0][9][29] = 127, ++ [0][0][2][0][8][29] = 54, ++ [0][0][2][0][11][29] = 52, ++ [0][0][2][0][2][31] = 76, ++ [0][0][2][0][1][31] = 58, ++ [0][0][2][0][3][31] = 76, ++ [0][0][2][0][5][31] = 76, ++ [0][0][2][0][6][31] = 58, ++ [0][0][2][0][9][31] = 58, ++ [0][0][2][0][8][31] = 54, ++ [0][0][2][0][11][31] = 52, ++ [0][0][2][0][2][33] = 76, ++ [0][0][2][0][1][33] = 58, ++ [0][0][2][0][3][33] = 76, ++ [0][0][2][0][5][33] = 76, ++ [0][0][2][0][6][33] = 58, ++ [0][0][2][0][9][33] = 58, ++ [0][0][2][0][8][33] = 54, ++ [0][0][2][0][11][33] = 52, ++ [0][0][2][0][2][35] = 70, ++ [0][0][2][0][1][35] = 58, ++ [0][0][2][0][3][35] = 76, ++ [0][0][2][0][5][35] = 70, ++ [0][0][2][0][6][35] = 58, ++ [0][0][2][0][9][35] = 58, ++ [0][0][2][0][8][35] = 54, ++ [0][0][2][0][11][35] = 52, ++ [0][0][2][0][2][37] = 76, ++ [0][0][2][0][1][37] = 127, ++ [0][0][2][0][3][37] = 76, ++ [0][0][2][0][5][37] = 76, ++ [0][0][2][0][6][37] = 58, ++ [0][0][2][0][9][37] = 76, ++ [0][0][2][0][8][37] = 54, ++ [0][0][2][0][11][37] = 127, ++ [0][0][2][0][2][38] = 76, ++ [0][0][2][0][1][38] = 28, ++ [0][0][2][0][3][38] = 127, ++ [0][0][2][0][5][38] = 76, ++ [0][0][2][0][6][38] = 28, ++ [0][0][2][0][9][38] = 76, ++ [0][0][2][0][8][38] = 54, ++ [0][0][2][0][11][38] = 52, ++ [0][0][2][0][2][40] = 76, ++ [0][0][2][0][1][40] = 28, ++ [0][0][2][0][3][40] = 127, ++ [0][0][2][0][5][40] = 76, ++ [0][0][2][0][6][40] = 28, ++ [0][0][2][0][9][40] = 76, ++ [0][0][2][0][8][40] = 54, ++ [0][0][2][0][11][40] = 52, ++ [0][0][2][0][2][42] = 76, ++ [0][0][2][0][1][42] = 28, ++ [0][0][2][0][3][42] = 127, ++ [0][0][2][0][5][42] = 76, ++ [0][0][2][0][6][42] = 28, ++ [0][0][2][0][9][42] = 76, ++ [0][0][2][0][8][42] = 54, ++ [0][0][2][0][11][42] = 52, ++ [0][0][2][0][2][44] = 76, ++ [0][0][2][0][1][44] = 28, ++ [0][0][2][0][3][44] = 127, ++ [0][0][2][0][5][44] = 76, ++ [0][0][2][0][6][44] = 28, ++ [0][0][2][0][9][44] = 76, ++ [0][0][2][0][8][44] = 54, ++ [0][0][2][0][11][44] = 52, ++ [0][0][2][0][2][46] = 76, ++ [0][0][2][0][1][46] = 28, ++ [0][0][2][0][3][46] = 127, ++ [0][0][2][0][5][46] = 76, ++ [0][0][2][0][6][46] = 28, ++ [0][0][2][0][9][46] = 76, ++ [0][0][2][0][8][46] = 54, ++ [0][0][2][0][11][46] = 52, ++ [0][1][2][0][2][0] = 68, ++ [0][1][2][0][1][0] = 46, ++ [0][1][2][0][3][0] = 50, ++ [0][1][2][0][5][0] = 40, ++ [0][1][2][0][6][0] = 46, ++ [0][1][2][0][9][0] = 46, ++ [0][1][2][0][8][0] = 18, ++ [0][1][2][0][11][0] = 40, ++ [0][1][2][0][2][2] = 68, ++ [0][1][2][0][1][2] = 46, ++ [0][1][2][0][3][2] = 50, ++ [0][1][2][0][5][2] = 40, ++ [0][1][2][0][6][2] = 46, ++ [0][1][2][0][9][2] = 46, ++ [0][1][2][0][8][2] = 18, ++ [0][1][2][0][11][2] = 40, ++ [0][1][2][0][2][4] = 68, ++ [0][1][2][0][1][4] = 46, ++ [0][1][2][0][3][4] = 50, ++ [0][1][2][0][5][4] = 40, ++ [0][1][2][0][6][4] = 46, ++ [0][1][2][0][9][4] = 46, ++ [0][1][2][0][8][4] = 18, ++ [0][1][2][0][11][4] = 40, ++ [0][1][2][0][2][6] = 68, ++ [0][1][2][0][1][6] = 46, ++ [0][1][2][0][3][6] = 50, ++ [0][1][2][0][5][6] = 40, ++ [0][1][2][0][6][6] = 36, ++ [0][1][2][0][9][6] = 46, ++ [0][1][2][0][8][6] = 18, ++ [0][1][2][0][11][6] = 40, ++ [0][1][2][0][2][8] = 68, ++ [0][1][2][0][1][8] = 46, ++ [0][1][2][0][3][8] = 50, ++ [0][1][2][0][5][8] = 52, ++ [0][1][2][0][6][8] = 46, ++ [0][1][2][0][9][8] = 46, ++ [0][1][2][0][8][8] = 42, ++ [0][1][2][0][11][8] = 40, ++ [0][1][2][0][2][10] = 68, ++ [0][1][2][0][1][10] = 46, ++ [0][1][2][0][3][10] = 50, ++ [0][1][2][0][5][10] = 52, ++ [0][1][2][0][6][10] = 46, ++ [0][1][2][0][9][10] = 46, ++ [0][1][2][0][8][10] = 42, ++ [0][1][2][0][11][10] = 40, ++ [0][1][2][0][2][12] = 68, ++ [0][1][2][0][1][12] = 46, ++ [0][1][2][0][3][12] = 50, ++ [0][1][2][0][5][12] = 52, ++ [0][1][2][0][6][12] = 46, ++ [0][1][2][0][9][12] = 46, ++ [0][1][2][0][8][12] = 42, ++ [0][1][2][0][11][12] = 40, ++ [0][1][2][0][2][14] = 68, ++ [0][1][2][0][1][14] = 46, ++ [0][1][2][0][3][14] = 50, ++ [0][1][2][0][5][14] = 52, ++ [0][1][2][0][6][14] = 46, ++ [0][1][2][0][9][14] = 46, ++ [0][1][2][0][8][14] = 42, ++ [0][1][2][0][11][14] = 40, ++ [0][1][2][0][2][15] = 68, ++ [0][1][2][0][1][15] = 46, ++ [0][1][2][0][3][15] = 70, ++ [0][1][2][0][5][15] = 68, ++ [0][1][2][0][6][15] = 46, ++ [0][1][2][0][9][15] = 46, ++ [0][1][2][0][8][15] = 42, ++ [0][1][2][0][11][15] = 40, ++ [0][1][2][0][2][17] = 68, ++ [0][1][2][0][1][17] = 46, ++ [0][1][2][0][3][17] = 70, ++ [0][1][2][0][5][17] = 68, ++ [0][1][2][0][6][17] = 46, ++ [0][1][2][0][9][17] = 46, ++ [0][1][2][0][8][17] = 42, ++ [0][1][2][0][11][17] = 40, ++ [0][1][2][0][2][19] = 68, ++ [0][1][2][0][1][19] = 46, ++ [0][1][2][0][3][19] = 70, ++ [0][1][2][0][5][19] = 68, ++ [0][1][2][0][6][19] = 46, ++ [0][1][2][0][9][19] = 46, ++ [0][1][2][0][8][19] = 42, ++ [0][1][2][0][11][19] = 40, ++ [0][1][2][0][2][21] = 68, ++ [0][1][2][0][1][21] = 46, ++ [0][1][2][0][3][21] = 70, ++ [0][1][2][0][5][21] = 68, ++ [0][1][2][0][6][21] = 46, ++ [0][1][2][0][9][21] = 46, ++ [0][1][2][0][8][21] = 42, ++ [0][1][2][0][11][21] = 40, ++ [0][1][2][0][2][23] = 68, ++ [0][1][2][0][1][23] = 46, ++ [0][1][2][0][3][23] = 70, ++ [0][1][2][0][5][23] = 68, ++ [0][1][2][0][6][23] = 46, ++ [0][1][2][0][9][23] = 46, ++ [0][1][2][0][8][23] = 42, ++ [0][1][2][0][11][23] = 40, ++ [0][1][2][0][2][25] = 68, ++ [0][1][2][0][1][25] = 46, ++ [0][1][2][0][3][25] = 70, ++ [0][1][2][0][5][25] = 127, ++ [0][1][2][0][6][25] = 46, ++ [0][1][2][0][9][25] = 127, ++ [0][1][2][0][8][25] = 42, ++ [0][1][2][0][11][25] = 40, ++ [0][1][2][0][2][27] = 68, ++ [0][1][2][0][1][27] = 46, ++ [0][1][2][0][3][27] = 70, ++ [0][1][2][0][5][27] = 127, ++ [0][1][2][0][6][27] = 46, ++ [0][1][2][0][9][27] = 127, ++ [0][1][2][0][8][27] = 42, ++ [0][1][2][0][11][27] = 40, ++ [0][1][2][0][2][29] = 68, ++ [0][1][2][0][1][29] = 46, ++ [0][1][2][0][3][29] = 70, ++ [0][1][2][0][5][29] = 127, ++ [0][1][2][0][6][29] = 46, ++ [0][1][2][0][9][29] = 127, ++ [0][1][2][0][8][29] = 42, ++ [0][1][2][0][11][29] = 40, ++ [0][1][2][0][2][31] = 68, ++ [0][1][2][0][1][31] = 46, ++ [0][1][2][0][3][31] = 70, ++ [0][1][2][0][5][31] = 68, ++ [0][1][2][0][6][31] = 46, ++ [0][1][2][0][9][31] = 46, ++ [0][1][2][0][8][31] = 42, ++ [0][1][2][0][11][31] = 40, ++ [0][1][2][0][2][33] = 68, ++ [0][1][2][0][1][33] = 46, ++ [0][1][2][0][3][33] = 70, ++ [0][1][2][0][5][33] = 68, ++ [0][1][2][0][6][33] = 46, ++ [0][1][2][0][9][33] = 46, ++ [0][1][2][0][8][33] = 42, ++ [0][1][2][0][11][33] = 40, ++ [0][1][2][0][2][35] = 64, ++ [0][1][2][0][1][35] = 46, ++ [0][1][2][0][3][35] = 70, ++ [0][1][2][0][5][35] = 64, ++ [0][1][2][0][6][35] = 46, ++ [0][1][2][0][9][35] = 46, ++ [0][1][2][0][8][35] = 42, ++ [0][1][2][0][11][35] = 40, ++ [0][1][2][0][2][37] = 68, ++ [0][1][2][0][1][37] = 127, ++ [0][1][2][0][3][37] = 70, ++ [0][1][2][0][5][37] = 68, ++ [0][1][2][0][6][37] = 46, ++ [0][1][2][0][9][37] = 68, ++ [0][1][2][0][8][37] = 42, ++ [0][1][2][0][11][37] = 127, ++ [0][1][2][0][2][38] = 76, ++ [0][1][2][0][1][38] = 16, ++ [0][1][2][0][3][38] = 127, ++ [0][1][2][0][5][38] = 76, ++ [0][1][2][0][6][38] = 16, ++ [0][1][2][0][9][38] = 76, ++ [0][1][2][0][8][38] = 42, ++ [0][1][2][0][11][38] = 40, ++ [0][1][2][0][2][40] = 76, ++ [0][1][2][0][1][40] = 16, ++ [0][1][2][0][3][40] = 127, ++ [0][1][2][0][5][40] = 76, ++ [0][1][2][0][6][40] = 16, ++ [0][1][2][0][9][40] = 76, ++ [0][1][2][0][8][40] = 42, ++ [0][1][2][0][11][40] = 40, ++ [0][1][2][0][2][42] = 76, ++ [0][1][2][0][1][42] = 16, ++ [0][1][2][0][3][42] = 127, ++ [0][1][2][0][5][42] = 76, ++ [0][1][2][0][6][42] = 16, ++ [0][1][2][0][9][42] = 76, ++ [0][1][2][0][8][42] = 42, ++ [0][1][2][0][11][42] = 40, ++ [0][1][2][0][2][44] = 76, ++ [0][1][2][0][1][44] = 16, ++ [0][1][2][0][3][44] = 127, ++ [0][1][2][0][5][44] = 76, ++ [0][1][2][0][6][44] = 16, ++ [0][1][2][0][9][44] = 76, ++ [0][1][2][0][8][44] = 42, ++ [0][1][2][0][11][44] = 40, ++ [0][1][2][0][2][46] = 76, ++ [0][1][2][0][1][46] = 16, ++ [0][1][2][0][3][46] = 127, ++ [0][1][2][0][5][46] = 76, ++ [0][1][2][0][6][46] = 16, ++ [0][1][2][0][9][46] = 76, ++ [0][1][2][0][8][46] = 42, ++ [0][1][2][0][11][46] = 40, ++ [0][1][2][1][2][0] = 68, ++ [0][1][2][1][1][0] = 34, ++ [0][1][2][1][3][0] = 50, ++ [0][1][2][1][5][0] = 38, ++ [0][1][2][1][6][0] = 34, ++ [0][1][2][1][9][0] = 34, ++ [0][1][2][1][8][0] = 6, ++ [0][1][2][1][11][0] = 28, ++ [0][1][2][1][2][2] = 68, ++ [0][1][2][1][1][2] = 34, ++ [0][1][2][1][3][2] = 50, ++ [0][1][2][1][5][2] = 38, ++ [0][1][2][1][6][2] = 34, ++ [0][1][2][1][9][2] = 34, ++ [0][1][2][1][8][2] = 6, ++ [0][1][2][1][11][2] = 28, ++ [0][1][2][1][2][4] = 68, ++ [0][1][2][1][1][4] = 34, ++ [0][1][2][1][3][4] = 50, ++ [0][1][2][1][5][4] = 38, ++ [0][1][2][1][6][4] = 34, ++ [0][1][2][1][9][4] = 34, ++ [0][1][2][1][8][4] = 6, ++ [0][1][2][1][11][4] = 28, ++ [0][1][2][1][2][6] = 68, ++ [0][1][2][1][1][6] = 34, ++ [0][1][2][1][3][6] = 50, ++ [0][1][2][1][5][6] = 38, ++ [0][1][2][1][6][6] = 34, ++ [0][1][2][1][9][6] = 34, ++ [0][1][2][1][8][6] = 6, ++ [0][1][2][1][11][6] = 28, ++ [0][1][2][1][2][8] = 68, ++ [0][1][2][1][1][8] = 34, ++ [0][1][2][1][3][8] = 50, ++ [0][1][2][1][5][8] = 38, ++ [0][1][2][1][6][8] = 34, ++ [0][1][2][1][9][8] = 34, ++ [0][1][2][1][8][8] = 30, ++ [0][1][2][1][11][8] = 28, ++ [0][1][2][1][2][10] = 68, ++ [0][1][2][1][1][10] = 34, ++ [0][1][2][1][3][10] = 50, ++ [0][1][2][1][5][10] = 38, ++ [0][1][2][1][6][10] = 34, ++ [0][1][2][1][9][10] = 34, ++ [0][1][2][1][8][10] = 30, ++ [0][1][2][1][11][10] = 28, ++ [0][1][2][1][2][12] = 68, ++ [0][1][2][1][1][12] = 34, ++ [0][1][2][1][3][12] = 50, ++ [0][1][2][1][5][12] = 38, ++ [0][1][2][1][6][12] = 34, ++ [0][1][2][1][9][12] = 34, ++ [0][1][2][1][8][12] = 30, ++ [0][1][2][1][11][12] = 28, ++ [0][1][2][1][2][14] = 68, ++ [0][1][2][1][1][14] = 34, ++ [0][1][2][1][3][14] = 50, ++ [0][1][2][1][5][14] = 38, ++ [0][1][2][1][6][14] = 34, ++ [0][1][2][1][9][14] = 34, ++ [0][1][2][1][8][14] = 30, ++ [0][1][2][1][11][14] = 28, ++ [0][1][2][1][2][15] = 68, ++ [0][1][2][1][1][15] = 34, ++ [0][1][2][1][3][15] = 70, ++ [0][1][2][1][5][15] = 62, ++ [0][1][2][1][6][15] = 34, ++ [0][1][2][1][9][15] = 34, ++ [0][1][2][1][8][15] = 30, ++ [0][1][2][1][11][15] = 28, ++ [0][1][2][1][2][17] = 68, ++ [0][1][2][1][1][17] = 34, ++ [0][1][2][1][3][17] = 70, ++ [0][1][2][1][5][17] = 62, ++ [0][1][2][1][6][17] = 34, ++ [0][1][2][1][9][17] = 34, ++ [0][1][2][1][8][17] = 30, ++ [0][1][2][1][11][17] = 28, ++ [0][1][2][1][2][19] = 68, ++ [0][1][2][1][1][19] = 34, ++ [0][1][2][1][3][19] = 70, ++ [0][1][2][1][5][19] = 62, ++ [0][1][2][1][6][19] = 34, ++ [0][1][2][1][9][19] = 34, ++ [0][1][2][1][8][19] = 30, ++ [0][1][2][1][11][19] = 28, ++ [0][1][2][1][2][21] = 68, ++ [0][1][2][1][1][21] = 34, ++ [0][1][2][1][3][21] = 70, ++ [0][1][2][1][5][21] = 62, ++ [0][1][2][1][6][21] = 34, ++ [0][1][2][1][9][21] = 34, ++ [0][1][2][1][8][21] = 30, ++ [0][1][2][1][11][21] = 28, ++ [0][1][2][1][2][23] = 68, ++ [0][1][2][1][1][23] = 34, ++ [0][1][2][1][3][23] = 70, ++ [0][1][2][1][5][23] = 62, ++ [0][1][2][1][6][23] = 34, ++ [0][1][2][1][9][23] = 34, ++ [0][1][2][1][8][23] = 30, ++ [0][1][2][1][11][23] = 28, ++ [0][1][2][1][2][25] = 68, ++ [0][1][2][1][1][25] = 34, ++ [0][1][2][1][3][25] = 70, ++ [0][1][2][1][5][25] = 127, ++ [0][1][2][1][6][25] = 34, ++ [0][1][2][1][9][25] = 127, ++ [0][1][2][1][8][25] = 30, ++ [0][1][2][1][11][25] = 28, ++ [0][1][2][1][2][27] = 68, ++ [0][1][2][1][1][27] = 34, ++ [0][1][2][1][3][27] = 70, ++ [0][1][2][1][5][27] = 127, ++ [0][1][2][1][6][27] = 34, ++ [0][1][2][1][9][27] = 127, ++ [0][1][2][1][8][27] = 30, ++ [0][1][2][1][11][27] = 28, ++ [0][1][2][1][2][29] = 68, ++ [0][1][2][1][1][29] = 34, ++ [0][1][2][1][3][29] = 70, ++ [0][1][2][1][5][29] = 127, ++ [0][1][2][1][6][29] = 34, ++ [0][1][2][1][9][29] = 127, ++ [0][1][2][1][8][29] = 30, ++ [0][1][2][1][11][29] = 28, ++ [0][1][2][1][2][31] = 68, ++ [0][1][2][1][1][31] = 34, ++ [0][1][2][1][3][31] = 70, ++ [0][1][2][1][5][31] = 62, ++ [0][1][2][1][6][31] = 34, ++ [0][1][2][1][9][31] = 34, ++ [0][1][2][1][8][31] = 30, ++ [0][1][2][1][11][31] = 28, ++ [0][1][2][1][2][33] = 68, ++ [0][1][2][1][1][33] = 34, ++ [0][1][2][1][3][33] = 70, ++ [0][1][2][1][5][33] = 62, ++ [0][1][2][1][6][33] = 34, ++ [0][1][2][1][9][33] = 34, ++ [0][1][2][1][8][33] = 30, ++ [0][1][2][1][11][33] = 28, ++ [0][1][2][1][2][35] = 64, ++ [0][1][2][1][1][35] = 34, ++ [0][1][2][1][3][35] = 70, ++ [0][1][2][1][5][35] = 62, ++ [0][1][2][1][6][35] = 34, ++ [0][1][2][1][9][35] = 34, ++ [0][1][2][1][8][35] = 30, ++ [0][1][2][1][11][35] = 28, ++ [0][1][2][1][2][37] = 68, ++ [0][1][2][1][1][37] = 127, ++ [0][1][2][1][3][37] = 70, ++ [0][1][2][1][5][37] = 62, ++ [0][1][2][1][6][37] = 34, ++ [0][1][2][1][9][37] = 68, ++ [0][1][2][1][8][37] = 30, ++ [0][1][2][1][11][37] = 127, ++ [0][1][2][1][2][38] = 76, ++ [0][1][2][1][1][38] = 4, ++ [0][1][2][1][3][38] = 127, ++ [0][1][2][1][5][38] = 76, ++ [0][1][2][1][6][38] = 4, ++ [0][1][2][1][9][38] = 76, ++ [0][1][2][1][8][38] = 30, ++ [0][1][2][1][11][38] = 28, ++ [0][1][2][1][2][40] = 76, ++ [0][1][2][1][1][40] = 4, ++ [0][1][2][1][3][40] = 127, ++ [0][1][2][1][5][40] = 76, ++ [0][1][2][1][6][40] = 4, ++ [0][1][2][1][9][40] = 76, ++ [0][1][2][1][8][40] = 30, ++ [0][1][2][1][11][40] = 28, ++ [0][1][2][1][2][42] = 76, ++ [0][1][2][1][1][42] = 4, ++ [0][1][2][1][3][42] = 127, ++ [0][1][2][1][5][42] = 76, ++ [0][1][2][1][6][42] = 4, ++ [0][1][2][1][9][42] = 76, ++ [0][1][2][1][8][42] = 30, ++ [0][1][2][1][11][42] = 28, ++ [0][1][2][1][2][44] = 76, ++ [0][1][2][1][1][44] = 4, ++ [0][1][2][1][3][44] = 127, ++ [0][1][2][1][5][44] = 76, ++ [0][1][2][1][6][44] = 4, ++ [0][1][2][1][9][44] = 76, ++ [0][1][2][1][8][44] = 30, ++ [0][1][2][1][11][44] = 28, ++ [0][1][2][1][2][46] = 76, ++ [0][1][2][1][1][46] = 4, ++ [0][1][2][1][3][46] = 127, ++ [0][1][2][1][5][46] = 76, ++ [0][1][2][1][6][46] = 4, ++ [0][1][2][1][9][46] = 76, ++ [0][1][2][1][8][46] = 30, ++ [0][1][2][1][11][46] = 28, ++ [1][0][2][0][2][1] = 68, ++ [1][0][2][0][1][1] = 64, ++ [1][0][2][0][3][1] = 62, ++ [1][0][2][0][5][1] = 64, ++ [1][0][2][0][6][1] = 64, ++ [1][0][2][0][9][1] = 64, ++ [1][0][2][0][8][1] = 30, ++ [1][0][2][0][11][1] = 52, ++ [1][0][2][0][2][5] = 72, ++ [1][0][2][0][1][5] = 64, ++ [1][0][2][0][3][5] = 62, ++ [1][0][2][0][5][5] = 64, ++ [1][0][2][0][6][5] = 60, ++ [1][0][2][0][9][5] = 64, ++ [1][0][2][0][8][5] = 30, ++ [1][0][2][0][11][5] = 52, ++ [1][0][2][0][2][9] = 72, ++ [1][0][2][0][1][9] = 64, ++ [1][0][2][0][3][9] = 62, ++ [1][0][2][0][5][9] = 64, ++ [1][0][2][0][6][9] = 64, ++ [1][0][2][0][9][9] = 64, ++ [1][0][2][0][8][9] = 54, ++ [1][0][2][0][11][9] = 52, ++ [1][0][2][0][2][13] = 66, ++ [1][0][2][0][1][13] = 64, ++ [1][0][2][0][3][13] = 62, ++ [1][0][2][0][5][13] = 64, ++ [1][0][2][0][6][13] = 64, ++ [1][0][2][0][9][13] = 64, ++ [1][0][2][0][8][13] = 54, ++ [1][0][2][0][11][13] = 52, ++ [1][0][2][0][2][16] = 62, ++ [1][0][2][0][1][16] = 64, ++ [1][0][2][0][3][16] = 72, ++ [1][0][2][0][5][16] = 62, ++ [1][0][2][0][6][16] = 64, ++ [1][0][2][0][9][16] = 64, ++ [1][0][2][0][8][16] = 54, ++ [1][0][2][0][11][16] = 52, ++ [1][0][2][0][2][20] = 72, ++ [1][0][2][0][1][20] = 64, ++ [1][0][2][0][3][20] = 72, ++ [1][0][2][0][5][20] = 72, ++ [1][0][2][0][6][20] = 64, ++ [1][0][2][0][9][20] = 64, ++ [1][0][2][0][8][20] = 54, ++ [1][0][2][0][11][20] = 52, ++ [1][0][2][0][2][24] = 72, ++ [1][0][2][0][1][24] = 64, ++ [1][0][2][0][3][24] = 72, ++ [1][0][2][0][5][24] = 127, ++ [1][0][2][0][6][24] = 64, ++ [1][0][2][0][9][24] = 127, ++ [1][0][2][0][8][24] = 54, ++ [1][0][2][0][11][24] = 52, ++ [1][0][2][0][2][28] = 72, ++ [1][0][2][0][1][28] = 64, ++ [1][0][2][0][3][28] = 72, ++ [1][0][2][0][5][28] = 127, ++ [1][0][2][0][6][28] = 64, ++ [1][0][2][0][9][28] = 127, ++ [1][0][2][0][8][28] = 54, ++ [1][0][2][0][11][28] = 52, ++ [1][0][2][0][2][32] = 72, ++ [1][0][2][0][1][32] = 64, ++ [1][0][2][0][3][32] = 72, ++ [1][0][2][0][5][32] = 72, ++ [1][0][2][0][6][32] = 64, ++ [1][0][2][0][9][32] = 64, ++ [1][0][2][0][8][32] = 54, ++ [1][0][2][0][11][32] = 52, ++ [1][0][2][0][2][36] = 72, ++ [1][0][2][0][1][36] = 127, ++ [1][0][2][0][3][36] = 72, ++ [1][0][2][0][5][36] = 72, ++ [1][0][2][0][6][36] = 64, ++ [1][0][2][0][9][36] = 72, ++ [1][0][2][0][8][36] = 54, ++ [1][0][2][0][11][36] = 127, ++ [1][0][2][0][2][39] = 72, ++ [1][0][2][0][1][39] = 28, ++ [1][0][2][0][3][39] = 127, ++ [1][0][2][0][5][39] = 72, ++ [1][0][2][0][6][39] = 28, ++ [1][0][2][0][9][39] = 72, ++ [1][0][2][0][8][39] = 54, ++ [1][0][2][0][11][39] = 52, ++ [1][0][2][0][2][43] = 72, ++ [1][0][2][0][1][43] = 28, ++ [1][0][2][0][3][43] = 127, ++ [1][0][2][0][5][43] = 72, ++ [1][0][2][0][6][43] = 28, ++ [1][0][2][0][9][43] = 72, ++ [1][0][2][0][8][43] = 54, ++ [1][0][2][0][11][43] = 52, ++ [1][1][2][0][2][1] = 58, ++ [1][1][2][0][1][1] = 52, ++ [1][1][2][0][3][1] = 50, ++ [1][1][2][0][5][1] = 52, ++ [1][1][2][0][6][1] = 52, ++ [1][1][2][0][9][1] = 52, ++ [1][1][2][0][8][1] = 18, ++ [1][1][2][0][11][1] = 40, ++ [1][1][2][0][2][5] = 72, ++ [1][1][2][0][1][5] = 52, ++ [1][1][2][0][3][5] = 50, ++ [1][1][2][0][5][5] = 52, ++ [1][1][2][0][6][5] = 46, ++ [1][1][2][0][9][5] = 52, ++ [1][1][2][0][8][5] = 18, ++ [1][1][2][0][11][5] = 40, ++ [1][1][2][0][2][9] = 72, ++ [1][1][2][0][1][9] = 52, ++ [1][1][2][0][3][9] = 50, ++ [1][1][2][0][5][9] = 52, ++ [1][1][2][0][6][9] = 52, ++ [1][1][2][0][9][9] = 52, ++ [1][1][2][0][8][9] = 42, ++ [1][1][2][0][11][9] = 40, ++ [1][1][2][0][2][13] = 58, ++ [1][1][2][0][1][13] = 52, ++ [1][1][2][0][3][13] = 50, ++ [1][1][2][0][5][13] = 52, ++ [1][1][2][0][6][13] = 52, ++ [1][1][2][0][9][13] = 52, ++ [1][1][2][0][8][13] = 42, ++ [1][1][2][0][11][13] = 40, ++ [1][1][2][0][2][16] = 56, ++ [1][1][2][0][1][16] = 52, ++ [1][1][2][0][3][16] = 72, ++ [1][1][2][0][5][16] = 56, ++ [1][1][2][0][6][16] = 52, ++ [1][1][2][0][9][16] = 52, ++ [1][1][2][0][8][16] = 42, ++ [1][1][2][0][11][16] = 40, ++ [1][1][2][0][2][20] = 72, ++ [1][1][2][0][1][20] = 52, ++ [1][1][2][0][3][20] = 72, ++ [1][1][2][0][5][20] = 72, ++ [1][1][2][0][6][20] = 52, ++ [1][1][2][0][9][20] = 52, ++ [1][1][2][0][8][20] = 42, ++ [1][1][2][0][11][20] = 40, ++ [1][1][2][0][2][24] = 72, ++ [1][1][2][0][1][24] = 52, ++ [1][1][2][0][3][24] = 72, ++ [1][1][2][0][5][24] = 127, ++ [1][1][2][0][6][24] = 52, ++ [1][1][2][0][9][24] = 127, ++ [1][1][2][0][8][24] = 42, ++ [1][1][2][0][11][24] = 40, ++ [1][1][2][0][2][28] = 72, ++ [1][1][2][0][1][28] = 52, ++ [1][1][2][0][3][28] = 72, ++ [1][1][2][0][5][28] = 127, ++ [1][1][2][0][6][28] = 52, ++ [1][1][2][0][9][28] = 127, ++ [1][1][2][0][8][28] = 42, ++ [1][1][2][0][11][28] = 40, ++ [1][1][2][0][2][32] = 68, ++ [1][1][2][0][1][32] = 52, ++ [1][1][2][0][3][32] = 72, ++ [1][1][2][0][5][32] = 68, ++ [1][1][2][0][6][32] = 52, ++ [1][1][2][0][9][32] = 52, ++ [1][1][2][0][8][32] = 42, ++ [1][1][2][0][11][32] = 40, ++ [1][1][2][0][2][36] = 72, ++ [1][1][2][0][1][36] = 127, ++ [1][1][2][0][3][36] = 72, ++ [1][1][2][0][5][36] = 72, ++ [1][1][2][0][6][36] = 52, ++ [1][1][2][0][9][36] = 72, ++ [1][1][2][0][8][36] = 42, ++ [1][1][2][0][11][36] = 127, ++ [1][1][2][0][2][39] = 72, ++ [1][1][2][0][1][39] = 16, ++ [1][1][2][0][3][39] = 127, ++ [1][1][2][0][5][39] = 72, ++ [1][1][2][0][6][39] = 16, ++ [1][1][2][0][9][39] = 72, ++ [1][1][2][0][8][39] = 42, ++ [1][1][2][0][11][39] = 40, ++ [1][1][2][0][2][43] = 72, ++ [1][1][2][0][1][43] = 16, ++ [1][1][2][0][3][43] = 127, ++ [1][1][2][0][5][43] = 72, ++ [1][1][2][0][6][43] = 16, ++ [1][1][2][0][9][43] = 72, ++ [1][1][2][0][8][43] = 42, ++ [1][1][2][0][11][43] = 40, ++ [1][1][2][1][2][1] = 58, ++ [1][1][2][1][1][1] = 40, ++ [1][1][2][1][3][1] = 50, ++ [1][1][2][1][5][1] = 40, ++ [1][1][2][1][6][1] = 40, ++ [1][1][2][1][9][1] = 40, ++ [1][1][2][1][8][1] = 6, ++ [1][1][2][1][11][1] = 28, ++ [1][1][2][1][2][5] = 68, ++ [1][1][2][1][1][5] = 40, ++ [1][1][2][1][3][5] = 50, ++ [1][1][2][1][5][5] = 40, ++ [1][1][2][1][6][5] = 40, ++ [1][1][2][1][9][5] = 40, ++ [1][1][2][1][8][5] = 6, ++ [1][1][2][1][11][5] = 28, ++ [1][1][2][1][2][9] = 68, ++ [1][1][2][1][1][9] = 40, ++ [1][1][2][1][3][9] = 50, ++ [1][1][2][1][5][9] = 40, ++ [1][1][2][1][6][9] = 40, ++ [1][1][2][1][9][9] = 40, ++ [1][1][2][1][8][9] = 30, ++ [1][1][2][1][11][9] = 28, ++ [1][1][2][1][2][13] = 58, ++ [1][1][2][1][1][13] = 40, ++ [1][1][2][1][3][13] = 50, ++ [1][1][2][1][5][13] = 40, ++ [1][1][2][1][6][13] = 40, ++ [1][1][2][1][9][13] = 40, ++ [1][1][2][1][8][13] = 30, ++ [1][1][2][1][11][13] = 28, ++ [1][1][2][1][2][16] = 56, ++ [1][1][2][1][1][16] = 40, ++ [1][1][2][1][3][16] = 72, ++ [1][1][2][1][5][16] = 56, ++ [1][1][2][1][6][16] = 40, ++ [1][1][2][1][9][16] = 40, ++ [1][1][2][1][8][16] = 30, ++ [1][1][2][1][11][16] = 28, ++ [1][1][2][1][2][20] = 68, ++ [1][1][2][1][1][20] = 40, ++ [1][1][2][1][3][20] = 72, ++ [1][1][2][1][5][20] = 68, ++ [1][1][2][1][6][20] = 40, ++ [1][1][2][1][9][20] = 40, ++ [1][1][2][1][8][20] = 30, ++ [1][1][2][1][11][20] = 28, ++ [1][1][2][1][2][24] = 68, ++ [1][1][2][1][1][24] = 40, ++ [1][1][2][1][3][24] = 72, ++ [1][1][2][1][5][24] = 127, ++ [1][1][2][1][6][24] = 40, ++ [1][1][2][1][9][24] = 127, ++ [1][1][2][1][8][24] = 30, ++ [1][1][2][1][11][24] = 28, ++ [1][1][2][1][2][28] = 68, ++ [1][1][2][1][1][28] = 40, ++ [1][1][2][1][3][28] = 72, ++ [1][1][2][1][5][28] = 127, ++ [1][1][2][1][6][28] = 40, ++ [1][1][2][1][9][28] = 127, ++ [1][1][2][1][8][28] = 30, ++ [1][1][2][1][11][28] = 28, ++ [1][1][2][1][2][32] = 68, ++ [1][1][2][1][1][32] = 40, ++ [1][1][2][1][3][32] = 72, ++ [1][1][2][1][5][32] = 68, ++ [1][1][2][1][6][32] = 40, ++ [1][1][2][1][9][32] = 40, ++ [1][1][2][1][8][32] = 30, ++ [1][1][2][1][11][32] = 28, ++ [1][1][2][1][2][36] = 68, ++ [1][1][2][1][1][36] = 127, ++ [1][1][2][1][3][36] = 72, ++ [1][1][2][1][5][36] = 68, ++ [1][1][2][1][6][36] = 40, ++ [1][1][2][1][9][36] = 68, ++ [1][1][2][1][8][36] = 30, ++ [1][1][2][1][11][36] = 127, ++ [1][1][2][1][2][39] = 72, ++ [1][1][2][1][1][39] = 4, ++ [1][1][2][1][3][39] = 127, ++ [1][1][2][1][5][39] = 72, ++ [1][1][2][1][6][39] = 4, ++ [1][1][2][1][9][39] = 72, ++ [1][1][2][1][8][39] = 30, ++ [1][1][2][1][11][39] = 28, ++ [1][1][2][1][2][43] = 72, ++ [1][1][2][1][1][43] = 4, ++ [1][1][2][1][3][43] = 127, ++ [1][1][2][1][5][43] = 72, ++ [1][1][2][1][6][43] = 4, ++ [1][1][2][1][9][43] = 72, ++ [1][1][2][1][8][43] = 30, ++ [1][1][2][1][11][43] = 28, ++ [2][0][2][0][2][3] = 64, ++ [2][0][2][0][1][3] = 64, ++ [2][0][2][0][3][3] = 64, ++ [2][0][2][0][5][3] = 62, ++ [2][0][2][0][6][3] = 64, ++ [2][0][2][0][9][3] = 64, ++ [2][0][2][0][8][3] = 30, ++ [2][0][2][0][11][3] = 52, ++ [2][0][2][0][2][11] = 64, ++ [2][0][2][0][1][11] = 64, ++ [2][0][2][0][3][11] = 64, ++ [2][0][2][0][5][11] = 62, ++ [2][0][2][0][6][11] = 64, ++ [2][0][2][0][9][11] = 64, ++ [2][0][2][0][8][11] = 54, ++ [2][0][2][0][11][11] = 52, ++ [2][0][2][0][2][18] = 62, ++ [2][0][2][0][1][18] = 64, ++ [2][0][2][0][3][18] = 72, ++ [2][0][2][0][5][18] = 66, ++ [2][0][2][0][6][18] = 64, ++ [2][0][2][0][9][18] = 64, ++ [2][0][2][0][8][18] = 54, ++ [2][0][2][0][11][18] = 52, ++ [2][0][2][0][2][26] = 72, ++ [2][0][2][0][1][26] = 64, ++ [2][0][2][0][3][26] = 72, ++ [2][0][2][0][5][26] = 127, ++ [2][0][2][0][6][26] = 64, ++ [2][0][2][0][9][26] = 127, ++ [2][0][2][0][8][26] = 54, ++ [2][0][2][0][11][26] = 52, ++ [2][0][2][0][2][34] = 72, ++ [2][0][2][0][1][34] = 127, ++ [2][0][2][0][3][34] = 72, ++ [2][0][2][0][5][34] = 72, ++ [2][0][2][0][6][34] = 64, ++ [2][0][2][0][9][34] = 72, ++ [2][0][2][0][8][34] = 54, ++ [2][0][2][0][11][34] = 127, ++ [2][0][2][0][2][41] = 72, ++ [2][0][2][0][1][41] = 28, ++ [2][0][2][0][3][41] = 127, ++ [2][0][2][0][5][41] = 72, ++ [2][0][2][0][6][41] = 28, ++ [2][0][2][0][9][41] = 72, ++ [2][0][2][0][8][41] = 54, ++ [2][0][2][0][11][41] = 52, ++ [2][1][2][0][2][3] = 56, ++ [2][1][2][0][1][3] = 52, ++ [2][1][2][0][3][3] = 52, ++ [2][1][2][0][5][3] = 52, ++ [2][1][2][0][6][3] = 52, ++ [2][1][2][0][9][3] = 52, ++ [2][1][2][0][8][3] = 18, ++ [2][1][2][0][11][3] = 40, ++ [2][1][2][0][2][11] = 56, ++ [2][1][2][0][1][11] = 52, ++ [2][1][2][0][3][11] = 52, ++ [2][1][2][0][5][11] = 52, ++ [2][1][2][0][6][11] = 52, ++ [2][1][2][0][9][11] = 52, ++ [2][1][2][0][8][11] = 42, ++ [2][1][2][0][11][11] = 40, ++ [2][1][2][0][2][18] = 56, ++ [2][1][2][0][1][18] = 52, ++ [2][1][2][0][3][18] = 72, ++ [2][1][2][0][5][18] = 56, ++ [2][1][2][0][6][18] = 52, ++ [2][1][2][0][9][18] = 52, ++ [2][1][2][0][8][18] = 42, ++ [2][1][2][0][11][18] = 40, ++ [2][1][2][0][2][26] = 72, ++ [2][1][2][0][1][26] = 52, ++ [2][1][2][0][3][26] = 72, ++ [2][1][2][0][5][26] = 127, ++ [2][1][2][0][6][26] = 52, ++ [2][1][2][0][9][26] = 127, ++ [2][1][2][0][8][26] = 42, ++ [2][1][2][0][11][26] = 40, ++ [2][1][2][0][2][34] = 72, ++ [2][1][2][0][1][34] = 127, ++ [2][1][2][0][3][34] = 72, ++ [2][1][2][0][5][34] = 72, ++ [2][1][2][0][6][34] = 52, ++ [2][1][2][0][9][34] = 72, ++ [2][1][2][0][8][34] = 42, ++ [2][1][2][0][11][34] = 127, ++ [2][1][2][0][2][41] = 72, ++ [2][1][2][0][1][41] = 16, ++ [2][1][2][0][3][41] = 127, ++ [2][1][2][0][5][41] = 72, ++ [2][1][2][0][6][41] = 16, ++ [2][1][2][0][9][41] = 72, ++ [2][1][2][0][8][41] = 42, ++ [2][1][2][0][11][41] = 40, ++ [2][1][2][1][2][3] = 56, ++ [2][1][2][1][1][3] = 40, ++ [2][1][2][1][3][3] = 52, ++ [2][1][2][1][5][3] = 40, ++ [2][1][2][1][6][3] = 40, ++ [2][1][2][1][9][3] = 40, ++ [2][1][2][1][8][3] = 6, ++ [2][1][2][1][11][3] = 28, ++ [2][1][2][1][2][11] = 56, ++ [2][1][2][1][1][11] = 40, ++ [2][1][2][1][3][11] = 52, ++ [2][1][2][1][5][11] = 40, ++ [2][1][2][1][6][11] = 40, ++ [2][1][2][1][9][11] = 40, ++ [2][1][2][1][8][11] = 30, ++ [2][1][2][1][11][11] = 28, ++ [2][1][2][1][2][18] = 56, ++ [2][1][2][1][1][18] = 40, ++ [2][1][2][1][3][18] = 72, ++ [2][1][2][1][5][18] = 56, ++ [2][1][2][1][6][18] = 40, ++ [2][1][2][1][9][18] = 40, ++ [2][1][2][1][8][18] = 30, ++ [2][1][2][1][11][18] = 28, ++ [2][1][2][1][2][26] = 68, ++ [2][1][2][1][1][26] = 40, ++ [2][1][2][1][3][26] = 72, ++ [2][1][2][1][5][26] = 127, ++ [2][1][2][1][6][26] = 40, ++ [2][1][2][1][9][26] = 127, ++ [2][1][2][1][8][26] = 30, ++ [2][1][2][1][11][26] = 28, ++ [2][1][2][1][2][34] = 68, ++ [2][1][2][1][1][34] = 127, ++ [2][1][2][1][3][34] = 72, ++ [2][1][2][1][5][34] = 68, ++ [2][1][2][1][6][34] = 40, ++ [2][1][2][1][9][34] = 68, ++ [2][1][2][1][8][34] = 30, ++ [2][1][2][1][11][34] = 127, ++ [2][1][2][1][2][41] = 72, ++ [2][1][2][1][1][41] = 4, ++ [2][1][2][1][3][41] = 127, ++ [2][1][2][1][5][41] = 72, ++ [2][1][2][1][6][41] = 4, ++ [2][1][2][1][9][41] = 72, ++ [2][1][2][1][8][41] = 30, ++ [2][1][2][1][11][41] = 28, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { ++ [0][0][0][0] = 32, ++ [0][0][0][1] = 32, ++ [0][0][0][2] = 32, ++ [0][0][0][3] = 32, ++ [0][0][0][4] = 32, ++ [0][0][0][5] = 32, ++ [0][0][0][6] = 32, ++ [0][0][0][7] = 32, ++ [0][0][0][8] = 32, ++ [0][0][0][9] = 32, ++ [0][0][0][10] = 32, ++ [0][0][0][11] = 32, ++ [0][0][0][12] = 32, ++ [0][0][0][13] = 0, ++ [0][1][0][0] = 20, ++ [0][1][0][1] = 20, ++ [0][1][0][2] = 20, ++ [0][1][0][3] = 20, ++ [0][1][0][4] = 20, ++ [0][1][0][5] = 20, ++ [0][1][0][6] = 20, ++ [0][1][0][7] = 20, ++ [0][1][0][8] = 20, ++ [0][1][0][9] = 20, ++ [0][1][0][10] = 20, ++ [0][1][0][11] = 20, ++ [0][1][0][12] = 20, ++ [0][1][0][13] = 0, ++ [1][0][0][0] = 42, ++ [1][0][0][1] = 42, ++ [1][0][0][2] = 42, ++ [1][0][0][3] = 42, ++ [1][0][0][4] = 42, ++ [1][0][0][5] = 42, ++ [1][0][0][6] = 42, ++ [1][0][0][7] = 42, ++ [1][0][0][8] = 42, ++ [1][0][0][9] = 42, ++ [1][0][0][10] = 42, ++ [1][0][0][11] = 42, ++ [1][0][0][12] = 36, ++ [1][0][0][13] = 0, ++ [1][1][0][0] = 30, ++ [1][1][0][1] = 30, ++ [1][1][0][2] = 30, ++ [1][1][0][3] = 30, ++ [1][1][0][4] = 30, ++ [1][1][0][5] = 30, ++ [1][1][0][6] = 30, ++ [1][1][0][7] = 30, ++ [1][1][0][8] = 30, ++ [1][1][0][9] = 30, ++ [1][1][0][10] = 30, ++ [1][1][0][11] = 30, ++ [1][1][0][12] = 30, ++ [1][1][0][13] = 0, ++ [2][0][0][0] = 52, ++ [2][0][0][1] = 52, ++ [2][0][0][2] = 52, ++ [2][0][0][3] = 52, ++ [2][0][0][4] = 52, ++ [2][0][0][5] = 52, ++ [2][0][0][6] = 52, ++ [2][0][0][7] = 52, ++ [2][0][0][8] = 52, ++ [2][0][0][9] = 52, ++ [2][0][0][10] = 52, ++ [2][0][0][11] = 52, ++ [2][0][0][12] = 40, ++ [2][0][0][13] = 0, ++ [2][1][0][0] = 40, ++ [2][1][0][1] = 40, ++ [2][1][0][2] = 40, ++ [2][1][0][3] = 40, ++ [2][1][0][4] = 40, ++ [2][1][0][5] = 40, ++ [2][1][0][6] = 40, ++ [2][1][0][7] = 40, ++ [2][1][0][8] = 40, ++ [2][1][0][9] = 40, ++ [2][1][0][10] = 40, ++ [2][1][0][11] = 40, ++ [2][1][0][12] = 26, ++ [2][1][0][13] = 0, ++ [0][0][2][0] = 70, ++ [0][0][1][0] = 32, ++ [0][0][3][0] = 40, ++ [0][0][5][0] = 70, ++ [0][0][6][0] = 32, ++ [0][0][9][0] = 32, ++ [0][0][8][0] = 60, ++ [0][0][11][0] = 32, ++ [0][0][2][1] = 70, ++ [0][0][1][1] = 32, ++ [0][0][3][1] = 40, ++ [0][0][5][1] = 70, ++ [0][0][6][1] = 32, ++ [0][0][9][1] = 32, ++ [0][0][8][1] = 60, ++ [0][0][11][1] = 32, ++ [0][0][2][2] = 74, ++ [0][0][1][2] = 32, ++ [0][0][3][2] = 40, ++ [0][0][5][2] = 74, ++ [0][0][6][2] = 32, ++ [0][0][9][2] = 32, ++ [0][0][8][2] = 60, ++ [0][0][11][2] = 32, ++ [0][0][2][3] = 78, ++ [0][0][1][3] = 32, ++ [0][0][3][3] = 40, ++ [0][0][5][3] = 78, ++ [0][0][6][3] = 32, ++ [0][0][9][3] = 32, ++ [0][0][8][3] = 60, ++ [0][0][11][3] = 32, ++ [0][0][2][4] = 78, ++ [0][0][1][4] = 32, ++ [0][0][3][4] = 40, ++ [0][0][5][4] = 78, ++ [0][0][6][4] = 32, ++ [0][0][9][4] = 32, ++ [0][0][8][4] = 60, ++ [0][0][11][4] = 32, ++ [0][0][2][5] = 78, ++ [0][0][1][5] = 32, ++ [0][0][3][5] = 40, ++ [0][0][5][5] = 78, ++ [0][0][6][5] = 32, ++ [0][0][9][5] = 32, ++ [0][0][8][5] = 60, ++ [0][0][11][5] = 32, ++ [0][0][2][6] = 78, ++ [0][0][1][6] = 32, ++ [0][0][3][6] = 40, ++ [0][0][5][6] = 78, ++ [0][0][6][6] = 32, ++ [0][0][9][6] = 32, ++ [0][0][8][6] = 60, ++ [0][0][11][6] = 32, ++ [0][0][2][7] = 78, ++ [0][0][1][7] = 32, ++ [0][0][3][7] = 40, ++ [0][0][5][7] = 78, ++ [0][0][6][7] = 32, ++ [0][0][9][7] = 32, ++ [0][0][8][7] = 60, ++ [0][0][11][7] = 32, ++ [0][0][2][8] = 74, ++ [0][0][1][8] = 32, ++ [0][0][3][8] = 40, ++ [0][0][5][8] = 74, ++ [0][0][6][8] = 32, ++ [0][0][9][8] = 32, ++ [0][0][8][8] = 60, ++ [0][0][11][8] = 32, ++ [0][0][2][9] = 70, ++ [0][0][1][9] = 32, ++ [0][0][3][9] = 40, ++ [0][0][5][9] = 70, ++ [0][0][6][9] = 32, ++ [0][0][9][9] = 32, ++ [0][0][8][9] = 60, ++ [0][0][11][9] = 32, ++ [0][0][2][10] = 70, ++ [0][0][1][10] = 32, ++ [0][0][3][10] = 40, ++ [0][0][5][10] = 70, ++ [0][0][6][10] = 32, ++ [0][0][9][10] = 32, ++ [0][0][8][10] = 60, ++ [0][0][11][10] = 32, ++ [0][0][2][11] = 58, ++ [0][0][1][11] = 32, ++ [0][0][3][11] = 40, ++ [0][0][5][11] = 58, ++ [0][0][6][11] = 32, ++ [0][0][9][11] = 32, ++ [0][0][8][11] = 60, ++ [0][0][11][11] = 32, ++ [0][0][2][12] = 34, ++ [0][0][1][12] = 32, ++ [0][0][3][12] = 40, ++ [0][0][5][12] = 34, ++ [0][0][6][12] = 32, ++ [0][0][9][12] = 32, ++ [0][0][8][12] = 60, ++ [0][0][11][12] = 32, ++ [0][0][2][13] = 127, ++ [0][0][1][13] = 127, ++ [0][0][3][13] = 127, ++ [0][0][5][13] = 127, ++ [0][0][6][13] = 127, ++ [0][0][9][13] = 127, ++ [0][0][8][13] = 127, ++ [0][0][11][13] = 127, ++ [0][1][2][0] = 64, ++ [0][1][1][0] = 20, ++ [0][1][3][0] = 28, ++ [0][1][5][0] = 64, ++ [0][1][6][0] = 20, ++ [0][1][9][0] = 20, ++ [0][1][8][0] = 48, ++ [0][1][11][0] = 20, ++ [0][1][2][1] = 64, ++ [0][1][1][1] = 20, ++ [0][1][3][1] = 28, ++ [0][1][5][1] = 64, ++ [0][1][6][1] = 20, ++ [0][1][9][1] = 20, ++ [0][1][8][1] = 48, ++ [0][1][11][1] = 20, ++ [0][1][2][2] = 68, ++ [0][1][1][2] = 20, ++ [0][1][3][2] = 28, ++ [0][1][5][2] = 68, ++ [0][1][6][2] = 20, ++ [0][1][9][2] = 20, ++ [0][1][8][2] = 48, ++ [0][1][11][2] = 20, ++ [0][1][2][3] = 72, ++ [0][1][1][3] = 20, ++ [0][1][3][3] = 28, ++ [0][1][5][3] = 72, ++ [0][1][6][3] = 20, ++ [0][1][9][3] = 20, ++ [0][1][8][3] = 48, ++ [0][1][11][3] = 20, ++ [0][1][2][4] = 76, ++ [0][1][1][4] = 20, ++ [0][1][3][4] = 28, ++ [0][1][5][4] = 76, ++ [0][1][6][4] = 20, ++ [0][1][9][4] = 20, ++ [0][1][8][4] = 48, ++ [0][1][11][4] = 20, ++ [0][1][2][5] = 78, ++ [0][1][1][5] = 20, ++ [0][1][3][5] = 28, ++ [0][1][5][5] = 78, ++ [0][1][6][5] = 20, ++ [0][1][9][5] = 20, ++ [0][1][8][5] = 48, ++ [0][1][11][5] = 20, ++ [0][1][2][6] = 76, ++ [0][1][1][6] = 20, ++ [0][1][3][6] = 28, ++ [0][1][5][6] = 76, ++ [0][1][6][6] = 20, ++ [0][1][9][6] = 20, ++ [0][1][8][6] = 48, ++ [0][1][11][6] = 20, ++ [0][1][2][7] = 72, ++ [0][1][1][7] = 20, ++ [0][1][3][7] = 28, ++ [0][1][5][7] = 72, ++ [0][1][6][7] = 20, ++ [0][1][9][7] = 20, ++ [0][1][8][7] = 48, ++ [0][1][11][7] = 20, ++ [0][1][2][8] = 68, ++ [0][1][1][8] = 20, ++ [0][1][3][8] = 28, ++ [0][1][5][8] = 68, ++ [0][1][6][8] = 20, ++ [0][1][9][8] = 20, ++ [0][1][8][8] = 48, ++ [0][1][11][8] = 20, ++ [0][1][2][9] = 64, ++ [0][1][1][9] = 20, ++ [0][1][3][9] = 28, ++ [0][1][5][9] = 64, ++ [0][1][6][9] = 20, ++ [0][1][9][9] = 20, ++ [0][1][8][9] = 48, ++ [0][1][11][9] = 20, ++ [0][1][2][10] = 64, ++ [0][1][1][10] = 20, ++ [0][1][3][10] = 28, ++ [0][1][5][10] = 64, ++ [0][1][6][10] = 20, ++ [0][1][9][10] = 20, ++ [0][1][8][10] = 48, ++ [0][1][11][10] = 20, ++ [0][1][2][11] = 54, ++ [0][1][1][11] = 20, ++ [0][1][3][11] = 28, ++ [0][1][5][11] = 54, ++ [0][1][6][11] = 20, ++ [0][1][9][11] = 20, ++ [0][1][8][11] = 48, ++ [0][1][11][11] = 20, ++ [0][1][2][12] = 32, ++ [0][1][1][12] = 20, ++ [0][1][3][12] = 28, ++ [0][1][5][12] = 32, ++ [0][1][6][12] = 20, ++ [0][1][9][12] = 20, ++ [0][1][8][12] = 48, ++ [0][1][11][12] = 20, ++ [0][1][2][13] = 127, ++ [0][1][1][13] = 127, ++ [0][1][3][13] = 127, ++ [0][1][5][13] = 127, ++ [0][1][6][13] = 127, ++ [0][1][9][13] = 127, ++ [0][1][8][13] = 127, ++ [0][1][11][13] = 127, ++ [1][0][2][0] = 72, ++ [1][0][1][0] = 42, ++ [1][0][3][0] = 50, ++ [1][0][5][0] = 72, ++ [1][0][6][0] = 42, ++ [1][0][9][0] = 42, ++ [1][0][8][0] = 60, ++ [1][0][11][0] = 42, ++ [1][0][2][1] = 72, ++ [1][0][1][1] = 42, ++ [1][0][3][1] = 50, ++ [1][0][5][1] = 72, ++ [1][0][6][1] = 42, ++ [1][0][9][1] = 42, ++ [1][0][8][1] = 60, ++ [1][0][11][1] = 42, ++ [1][0][2][2] = 76, ++ [1][0][1][2] = 42, ++ [1][0][3][2] = 50, ++ [1][0][5][2] = 76, ++ [1][0][6][2] = 42, ++ [1][0][9][2] = 42, ++ [1][0][8][2] = 60, ++ [1][0][11][2] = 42, ++ [1][0][2][3] = 78, ++ [1][0][1][3] = 42, ++ [1][0][3][3] = 50, ++ [1][0][5][3] = 78, ++ [1][0][6][3] = 42, ++ [1][0][9][3] = 42, ++ [1][0][8][3] = 60, ++ [1][0][11][3] = 42, ++ [1][0][2][4] = 78, ++ [1][0][1][4] = 42, ++ [1][0][3][4] = 50, ++ [1][0][5][4] = 78, ++ [1][0][6][4] = 42, ++ [1][0][9][4] = 42, ++ [1][0][8][4] = 60, ++ [1][0][11][4] = 42, ++ [1][0][2][5] = 78, ++ [1][0][1][5] = 42, ++ [1][0][3][5] = 50, ++ [1][0][5][5] = 78, ++ [1][0][6][5] = 42, ++ [1][0][9][5] = 42, ++ [1][0][8][5] = 60, ++ [1][0][11][5] = 42, ++ [1][0][2][6] = 78, ++ [1][0][1][6] = 42, ++ [1][0][3][6] = 50, ++ [1][0][5][6] = 78, ++ [1][0][6][6] = 42, ++ [1][0][9][6] = 42, ++ [1][0][8][6] = 60, ++ [1][0][11][6] = 42, ++ [1][0][2][7] = 78, ++ [1][0][1][7] = 42, ++ [1][0][3][7] = 50, ++ [1][0][5][7] = 78, ++ [1][0][6][7] = 42, ++ [1][0][9][7] = 42, ++ [1][0][8][7] = 60, ++ [1][0][11][7] = 42, ++ [1][0][2][8] = 78, ++ [1][0][1][8] = 42, ++ [1][0][3][8] = 50, ++ [1][0][5][8] = 78, ++ [1][0][6][8] = 42, ++ [1][0][9][8] = 42, ++ [1][0][8][8] = 60, ++ [1][0][11][8] = 42, ++ [1][0][2][9] = 74, ++ [1][0][1][9] = 42, ++ [1][0][3][9] = 50, ++ [1][0][5][9] = 74, ++ [1][0][6][9] = 42, ++ [1][0][9][9] = 42, ++ [1][0][8][9] = 60, ++ [1][0][11][9] = 42, ++ [1][0][2][10] = 74, ++ [1][0][1][10] = 42, ++ [1][0][3][10] = 50, ++ [1][0][5][10] = 74, ++ [1][0][6][10] = 42, ++ [1][0][9][10] = 42, ++ [1][0][8][10] = 60, ++ [1][0][11][10] = 42, ++ [1][0][2][11] = 64, ++ [1][0][1][11] = 42, ++ [1][0][3][11] = 50, ++ [1][0][5][11] = 64, ++ [1][0][6][11] = 42, ++ [1][0][9][11] = 42, ++ [1][0][8][11] = 60, ++ [1][0][11][11] = 42, ++ [1][0][2][12] = 36, ++ [1][0][1][12] = 42, ++ [1][0][3][12] = 50, ++ [1][0][5][12] = 36, ++ [1][0][6][12] = 42, ++ [1][0][9][12] = 42, ++ [1][0][8][12] = 60, ++ [1][0][11][12] = 42, ++ [1][0][2][13] = 127, ++ [1][0][1][13] = 127, ++ [1][0][3][13] = 127, ++ [1][0][5][13] = 127, ++ [1][0][6][13] = 127, ++ [1][0][9][13] = 127, ++ [1][0][8][13] = 127, ++ [1][0][11][13] = 127, ++ [1][1][2][0] = 66, ++ [1][1][1][0] = 30, ++ [1][1][3][0] = 38, ++ [1][1][5][0] = 66, ++ [1][1][6][0] = 30, ++ [1][1][9][0] = 30, ++ [1][1][8][0] = 48, ++ [1][1][11][0] = 30, ++ [1][1][2][1] = 66, ++ [1][1][1][1] = 30, ++ [1][1][3][1] = 38, ++ [1][1][5][1] = 66, ++ [1][1][6][1] = 30, ++ [1][1][9][1] = 30, ++ [1][1][8][1] = 48, ++ [1][1][11][1] = 30, ++ [1][1][2][2] = 70, ++ [1][1][1][2] = 30, ++ [1][1][3][2] = 38, ++ [1][1][5][2] = 70, ++ [1][1][6][2] = 30, ++ [1][1][9][2] = 30, ++ [1][1][8][2] = 48, ++ [1][1][11][2] = 30, ++ [1][1][2][3] = 74, ++ [1][1][1][3] = 30, ++ [1][1][3][3] = 38, ++ [1][1][5][3] = 74, ++ [1][1][6][3] = 30, ++ [1][1][9][3] = 30, ++ [1][1][8][3] = 48, ++ [1][1][11][3] = 30, ++ [1][1][2][4] = 78, ++ [1][1][1][4] = 30, ++ [1][1][3][4] = 38, ++ [1][1][5][4] = 78, ++ [1][1][6][4] = 30, ++ [1][1][9][4] = 30, ++ [1][1][8][4] = 48, ++ [1][1][11][4] = 30, ++ [1][1][2][5] = 78, ++ [1][1][1][5] = 30, ++ [1][1][3][5] = 38, ++ [1][1][5][5] = 78, ++ [1][1][6][5] = 30, ++ [1][1][9][5] = 30, ++ [1][1][8][5] = 48, ++ [1][1][11][5] = 30, ++ [1][1][2][6] = 78, ++ [1][1][1][6] = 30, ++ [1][1][3][6] = 38, ++ [1][1][5][6] = 78, ++ [1][1][6][6] = 30, ++ [1][1][9][6] = 30, ++ [1][1][8][6] = 48, ++ [1][1][11][6] = 30, ++ [1][1][2][7] = 74, ++ [1][1][1][7] = 30, ++ [1][1][3][7] = 38, ++ [1][1][5][7] = 74, ++ [1][1][6][7] = 30, ++ [1][1][9][7] = 30, ++ [1][1][8][7] = 48, ++ [1][1][11][7] = 30, ++ [1][1][2][8] = 70, ++ [1][1][1][8] = 30, ++ [1][1][3][8] = 38, ++ [1][1][5][8] = 70, ++ [1][1][6][8] = 30, ++ [1][1][9][8] = 30, ++ [1][1][8][8] = 48, ++ [1][1][11][8] = 30, ++ [1][1][2][9] = 66, ++ [1][1][1][9] = 30, ++ [1][1][3][9] = 38, ++ [1][1][5][9] = 66, ++ [1][1][6][9] = 30, ++ [1][1][9][9] = 30, ++ [1][1][8][9] = 48, ++ [1][1][11][9] = 30, ++ [1][1][2][10] = 66, ++ [1][1][1][10] = 30, ++ [1][1][3][10] = 38, ++ [1][1][5][10] = 66, ++ [1][1][6][10] = 30, ++ [1][1][9][10] = 30, ++ [1][1][8][10] = 48, ++ [1][1][11][10] = 30, ++ [1][1][2][11] = 60, ++ [1][1][1][11] = 30, ++ [1][1][3][11] = 38, ++ [1][1][5][11] = 60, ++ [1][1][6][11] = 30, ++ [1][1][9][11] = 30, ++ [1][1][8][11] = 48, ++ [1][1][11][11] = 30, ++ [1][1][2][12] = 32, ++ [1][1][1][12] = 30, ++ [1][1][3][12] = 38, ++ [1][1][5][12] = 32, ++ [1][1][6][12] = 30, ++ [1][1][9][12] = 30, ++ [1][1][8][12] = 48, ++ [1][1][11][12] = 30, ++ [1][1][2][13] = 127, ++ [1][1][1][13] = 127, ++ [1][1][3][13] = 127, ++ [1][1][5][13] = 127, ++ [1][1][6][13] = 127, ++ [1][1][9][13] = 127, ++ [1][1][8][13] = 127, ++ [1][1][11][13] = 127, ++ [2][0][2][0] = 76, ++ [2][0][1][0] = 52, ++ [2][0][3][0] = 64, ++ [2][0][5][0] = 76, ++ [2][0][6][0] = 52, ++ [2][0][9][0] = 52, ++ [2][0][8][0] = 60, ++ [2][0][11][0] = 52, ++ [2][0][2][1] = 76, ++ [2][0][1][1] = 52, ++ [2][0][3][1] = 64, ++ [2][0][5][1] = 76, ++ [2][0][6][1] = 52, ++ [2][0][9][1] = 52, ++ [2][0][8][1] = 60, ++ [2][0][11][1] = 52, ++ [2][0][2][2] = 78, ++ [2][0][1][2] = 52, ++ [2][0][3][2] = 64, ++ [2][0][5][2] = 78, ++ [2][0][6][2] = 52, ++ [2][0][9][2] = 52, ++ [2][0][8][2] = 60, ++ [2][0][11][2] = 52, ++ [2][0][2][3] = 78, ++ [2][0][1][3] = 52, ++ [2][0][3][3] = 64, ++ [2][0][5][3] = 78, ++ [2][0][6][3] = 52, ++ [2][0][9][3] = 52, ++ [2][0][8][3] = 60, ++ [2][0][11][3] = 52, ++ [2][0][2][4] = 78, ++ [2][0][1][4] = 52, ++ [2][0][3][4] = 64, ++ [2][0][5][4] = 78, ++ [2][0][6][4] = 52, ++ [2][0][9][4] = 52, ++ [2][0][8][4] = 60, ++ [2][0][11][4] = 52, ++ [2][0][2][5] = 78, ++ [2][0][1][5] = 52, ++ [2][0][3][5] = 64, ++ [2][0][5][5] = 78, ++ [2][0][6][5] = 52, ++ [2][0][9][5] = 52, ++ [2][0][8][5] = 60, ++ [2][0][11][5] = 52, ++ [2][0][2][6] = 78, ++ [2][0][1][6] = 52, ++ [2][0][3][6] = 64, ++ [2][0][5][6] = 78, ++ [2][0][6][6] = 52, ++ [2][0][9][6] = 52, ++ [2][0][8][6] = 60, ++ [2][0][11][6] = 52, ++ [2][0][2][7] = 78, ++ [2][0][1][7] = 52, ++ [2][0][3][7] = 64, ++ [2][0][5][7] = 78, ++ [2][0][6][7] = 52, ++ [2][0][9][7] = 52, ++ [2][0][8][7] = 60, ++ [2][0][11][7] = 52, ++ [2][0][2][8] = 78, ++ [2][0][1][8] = 52, ++ [2][0][3][8] = 64, ++ [2][0][5][8] = 78, ++ [2][0][6][8] = 52, ++ [2][0][9][8] = 52, ++ [2][0][8][8] = 60, ++ [2][0][11][8] = 52, ++ [2][0][2][9] = 76, ++ [2][0][1][9] = 52, ++ [2][0][3][9] = 64, ++ [2][0][5][9] = 76, ++ [2][0][6][9] = 52, ++ [2][0][9][9] = 52, ++ [2][0][8][9] = 60, ++ [2][0][11][9] = 52, ++ [2][0][2][10] = 76, ++ [2][0][1][10] = 52, ++ [2][0][3][10] = 64, ++ [2][0][5][10] = 76, ++ [2][0][6][10] = 52, ++ [2][0][9][10] = 52, ++ [2][0][8][10] = 60, ++ [2][0][11][10] = 52, ++ [2][0][2][11] = 68, ++ [2][0][1][11] = 52, ++ [2][0][3][11] = 64, ++ [2][0][5][11] = 68, ++ [2][0][6][11] = 52, ++ [2][0][9][11] = 52, ++ [2][0][8][11] = 60, ++ [2][0][11][11] = 52, ++ [2][0][2][12] = 40, ++ [2][0][1][12] = 52, ++ [2][0][3][12] = 64, ++ [2][0][5][12] = 40, ++ [2][0][6][12] = 52, ++ [2][0][9][12] = 52, ++ [2][0][8][12] = 60, ++ [2][0][11][12] = 52, ++ [2][0][2][13] = 127, ++ [2][0][1][13] = 127, ++ [2][0][3][13] = 127, ++ [2][0][5][13] = 127, ++ [2][0][6][13] = 127, ++ [2][0][9][13] = 127, ++ [2][0][8][13] = 127, ++ [2][0][11][13] = 127, ++ [2][1][2][0] = 68, ++ [2][1][1][0] = 40, ++ [2][1][3][0] = 52, ++ [2][1][5][0] = 68, ++ [2][1][6][0] = 40, ++ [2][1][9][0] = 40, ++ [2][1][8][0] = 48, ++ [2][1][11][0] = 40, ++ [2][1][2][1] = 68, ++ [2][1][1][1] = 40, ++ [2][1][3][1] = 52, ++ [2][1][5][1] = 68, ++ [2][1][6][1] = 40, ++ [2][1][9][1] = 40, ++ [2][1][8][1] = 48, ++ [2][1][11][1] = 40, ++ [2][1][2][2] = 72, ++ [2][1][1][2] = 40, ++ [2][1][3][2] = 52, ++ [2][1][5][2] = 72, ++ [2][1][6][2] = 40, ++ [2][1][9][2] = 40, ++ [2][1][8][2] = 48, ++ [2][1][11][2] = 40, ++ [2][1][2][3] = 76, ++ [2][1][1][3] = 40, ++ [2][1][3][3] = 52, ++ [2][1][5][3] = 76, ++ [2][1][6][3] = 40, ++ [2][1][9][3] = 40, ++ [2][1][8][3] = 48, ++ [2][1][11][3] = 40, ++ [2][1][2][4] = 78, ++ [2][1][1][4] = 40, ++ [2][1][3][4] = 52, ++ [2][1][5][4] = 78, ++ [2][1][6][4] = 40, ++ [2][1][9][4] = 40, ++ [2][1][8][4] = 48, ++ [2][1][11][4] = 40, ++ [2][1][2][5] = 78, ++ [2][1][1][5] = 40, ++ [2][1][3][5] = 52, ++ [2][1][5][5] = 78, ++ [2][1][6][5] = 40, ++ [2][1][9][5] = 40, ++ [2][1][8][5] = 48, ++ [2][1][11][5] = 40, ++ [2][1][2][6] = 78, ++ [2][1][1][6] = 40, ++ [2][1][3][6] = 52, ++ [2][1][5][6] = 78, ++ [2][1][6][6] = 40, ++ [2][1][9][6] = 40, ++ [2][1][8][6] = 48, ++ [2][1][11][6] = 40, ++ [2][1][2][7] = 78, ++ [2][1][1][7] = 40, ++ [2][1][3][7] = 52, ++ [2][1][5][7] = 78, ++ [2][1][6][7] = 40, ++ [2][1][9][7] = 40, ++ [2][1][8][7] = 48, ++ [2][1][11][7] = 40, ++ [2][1][2][8] = 74, ++ [2][1][1][8] = 40, ++ [2][1][3][8] = 52, ++ [2][1][5][8] = 74, ++ [2][1][6][8] = 40, ++ [2][1][9][8] = 40, ++ [2][1][8][8] = 48, ++ [2][1][11][8] = 40, ++ [2][1][2][9] = 70, ++ [2][1][1][9] = 40, ++ [2][1][3][9] = 52, ++ [2][1][5][9] = 70, ++ [2][1][6][9] = 40, ++ [2][1][9][9] = 40, ++ [2][1][8][9] = 48, ++ [2][1][11][9] = 40, ++ [2][1][2][10] = 70, ++ [2][1][1][10] = 40, ++ [2][1][3][10] = 52, ++ [2][1][5][10] = 70, ++ [2][1][6][10] = 40, ++ [2][1][9][10] = 40, ++ [2][1][8][10] = 48, ++ [2][1][11][10] = 40, ++ [2][1][2][11] = 48, ++ [2][1][1][11] = 40, ++ [2][1][3][11] = 52, ++ [2][1][5][11] = 48, ++ [2][1][6][11] = 40, ++ [2][1][9][11] = 40, ++ [2][1][8][11] = 48, ++ [2][1][11][11] = 40, ++ [2][1][2][12] = 26, ++ [2][1][1][12] = 40, ++ [2][1][3][12] = 52, ++ [2][1][5][12] = 26, ++ [2][1][6][12] = 40, ++ [2][1][9][12] = 40, ++ [2][1][8][12] = 48, ++ [2][1][11][12] = 40, ++ [2][1][2][13] = 127, ++ [2][1][1][13] = 127, ++ [2][1][3][13] = 127, ++ [2][1][5][13] = 127, ++ [2][1][6][13] = 127, ++ [2][1][9][13] = 127, ++ [2][1][8][13] = 127, ++ [2][1][11][13] = 127, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { ++ [0][0][0][0] = 22, ++ [0][0][0][2] = 22, ++ [0][0][0][4] = 22, ++ [0][0][0][6] = 22, ++ [0][0][0][8] = 24, ++ [0][0][0][10] = 24, ++ [0][0][0][12] = 24, ++ [0][0][0][14] = 24, ++ [0][0][0][15] = 24, ++ [0][0][0][17] = 24, ++ [0][0][0][19] = 24, ++ [0][0][0][21] = 24, ++ [0][0][0][23] = 24, ++ [0][0][0][25] = 24, ++ [0][0][0][27] = 24, ++ [0][0][0][29] = 24, ++ [0][0][0][31] = 24, ++ [0][0][0][33] = 24, ++ [0][0][0][35] = 24, ++ [0][0][0][37] = 24, ++ [0][0][0][38] = 28, ++ [0][0][0][40] = 28, ++ [0][0][0][42] = 28, ++ [0][0][0][44] = 28, ++ [0][0][0][46] = 28, ++ [0][1][0][0] = 8, ++ [0][1][0][2] = 8, ++ [0][1][0][4] = 8, ++ [0][1][0][6] = 8, ++ [0][1][0][8] = 12, ++ [0][1][0][10] = 12, ++ [0][1][0][12] = 12, ++ [0][1][0][14] = 12, ++ [0][1][0][15] = 12, ++ [0][1][0][17] = 12, ++ [0][1][0][19] = 12, ++ [0][1][0][21] = 12, ++ [0][1][0][23] = 12, ++ [0][1][0][25] = 12, ++ [0][1][0][27] = 12, ++ [0][1][0][29] = 12, ++ [0][1][0][31] = 12, ++ [0][1][0][33] = 12, ++ [0][1][0][35] = 12, ++ [0][1][0][37] = 12, ++ [0][1][0][38] = 16, ++ [0][1][0][40] = 16, ++ [0][1][0][42] = 16, ++ [0][1][0][44] = 16, ++ [0][1][0][46] = 16, ++ [1][0][0][0] = 30, ++ [1][0][0][2] = 30, ++ [1][0][0][4] = 30, ++ [1][0][0][6] = 30, ++ [1][0][0][8] = 36, ++ [1][0][0][10] = 36, ++ [1][0][0][12] = 36, ++ [1][0][0][14] = 36, ++ [1][0][0][15] = 36, ++ [1][0][0][17] = 36, ++ [1][0][0][19] = 36, ++ [1][0][0][21] = 36, ++ [1][0][0][23] = 36, ++ [1][0][0][25] = 36, ++ [1][0][0][27] = 36, ++ [1][0][0][29] = 36, ++ [1][0][0][31] = 36, ++ [1][0][0][33] = 36, ++ [1][0][0][35] = 36, ++ [1][0][0][37] = 36, ++ [1][0][0][38] = 28, ++ [1][0][0][40] = 28, ++ [1][0][0][42] = 28, ++ [1][0][0][44] = 28, ++ [1][0][0][46] = 28, ++ [1][1][0][0] = 18, ++ [1][1][0][2] = 18, ++ [1][1][0][4] = 18, ++ [1][1][0][6] = 18, ++ [1][1][0][8] = 22, ++ [1][1][0][10] = 22, ++ [1][1][0][12] = 22, ++ [1][1][0][14] = 22, ++ [1][1][0][15] = 22, ++ [1][1][0][17] = 22, ++ [1][1][0][19] = 22, ++ [1][1][0][21] = 22, ++ [1][1][0][23] = 22, ++ [1][1][0][25] = 22, ++ [1][1][0][27] = 22, ++ [1][1][0][29] = 22, ++ [1][1][0][31] = 22, ++ [1][1][0][33] = 22, ++ [1][1][0][35] = 22, ++ [1][1][0][37] = 22, ++ [1][1][0][38] = 16, ++ [1][1][0][40] = 16, ++ [1][1][0][42] = 16, ++ [1][1][0][44] = 16, ++ [1][1][0][46] = 16, ++ [2][0][0][0] = 30, ++ [2][0][0][2] = 30, ++ [2][0][0][4] = 30, ++ [2][0][0][6] = 30, ++ [2][0][0][8] = 46, ++ [2][0][0][10] = 46, ++ [2][0][0][12] = 46, ++ [2][0][0][14] = 46, ++ [2][0][0][15] = 46, ++ [2][0][0][17] = 46, ++ [2][0][0][19] = 46, ++ [2][0][0][21] = 46, ++ [2][0][0][23] = 46, ++ [2][0][0][25] = 46, ++ [2][0][0][27] = 46, ++ [2][0][0][29] = 46, ++ [2][0][0][31] = 46, ++ [2][0][0][33] = 46, ++ [2][0][0][35] = 46, ++ [2][0][0][37] = 46, ++ [2][0][0][38] = 28, ++ [2][0][0][40] = 28, ++ [2][0][0][42] = 28, ++ [2][0][0][44] = 28, ++ [2][0][0][46] = 28, ++ [2][1][0][0] = 18, ++ [2][1][0][2] = 18, ++ [2][1][0][4] = 18, ++ [2][1][0][6] = 18, ++ [2][1][0][8] = 32, ++ [2][1][0][10] = 32, ++ [2][1][0][12] = 32, ++ [2][1][0][14] = 32, ++ [2][1][0][15] = 32, ++ [2][1][0][17] = 32, ++ [2][1][0][19] = 32, ++ [2][1][0][21] = 32, ++ [2][1][0][23] = 32, ++ [2][1][0][25] = 32, ++ [2][1][0][27] = 32, ++ [2][1][0][29] = 32, ++ [2][1][0][31] = 32, ++ [2][1][0][33] = 32, ++ [2][1][0][35] = 32, ++ [2][1][0][37] = 32, ++ [2][1][0][38] = 16, ++ [2][1][0][40] = 16, ++ [2][1][0][42] = 16, ++ [2][1][0][44] = 16, ++ [2][1][0][46] = 16, ++ [0][0][2][0] = 48, ++ [0][0][1][0] = 24, ++ [0][0][3][0] = 26, ++ [0][0][5][0] = 22, ++ [0][0][6][0] = 24, ++ [0][0][9][0] = 24, ++ [0][0][8][0] = 30, ++ [0][0][11][0] = 24, ++ [0][0][2][2] = 48, ++ [0][0][1][2] = 24, ++ [0][0][3][2] = 26, ++ [0][0][5][2] = 22, ++ [0][0][6][2] = 24, ++ [0][0][9][2] = 24, ++ [0][0][8][2] = 30, ++ [0][0][11][2] = 24, ++ [0][0][2][4] = 48, ++ [0][0][1][4] = 24, ++ [0][0][3][4] = 26, ++ [0][0][5][4] = 22, ++ [0][0][6][4] = 24, ++ [0][0][9][4] = 24, ++ [0][0][8][4] = 30, ++ [0][0][11][4] = 24, ++ [0][0][2][6] = 48, ++ [0][0][1][6] = 24, ++ [0][0][3][6] = 26, ++ [0][0][5][6] = 22, ++ [0][0][6][6] = 24, ++ [0][0][9][6] = 24, ++ [0][0][8][6] = 30, ++ [0][0][11][6] = 24, ++ [0][0][2][8] = 48, ++ [0][0][1][8] = 24, ++ [0][0][3][8] = 26, ++ [0][0][5][8] = 48, ++ [0][0][6][8] = 24, ++ [0][0][9][8] = 24, ++ [0][0][8][8] = 54, ++ [0][0][11][8] = 24, ++ [0][0][2][10] = 48, ++ [0][0][1][10] = 24, ++ [0][0][3][10] = 26, ++ [0][0][5][10] = 48, ++ [0][0][6][10] = 24, ++ [0][0][9][10] = 24, ++ [0][0][8][10] = 54, ++ [0][0][11][10] = 24, ++ [0][0][2][12] = 48, ++ [0][0][1][12] = 24, ++ [0][0][3][12] = 26, ++ [0][0][5][12] = 48, ++ [0][0][6][12] = 24, ++ [0][0][9][12] = 24, ++ [0][0][8][12] = 54, ++ [0][0][11][12] = 24, ++ [0][0][2][14] = 48, ++ [0][0][1][14] = 24, ++ [0][0][3][14] = 26, ++ [0][0][5][14] = 48, ++ [0][0][6][14] = 24, ++ [0][0][9][14] = 24, ++ [0][0][8][14] = 54, ++ [0][0][11][14] = 24, ++ [0][0][2][15] = 48, ++ [0][0][1][15] = 24, ++ [0][0][3][15] = 44, ++ [0][0][5][15] = 48, ++ [0][0][6][15] = 24, ++ [0][0][9][15] = 24, ++ [0][0][8][15] = 54, ++ [0][0][11][15] = 24, ++ [0][0][2][17] = 48, ++ [0][0][1][17] = 24, ++ [0][0][3][17] = 44, ++ [0][0][5][17] = 48, ++ [0][0][6][17] = 24, ++ [0][0][9][17] = 24, ++ [0][0][8][17] = 54, ++ [0][0][11][17] = 24, ++ [0][0][2][19] = 48, ++ [0][0][1][19] = 24, ++ [0][0][3][19] = 44, ++ [0][0][5][19] = 48, ++ [0][0][6][19] = 24, ++ [0][0][9][19] = 24, ++ [0][0][8][19] = 54, ++ [0][0][11][19] = 24, ++ [0][0][2][21] = 48, ++ [0][0][1][21] = 24, ++ [0][0][3][21] = 44, ++ [0][0][5][21] = 48, ++ [0][0][6][21] = 24, ++ [0][0][9][21] = 24, ++ [0][0][8][21] = 54, ++ [0][0][11][21] = 24, ++ [0][0][2][23] = 48, ++ [0][0][1][23] = 24, ++ [0][0][3][23] = 44, ++ [0][0][5][23] = 48, ++ [0][0][6][23] = 24, ++ [0][0][9][23] = 24, ++ [0][0][8][23] = 54, ++ [0][0][11][23] = 24, ++ [0][0][2][25] = 48, ++ [0][0][1][25] = 24, ++ [0][0][3][25] = 44, ++ [0][0][5][25] = 127, ++ [0][0][6][25] = 24, ++ [0][0][9][25] = 127, ++ [0][0][8][25] = 54, ++ [0][0][11][25] = 24, ++ [0][0][2][27] = 48, ++ [0][0][1][27] = 24, ++ [0][0][3][27] = 44, ++ [0][0][5][27] = 127, ++ [0][0][6][27] = 24, ++ [0][0][9][27] = 127, ++ [0][0][8][27] = 54, ++ [0][0][11][27] = 24, ++ [0][0][2][29] = 48, ++ [0][0][1][29] = 24, ++ [0][0][3][29] = 44, ++ [0][0][5][29] = 127, ++ [0][0][6][29] = 24, ++ [0][0][9][29] = 127, ++ [0][0][8][29] = 54, ++ [0][0][11][29] = 24, ++ [0][0][2][31] = 48, ++ [0][0][1][31] = 24, ++ [0][0][3][31] = 44, ++ [0][0][5][31] = 48, ++ [0][0][6][31] = 24, ++ [0][0][9][31] = 24, ++ [0][0][8][31] = 54, ++ [0][0][11][31] = 24, ++ [0][0][2][33] = 48, ++ [0][0][1][33] = 24, ++ [0][0][3][33] = 44, ++ [0][0][5][33] = 48, ++ [0][0][6][33] = 24, ++ [0][0][9][33] = 24, ++ [0][0][8][33] = 54, ++ [0][0][11][33] = 24, ++ [0][0][2][35] = 48, ++ [0][0][1][35] = 24, ++ [0][0][3][35] = 44, ++ [0][0][5][35] = 48, ++ [0][0][6][35] = 24, ++ [0][0][9][35] = 24, ++ [0][0][8][35] = 54, ++ [0][0][11][35] = 24, ++ [0][0][2][37] = 48, ++ [0][0][1][37] = 127, ++ [0][0][3][37] = 44, ++ [0][0][5][37] = 48, ++ [0][0][6][37] = 24, ++ [0][0][9][37] = 48, ++ [0][0][8][37] = 54, ++ [0][0][11][37] = 127, ++ [0][0][2][38] = 76, ++ [0][0][1][38] = 28, ++ [0][0][3][38] = 127, ++ [0][0][5][38] = 76, ++ [0][0][6][38] = 28, ++ [0][0][9][38] = 76, ++ [0][0][8][38] = 54, ++ [0][0][11][38] = 28, ++ [0][0][2][40] = 76, ++ [0][0][1][40] = 28, ++ [0][0][3][40] = 127, ++ [0][0][5][40] = 76, ++ [0][0][6][40] = 28, ++ [0][0][9][40] = 76, ++ [0][0][8][40] = 54, ++ [0][0][11][40] = 28, ++ [0][0][2][42] = 76, ++ [0][0][1][42] = 28, ++ [0][0][3][42] = 127, ++ [0][0][5][42] = 76, ++ [0][0][6][42] = 28, ++ [0][0][9][42] = 76, ++ [0][0][8][42] = 54, ++ [0][0][11][42] = 28, ++ [0][0][2][44] = 76, ++ [0][0][1][44] = 28, ++ [0][0][3][44] = 127, ++ [0][0][5][44] = 76, ++ [0][0][6][44] = 28, ++ [0][0][9][44] = 76, ++ [0][0][8][44] = 54, ++ [0][0][11][44] = 28, ++ [0][0][2][46] = 76, ++ [0][0][1][46] = 28, ++ [0][0][3][46] = 127, ++ [0][0][5][46] = 76, ++ [0][0][6][46] = 28, ++ [0][0][9][46] = 76, ++ [0][0][8][46] = 54, ++ [0][0][11][46] = 28, ++ [0][1][2][0] = 36, ++ [0][1][1][0] = 12, ++ [0][1][3][0] = 14, ++ [0][1][5][0] = 8, ++ [0][1][6][0] = 12, ++ [0][1][9][0] = 12, ++ [0][1][8][0] = 18, ++ [0][1][11][0] = 12, ++ [0][1][2][2] = 36, ++ [0][1][1][2] = 12, ++ [0][1][3][2] = 14, ++ [0][1][5][2] = 8, ++ [0][1][6][2] = 12, ++ [0][1][9][2] = 12, ++ [0][1][8][2] = 18, ++ [0][1][11][2] = 12, ++ [0][1][2][4] = 36, ++ [0][1][1][4] = 12, ++ [0][1][3][4] = 14, ++ [0][1][5][4] = 8, ++ [0][1][6][4] = 12, ++ [0][1][9][4] = 12, ++ [0][1][8][4] = 18, ++ [0][1][11][4] = 12, ++ [0][1][2][6] = 36, ++ [0][1][1][6] = 12, ++ [0][1][3][6] = 14, ++ [0][1][5][6] = 8, ++ [0][1][6][6] = 12, ++ [0][1][9][6] = 12, ++ [0][1][8][6] = 18, ++ [0][1][11][6] = 12, ++ [0][1][2][8] = 36, ++ [0][1][1][8] = 12, ++ [0][1][3][8] = 14, ++ [0][1][5][8] = 36, ++ [0][1][6][8] = 12, ++ [0][1][9][8] = 12, ++ [0][1][8][8] = 42, ++ [0][1][11][8] = 12, ++ [0][1][2][10] = 36, ++ [0][1][1][10] = 12, ++ [0][1][3][10] = 14, ++ [0][1][5][10] = 36, ++ [0][1][6][10] = 12, ++ [0][1][9][10] = 12, ++ [0][1][8][10] = 42, ++ [0][1][11][10] = 12, ++ [0][1][2][12] = 36, ++ [0][1][1][12] = 12, ++ [0][1][3][12] = 14, ++ [0][1][5][12] = 36, ++ [0][1][6][12] = 12, ++ [0][1][9][12] = 12, ++ [0][1][8][12] = 42, ++ [0][1][11][12] = 12, ++ [0][1][2][14] = 36, ++ [0][1][1][14] = 12, ++ [0][1][3][14] = 14, ++ [0][1][5][14] = 36, ++ [0][1][6][14] = 12, ++ [0][1][9][14] = 12, ++ [0][1][8][14] = 42, ++ [0][1][11][14] = 12, ++ [0][1][2][15] = 36, ++ [0][1][1][15] = 12, ++ [0][1][3][15] = 32, ++ [0][1][5][15] = 36, ++ [0][1][6][15] = 12, ++ [0][1][9][15] = 12, ++ [0][1][8][15] = 42, ++ [0][1][11][15] = 12, ++ [0][1][2][17] = 36, ++ [0][1][1][17] = 12, ++ [0][1][3][17] = 32, ++ [0][1][5][17] = 36, ++ [0][1][6][17] = 12, ++ [0][1][9][17] = 12, ++ [0][1][8][17] = 42, ++ [0][1][11][17] = 12, ++ [0][1][2][19] = 36, ++ [0][1][1][19] = 12, ++ [0][1][3][19] = 32, ++ [0][1][5][19] = 36, ++ [0][1][6][19] = 12, ++ [0][1][9][19] = 12, ++ [0][1][8][19] = 42, ++ [0][1][11][19] = 12, ++ [0][1][2][21] = 36, ++ [0][1][1][21] = 12, ++ [0][1][3][21] = 32, ++ [0][1][5][21] = 36, ++ [0][1][6][21] = 12, ++ [0][1][9][21] = 12, ++ [0][1][8][21] = 42, ++ [0][1][11][21] = 12, ++ [0][1][2][23] = 36, ++ [0][1][1][23] = 12, ++ [0][1][3][23] = 32, ++ [0][1][5][23] = 36, ++ [0][1][6][23] = 12, ++ [0][1][9][23] = 12, ++ [0][1][8][23] = 42, ++ [0][1][11][23] = 12, ++ [0][1][2][25] = 36, ++ [0][1][1][25] = 12, ++ [0][1][3][25] = 32, ++ [0][1][5][25] = 127, ++ [0][1][6][25] = 12, ++ [0][1][9][25] = 127, ++ [0][1][8][25] = 42, ++ [0][1][11][25] = 12, ++ [0][1][2][27] = 36, ++ [0][1][1][27] = 12, ++ [0][1][3][27] = 32, ++ [0][1][5][27] = 127, ++ [0][1][6][27] = 12, ++ [0][1][9][27] = 127, ++ [0][1][8][27] = 42, ++ [0][1][11][27] = 12, ++ [0][1][2][29] = 36, ++ [0][1][1][29] = 12, ++ [0][1][3][29] = 32, ++ [0][1][5][29] = 127, ++ [0][1][6][29] = 12, ++ [0][1][9][29] = 127, ++ [0][1][8][29] = 42, ++ [0][1][11][29] = 12, ++ [0][1][2][31] = 36, ++ [0][1][1][31] = 12, ++ [0][1][3][31] = 32, ++ [0][1][5][31] = 36, ++ [0][1][6][31] = 12, ++ [0][1][9][31] = 12, ++ [0][1][8][31] = 42, ++ [0][1][11][31] = 12, ++ [0][1][2][33] = 36, ++ [0][1][1][33] = 12, ++ [0][1][3][33] = 32, ++ [0][1][5][33] = 36, ++ [0][1][6][33] = 12, ++ [0][1][9][33] = 12, ++ [0][1][8][33] = 42, ++ [0][1][11][33] = 12, ++ [0][1][2][35] = 36, ++ [0][1][1][35] = 12, ++ [0][1][3][35] = 32, ++ [0][1][5][35] = 36, ++ [0][1][6][35] = 12, ++ [0][1][9][35] = 12, ++ [0][1][8][35] = 42, ++ [0][1][11][35] = 12, ++ [0][1][2][37] = 36, ++ [0][1][1][37] = 127, ++ [0][1][3][37] = 32, ++ [0][1][5][37] = 36, ++ [0][1][6][37] = 12, ++ [0][1][9][37] = 36, ++ [0][1][8][37] = 42, ++ [0][1][11][37] = 127, ++ [0][1][2][38] = 72, ++ [0][1][1][38] = 16, ++ [0][1][3][38] = 127, ++ [0][1][5][38] = 72, ++ [0][1][6][38] = 16, ++ [0][1][9][38] = 76, ++ [0][1][8][38] = 42, ++ [0][1][11][38] = 16, ++ [0][1][2][40] = 76, ++ [0][1][1][40] = 16, ++ [0][1][3][40] = 127, ++ [0][1][5][40] = 76, ++ [0][1][6][40] = 16, ++ [0][1][9][40] = 76, ++ [0][1][8][40] = 42, ++ [0][1][11][40] = 16, ++ [0][1][2][42] = 76, ++ [0][1][1][42] = 16, ++ [0][1][3][42] = 127, ++ [0][1][5][42] = 76, ++ [0][1][6][42] = 16, ++ [0][1][9][42] = 76, ++ [0][1][8][42] = 42, ++ [0][1][11][42] = 16, ++ [0][1][2][44] = 76, ++ [0][1][1][44] = 16, ++ [0][1][3][44] = 127, ++ [0][1][5][44] = 76, ++ [0][1][6][44] = 16, ++ [0][1][9][44] = 76, ++ [0][1][8][44] = 42, ++ [0][1][11][44] = 16, ++ [0][1][2][46] = 76, ++ [0][1][1][46] = 16, ++ [0][1][3][46] = 127, ++ [0][1][5][46] = 76, ++ [0][1][6][46] = 16, ++ [0][1][9][46] = 76, ++ [0][1][8][46] = 42, ++ [0][1][11][46] = 16, ++ [1][0][2][0] = 62, ++ [1][0][1][0] = 36, ++ [1][0][3][0] = 36, ++ [1][0][5][0] = 34, ++ [1][0][6][0] = 36, ++ [1][0][9][0] = 36, ++ [1][0][8][0] = 30, ++ [1][0][11][0] = 36, ++ [1][0][2][2] = 62, ++ [1][0][1][2] = 36, ++ [1][0][3][2] = 36, ++ [1][0][5][2] = 34, ++ [1][0][6][2] = 36, ++ [1][0][9][2] = 36, ++ [1][0][8][2] = 30, ++ [1][0][11][2] = 36, ++ [1][0][2][4] = 62, ++ [1][0][1][4] = 36, ++ [1][0][3][4] = 36, ++ [1][0][5][4] = 34, ++ [1][0][6][4] = 36, ++ [1][0][9][4] = 36, ++ [1][0][8][4] = 30, ++ [1][0][11][4] = 36, ++ [1][0][2][6] = 62, ++ [1][0][1][6] = 36, ++ [1][0][3][6] = 36, ++ [1][0][5][6] = 34, ++ [1][0][6][6] = 36, ++ [1][0][9][6] = 36, ++ [1][0][8][6] = 30, ++ [1][0][11][6] = 36, ++ [1][0][2][8] = 62, ++ [1][0][1][8] = 36, ++ [1][0][3][8] = 36, ++ [1][0][5][8] = 62, ++ [1][0][6][8] = 36, ++ [1][0][9][8] = 36, ++ [1][0][8][8] = 54, ++ [1][0][11][8] = 36, ++ [1][0][2][10] = 62, ++ [1][0][1][10] = 36, ++ [1][0][3][10] = 36, ++ [1][0][5][10] = 62, ++ [1][0][6][10] = 36, ++ [1][0][9][10] = 36, ++ [1][0][8][10] = 54, ++ [1][0][11][10] = 36, ++ [1][0][2][12] = 62, ++ [1][0][1][12] = 36, ++ [1][0][3][12] = 36, ++ [1][0][5][12] = 62, ++ [1][0][6][12] = 36, ++ [1][0][9][12] = 36, ++ [1][0][8][12] = 54, ++ [1][0][11][12] = 36, ++ [1][0][2][14] = 62, ++ [1][0][1][14] = 36, ++ [1][0][3][14] = 36, ++ [1][0][5][14] = 62, ++ [1][0][6][14] = 36, ++ [1][0][9][14] = 36, ++ [1][0][8][14] = 54, ++ [1][0][11][14] = 36, ++ [1][0][2][15] = 62, ++ [1][0][1][15] = 36, ++ [1][0][3][15] = 58, ++ [1][0][5][15] = 62, ++ [1][0][6][15] = 36, ++ [1][0][9][15] = 36, ++ [1][0][8][15] = 54, ++ [1][0][11][15] = 36, ++ [1][0][2][17] = 62, ++ [1][0][1][17] = 36, ++ [1][0][3][17] = 58, ++ [1][0][5][17] = 62, ++ [1][0][6][17] = 36, ++ [1][0][9][17] = 36, ++ [1][0][8][17] = 54, ++ [1][0][11][17] = 36, ++ [1][0][2][19] = 62, ++ [1][0][1][19] = 36, ++ [1][0][3][19] = 58, ++ [1][0][5][19] = 62, ++ [1][0][6][19] = 36, ++ [1][0][9][19] = 36, ++ [1][0][8][19] = 54, ++ [1][0][11][19] = 36, ++ [1][0][2][21] = 62, ++ [1][0][1][21] = 36, ++ [1][0][3][21] = 58, ++ [1][0][5][21] = 62, ++ [1][0][6][21] = 36, ++ [1][0][9][21] = 36, ++ [1][0][8][21] = 54, ++ [1][0][11][21] = 36, ++ [1][0][2][23] = 62, ++ [1][0][1][23] = 36, ++ [1][0][3][23] = 58, ++ [1][0][5][23] = 62, ++ [1][0][6][23] = 36, ++ [1][0][9][23] = 36, ++ [1][0][8][23] = 54, ++ [1][0][11][23] = 36, ++ [1][0][2][25] = 62, ++ [1][0][1][25] = 36, ++ [1][0][3][25] = 58, ++ [1][0][5][25] = 127, ++ [1][0][6][25] = 36, ++ [1][0][9][25] = 127, ++ [1][0][8][25] = 54, ++ [1][0][11][25] = 36, ++ [1][0][2][27] = 62, ++ [1][0][1][27] = 36, ++ [1][0][3][27] = 58, ++ [1][0][5][27] = 127, ++ [1][0][6][27] = 36, ++ [1][0][9][27] = 127, ++ [1][0][8][27] = 54, ++ [1][0][11][27] = 36, ++ [1][0][2][29] = 62, ++ [1][0][1][29] = 36, ++ [1][0][3][29] = 58, ++ [1][0][5][29] = 127, ++ [1][0][6][29] = 36, ++ [1][0][9][29] = 127, ++ [1][0][8][29] = 54, ++ [1][0][11][29] = 36, ++ [1][0][2][31] = 62, ++ [1][0][1][31] = 36, ++ [1][0][3][31] = 58, ++ [1][0][5][31] = 62, ++ [1][0][6][31] = 36, ++ [1][0][9][31] = 36, ++ [1][0][8][31] = 54, ++ [1][0][11][31] = 36, ++ [1][0][2][33] = 62, ++ [1][0][1][33] = 36, ++ [1][0][3][33] = 58, ++ [1][0][5][33] = 62, ++ [1][0][6][33] = 36, ++ [1][0][9][33] = 36, ++ [1][0][8][33] = 54, ++ [1][0][11][33] = 36, ++ [1][0][2][35] = 62, ++ [1][0][1][35] = 36, ++ [1][0][3][35] = 58, ++ [1][0][5][35] = 62, ++ [1][0][6][35] = 36, ++ [1][0][9][35] = 36, ++ [1][0][8][35] = 54, ++ [1][0][11][35] = 36, ++ [1][0][2][37] = 56, ++ [1][0][1][37] = 62, ++ [1][0][3][37] = 127, ++ [1][0][5][37] = 58, ++ [1][0][6][37] = 62, ++ [1][0][9][37] = 36, ++ [1][0][8][37] = 62, ++ [1][0][11][37] = 54, ++ [1][0][2][38] = 76, ++ [1][0][1][38] = 28, ++ [1][0][3][38] = 127, ++ [1][0][5][38] = 76, ++ [1][0][6][38] = 28, ++ [1][0][9][38] = 76, ++ [1][0][8][38] = 54, ++ [1][0][11][38] = 28, ++ [1][0][2][40] = 76, ++ [1][0][1][40] = 28, ++ [1][0][3][40] = 127, ++ [1][0][5][40] = 76, ++ [1][0][6][40] = 28, ++ [1][0][9][40] = 76, ++ [1][0][8][40] = 54, ++ [1][0][11][40] = 28, ++ [1][0][2][42] = 76, ++ [1][0][1][42] = 28, ++ [1][0][3][42] = 127, ++ [1][0][5][42] = 76, ++ [1][0][6][42] = 28, ++ [1][0][9][42] = 76, ++ [1][0][8][42] = 54, ++ [1][0][11][42] = 28, ++ [1][0][2][44] = 76, ++ [1][0][1][44] = 28, ++ [1][0][3][44] = 127, ++ [1][0][5][44] = 76, ++ [1][0][6][44] = 28, ++ [1][0][9][44] = 76, ++ [1][0][8][44] = 54, ++ [1][0][11][44] = 28, ++ [1][0][2][46] = 76, ++ [1][0][1][46] = 28, ++ [1][0][3][46] = 127, ++ [1][0][5][46] = 76, ++ [1][0][6][46] = 28, ++ [1][0][9][46] = 76, ++ [1][0][8][46] = 54, ++ [1][0][11][46] = 28, ++ [1][1][2][0] = 46, ++ [1][1][1][0] = 22, ++ [1][1][3][0] = 24, ++ [1][1][5][0] = 18, ++ [1][1][6][0] = 22, ++ [1][1][9][0] = 22, ++ [1][1][8][0] = 18, ++ [1][1][11][0] = 22, ++ [1][1][2][2] = 46, ++ [1][1][1][2] = 22, ++ [1][1][3][2] = 24, ++ [1][1][5][2] = 18, ++ [1][1][6][2] = 22, ++ [1][1][9][2] = 22, ++ [1][1][8][2] = 18, ++ [1][1][11][2] = 22, ++ [1][1][2][4] = 46, ++ [1][1][1][4] = 22, ++ [1][1][3][4] = 24, ++ [1][1][5][4] = 18, ++ [1][1][6][4] = 22, ++ [1][1][9][4] = 22, ++ [1][1][8][4] = 18, ++ [1][1][11][4] = 22, ++ [1][1][2][6] = 46, ++ [1][1][1][6] = 22, ++ [1][1][3][6] = 24, ++ [1][1][5][6] = 18, ++ [1][1][6][6] = 22, ++ [1][1][9][6] = 22, ++ [1][1][8][6] = 18, ++ [1][1][11][6] = 22, ++ [1][1][2][8] = 46, ++ [1][1][1][8] = 22, ++ [1][1][3][8] = 24, ++ [1][1][5][8] = 46, ++ [1][1][6][8] = 22, ++ [1][1][9][8] = 22, ++ [1][1][8][8] = 42, ++ [1][1][11][8] = 22, ++ [1][1][2][10] = 46, ++ [1][1][1][10] = 22, ++ [1][1][3][10] = 24, ++ [1][1][5][10] = 46, ++ [1][1][6][10] = 22, ++ [1][1][9][10] = 22, ++ [1][1][8][10] = 42, ++ [1][1][11][10] = 22, ++ [1][1][2][12] = 46, ++ [1][1][1][12] = 22, ++ [1][1][3][12] = 24, ++ [1][1][5][12] = 46, ++ [1][1][6][12] = 22, ++ [1][1][9][12] = 22, ++ [1][1][8][12] = 42, ++ [1][1][11][12] = 22, ++ [1][1][2][14] = 46, ++ [1][1][1][14] = 22, ++ [1][1][3][14] = 24, ++ [1][1][5][14] = 46, ++ [1][1][6][14] = 22, ++ [1][1][9][14] = 22, ++ [1][1][8][14] = 42, ++ [1][1][11][14] = 22, ++ [1][1][2][15] = 46, ++ [1][1][1][15] = 22, ++ [1][1][3][15] = 46, ++ [1][1][5][15] = 46, ++ [1][1][6][15] = 22, ++ [1][1][9][15] = 22, ++ [1][1][8][15] = 42, ++ [1][1][11][15] = 22, ++ [1][1][2][17] = 46, ++ [1][1][1][17] = 22, ++ [1][1][3][17] = 46, ++ [1][1][5][17] = 46, ++ [1][1][6][17] = 22, ++ [1][1][9][17] = 22, ++ [1][1][8][17] = 42, ++ [1][1][11][17] = 22, ++ [1][1][2][19] = 46, ++ [1][1][1][19] = 22, ++ [1][1][3][19] = 46, ++ [1][1][5][19] = 46, ++ [1][1][6][19] = 22, ++ [1][1][9][19] = 22, ++ [1][1][8][19] = 42, ++ [1][1][11][19] = 22, ++ [1][1][2][21] = 46, ++ [1][1][1][21] = 22, ++ [1][1][3][21] = 46, ++ [1][1][5][21] = 46, ++ [1][1][6][21] = 22, ++ [1][1][9][21] = 22, ++ [1][1][8][21] = 42, ++ [1][1][11][21] = 22, ++ [1][1][2][23] = 46, ++ [1][1][1][23] = 22, ++ [1][1][3][23] = 46, ++ [1][1][5][23] = 46, ++ [1][1][6][23] = 22, ++ [1][1][9][23] = 22, ++ [1][1][8][23] = 42, ++ [1][1][11][23] = 22, ++ [1][1][2][25] = 46, ++ [1][1][1][25] = 22, ++ [1][1][3][25] = 46, ++ [1][1][5][25] = 127, ++ [1][1][6][25] = 22, ++ [1][1][9][25] = 127, ++ [1][1][8][25] = 42, ++ [1][1][11][25] = 22, ++ [1][1][2][27] = 46, ++ [1][1][1][27] = 22, ++ [1][1][3][27] = 46, ++ [1][1][5][27] = 127, ++ [1][1][6][27] = 22, ++ [1][1][9][27] = 127, ++ [1][1][8][27] = 42, ++ [1][1][11][27] = 22, ++ [1][1][2][29] = 46, ++ [1][1][1][29] = 22, ++ [1][1][3][29] = 46, ++ [1][1][5][29] = 127, ++ [1][1][6][29] = 22, ++ [1][1][9][29] = 127, ++ [1][1][8][29] = 42, ++ [1][1][11][29] = 22, ++ [1][1][2][31] = 46, ++ [1][1][1][31] = 22, ++ [1][1][3][31] = 46, ++ [1][1][5][31] = 46, ++ [1][1][6][31] = 22, ++ [1][1][9][31] = 22, ++ [1][1][8][31] = 42, ++ [1][1][11][31] = 22, ++ [1][1][2][33] = 46, ++ [1][1][1][33] = 22, ++ [1][1][3][33] = 46, ++ [1][1][5][33] = 46, ++ [1][1][6][33] = 22, ++ [1][1][9][33] = 22, ++ [1][1][8][33] = 42, ++ [1][1][11][33] = 22, ++ [1][1][2][35] = 46, ++ [1][1][1][35] = 22, ++ [1][1][3][35] = 46, ++ [1][1][5][35] = 46, ++ [1][1][6][35] = 22, ++ [1][1][9][35] = 22, ++ [1][1][8][35] = 42, ++ [1][1][11][35] = 22, ++ [1][1][2][37] = 46, ++ [1][1][1][37] = 127, ++ [1][1][3][37] = 46, ++ [1][1][5][37] = 46, ++ [1][1][6][37] = 22, ++ [1][1][9][37] = 50, ++ [1][1][8][37] = 42, ++ [1][1][11][37] = 127, ++ [1][1][2][38] = 74, ++ [1][1][1][38] = 16, ++ [1][1][3][38] = 127, ++ [1][1][5][38] = 74, ++ [1][1][6][38] = 16, ++ [1][1][9][38] = 76, ++ [1][1][8][38] = 42, ++ [1][1][11][38] = 16, ++ [1][1][2][40] = 76, ++ [1][1][1][40] = 16, ++ [1][1][3][40] = 127, ++ [1][1][5][40] = 76, ++ [1][1][6][40] = 16, ++ [1][1][9][40] = 76, ++ [1][1][8][40] = 42, ++ [1][1][11][40] = 16, ++ [1][1][2][42] = 76, ++ [1][1][1][42] = 16, ++ [1][1][3][42] = 127, ++ [1][1][5][42] = 76, ++ [1][1][6][42] = 16, ++ [1][1][9][42] = 76, ++ [1][1][8][42] = 42, ++ [1][1][11][42] = 16, ++ [1][1][2][44] = 76, ++ [1][1][1][44] = 16, ++ [1][1][3][44] = 127, ++ [1][1][5][44] = 76, ++ [1][1][6][44] = 16, ++ [1][1][9][44] = 76, ++ [1][1][8][44] = 42, ++ [1][1][11][44] = 16, ++ [1][1][2][46] = 76, ++ [1][1][1][46] = 16, ++ [1][1][3][46] = 127, ++ [1][1][5][46] = 76, ++ [1][1][6][46] = 16, ++ [1][1][9][46] = 76, ++ [1][1][8][46] = 42, ++ [1][1][11][46] = 16, ++ [2][0][2][0] = 74, ++ [2][0][1][0] = 46, ++ [2][0][3][0] = 50, ++ [2][0][5][0] = 46, ++ [2][0][6][0] = 46, ++ [2][0][9][0] = 46, ++ [2][0][8][0] = 30, ++ [2][0][11][0] = 46, ++ [2][0][2][2] = 74, ++ [2][0][1][2] = 46, ++ [2][0][3][2] = 50, ++ [2][0][5][2] = 46, ++ [2][0][6][2] = 46, ++ [2][0][9][2] = 46, ++ [2][0][8][2] = 30, ++ [2][0][11][2] = 46, ++ [2][0][2][4] = 74, ++ [2][0][1][4] = 46, ++ [2][0][3][4] = 50, ++ [2][0][5][4] = 46, ++ [2][0][6][4] = 46, ++ [2][0][9][4] = 46, ++ [2][0][8][4] = 30, ++ [2][0][11][4] = 46, ++ [2][0][2][6] = 74, ++ [2][0][1][6] = 46, ++ [2][0][3][6] = 50, ++ [2][0][5][6] = 46, ++ [2][0][6][6] = 46, ++ [2][0][9][6] = 46, ++ [2][0][8][6] = 30, ++ [2][0][11][6] = 46, ++ [2][0][2][8] = 74, ++ [2][0][1][8] = 46, ++ [2][0][3][8] = 50, ++ [2][0][5][8] = 66, ++ [2][0][6][8] = 46, ++ [2][0][9][8] = 46, ++ [2][0][8][8] = 54, ++ [2][0][11][8] = 46, ++ [2][0][2][10] = 74, ++ [2][0][1][10] = 46, ++ [2][0][3][10] = 50, ++ [2][0][5][10] = 66, ++ [2][0][6][10] = 46, ++ [2][0][9][10] = 46, ++ [2][0][8][10] = 54, ++ [2][0][11][10] = 46, ++ [2][0][2][12] = 74, ++ [2][0][1][12] = 46, ++ [2][0][3][12] = 50, ++ [2][0][5][12] = 66, ++ [2][0][6][12] = 46, ++ [2][0][9][12] = 46, ++ [2][0][8][12] = 54, ++ [2][0][11][12] = 46, ++ [2][0][2][14] = 74, ++ [2][0][1][14] = 46, ++ [2][0][3][14] = 50, ++ [2][0][5][14] = 66, ++ [2][0][6][14] = 46, ++ [2][0][9][14] = 46, ++ [2][0][8][14] = 54, ++ [2][0][11][14] = 46, ++ [2][0][2][15] = 74, ++ [2][0][1][15] = 46, ++ [2][0][3][15] = 70, ++ [2][0][5][15] = 74, ++ [2][0][6][15] = 46, ++ [2][0][9][15] = 46, ++ [2][0][8][15] = 54, ++ [2][0][11][15] = 46, ++ [2][0][2][17] = 74, ++ [2][0][1][17] = 46, ++ [2][0][3][17] = 70, ++ [2][0][5][17] = 74, ++ [2][0][6][17] = 46, ++ [2][0][9][17] = 46, ++ [2][0][8][17] = 54, ++ [2][0][11][17] = 46, ++ [2][0][2][19] = 74, ++ [2][0][1][19] = 46, ++ [2][0][3][19] = 70, ++ [2][0][5][19] = 74, ++ [2][0][6][19] = 46, ++ [2][0][9][19] = 46, ++ [2][0][8][19] = 54, ++ [2][0][11][19] = 46, ++ [2][0][2][21] = 74, ++ [2][0][1][21] = 46, ++ [2][0][3][21] = 70, ++ [2][0][5][21] = 74, ++ [2][0][6][21] = 46, ++ [2][0][9][21] = 46, ++ [2][0][8][21] = 54, ++ [2][0][11][21] = 46, ++ [2][0][2][23] = 74, ++ [2][0][1][23] = 46, ++ [2][0][3][23] = 70, ++ [2][0][5][23] = 74, ++ [2][0][6][23] = 46, ++ [2][0][9][23] = 46, ++ [2][0][8][23] = 54, ++ [2][0][11][23] = 46, ++ [2][0][2][25] = 74, ++ [2][0][1][25] = 46, ++ [2][0][3][25] = 70, ++ [2][0][5][25] = 127, ++ [2][0][6][25] = 46, ++ [2][0][9][25] = 127, ++ [2][0][8][25] = 54, ++ [2][0][11][25] = 46, ++ [2][0][2][27] = 74, ++ [2][0][1][27] = 46, ++ [2][0][3][27] = 70, ++ [2][0][5][27] = 127, ++ [2][0][6][27] = 46, ++ [2][0][9][27] = 127, ++ [2][0][8][27] = 54, ++ [2][0][11][27] = 46, ++ [2][0][2][29] = 74, ++ [2][0][1][29] = 46, ++ [2][0][3][29] = 70, ++ [2][0][5][29] = 127, ++ [2][0][6][29] = 46, ++ [2][0][9][29] = 127, ++ [2][0][8][29] = 54, ++ [2][0][11][29] = 46, ++ [2][0][2][31] = 74, ++ [2][0][1][31] = 46, ++ [2][0][3][31] = 70, ++ [2][0][5][31] = 74, ++ [2][0][6][31] = 46, ++ [2][0][9][31] = 46, ++ [2][0][8][31] = 54, ++ [2][0][11][31] = 46, ++ [2][0][2][33] = 74, ++ [2][0][1][33] = 46, ++ [2][0][3][33] = 70, ++ [2][0][5][33] = 74, ++ [2][0][6][33] = 46, ++ [2][0][9][33] = 46, ++ [2][0][8][33] = 54, ++ [2][0][11][33] = 46, ++ [2][0][2][35] = 74, ++ [2][0][1][35] = 46, ++ [2][0][3][35] = 70, ++ [2][0][5][35] = 74, ++ [2][0][6][35] = 46, ++ [2][0][9][35] = 46, ++ [2][0][8][35] = 54, ++ [2][0][11][35] = 46, ++ [2][0][2][37] = 74, ++ [2][0][1][37] = 127, ++ [2][0][3][37] = 70, ++ [2][0][5][37] = 74, ++ [2][0][6][37] = 46, ++ [2][0][9][37] = 74, ++ [2][0][8][37] = 54, ++ [2][0][11][37] = 127, ++ [2][0][2][38] = 76, ++ [2][0][1][38] = 28, ++ [2][0][3][38] = 127, ++ [2][0][5][38] = 76, ++ [2][0][6][38] = 28, ++ [2][0][9][38] = 76, ++ [2][0][8][38] = 54, ++ [2][0][11][38] = 28, ++ [2][0][2][40] = 76, ++ [2][0][1][40] = 28, ++ [2][0][3][40] = 127, ++ [2][0][5][40] = 76, ++ [2][0][6][40] = 28, ++ [2][0][9][40] = 76, ++ [2][0][8][40] = 54, ++ [2][0][11][40] = 28, ++ [2][0][2][42] = 76, ++ [2][0][1][42] = 28, ++ [2][0][3][42] = 127, ++ [2][0][5][42] = 76, ++ [2][0][6][42] = 28, ++ [2][0][9][42] = 76, ++ [2][0][8][42] = 54, ++ [2][0][11][42] = 28, ++ [2][0][2][44] = 76, ++ [2][0][1][44] = 28, ++ [2][0][3][44] = 127, ++ [2][0][5][44] = 76, ++ [2][0][6][44] = 28, ++ [2][0][9][44] = 76, ++ [2][0][8][44] = 54, ++ [2][0][11][44] = 28, ++ [2][0][2][46] = 76, ++ [2][0][1][46] = 28, ++ [2][0][3][46] = 127, ++ [2][0][5][46] = 76, ++ [2][0][6][46] = 28, ++ [2][0][9][46] = 76, ++ [2][0][8][46] = 54, ++ [2][0][11][46] = 28, ++ [2][1][2][0] = 58, ++ [2][1][1][0] = 32, ++ [2][1][3][0] = 38, ++ [2][1][5][0] = 30, ++ [2][1][6][0] = 32, ++ [2][1][9][0] = 32, ++ [2][1][8][0] = 18, ++ [2][1][11][0] = 32, ++ [2][1][2][2] = 58, ++ [2][1][1][2] = 32, ++ [2][1][3][2] = 38, ++ [2][1][5][2] = 30, ++ [2][1][6][2] = 32, ++ [2][1][9][2] = 32, ++ [2][1][8][2] = 18, ++ [2][1][11][2] = 32, ++ [2][1][2][4] = 58, ++ [2][1][1][4] = 32, ++ [2][1][3][4] = 38, ++ [2][1][5][4] = 30, ++ [2][1][6][4] = 32, ++ [2][1][9][4] = 32, ++ [2][1][8][4] = 18, ++ [2][1][11][4] = 32, ++ [2][1][2][6] = 58, ++ [2][1][1][6] = 32, ++ [2][1][3][6] = 38, ++ [2][1][5][6] = 30, ++ [2][1][6][6] = 32, ++ [2][1][9][6] = 32, ++ [2][1][8][6] = 18, ++ [2][1][11][6] = 32, ++ [2][1][2][8] = 58, ++ [2][1][1][8] = 32, ++ [2][1][3][8] = 38, ++ [2][1][5][8] = 52, ++ [2][1][6][8] = 32, ++ [2][1][9][8] = 32, ++ [2][1][8][8] = 42, ++ [2][1][11][8] = 32, ++ [2][1][2][10] = 58, ++ [2][1][1][10] = 32, ++ [2][1][3][10] = 38, ++ [2][1][5][10] = 52, ++ [2][1][6][10] = 32, ++ [2][1][9][10] = 32, ++ [2][1][8][10] = 42, ++ [2][1][11][10] = 32, ++ [2][1][2][12] = 58, ++ [2][1][1][12] = 32, ++ [2][1][3][12] = 38, ++ [2][1][5][12] = 52, ++ [2][1][6][12] = 32, ++ [2][1][9][12] = 32, ++ [2][1][8][12] = 42, ++ [2][1][11][12] = 32, ++ [2][1][2][14] = 58, ++ [2][1][1][14] = 32, ++ [2][1][3][14] = 38, ++ [2][1][5][14] = 52, ++ [2][1][6][14] = 32, ++ [2][1][9][14] = 32, ++ [2][1][8][14] = 42, ++ [2][1][11][14] = 32, ++ [2][1][2][15] = 58, ++ [2][1][1][15] = 32, ++ [2][1][3][15] = 58, ++ [2][1][5][15] = 58, ++ [2][1][6][15] = 32, ++ [2][1][9][15] = 32, ++ [2][1][8][15] = 42, ++ [2][1][11][15] = 32, ++ [2][1][2][17] = 58, ++ [2][1][1][17] = 32, ++ [2][1][3][17] = 58, ++ [2][1][5][17] = 58, ++ [2][1][6][17] = 32, ++ [2][1][9][17] = 32, ++ [2][1][8][17] = 42, ++ [2][1][11][17] = 32, ++ [2][1][2][19] = 58, ++ [2][1][1][19] = 32, ++ [2][1][3][19] = 58, ++ [2][1][5][19] = 58, ++ [2][1][6][19] = 32, ++ [2][1][9][19] = 32, ++ [2][1][8][19] = 42, ++ [2][1][11][19] = 32, ++ [2][1][2][21] = 58, ++ [2][1][1][21] = 32, ++ [2][1][3][21] = 58, ++ [2][1][5][21] = 58, ++ [2][1][6][21] = 32, ++ [2][1][9][21] = 32, ++ [2][1][8][21] = 42, ++ [2][1][11][21] = 32, ++ [2][1][2][23] = 58, ++ [2][1][1][23] = 32, ++ [2][1][3][23] = 58, ++ [2][1][5][23] = 58, ++ [2][1][6][23] = 32, ++ [2][1][9][23] = 32, ++ [2][1][8][23] = 42, ++ [2][1][11][23] = 32, ++ [2][1][2][25] = 58, ++ [2][1][1][25] = 32, ++ [2][1][3][25] = 58, ++ [2][1][5][25] = 127, ++ [2][1][6][25] = 32, ++ [2][1][9][25] = 127, ++ [2][1][8][25] = 42, ++ [2][1][11][25] = 32, ++ [2][1][2][27] = 58, ++ [2][1][1][27] = 32, ++ [2][1][3][27] = 58, ++ [2][1][5][27] = 127, ++ [2][1][6][27] = 32, ++ [2][1][9][27] = 127, ++ [2][1][8][27] = 42, ++ [2][1][11][27] = 32, ++ [2][1][2][29] = 58, ++ [2][1][1][29] = 32, ++ [2][1][3][29] = 58, ++ [2][1][5][29] = 127, ++ [2][1][6][29] = 32, ++ [2][1][9][29] = 127, ++ [2][1][8][29] = 42, ++ [2][1][11][29] = 32, ++ [2][1][2][31] = 58, ++ [2][1][1][31] = 32, ++ [2][1][3][31] = 58, ++ [2][1][5][31] = 58, ++ [2][1][6][31] = 32, ++ [2][1][9][31] = 32, ++ [2][1][8][31] = 42, ++ [2][1][11][31] = 32, ++ [2][1][2][33] = 58, ++ [2][1][1][33] = 32, ++ [2][1][3][33] = 58, ++ [2][1][5][33] = 58, ++ [2][1][6][33] = 32, ++ [2][1][9][33] = 32, ++ [2][1][8][33] = 42, ++ [2][1][11][33] = 32, ++ [2][1][2][35] = 58, ++ [2][1][1][35] = 32, ++ [2][1][3][35] = 58, ++ [2][1][5][35] = 58, ++ [2][1][6][35] = 32, ++ [2][1][9][35] = 32, ++ [2][1][8][35] = 42, ++ [2][1][11][35] = 32, ++ [2][1][2][37] = 58, ++ [2][1][1][37] = 127, ++ [2][1][3][37] = 58, ++ [2][1][5][37] = 58, ++ [2][1][6][37] = 32, ++ [2][1][9][37] = 62, ++ [2][1][8][37] = 42, ++ [2][1][11][37] = 127, ++ [2][1][2][38] = 76, ++ [2][1][1][38] = 16, ++ [2][1][3][38] = 127, ++ [2][1][5][38] = 76, ++ [2][1][6][38] = 16, ++ [2][1][9][38] = 76, ++ [2][1][8][38] = 42, ++ [2][1][11][38] = 16, ++ [2][1][2][40] = 76, ++ [2][1][1][40] = 16, ++ [2][1][3][40] = 127, ++ [2][1][5][40] = 76, ++ [2][1][6][40] = 16, ++ [2][1][9][40] = 76, ++ [2][1][8][40] = 42, ++ [2][1][11][40] = 16, ++ [2][1][2][42] = 76, ++ [2][1][1][42] = 16, ++ [2][1][3][42] = 127, ++ [2][1][5][42] = 76, ++ [2][1][6][42] = 16, ++ [2][1][9][42] = 76, ++ [2][1][8][42] = 42, ++ [2][1][11][42] = 16, ++ [2][1][2][44] = 76, ++ [2][1][1][44] = 16, ++ [2][1][3][44] = 127, ++ [2][1][5][44] = 76, ++ [2][1][6][44] = 16, ++ [2][1][9][44] = 76, ++ [2][1][8][44] = 42, ++ [2][1][11][44] = 16, ++ [2][1][2][46] = 76, ++ [2][1][1][46] = 16, ++ [2][1][3][46] = 127, ++ [2][1][5][46] = 76, ++ [2][1][6][46] = 16, ++ [2][1][9][46] = 76, ++ [2][1][8][46] = 42, ++ [2][1][11][46] = 16, ++}; ++ ++#define DECLARE_DIG_TABLE(name) \ ++static const struct rtw89_phy_dig_gain_cfg name##_table = { \ ++ .table = name, \ ++ .size = ARRAY_SIZE(name) \ ++} ++ ++static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = { ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK}, ++ {R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g); ++ ++static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = { ++ {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK}, ++ {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g); ++ ++static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = { ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK}, ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a); ++ ++static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = { ++ {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK}, ++ {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a); ++ ++const struct rtw89_phy_table rtw89_8852a_phy_bb_table = { ++ .regs = rtw89_8852a_phy_bb_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_bb_regs), ++ .rf_path = 0, /* don't care */ ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_radioa_table = { ++ .regs = rtw89_8852a_phy_radioa_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_radioa_regs), ++ .rf_path = RF_PATH_A, ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_radiob_table = { ++ .regs = rtw89_8852a_phy_radiob_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_radiob_regs), ++ .rf_path = RF_PATH_B, ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_nctl_table = { ++ .regs = rtw89_8852a_phy_nctl_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_nctl_regs), ++ .rf_path = 0, /* don't care */ ++}; ++ ++const struct rtw89_txpwr_table rtw89_8852a_byr_table = { ++ .data = rtw89_8852a_txpwr_byrate, ++ .size = ARRAY_SIZE(rtw89_8852a_txpwr_byrate), ++ .load = rtw89_phy_load_txpwr_byrate, ++}; ++ ++const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg = { ++ .delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n, ++ .delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p, ++ .delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n, ++ .delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p, ++ .delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n, ++ .delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p, ++ .delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n, ++ .delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p, ++ .delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n, ++ .delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p, ++ .delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n, ++ .delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p, ++}; ++ ++const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = { ++ .cfg_lna_g = &rtw89_8852a_lna_gain_g_table, ++ .cfg_tia_g = &rtw89_8852a_tia_gain_g_table, ++ .cfg_lna_a = &rtw89_8852a_lna_gain_a_table, ++ .cfg_tia_a = &rtw89_8852a_tia_gain_a_table ++}; + +From patchwork Fri Aug 20 04:35:35 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448395 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id CB2F1C432BE + for ; + Fri, 20 Aug 2021 04:38:00 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id B5A8160EB5 + for ; + Fri, 20 Aug 2021 04:38:00 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S235484AbhHTEig (ORCPT + ); + Fri, 20 Aug 2021 00:38:36 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39298 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233646AbhHTEif (ORCPT + ); + Fri, 20 Aug 2021 00:38:35 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4btKkB004279, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4btKkB004279 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:37:55 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:53 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:53 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 21/24] rtw89: add ser to recover error reported by firmware +Date: Fri, 20 Aug 2021 12:35:35 +0800 +Message-ID: <20210820043538.12424-22-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +SER stands for System Error Recovery. When firmware detects error, it +interrupts driver. Driver read ser event code from register and do ser +processes as following: + +1. driver stop TX +2. driver stop DMA +3. driver stop RX +4. reset TRX variable and counter +5. Inform FW driver reset is finish + FW also resets itself when receiving driver's information +6. Wait FW to confirm reset finish +7. Enable DMA +8. driver resume rx +9. driver resume tx + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/ser.c | 491 +++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/ser.h | 15 + + 2 files changed, 506 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/ser.c + create mode 100644 drivers/net/wireless/realtek/rtw89/ser.h + +diff --git a/drivers/net/wireless/realtek/rtw89/ser.c b/drivers/net/wireless/realtek/rtw89/ser.c +new file mode 100644 +index 000000000000..837cdc366a61 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ser.c +@@ -0,0 +1,491 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "mac.h" ++#include "ps.h" ++#include "ser.h" ++#include "util.h" ++ ++#define SER_RECFG_TIMEOUT 1000 ++ ++enum ser_evt { ++ SER_EV_NONE, ++ SER_EV_STATE_IN, ++ SER_EV_STATE_OUT, ++ SER_EV_L1_RESET, /* M1 */ ++ SER_EV_DO_RECOVERY, /* M3 */ ++ SER_EV_MAC_RESET_DONE, /* M5 */ ++ SER_EV_L2_RESET, ++ SER_EV_L2_RECFG_DONE, ++ SER_EV_L2_RECFG_TIMEOUT, ++ SER_EV_M3_TIMEOUT, ++ SER_EV_FW_M5_TIMEOUT, ++ SER_EV_L0_RESET, ++ SER_EV_MAXX ++}; ++ ++enum ser_state { ++ SER_IDLE_ST, ++ SER_RESET_TRX_ST, ++ SER_DO_HCI_ST, ++ SER_L2_RESET_ST, ++ SER_ST_MAX_ST ++}; ++ ++struct ser_msg { ++ struct list_head list; ++ u8 event; ++}; ++ ++struct state_ent { ++ u8 state; ++ char *name; ++ void (*st_func)(struct rtw89_ser *ser, u8 event); ++}; ++ ++struct event_ent { ++ u8 event; ++ char *name; ++}; ++ ++static char *ser_ev_name(struct rtw89_ser *ser, u8 event) ++{ ++ if (event < SER_EV_MAXX) ++ return ser->ev_tbl[event].name; ++ ++ return "err_ev_name"; ++} ++ ++static char *ser_st_name(struct rtw89_ser *ser) ++{ ++ if (ser->state < SER_ST_MAX_ST) ++ return ser->st_tbl[ser->state].name; ++ ++ return "err_st_name"; ++} ++ ++static void ser_state_run(struct rtw89_ser *ser, u8 evt) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s receive %s\n", ++ ser_st_name(ser), ser_ev_name(ser, evt)); ++ ++ rtw89_leave_lps(rtwdev); ++ ser->st_tbl[ser->state].st_func(ser, evt); ++} ++ ++static void ser_state_goto(struct rtw89_ser *ser, u8 new_state) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (ser->state == new_state || new_state >= SER_ST_MAX_ST) ++ return; ++ ser_state_run(ser, SER_EV_STATE_OUT); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s goto -> %s\n", ++ ser_st_name(ser), ser->st_tbl[new_state].name); ++ ++ ser->state = new_state; ++ ser_state_run(ser, SER_EV_STATE_IN); ++} ++ ++static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser) ++{ ++ struct ser_msg *msg; ++ ++ spin_lock_irq(&ser->msg_q_lock); ++ msg = list_first_entry_or_null(&ser->msg_q, struct ser_msg, list); ++ if (msg) ++ list_del(&msg->list); ++ spin_unlock_irq(&ser->msg_q_lock); ++ ++ return msg; ++} ++ ++static void rtw89_ser_hdl_work(struct work_struct *work) ++{ ++ struct ser_msg *msg; ++ struct rtw89_ser *ser = container_of(work, struct rtw89_ser, ++ ser_hdl_work); ++ ++ while ((msg = __rtw89_ser_dequeue_msg(ser))) { ++ ser_state_run(ser, msg->event); ++ kfree(msg); ++ } ++} ++ ++static int ser_send_msg(struct rtw89_ser *ser, u8 event) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ struct ser_msg *msg = NULL; ++ ++ if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) ++ return -EIO; ++ ++ msg = kmalloc(sizeof(*msg), GFP_ATOMIC); ++ if (!msg) ++ return -ENOMEM; ++ ++ msg->event = event; ++ ++ spin_lock_irq(&ser->msg_q_lock); ++ list_add(&msg->list, &ser->msg_q); ++ spin_unlock_irq(&ser->msg_q_lock); ++ ++ ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work); ++ return 0; ++} ++ ++static void rtw89_ser_alarm_work(struct work_struct *work) ++{ ++ struct rtw89_ser *ser = container_of(work, struct rtw89_ser, ++ ser_alarm_work.work); ++ ++ ser_send_msg(ser, ser->alarm_event); ++ ser->alarm_event = SER_EV_NONE; ++} ++ ++static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) ++ return; ++ ++ ser->alarm_event = event; ++ ieee80211_queue_delayed_work(rtwdev->hw, &ser->ser_alarm_work, ++ msecs_to_jiffies(ms)); ++} ++ ++static void ser_del_alarm(struct rtw89_ser *ser) ++{ ++ cancel_delayed_work(&ser->ser_alarm_work); ++ ser->alarm_event = SER_EV_NONE; ++} ++ ++/* driver function */ ++static void drv_stop_tx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ ieee80211_stop_queues(rtwdev->hw); ++ set_bit(RTW89_SER_DRV_STOP_TX, ser->flags); ++} ++ ++static void drv_stop_rx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ set_bit(RTW89_SER_DRV_STOP_RX, ser->flags); ++} ++ ++static void drv_trx_reset(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_hci_reset(rtwdev); ++} ++ ++static void drv_resume_tx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (!test_bit(RTW89_SER_DRV_STOP_TX, ser->flags)) ++ return; ++ ++ ieee80211_wake_queues(rtwdev->hw); ++ clear_bit(RTW89_SER_DRV_STOP_TX, ser->flags); ++} ++ ++static void drv_resume_rx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (!test_bit(RTW89_SER_DRV_STOP_RX, ser->flags)) ++ return; ++ ++ set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ clear_bit(RTW89_SER_DRV_STOP_RX, ser->flags); ++} ++ ++static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; ++ rtwvif->trigger = false; ++} ++ ++static void ser_reset_mac_binding(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ rtw89_cam_reset_keys(rtwdev); ++ rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM); ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ ser_reset_vif(rtwdev, rtwvif); ++} ++ ++/* hal function */ ++static int hal_enable_dma(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ int ret; ++ ++ if (!test_bit(RTW89_SER_HAL_STOP_DMA, ser->flags)) ++ return 0; ++ ++ if (!rtwdev->hci.ops->mac_lv1_rcvy) ++ return -EIO; ++ ++ ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_2); ++ if (!ret) ++ clear_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); ++ ++ return ret; ++} ++ ++static int hal_stop_dma(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ int ret; ++ ++ if (!rtwdev->hci.ops->mac_lv1_rcvy) ++ return -EIO; ++ ++ ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_1); ++ if (!ret) ++ set_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); ++ ++ return ret; ++} ++ ++static void hal_send_m2_event(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_DISABLE_EN); ++} ++ ++static void hal_send_m4_event(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN); ++} ++ ++/* state handler */ ++static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ break; ++ case SER_EV_L1_RESET: ++ ser_state_goto(ser, SER_RESET_TRX_ST); ++ break; ++ case SER_EV_L2_RESET: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ case SER_EV_STATE_OUT: ++ default: ++ break; ++ } ++} ++ ++static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ drv_stop_tx(ser); ++ ++ if (hal_stop_dma(ser)) { ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ } ++ ++ drv_stop_rx(ser); ++ drv_trx_reset(ser); ++ ++ /* wait m3 */ ++ hal_send_m2_event(ser); ++ ++ /* set alarm to prevent FW response timeout */ ++ ser_set_alarm(ser, 1000, SER_EV_M3_TIMEOUT); ++ break; ++ ++ case SER_EV_DO_RECOVERY: ++ ser_state_goto(ser, SER_DO_HCI_ST); ++ break; ++ ++ case SER_EV_M3_TIMEOUT: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ hal_enable_dma(ser); ++ drv_resume_rx(ser); ++ drv_resume_tx(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ /* wait m5 */ ++ hal_send_m4_event(ser); ++ ++ /* prevent FW response timeout */ ++ ser_set_alarm(ser, 1000, SER_EV_FW_M5_TIMEOUT); ++ break; ++ ++ case SER_EV_FW_M5_TIMEOUT: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ ++ case SER_EV_MAC_RESET_DONE: ++ ser_state_goto(ser, SER_IDLE_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ mutex_lock(&rtwdev->mutex); ++ ser_reset_mac_binding(rtwdev); ++ rtw89_core_stop(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++ ++ ieee80211_restart_hw(rtwdev->hw); ++ ser_set_alarm(ser, SER_RECFG_TIMEOUT, SER_EV_L2_RECFG_TIMEOUT); ++ break; ++ ++ case SER_EV_L2_RECFG_TIMEOUT: ++ rtw89_info(rtwdev, "Err: ser L2 re-config timeout\n"); ++ fallthrough; ++ case SER_EV_L2_RECFG_DONE: ++ ser_state_goto(ser, SER_IDLE_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static struct event_ent ser_ev_tbl[] = { ++ {SER_EV_NONE, "SER_EV_NONE"}, ++ {SER_EV_STATE_IN, "SER_EV_STATE_IN"}, ++ {SER_EV_STATE_OUT, "SER_EV_STATE_OUT"}, ++ {SER_EV_L1_RESET, "SER_EV_L1_RESET"}, ++ {SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"}, ++ {SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"}, ++ {SER_EV_L2_RESET, "SER_EV_L2_RESET"}, ++ {SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"}, ++ {SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"}, ++ {SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"}, ++ {SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"}, ++ {SER_EV_L0_RESET, "SER_EV_L0_RESET"}, ++ {SER_EV_MAXX, "SER_EV_MAX"} ++}; ++ ++static struct state_ent ser_st_tbl[] = { ++ {SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl}, ++ {SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl}, ++ {SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl}, ++ {SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl} ++}; ++ ++int rtw89_ser_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_ser *ser = &rtwdev->ser; ++ ++ memset(ser, 0, sizeof(*ser)); ++ INIT_LIST_HEAD(&ser->msg_q); ++ ser->state = SER_IDLE_ST; ++ ser->st_tbl = ser_st_tbl; ++ ser->ev_tbl = ser_ev_tbl; ++ ++ bitmap_zero(ser->flags, RTW89_NUM_OF_SER_FLAGS); ++ spin_lock_init(&ser->msg_q_lock); ++ INIT_WORK(&ser->ser_hdl_work, rtw89_ser_hdl_work); ++ INIT_DELAYED_WORK(&ser->ser_alarm_work, rtw89_ser_alarm_work); ++ return 0; ++} ++ ++int rtw89_ser_deinit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_ser *ser = (struct rtw89_ser *)&rtwdev->ser; ++ ++ set_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); ++ cancel_delayed_work_sync(&ser->ser_alarm_work); ++ cancel_work_sync(&ser->ser_hdl_work); ++ clear_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); ++ return 0; ++} ++ ++void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev) ++{ ++ ser_send_msg(&rtwdev->ser, SER_EV_L2_RECFG_DONE); ++} ++ ++int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err) ++{ ++ u8 event = SER_EV_NONE; ++ ++ rtw89_info(rtwdev, "ser event = 0x%04x\n", err); ++ ++ switch (err) { ++ case MAC_AX_ERR_L1_ERR_DMAC: ++ case MAC_AX_ERR_L0_PROMOTE_TO_L1: ++ event = SER_EV_L1_RESET; /* M1 */ ++ break; ++ case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE: ++ event = SER_EV_DO_RECOVERY; /* M3 */ ++ break; ++ case MAC_AX_ERR_L1_RESET_RECOVERY_DONE: ++ event = SER_EV_MAC_RESET_DONE; /* M5 */ ++ break; ++ case MAC_AX_ERR_L0_ERR_CMAC0: ++ case MAC_AX_ERR_L0_ERR_CMAC1: ++ case MAC_AX_ERR_L0_RESET_DONE: ++ event = SER_EV_L0_RESET; ++ break; ++ default: ++ if (err == MAC_AX_ERR_L1_PROMOTE_TO_L2 || ++ (err >= MAC_AX_ERR_L2_ERR_AH_DMA && ++ err <= MAC_AX_GET_ERR_MAX)) ++ event = SER_EV_L2_RESET; ++ break; ++ } ++ ++ if (event == SER_EV_NONE) ++ return -EINVAL; ++ ++ ser_send_msg(&rtwdev->ser, event); ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_ser_notify); +diff --git a/drivers/net/wireless/realtek/rtw89/ser.h b/drivers/net/wireless/realtek/rtw89/ser.h +new file mode 100644 +index 000000000000..6b8e62019942 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ser.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ * Copyright(c) 2019-2020 Realtek Corporation ++ */ ++#ifndef __SER_H__ ++#define __SER_H__ ++ ++#include "core.h" ++ ++int rtw89_ser_init(struct rtw89_dev *rtwdev); ++int rtw89_ser_deinit(struct rtw89_dev *rtwdev); ++int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err); ++void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev); ++ ++#endif /* __SER_H__*/ ++ + +From patchwork Fri Aug 20 04:35:36 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448397 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 1B5E5C432BE + for ; + Fri, 20 Aug 2021 04:38:05 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id F1DC460F91 + for ; + Fri, 20 Aug 2021 04:38:04 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S235156AbhHTEil (ORCPT + ); + Fri, 20 Aug 2021 00:38:41 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39301 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S233646AbhHTEik (ORCPT + ); + Fri, 20 Aug 2021 00:38:40 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4c02m9004290, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4c02m9004290 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:38:00 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:37:59 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:37:59 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 22/24] rtw89: add PS files +Date: Fri, 20 Aug 2021 12:35:36 +0800 +Message-ID: <20210820043538.12424-23-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_all_Bitcoin, bb} +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + realtek.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +Power saving contains two main types -- IPS (idle PS) and LPS (Leisure PS). +If there's no any connection, wifi can enter IPS mode that power +consumption is the lowest. After connecting to an AP, it can only wake up +at TBTT to receive beacon to check if AP is buffering any packets; this +case is called LPS mode that the average power is low, but peak appears +at TBTT. With heavy traffic, no power saving mechanism operates, and it +costs high power in this case. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/ps.c | 154 ++++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/ps.h | 16 +++ + 2 files changed, 170 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/ps.c + create mode 100644 drivers/net/wireless/realtek/rtw89/ps.h + +diff --git a/drivers/net/wireless/realtek/rtw89/ps.c b/drivers/net/wireless/realtek/rtw89/ps.c +new file mode 100644 +index 000000000000..5cde9276ac82 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ps.c +@@ -0,0 +1,154 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "core.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "util.h" ++ ++static int rtw89_fw_leave_lps_check(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ u32 pwr_en_bit = 0xE; ++ u32 chk_msk = pwr_en_bit << (4 * macid); ++ u32 polling; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(rtw89_read32_mask, polling, !polling, ++ 1000, 50000, false, rtwdev, ++ R_AX_PPWRBIT_SETTING, chk_msk); ++ if (ret) { ++ rtw89_info(rtwdev, "rtw89: failed to leave lps state\n"); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ if (!rtwdev->ps_mode) ++ return; ++ ++ if (test_and_set_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) ++ return; ++ ++ rtw89_mac_power_mode_change(rtwdev, true); ++} ++ ++void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ if (!rtwdev->ps_mode) ++ return; ++ ++ if (test_and_clear_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) ++ rtw89_mac_power_mode_change(rtwdev, false); ++} ++ ++static void __rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ struct rtw89_lps_parm lps_param = { ++ .macid = mac_id, ++ .psmode = RTW89_MAC_AX_PS_MODE_LEGACY, ++ .lastrpwm = RTW89_LAST_RPWM_PS, ++ }; ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_FW_CTRL); ++ rtw89_fw_h2c_lps_parm(rtwdev, &lps_param); ++} ++ ++static void __rtw89_leave_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ struct rtw89_lps_parm lps_param = { ++ .macid = mac_id, ++ .psmode = RTW89_MAC_AX_PS_MODE_ACTIVE, ++ .lastrpwm = RTW89_LAST_RPWM_ACTIVE, ++ }; ++ ++ rtw89_fw_h2c_lps_parm(rtwdev, &lps_param); ++ rtw89_fw_leave_lps_check(rtwdev, 0); ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); ++} ++ ++void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ __rtw89_leave_ps_mode(rtwdev); ++} ++ ++void rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (test_and_set_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) ++ return; ++ ++ __rtw89_enter_lps(rtwdev, mac_id); ++ __rtw89_enter_ps_mode(rtwdev); ++ rtw89_hci_link_ps(rtwdev, true); ++} ++ ++static void rtw89_leave_lps_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) ++ return; ++ ++ __rtw89_leave_ps_mode(rtwdev); ++ __rtw89_leave_lps(rtwdev, rtwvif->mac_id); ++} ++ ++void rtw89_leave_lps(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (!test_and_clear_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) ++ return; ++ ++ rtw89_hci_link_ps(rtwdev, false); ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_leave_lps_vif(rtwdev, rtwvif); ++} ++ ++void rtw89_enter_ips(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ set_bit(RTW89_FLAG_INACTIVE_PS, rtwdev->flags); ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_vif_deinit(rtwdev, rtwvif); ++ ++ rtw89_core_stop(rtwdev); ++ rtw89_hci_link_ps(rtwdev, true); ++} ++ ++void rtw89_leave_ips(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ int ret; ++ ++ rtw89_hci_link_ps(rtwdev, false); ++ ret = rtw89_core_start(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "failed to leave idle state\n"); ++ ++ rtw89_set_channel(rtwdev); ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_vif_init(rtwdev, rtwvif); ++ ++ clear_bit(RTW89_FLAG_INACTIVE_PS, rtwdev->flags); ++} ++ ++void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl) ++{ ++ if (btc_ctrl) ++ rtw89_leave_lps(rtwdev); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/ps.h b/drivers/net/wireless/realtek/rtw89/ps.h +new file mode 100644 +index 000000000000..a184b68994aa +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ps.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PS_H_ ++#define __RTW89_PS_H_ ++ ++void rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id); ++void rtw89_leave_lps(struct rtw89_dev *rtwdev); ++void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev); ++void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev); ++void rtw89_enter_ips(struct rtw89_dev *rtwdev); ++void rtw89_leave_ips(struct rtw89_dev *rtwdev); ++void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl); ++ ++#endif + +From patchwork Fri Aug 20 04:35:37 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448399 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id ECE83C432BE + for ; + Fri, 20 Aug 2021 04:38:10 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id D034160EB5 + for ; + Fri, 20 Aug 2021 04:38:10 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S237795AbhHTEiq (ORCPT + ); + Fri, 20 Aug 2021 00:38:46 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39307 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S236436AbhHTEio (ORCPT + ); + Fri, 20 Aug 2021 00:38:44 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4c32h9004298, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (smtpsrv.realtek.com[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4c32h9004298 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:38:03 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:38:03 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:38:02 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 23/24] rtw89: add SAR files +Date: Fri, 20 Aug 2021 12:35:37 +0800 +Message-ID: <20210820043538.12424-24-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;127.0.0.199:7.1.2;realtek.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +SAR stands for specific absorption rate. Driver controls TX power to follow +the regulation of SAR. + +Signed-off-by: Ping-Ke Shih +--- + drivers/net/wireless/realtek/rtw89/sar.c | 190 +++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/sar.h | 26 ++++ + 2 files changed, 216 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/sar.c + create mode 100644 drivers/net/wireless/realtek/rtw89/sar.h + +diff --git a/drivers/net/wireless/realtek/rtw89/sar.c b/drivers/net/wireless/realtek/rtw89/sar.c +new file mode 100644 +index 000000000000..097c87899cea +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/sar.c +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "sar.h" ++ ++static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, s32 *cfg) ++{ ++ struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common; ++ enum rtw89_subband subband = rtwdev->hal.current_subband; ++ ++ if (!rtwsar->set[subband]) ++ return -ENODATA; ++ ++ *cfg = rtwsar->cfg[subband]; ++ return 0; ++} ++ ++static const ++struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = { ++ [RTW89_SAR_SOURCE_COMMON] = { ++ .descr_sar_source = "RTW89_SAR_SOURCE_COMMON", ++ .txpwr_factor_sar = 2, ++ .query_sar_config = rtw89_query_sar_config_common, ++ }, ++}; ++ ++#define rtw89_sar_set_src(_dev, _src, _cfg_name, _cfg_data) \ ++ do { \ ++ typeof(_src) _s = (_src); \ ++ typeof(_dev) _d = (_dev); \ ++ BUILD_BUG_ON(!rtw89_sar_handlers[_s].descr_sar_source); \ ++ BUILD_BUG_ON(!rtw89_sar_handlers[_s].query_sar_config); \ ++ lockdep_assert_held(&_d->mutex); \ ++ _d->sar._cfg_name = *(_cfg_data); \ ++ _d->sar.src = _s; \ ++ } while (0) ++ ++static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg) ++{ ++ const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; ++ s32 cfg_mac; ++ ++ cfg_mac = fct > fct_mac ? ++ cfg >> (fct - fct_mac) : cfg << (fct_mac - fct); ++ ++ return (s8)clamp_t(s32, cfg_mac, ++ RTW89_SAR_TXPWR_MAC_MIN, ++ RTW89_SAR_TXPWR_MAC_MAX); ++} ++ ++s8 rtw89_query_sar(struct rtw89_dev *rtwdev) ++{ ++ const enum rtw89_sar_sources src = rtwdev->sar.src; ++ /* its members are protected by rtw89_sar_set_src() */ ++ const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; ++ int ret; ++ s32 cfg; ++ u8 fct; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (src == RTW89_SAR_SOURCE_NONE) ++ return RTW89_SAR_TXPWR_MAC_MAX; ++ ++ ret = sar_hdl->query_sar_config(rtwdev, &cfg); ++ if (ret) ++ return RTW89_SAR_TXPWR_MAC_MAX; ++ ++ fct = sar_hdl->txpwr_factor_sar; ++ ++ return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg); ++} ++ ++void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev) ++{ ++ const enum rtw89_sar_sources src = rtwdev->sar.src; ++ /* its members are protected by rtw89_sar_set_src() */ ++ const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; ++ const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; ++ int ret; ++ s32 cfg; ++ u8 fct; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (src == RTW89_SAR_SOURCE_NONE) { ++ seq_puts(m, "no SAR is applied\n"); ++ return; ++ } ++ ++ seq_printf(m, "source: %d (%s)\n", src, sar_hdl->descr_sar_source); ++ ++ ret = sar_hdl->query_sar_config(rtwdev, &cfg); ++ if (ret) { ++ seq_printf(m, "config: return code: %d\n", ret); ++ seq_printf(m, "assign: max setting: %d (unit: 1/%lu dBm)\n", ++ RTW89_SAR_TXPWR_MAC_MAX, BIT(fct_mac)); ++ return; ++ } ++ ++ fct = sar_hdl->txpwr_factor_sar; ++ ++ seq_printf(m, "config: %d (unit: 1/%lu dBm)\n", cfg, BIT(fct)); ++} ++ ++static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev, ++ const struct rtw89_sar_cfg_common *sar) ++{ ++ enum rtw89_sar_sources src; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ src = rtwdev->sar.src; ++ if (src != RTW89_SAR_SOURCE_NONE && src != RTW89_SAR_SOURCE_COMMON) { ++ rtw89_warn(rtwdev, "SAR source: %d is in use", src); ++ ret = -EBUSY; ++ goto exit; ++ } ++ ++ rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar); ++ rtw89_chip_set_txpwr(rtwdev); ++ ++exit: ++ mutex_unlock(&rtwdev->mutex); ++ return ret; ++} ++ ++static const u8 rtw89_common_sar_subband_map[] = { ++ RTW89_CH_2G, ++ RTW89_CH_5G_BAND_1, ++ RTW89_CH_5G_BAND_3, ++ RTW89_CH_5G_BAND_4, ++}; ++ ++static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = { ++ { .start_freq = 2412, .end_freq = 2484, }, ++ { .start_freq = 5180, .end_freq = 5320, }, ++ { .start_freq = 5500, .end_freq = 5720, }, ++ { .start_freq = 5745, .end_freq = 5825, }, ++}; ++ ++static_assert(ARRAY_SIZE(rtw89_common_sar_subband_map) == ++ ARRAY_SIZE(rtw89_common_sar_freq_ranges)); ++ ++const struct cfg80211_sar_capa rtw89_sar_capa = { ++ .type = NL80211_SAR_TYPE_POWER, ++ .num_freq_ranges = ARRAY_SIZE(rtw89_common_sar_freq_ranges), ++ .freq_ranges = rtw89_common_sar_freq_ranges, ++}; ++ ++int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, ++ const struct cfg80211_sar_specs *sar) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_sar_cfg_common sar_common = {0}; ++ u8 fct; ++ u32 freq_start; ++ u32 freq_end; ++ u32 band; ++ s32 power; ++ u32 i, idx; ++ ++ if (sar->type != NL80211_SAR_TYPE_POWER) ++ return -EINVAL; ++ ++ fct = rtw89_sar_handlers[RTW89_SAR_SOURCE_COMMON].txpwr_factor_sar; ++ ++ for (i = 0; i < sar->num_sub_specs; i++) { ++ idx = sar->sub_specs[i].freq_range_index; ++ if (idx >= ARRAY_SIZE(rtw89_common_sar_freq_ranges)) ++ return -EINVAL; ++ ++ freq_start = rtw89_common_sar_freq_ranges[idx].start_freq; ++ freq_end = rtw89_common_sar_freq_ranges[idx].end_freq; ++ band = rtw89_common_sar_subband_map[idx]; ++ power = sar->sub_specs[i].power; ++ ++ rtw89_info(rtwdev, "On freq %u to %u, ", freq_start, freq_end); ++ rtw89_info(rtwdev, "set SAR power limit %d (unit: 1/%lu dBm)\n", ++ power, BIT(fct)); ++ ++ sar_common.set[band] = true; ++ sar_common.cfg[band] = power; ++ } ++ ++ return rtw89_apply_sar_common(rtwdev, &sar_common); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/sar.h b/drivers/net/wireless/realtek/rtw89/sar.h +new file mode 100644 +index 000000000000..7b5484c84eb1 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/sar.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_SAR_H__ ++#define __RTW89_SAR_H__ ++ ++#include "core.h" ++ ++#define RTW89_SAR_TXPWR_MAC_MAX S8_MAX ++#define RTW89_SAR_TXPWR_MAC_MIN S8_MIN ++ ++struct rtw89_sar_handler { ++ const char *descr_sar_source; ++ u8 txpwr_factor_sar; ++ int (*query_sar_config)(struct rtw89_dev *rtwdev, s32 *cfg); ++}; ++ ++extern const struct cfg80211_sar_capa rtw89_sar_capa; ++ ++s8 rtw89_query_sar(struct rtw89_dev *rtwdev); ++void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev); ++int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, ++ const struct cfg80211_sar_specs *sar); ++ ++#endif + +From patchwork Fri Aug 20 04:35:38 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pkshih +X-Patchwork-Id: 12448405 +X-Patchwork-Delegate: kvalo@adurom.com +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, + HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id AD778C4320A + for ; + Fri, 20 Aug 2021 04:38:12 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 903D860EB5 + for ; + Fri, 20 Aug 2021 04:38:12 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S236436AbhHTEis (ORCPT + ); + Fri, 20 Aug 2021 00:38:48 -0400 +Received: from rtits2.realtek.com ([211.75.126.72]:39312 "EHLO + rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S230007AbhHTEis (ORCPT + ); + Fri, 20 Aug 2021 00:38:48 -0400 +Authenticated-By: +X-SpamFilter-By: ArmorX SpamTrap 5.73 with qID 17K4c7Eh9004321, + This message is accepted by code: ctloc85258 +Received: from mail.realtek.com (rtexh36502.realtek.com.tw[172.21.6.25]) + by rtits2.realtek.com.tw (8.15.2/2.71/5.88) with ESMTPS id + 17K4c7Eh9004321 + (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 + verify=NOT); + Fri, 20 Aug 2021 12:38:07 +0800 +Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by + RTEXH36502.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id + 15.1.2308.14; Fri, 20 Aug 2021 12:38:06 +0800 +Received: from localhost (172.21.69.146) by RTEXMBS04.realtek.com.tw + (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 20 Aug + 2021 12:38:06 +0800 +From: Ping-Ke Shih +To: +CC: +Subject: [PATCH v6 24/24] rtw89: add Kconfig and Makefile +Date: Fri, 20 Aug 2021 12:35:38 +0800 +Message-ID: <20210820043538.12424-25-pkshih@realtek.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210820043538.12424-1-pkshih@realtek.com> +References: <20210820043538.12424-1-pkshih@realtek.com> +MIME-Version: 1.0 +X-Originating-IP: [172.21.69.146] +X-ClientProxiedBy: RTEXMBS02.realtek.com.tw (172.21.6.95) To + RTEXMBS04.realtek.com.tw (172.21.6.97) +X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 +X-KSE-AntiSpam-Interceptor-Info: trusted connection +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Deterministic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +X-KSE-AttachmentFiltering-Interceptor-Info: no applicable attachment filtering + rules found +X-KSE-Antivirus-Interceptor-Info: scan successful +X-KSE-Antivirus-Info: + =?big5_tw?b?Q2xlYW4sIGJhc2VzOiAyMDIxLzgvMjAgpFekyCAwMzow?= + =?big5_tw?b?ODowMA==?= +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-ServerInfo: RTEXH36502.realtek.com.tw, 9 +X-KSE-Attachment-Filter-Triggered-Rules: Clean +X-KSE-Attachment-Filter-Triggered-Filters: Clean +X-KSE-BulkMessagesFiltering-Scan-Result: protection disabled +X-KSE-AntiSpam-Outbound-Interceptor-Info: scan successful +X-KSE-AntiSpam-Version: 5.9.20, Database issued on: 08/20/2021 04:18:54 +X-KSE-AntiSpam-Status: KAS_STATUS_NOT_DETECTED +X-KSE-AntiSpam-Method: none +X-KSE-AntiSpam-Rate: 0 +X-KSE-AntiSpam-Info: Lua profiles 165674 [Aug 20 2021] +X-KSE-AntiSpam-Info: Version: 5.9.20.0 +X-KSE-AntiSpam-Info: Envelope from: pkshih@realtek.com +X-KSE-AntiSpam-Info: LuaCore: 454 454 39c6e442fd417993330528e7f9d13ac1bf7fdf8c +X-KSE-AntiSpam-Info: {Tracking_from_domain_doesnt_match_to} +X-KSE-AntiSpam-Info: + d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;127.0.0.199:7.1.2;realtek.com:7.1.1 +X-KSE-AntiSpam-Info: Rate: 0 +X-KSE-AntiSpam-Info: Status: not_detected +X-KSE-AntiSpam-Info: Method: none +X-KSE-AntiSpam-Info: Auth:dkim=none +X-KSE-Antiphishing-Info: Clean +X-KSE-Antiphishing-ScanningType: Heuristic +X-KSE-Antiphishing-Method: None +X-KSE-Antiphishing-Bases: 08/20/2021 04:22:00 +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org + +With Kconfig and Makefile, we can build rtw89 and support 8852AE chip. + +Signed-off-by: Ping-Ke Shih +Reported-by: kernel test robot +--- + drivers/net/wireless/realtek/Kconfig | 1 + + drivers/net/wireless/realtek/Makefile | 1 + + drivers/net/wireless/realtek/rtw89/Kconfig | 50 +++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/Makefile | 25 +++++++++++ + 4 files changed, 77 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/Kconfig + create mode 100644 drivers/net/wireless/realtek/rtw89/Makefile + +diff --git a/drivers/net/wireless/realtek/Kconfig b/drivers/net/wireless/realtek/Kconfig +index 474843277fa1..4a1f0e64df03 100644 +--- a/drivers/net/wireless/realtek/Kconfig ++++ b/drivers/net/wireless/realtek/Kconfig +@@ -16,5 +16,6 @@ source "drivers/net/wireless/realtek/rtl818x/Kconfig" + source "drivers/net/wireless/realtek/rtlwifi/Kconfig" + source "drivers/net/wireless/realtek/rtl8xxxu/Kconfig" + source "drivers/net/wireless/realtek/rtw88/Kconfig" ++source "drivers/net/wireless/realtek/rtw89/Kconfig" + + endif # WLAN_VENDOR_REALTEK +diff --git a/drivers/net/wireless/realtek/Makefile b/drivers/net/wireless/realtek/Makefile +index 888b5d594e79..ab25419f56c6 100644 +--- a/drivers/net/wireless/realtek/Makefile ++++ b/drivers/net/wireless/realtek/Makefile +@@ -8,4 +8,5 @@ obj-$(CONFIG_RTL8187) += rtl818x/ + obj-$(CONFIG_RTLWIFI) += rtlwifi/ + obj-$(CONFIG_RTL8XXXU) += rtl8xxxu/ + obj-$(CONFIG_RTW88) += rtw88/ ++obj-$(CONFIG_RTW89) += rtw89/ + +diff --git a/drivers/net/wireless/realtek/rtw89/Kconfig b/drivers/net/wireless/realtek/rtw89/Kconfig +new file mode 100644 +index 000000000000..055d45103a4b +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/Kconfig +@@ -0,0 +1,50 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++menuconfig RTW89 ++ tristate "Realtek 802.11ax wireless chips support" ++ depends on MAC80211 ++ help ++ This module adds support for mac80211-based wireless drivers that ++ enables Realtek IEEE 802.11ax wireless chipsets. ++ ++ If you choose to build a module, it'll be called rtw89. ++ ++if RTW89 ++ ++config RTW89_CORE ++ tristate ++ ++config RTW89_PCI ++ tristate ++ ++config RTW89_8852AE ++ tristate "Realtek 8852AE PCI wireless network adapter" ++ depends on PCI ++ select RTW89_CORE ++ select RTW89_PCI ++ help ++ Select this option will enable support for 8852AE chipset ++ ++ 802.11ax PCIe wireless network adapter ++ ++config RTW89_DEBUG ++ bool ++ ++config RTW89_DEBUGMSG ++ bool "Realtek rtw89 debug message support" ++ depends on RTW89_CORE ++ select RTW89_DEBUG ++ help ++ Enable debug message support ++ ++ If unsure, say Y to simplify debug problems ++ ++config RTW89_DEBUGFS ++ bool "Realtek rtw89 debugfs support" ++ depends on RTW89_CORE ++ select RTW89_DEBUG ++ help ++ Enable debugfs support ++ ++ If unsure, say Y to simplify debug problems ++ ++endif +diff --git a/drivers/net/wireless/realtek/rtw89/Makefile b/drivers/net/wireless/realtek/rtw89/Makefile +new file mode 100644 +index 000000000000..077e8fe23f60 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/Makefile +@@ -0,0 +1,25 @@ ++# SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ ++obj-$(CONFIG_RTW89_CORE) += rtw89_core.o ++rtw89_core-y += core.o \ ++ mac80211.o \ ++ mac.o \ ++ phy.o \ ++ fw.o \ ++ rtw8852a.o \ ++ rtw8852a_table.o \ ++ rtw8852a_rfk.o \ ++ rtw8852a_rfk_table.o \ ++ cam.o \ ++ efuse.o \ ++ regd.o \ ++ sar.o \ ++ coex.o \ ++ ps.o \ ++ ser.o ++ ++rtw89_core-$(CONFIG_RTW89_DEBUG) += debug.o ++ ++obj-$(CONFIG_RTW89_PCI) += rtw89_pci.o ++rtw89_pci-y := pci.o ++