105 lines
4.3 KiB
Diff
105 lines
4.3 KiB
Diff
From: Tim Harvey <tharvey@gateworks.com>
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Subject: [PATCH] PCI: imx6: remove outbound io/mem ATU region mapping
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The IMX6 iATU is used for address translation between the AXI bus
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address space and PCI address space. This is used for type0 and type1
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config cycles but is not necessary for outbound io/mem regions.
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This patch removes the calls that inappropriately re-configures the ATU
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viewport for outbound memory and IO after config cycles and removes them
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altogether as they are not necessary.
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This resolves issues with PCI devices behind switches and has been tested with
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a Gige device behind a PLX PEX860x switch.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pcie-designware.c | 41 +++---------------------------------
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1 file changed, 3 insertions(+), 38 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -43,7 +43,6 @@
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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@@ -264,8 +263,8 @@ static void dw_pcie_prog_viewport_cfg0(s
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static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
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{
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- /* Program viewport 1 : OUTBOUND : CFG1 */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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+ /* Program viewport 0 : OUTBOUND : CFG1 */
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+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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@@ -275,38 +274,8 @@ static void dw_pcie_prog_viewport_cfg1(s
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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-}
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-
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-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
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-{
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- /* Program viewport 0 : OUTBOUND : MEM */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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- PCIE_ATU_VIEWPORT);
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- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
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- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
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- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
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- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
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- PCIE_ATU_LIMIT);
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- dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
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- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
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- PCIE_ATU_UPPER_TARGET);
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-}
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-
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-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
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-{
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- /* Program viewport 1 : OUTBOUND : IO */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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- PCIE_ATU_VIEWPORT);
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- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
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+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
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- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
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- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
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- PCIE_ATU_LIMIT);
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- dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
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- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
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- PCIE_ATU_UPPER_TARGET);
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}
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static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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@@ -322,11 +291,9 @@ static int dw_pcie_rd_other_conf(struct
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_viewport_cfg0(pp, busdev);
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ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
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- dw_pcie_prog_viewport_mem_outbound(pp);
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} else {
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dw_pcie_prog_viewport_cfg1(pp, busdev);
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ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
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- dw_pcie_prog_viewport_io_outbound(pp);
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}
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return ret;
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@@ -345,11 +312,9 @@ static int dw_pcie_wr_other_conf(struct
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_viewport_cfg0(pp, busdev);
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ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
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- dw_pcie_prog_viewport_mem_outbound(pp);
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} else {
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dw_pcie_prog_viewport_cfg1(pp, busdev);
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ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
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- dw_pcie_prog_viewport_io_outbound(pp);
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}
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return ret;
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