04ad02d132
Compared to the "old" driver: - Each device must assign a pinctrl setting to the SPI node to allow the new SPI driver to configure the SPI pins. While here we are also using separate input and output settings so we are independent of whether the bootloader configures the pins correctly. - We use the new "compatible" strings to make the driver choose the correct number of chip-selects for each SoC. - The new driver starts counting the chip-selects at 1 (instead of 0, like the old one did). Thus we have to adjust the devices accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48293
205 lines
4.3 KiB
Plaintext
205 lines
4.3 KiB
Plaintext
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "lantiq,xway", "lantiq,ar9";
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
compatible = "mips,mips34K";
|
|
};
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
};
|
|
|
|
biu@1F800000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "lantiq,biu", "simple-bus";
|
|
reg = <0x1F800000 0x800000>;
|
|
ranges = <0x0 0x1F800000 0x7FFFFF>;
|
|
|
|
icu0: icu@80200 {
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "lantiq,icu";
|
|
reg = <0x80200 0x28
|
|
0x80228 0x28
|
|
0x80250 0x28
|
|
0x80278 0x28
|
|
0x802a0 0x28>;
|
|
};
|
|
|
|
watchdog@803F0 {
|
|
compatible = "lantiq,wdt";
|
|
reg = <0x803F0 0x10>;
|
|
};
|
|
};
|
|
|
|
sram@1F000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "lantiq,sram";
|
|
reg = <0x1F000000 0x800000>;
|
|
ranges = <0x0 0x1F000000 0x7FFFFF>;
|
|
|
|
eiu0: eiu@101000 {
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "lantiq,eiu-xway";
|
|
reg = <0x101000 0x1000>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <166 135 66 40 41 42>;
|
|
};
|
|
|
|
pmu0: pmu@102000 {
|
|
compatible = "lantiq,pmu-xway";
|
|
reg = <0x102000 0x1000>;
|
|
};
|
|
|
|
cgu0: cgu@103000 {
|
|
compatible = "lantiq,cgu-xway";
|
|
reg = <0x103000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rcu0: rcu@203000 {
|
|
compatible = "lantiq,rcu-xway";
|
|
reg = <0x203000 0x1000>;
|
|
};
|
|
};
|
|
|
|
fpi@10000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "lantiq,fpi", "simple-bus";
|
|
ranges = <0x0 0x10000000 0xEEFFFFF>;
|
|
reg = <0x10000000 0xEF00000>;
|
|
|
|
localbus@0 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
|
|
1 0 0x4000000 0x4000010>; /* addsel1 */
|
|
compatible = "lantiq,localbus", "simple-bus";
|
|
};
|
|
|
|
gptu@E100A00 {
|
|
compatible = "lantiq,gptu-xway";
|
|
reg = <0xE100A00 0x100>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <126 127 128 129 130 131>;
|
|
};
|
|
|
|
asc0: serial@E100400 {
|
|
compatible = "lantiq,asc";
|
|
reg = <0xE100400 0x400>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <104 105 106>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@E100800 {
|
|
compatible = "lantiq,xrx100-spi";
|
|
reg = <0xE100800 0x100>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <22 23 24>;
|
|
interrupt-names = "spi_rx", "spi_tx", "spi_err",
|
|
"spi_frm";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio: pinmux@E100B10 {
|
|
compatible = "lantiq,xrx100-pinctrl";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0xE100B10 0xA0>;
|
|
};
|
|
|
|
asc1: serial@E100C00 {
|
|
compatible = "lantiq,asc";
|
|
reg = <0xE100C00 0x400>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <112 113 114>;
|
|
};
|
|
|
|
ifxhcd@E101000 {
|
|
compatible = "lantiq,ifxhcd-arx100", "lantiq,ifxhcd-arx100-dwc2";
|
|
reg = <0xE101000 0x1000
|
|
0xE120000 0x3f000>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <62 91>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ifxhcd@E106000 {
|
|
compatible = "lantiq,ifxhcd-arx100-dwc2";
|
|
reg = <0xE106000 0x1000
|
|
0xE1E0000 0x3f000>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <91>;
|
|
status = "disabled";
|
|
};
|
|
|
|
deu@E103100 {
|
|
compatible = "lantiq,deu-arx100";
|
|
reg = <0xE103100 0xf00>;
|
|
};
|
|
|
|
dma0: dma@E104100 {
|
|
compatible = "lantiq,dma-xway";
|
|
reg = <0xE104100 0x800>;
|
|
};
|
|
|
|
ebu0: ebu@E105300 {
|
|
compatible = "lantiq,ebu-xway";
|
|
reg = <0xE105300 0x100>;
|
|
};
|
|
|
|
mei@E116000 {
|
|
compatible = "lantiq,mei-xway";
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <63>;
|
|
};
|
|
|
|
etop@E180000 {
|
|
compatible = "lantiq,etop-xway";
|
|
reg = <0xE180000 0x40000
|
|
0xE108000 0x200>;
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <73 72>;
|
|
mac-address = [ 00 11 22 33 44 55 ];
|
|
};
|
|
|
|
ppe@E234000 {
|
|
compatible = "lantiq,ppe-arx100";
|
|
interrupt-parent = <&icu0>;
|
|
interrupts = <96>;
|
|
};
|
|
|
|
pci0: pci@E105400 {
|
|
status = "disabled";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
compatible = "lantiq,pci-xway";
|
|
bus-range = <0x0 0x0>;
|
|
ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
|
|
0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
|
|
reg = <0x7000000 0x8000 /* config space */
|
|
0xE105400 0x400>; /* pci bridge */
|
|
lantiq,bus-clock = <33333333>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <0x7000 0 0 1 &icu0 30 1>;
|
|
req-mask = <0x1>;
|
|
};
|
|
};
|
|
|
|
adsl {
|
|
compatible = "lantiq,adsl-arx100";
|
|
};
|
|
};
|