116 lines
3.5 KiB
Diff
116 lines
3.5 KiB
Diff
From 7d6656dc127b54e53e507e8f264bb7e14e620cad Mon Sep 17 00:00:00 2001
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From: Axel Gembe <ago@bastart.eu.org>
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Date: Sat, 17 May 2008 15:02:39 +0200
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Subject: [PATCH] bcm963xx: add new timer code
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This basically selects the new generic MIPS timer code for BCM963xx and
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simplifies the timer setup code.
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Signed-off-by: Axel Gembe <ago@bastart.eu.org>
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---
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arch/mips/Kconfig | 2 +
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arch/mips/bcm963xx/time.c | 64 ++++++++++++++++++++------------------------
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2 files changed, 31 insertions(+), 35 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -67,6 +67,8 @@
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select HW_HAS_PCI
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select DMA_NONCOHERENT
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select IRQ_CPU
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+ select CEVT_R4K
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+ select CSRC_R4K
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help
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This is a fmaily of boards based on the Broadcom MIPS32
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--- a/arch/mips/bcm963xx/time.c
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+++ b/arch/mips/bcm963xx/time.c
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@@ -1,6 +1,7 @@
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/*
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<:copyright-gpl
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Copyright 2004 Broadcom Corp. All Rights Reserved.
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+ Copyright (C) 2008 Axel Gembe <ago@bastart.eu.org>
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This program is free software; you can distribute it and/or modify it
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under the terms of the GNU General Public License (Version 2) as
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@@ -40,50 +41,43 @@
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#include <bcm_map_part.h>
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#include <bcm_intr.h>
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-static unsigned long r4k_offset; /* Amount to increment compare reg each time */
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-static unsigned long r4k_cur; /* What counter should be at next timer irq */
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-
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-/* *********************************************************************
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- * calculateCpuSpeed()
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- * Calculate the BCM6348 CPU speed by reading the PLL strap register
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- * and applying the following formula:
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- * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
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- * Input parameters:
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- * none
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- * Return value:
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- * none
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- ********************************************************************* */
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-
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+/*
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+ * calculateCpuSpeed()
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+ *
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+ * Calculate the BCM6348 CPU speed by reading the PLL strap register and applying
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+ * the following formula:
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+ *
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+ * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
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+ */
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static inline unsigned long __init calculateCpuSpeed(void)
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{
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- u32 pllStrap = PERF->PllStrap;
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- int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
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- int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
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- int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
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+ u32 pllStrap;
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+ int n1, n2, m1cpu;
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+
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+ pllStrap = PERF->PllStrap;
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+ n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
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+ n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
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+ m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
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return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000;
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}
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-static inline unsigned long __init cal_r4koff(void)
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-{
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- mips_hpt_frequency = calculateCpuSpeed() / 2;
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- return (mips_hpt_frequency / HZ);
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-}
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-
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void __init plat_time_init(void)
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{
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- unsigned int est_freq, flags;
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- local_irq_save(flags);
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+ unsigned long cpu_clock;
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+
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+ cpu_clock = calculateCpuSpeed();
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+
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+ printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000,
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+ (cpu_clock % 1000000) * 100 / 1000000);
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+
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+ mips_hpt_frequency = cpu_clock / 2;
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- printk("calculating r4koff... ");
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- r4k_offset = cal_r4koff();
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- printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
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-
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- est_freq = 2 * r4k_offset * HZ;
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- est_freq += 5000; /* round */
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- est_freq -= est_freq % 10000;
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- printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
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- (est_freq % 1000000) * 100 / 1000000);
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- local_irq_restore(flags);
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+ /*
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+ * Use deterministic values for initial counter interrupt
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+ * so that calibrate delay avoids encountering a counter wrap.
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+ */
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+ write_c0_count(0);
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+ write_c0_compare(0xffff);
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}
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