11e3592531
SVN-Revision: 35264
2640 lines
106 KiB
Diff
2640 lines
106 KiB
Diff
--- a/net/mac80211/agg-rx.c
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+++ b/net/mac80211/agg-rx.c
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@@ -203,6 +203,8 @@ static void ieee80211_send_addba_resp(st
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memcpy(mgmt->bssid, sdata->u.mgd.bssid, ETH_ALEN);
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else if (sdata->vif.type == NL80211_IFTYPE_ADHOC)
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memcpy(mgmt->bssid, sdata->u.ibss.bssid, ETH_ALEN);
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+ else if (sdata->vif.type == NL80211_IFTYPE_WDS)
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+ memcpy(mgmt->bssid, da, ETH_ALEN);
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mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
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IEEE80211_STYPE_ACTION);
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--- a/net/mac80211/agg-tx.c
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+++ b/net/mac80211/agg-tx.c
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@@ -81,7 +81,8 @@ static void ieee80211_send_addba_request
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memcpy(mgmt->sa, sdata->vif.addr, ETH_ALEN);
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if (sdata->vif.type == NL80211_IFTYPE_AP ||
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sdata->vif.type == NL80211_IFTYPE_AP_VLAN ||
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- sdata->vif.type == NL80211_IFTYPE_MESH_POINT)
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+ sdata->vif.type == NL80211_IFTYPE_MESH_POINT ||
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+ sdata->vif.type == NL80211_IFTYPE_WDS)
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memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
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else if (sdata->vif.type == NL80211_IFTYPE_STATION)
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memcpy(mgmt->bssid, sdata->u.mgd.bssid, ETH_ALEN);
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@@ -520,6 +521,7 @@ int ieee80211_start_tx_ba_session(struct
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sdata->vif.type != NL80211_IFTYPE_MESH_POINT &&
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sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
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sdata->vif.type != NL80211_IFTYPE_AP &&
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+ sdata->vif.type != NL80211_IFTYPE_WDS &&
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sdata->vif.type != NL80211_IFTYPE_ADHOC)
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return -EINVAL;
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--- a/net/mac80211/debugfs_sta.c
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+++ b/net/mac80211/debugfs_sta.c
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@@ -65,11 +65,11 @@ static ssize_t sta_flags_read(struct fil
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test_sta_flag(sta, WLAN_STA_##flg) ? #flg "\n" : ""
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int res = scnprintf(buf, sizeof(buf),
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- "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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+ "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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TEST(AUTH), TEST(ASSOC), TEST(PS_STA),
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TEST(PS_DRIVER), TEST(AUTHORIZED),
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TEST(SHORT_PREAMBLE),
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- TEST(WME), TEST(WDS), TEST(CLEAR_PS_FILT),
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+ TEST(WME), TEST(CLEAR_PS_FILT),
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TEST(MFP), TEST(BLOCK_BA), TEST(PSPOLL),
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TEST(UAPSD), TEST(SP), TEST(TDLS_PEER),
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TEST(TDLS_PEER_AUTH), TEST(4ADDR_EVENT),
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--- a/net/mac80211/iface.c
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+++ b/net/mac80211/iface.c
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@@ -501,7 +501,6 @@ int ieee80211_do_open(struct wireless_de
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struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev);
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struct net_device *dev = wdev->netdev;
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struct ieee80211_local *local = sdata->local;
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- struct sta_info *sta;
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u32 changed = 0;
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int res;
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u32 hw_reconf_flags = 0;
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@@ -658,30 +657,8 @@ int ieee80211_do_open(struct wireless_de
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set_bit(SDATA_STATE_RUNNING, &sdata->state);
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- if (sdata->vif.type == NL80211_IFTYPE_WDS) {
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- /* Create STA entry for the WDS peer */
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- sta = sta_info_alloc(sdata, sdata->u.wds.remote_addr,
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- GFP_KERNEL);
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- if (!sta) {
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- res = -ENOMEM;
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- goto err_del_interface;
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- }
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-
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- sta_info_pre_move_state(sta, IEEE80211_STA_AUTH);
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- sta_info_pre_move_state(sta, IEEE80211_STA_ASSOC);
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- sta_info_pre_move_state(sta, IEEE80211_STA_AUTHORIZED);
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-
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- res = sta_info_insert(sta);
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- if (res) {
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- /* STA has been freed */
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- goto err_del_interface;
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- }
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-
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- rate_control_rate_init(sta);
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- netif_carrier_on(dev);
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- } else if (sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE) {
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+ if (sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE)
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rcu_assign_pointer(local->p2p_sdata, sdata);
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- }
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/*
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* set_multicast_list will be invoked by the networking core
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@@ -1066,6 +1043,72 @@ static void ieee80211_if_setup(struct ne
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dev->destructor = free_netdev;
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}
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+static void ieee80211_wds_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata,
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+ struct sk_buff *skb)
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+{
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+ struct ieee80211_local *local = sdata->local;
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+ struct ieee80211_rx_status *rx_status;
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+ struct ieee802_11_elems elems;
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+ struct ieee80211_mgmt *mgmt;
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+ struct sta_info *sta;
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+ size_t baselen;
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+ u32 rates = 0;
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+ u16 stype;
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+ bool new = false;
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+ enum ieee80211_band band = local->hw.conf.channel->band;
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+ struct ieee80211_supported_band *sband = local->hw.wiphy->bands[band];
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+
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+ rx_status = IEEE80211_SKB_RXCB(skb);
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+ mgmt = (struct ieee80211_mgmt *) skb->data;
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+ stype = le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE;
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+
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+ if (stype != IEEE80211_STYPE_BEACON)
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+ return;
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+
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+ baselen = (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt;
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+ if (baselen > skb->len)
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+ return;
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+
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+ ieee802_11_parse_elems(mgmt->u.probe_resp.variable,
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+ skb->len - baselen, &elems);
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+
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+ rates = ieee80211_sta_get_rates(local, &elems, band, NULL);
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+
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+ rcu_read_lock();
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+
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+ sta = sta_info_get(sdata, sdata->u.wds.remote_addr);
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+
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+ if (!sta) {
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+ rcu_read_unlock();
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+ sta = sta_info_alloc(sdata, sdata->u.wds.remote_addr,
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+ GFP_KERNEL);
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+ if (!sta)
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+ return;
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+
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+ new = true;
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+ }
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+
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+ sta->last_rx = jiffies;
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+ sta->sta.supp_rates[local->hw.conf.channel->band] = rates;
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+
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+ if (elems.ht_cap_elem)
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+ ieee80211_ht_cap_ie_to_sta_ht_cap(sdata, sband,
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+ elems.ht_cap_elem, &sta->sta.ht_cap);
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+
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+ if (elems.wmm_param)
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+ set_sta_flag(sta, WLAN_STA_WME);
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+
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+ if (new) {
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+ sta_info_pre_move_state(sta, IEEE80211_STA_AUTH);
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+ sta_info_pre_move_state(sta, IEEE80211_STA_ASSOC);
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+ sta_info_pre_move_state(sta, IEEE80211_STA_AUTHORIZED);
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+ rate_control_rate_init(sta);
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+ sta_info_insert_rcu(sta);
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+ }
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+
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+ rcu_read_unlock();
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+}
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+
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static void ieee80211_iface_work(struct work_struct *work)
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{
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struct ieee80211_sub_if_data *sdata =
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@@ -1170,6 +1213,9 @@ static void ieee80211_iface_work(struct
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break;
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ieee80211_mesh_rx_queued_mgmt(sdata, skb);
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break;
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+ case NL80211_IFTYPE_WDS:
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+ ieee80211_wds_rx_queued_mgmt(sdata, skb);
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+ break;
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default:
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WARN(1, "frame for unexpected interface type");
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break;
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--- a/net/mac80211/rx.c
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+++ b/net/mac80211/rx.c
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@@ -2350,6 +2350,7 @@ ieee80211_rx_h_action(struct ieee80211_r
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sdata->vif.type != NL80211_IFTYPE_MESH_POINT &&
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sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
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sdata->vif.type != NL80211_IFTYPE_AP &&
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+ sdata->vif.type != NL80211_IFTYPE_WDS &&
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sdata->vif.type != NL80211_IFTYPE_ADHOC)
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break;
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@@ -2655,14 +2656,15 @@ ieee80211_rx_h_mgmt(struct ieee80211_rx_
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if (!ieee80211_vif_is_mesh(&sdata->vif) &&
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sdata->vif.type != NL80211_IFTYPE_ADHOC &&
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- sdata->vif.type != NL80211_IFTYPE_STATION)
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+ sdata->vif.type != NL80211_IFTYPE_STATION &&
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+ sdata->vif.type != NL80211_IFTYPE_WDS)
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return RX_DROP_MONITOR;
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switch (stype) {
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case cpu_to_le16(IEEE80211_STYPE_AUTH):
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case cpu_to_le16(IEEE80211_STYPE_BEACON):
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case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
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- /* process for all: mesh, mlme, ibss */
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+ /* process for all: mesh, mlme, ibss, wds */
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break;
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case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
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case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
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@@ -2987,10 +2989,16 @@ static int prepare_for_handlers(struct i
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}
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break;
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case NL80211_IFTYPE_WDS:
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- if (bssid || !ieee80211_is_data(hdr->frame_control))
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- return 0;
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if (!ether_addr_equal(sdata->u.wds.remote_addr, hdr->addr2))
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return 0;
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+
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+ if (ieee80211_is_data(hdr->frame_control) ||
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+ ieee80211_is_action(hdr->frame_control)) {
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+ if (compare_ether_addr(sdata->vif.addr, hdr->addr1))
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+ return 0;
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+ } else if (!ieee80211_is_beacon(hdr->frame_control))
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+ return 0;
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+
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break;
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case NL80211_IFTYPE_P2P_DEVICE:
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if (!ieee80211_is_public_action(hdr, skb->len) &&
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--- a/net/mac80211/sta_info.h
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+++ b/net/mac80211/sta_info.h
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@@ -32,7 +32,6 @@
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* @WLAN_STA_SHORT_PREAMBLE: Station is capable of receiving short-preamble
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* frames.
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* @WLAN_STA_WME: Station is a QoS-STA.
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- * @WLAN_STA_WDS: Station is one of our WDS peers.
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* @WLAN_STA_CLEAR_PS_FILT: Clear PS filter in hardware (using the
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* IEEE80211_TX_CTL_CLEAR_PS_FILT control flag) when the next
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* frame to this station is transmitted.
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@@ -64,7 +63,6 @@ enum ieee80211_sta_info_flags {
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WLAN_STA_AUTHORIZED,
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WLAN_STA_SHORT_PREAMBLE,
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WLAN_STA_WME,
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- WLAN_STA_WDS,
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WLAN_STA_CLEAR_PS_FILT,
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WLAN_STA_MFP,
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WLAN_STA_BLOCK_BA,
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--- a/drivers/net/wireless/ath/ath9k/ath9k.h
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+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
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@@ -314,7 +314,6 @@ struct ath_rx {
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u32 *rxlink;
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u32 num_pkts;
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unsigned int rxfilter;
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- spinlock_t rxbuflock;
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struct list_head rxbuf;
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struct ath_descdma rxdma;
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struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
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@@ -324,7 +323,6 @@ struct ath_rx {
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int ath_startrecv(struct ath_softc *sc);
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bool ath_stoprecv(struct ath_softc *sc);
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-void ath_flushrecv(struct ath_softc *sc);
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u32 ath_calcrxfilter(struct ath_softc *sc);
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int ath_rx_init(struct ath_softc *sc, int nbufs);
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void ath_rx_cleanup(struct ath_softc *sc);
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@@ -334,9 +332,8 @@ void ath_txq_lock(struct ath_softc *sc,
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void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
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void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
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void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
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-bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
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-void ath_draintxq(struct ath_softc *sc,
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- struct ath_txq *txq, bool retry_tx);
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+bool ath_drain_all_txq(struct ath_softc *sc);
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+void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
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void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
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void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
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void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
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@@ -641,7 +638,6 @@ void ath_ant_comb_update(struct ath_soft
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enum sc_op_flags {
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SC_OP_INVALID,
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SC_OP_BEACONS,
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- SC_OP_RXFLUSH,
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SC_OP_ANI_RUN,
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SC_OP_PRIM_STA_VIF,
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SC_OP_HW_RESET,
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--- a/drivers/net/wireless/ath/ath9k/beacon.c
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+++ b/drivers/net/wireless/ath/ath9k/beacon.c
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@@ -147,6 +147,7 @@ static struct ath_buf *ath9k_beacon_gene
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skb->len, DMA_TO_DEVICE);
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dev_kfree_skb_any(skb);
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bf->bf_buf_addr = 0;
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+ bf->bf_mpdu = NULL;
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}
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skb = ieee80211_beacon_get(hw, vif);
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@@ -198,7 +199,7 @@ static struct ath_buf *ath9k_beacon_gene
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if (sc->nvifs > 1) {
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ath_dbg(common, BEACON,
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"Flushing previous cabq traffic\n");
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- ath_draintxq(sc, cabq, false);
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+ ath_draintxq(sc, cabq);
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}
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}
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@@ -359,7 +360,6 @@ void ath9k_beacon_tasklet(unsigned long
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return;
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bf = ath9k_beacon_generate(sc->hw, vif);
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- WARN_ON(!bf);
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if (sc->beacon.bmisscnt != 0) {
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ath_dbg(common, BSTUCK, "resume beacon xmit after %u misses\n",
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--- a/drivers/net/wireless/ath/ath9k/debug.c
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+++ b/drivers/net/wireless/ath/ath9k/debug.c
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@@ -861,7 +861,6 @@ static ssize_t read_file_recv(struct fil
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RXS_ERR("RX-LENGTH-ERR", rx_len_err);
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RXS_ERR("RX-OOM-ERR", rx_oom_err);
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RXS_ERR("RX-RATE-ERR", rx_rate_err);
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- RXS_ERR("RX-DROP-RXFLUSH", rx_drop_rxflush);
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RXS_ERR("RX-TOO-MANY-FRAGS", rx_too_many_frags_err);
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PHY_ERR("UNDERRUN ERR", ATH9K_PHYERR_UNDERRUN);
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--- a/drivers/net/wireless/ath/ath9k/debug.h
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+++ b/drivers/net/wireless/ath/ath9k/debug.h
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@@ -216,7 +216,6 @@ struct ath_tx_stats {
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* @rx_oom_err: No. of frames dropped due to OOM issues.
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* @rx_rate_err: No. of frames dropped due to rate errors.
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* @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
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- * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
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* @rx_beacons: No. of beacons received.
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* @rx_frags: No. of rx-fragements received.
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*/
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@@ -235,7 +234,6 @@ struct ath_rx_stats {
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u32 rx_oom_err;
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u32 rx_rate_err;
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u32 rx_too_many_frags_err;
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- u32 rx_drop_rxflush;
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u32 rx_beacons;
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u32 rx_frags;
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};
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--- a/drivers/net/wireless/ath/ath9k/main.c
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+++ b/drivers/net/wireless/ath/ath9k/main.c
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@@ -182,7 +182,7 @@ static void ath_restart_work(struct ath_
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ath_start_ani(sc);
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}
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-static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
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+static bool ath_prepare_reset(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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bool ret = true;
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@@ -196,20 +196,12 @@ static bool ath_prepare_reset(struct ath
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ath9k_debug_samp_bb_mac(sc);
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ath9k_hw_disable_interrupts(ah);
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|
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- if (!ath_stoprecv(sc))
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+ if (!ath_drain_all_txq(sc))
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ret = false;
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- if (!ath_drain_all_txq(sc, retry_tx))
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+ if (!ath_stoprecv(sc))
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ret = false;
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|
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- if (!flush) {
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- if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
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- ath_rx_tasklet(sc, 1, true);
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- ath_rx_tasklet(sc, 1, false);
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- } else {
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- ath_flushrecv(sc);
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- }
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-
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return ret;
|
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}
|
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|
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@@ -255,18 +247,17 @@ static bool ath_complete_reset(struct at
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return true;
|
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}
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|
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-static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
|
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- bool retry_tx)
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+static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
|
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{
|
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struct ath_hw *ah = sc->sc_ah;
|
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struct ath_common *common = ath9k_hw_common(ah);
|
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struct ath9k_hw_cal_data *caldata = NULL;
|
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bool fastcc = true;
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- bool flush = false;
|
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int r;
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|
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__ath_cancel_work(sc);
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|
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+ tasklet_disable(&sc->intr_tq);
|
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spin_lock_bh(&sc->sc_pcu_lock);
|
|
|
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if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
|
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@@ -276,11 +267,10 @@ static int ath_reset_internal(struct ath
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|
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if (!hchan) {
|
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fastcc = false;
|
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- flush = true;
|
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hchan = ah->curchan;
|
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}
|
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|
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- if (!ath_prepare_reset(sc, retry_tx, flush))
|
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+ if (!ath_prepare_reset(sc))
|
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fastcc = false;
|
|
|
|
ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
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@@ -302,6 +292,8 @@ static int ath_reset_internal(struct ath
|
|
|
|
out:
|
|
spin_unlock_bh(&sc->sc_pcu_lock);
|
|
+ tasklet_enable(&sc->intr_tq);
|
|
+
|
|
return r;
|
|
}
|
|
|
|
@@ -319,7 +311,7 @@ static int ath_set_channel(struct ath_so
|
|
if (test_bit(SC_OP_INVALID, &sc->sc_flags))
|
|
return -EIO;
|
|
|
|
- r = ath_reset_internal(sc, hchan, false);
|
|
+ r = ath_reset_internal(sc, hchan);
|
|
|
|
return r;
|
|
}
|
|
@@ -549,23 +541,21 @@ chip_reset:
|
|
#undef SCHED_INTR
|
|
}
|
|
|
|
-static int ath_reset(struct ath_softc *sc, bool retry_tx)
|
|
+static int ath_reset(struct ath_softc *sc)
|
|
{
|
|
- int r;
|
|
+ int i, r;
|
|
|
|
ath9k_ps_wakeup(sc);
|
|
|
|
- r = ath_reset_internal(sc, NULL, retry_tx);
|
|
+ r = ath_reset_internal(sc, NULL);
|
|
|
|
- if (retry_tx) {
|
|
- int i;
|
|
- for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
|
- if (ATH_TXQ_SETUP(sc, i)) {
|
|
- spin_lock_bh(&sc->tx.txq[i].axq_lock);
|
|
- ath_txq_schedule(sc, &sc->tx.txq[i]);
|
|
- spin_unlock_bh(&sc->tx.txq[i].axq_lock);
|
|
- }
|
|
- }
|
|
+ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
|
+ if (!ATH_TXQ_SETUP(sc, i))
|
|
+ continue;
|
|
+
|
|
+ spin_lock_bh(&sc->tx.txq[i].axq_lock);
|
|
+ ath_txq_schedule(sc, &sc->tx.txq[i]);
|
|
+ spin_unlock_bh(&sc->tx.txq[i].axq_lock);
|
|
}
|
|
|
|
ath9k_ps_restore(sc);
|
|
@@ -586,7 +576,7 @@ void ath_reset_work(struct work_struct *
|
|
{
|
|
struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
|
|
|
|
- ath_reset(sc, true);
|
|
+ ath_reset(sc);
|
|
}
|
|
|
|
/**********************/
|
|
@@ -804,7 +794,7 @@ static void ath9k_stop(struct ieee80211_
|
|
ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
|
|
}
|
|
|
|
- ath_prepare_reset(sc, false, true);
|
|
+ ath_prepare_reset(sc);
|
|
|
|
if (sc->rx.frag) {
|
|
dev_kfree_skb_any(sc->rx.frag);
|
|
@@ -1731,11 +1721,11 @@ static void ath9k_flush(struct ieee80211
|
|
if (drop) {
|
|
ath9k_ps_wakeup(sc);
|
|
spin_lock_bh(&sc->sc_pcu_lock);
|
|
- drain_txq = ath_drain_all_txq(sc, false);
|
|
+ drain_txq = ath_drain_all_txq(sc);
|
|
spin_unlock_bh(&sc->sc_pcu_lock);
|
|
|
|
if (!drain_txq)
|
|
- ath_reset(sc, false);
|
|
+ ath_reset(sc);
|
|
|
|
ath9k_ps_restore(sc);
|
|
ieee80211_wake_queues(hw);
|
|
@@ -1835,6 +1825,9 @@ static u32 fill_chainmask(u32 cap, u32 n
|
|
|
|
static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
|
|
{
|
|
+ if (AR_SREV_9300_20_OR_LATER(ah))
|
|
+ return true;
|
|
+
|
|
switch (val & 0x7) {
|
|
case 0x1:
|
|
case 0x3:
|
|
--- a/drivers/net/wireless/ath/ath9k/recv.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/recv.c
|
|
@@ -248,8 +248,6 @@ rx_init_fail:
|
|
|
|
static void ath_edma_start_recv(struct ath_softc *sc)
|
|
{
|
|
- spin_lock_bh(&sc->rx.rxbuflock);
|
|
-
|
|
ath9k_hw_rxena(sc->sc_ah);
|
|
|
|
ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
|
|
@@ -261,8 +259,6 @@ static void ath_edma_start_recv(struct a
|
|
ath_opmode_init(sc);
|
|
|
|
ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
|
|
-
|
|
- spin_unlock_bh(&sc->rx.rxbuflock);
|
|
}
|
|
|
|
static void ath_edma_stop_recv(struct ath_softc *sc)
|
|
@@ -279,8 +275,6 @@ int ath_rx_init(struct ath_softc *sc, in
|
|
int error = 0;
|
|
|
|
spin_lock_init(&sc->sc_pcu_lock);
|
|
- spin_lock_init(&sc->rx.rxbuflock);
|
|
- clear_bit(SC_OP_RXFLUSH, &sc->sc_flags);
|
|
|
|
common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
|
|
sc->sc_ah->caps.rx_status_len;
|
|
@@ -438,7 +432,6 @@ int ath_startrecv(struct ath_softc *sc)
|
|
return 0;
|
|
}
|
|
|
|
- spin_lock_bh(&sc->rx.rxbuflock);
|
|
if (list_empty(&sc->rx.rxbuf))
|
|
goto start_recv;
|
|
|
|
@@ -459,26 +452,31 @@ start_recv:
|
|
ath_opmode_init(sc);
|
|
ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
|
|
|
|
- spin_unlock_bh(&sc->rx.rxbuflock);
|
|
-
|
|
return 0;
|
|
}
|
|
|
|
+static void ath_flushrecv(struct ath_softc *sc)
|
|
+{
|
|
+ if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
|
|
+ ath_rx_tasklet(sc, 1, true);
|
|
+ ath_rx_tasklet(sc, 1, false);
|
|
+}
|
|
+
|
|
bool ath_stoprecv(struct ath_softc *sc)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
bool stopped, reset = false;
|
|
|
|
- spin_lock_bh(&sc->rx.rxbuflock);
|
|
ath9k_hw_abortpcurecv(ah);
|
|
ath9k_hw_setrxfilter(ah, 0);
|
|
stopped = ath9k_hw_stopdmarecv(ah, &reset);
|
|
|
|
+ ath_flushrecv(sc);
|
|
+
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
|
|
ath_edma_stop_recv(sc);
|
|
else
|
|
sc->rx.rxlink = NULL;
|
|
- spin_unlock_bh(&sc->rx.rxbuflock);
|
|
|
|
if (!(ah->ah_flags & AH_UNPLUGGED) &&
|
|
unlikely(!stopped)) {
|
|
@@ -490,15 +488,6 @@ bool ath_stoprecv(struct ath_softc *sc)
|
|
return stopped && !reset;
|
|
}
|
|
|
|
-void ath_flushrecv(struct ath_softc *sc)
|
|
-{
|
|
- set_bit(SC_OP_RXFLUSH, &sc->sc_flags);
|
|
- if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
|
|
- ath_rx_tasklet(sc, 1, true);
|
|
- ath_rx_tasklet(sc, 1, false);
|
|
- clear_bit(SC_OP_RXFLUSH, &sc->sc_flags);
|
|
-}
|
|
-
|
|
static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
|
|
{
|
|
/* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
|
|
@@ -735,6 +724,7 @@ static struct ath_buf *ath_get_next_rx_b
|
|
return NULL;
|
|
}
|
|
|
|
+ list_del(&bf->list);
|
|
if (!bf->bf_mpdu)
|
|
return bf;
|
|
|
|
@@ -1050,16 +1040,12 @@ int ath_rx_tasklet(struct ath_softc *sc,
|
|
dma_type = DMA_FROM_DEVICE;
|
|
|
|
qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
|
|
- spin_lock_bh(&sc->rx.rxbuflock);
|
|
|
|
tsf = ath9k_hw_gettsf64(ah);
|
|
tsf_lower = tsf & 0xffffffff;
|
|
|
|
do {
|
|
bool decrypt_error = false;
|
|
- /* If handling rx interrupt and flush is in progress => exit */
|
|
- if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags) && (flush == 0))
|
|
- break;
|
|
|
|
memset(&rs, 0, sizeof(rs));
|
|
if (edma)
|
|
@@ -1102,15 +1088,6 @@ int ath_rx_tasklet(struct ath_softc *sc,
|
|
|
|
ath_debug_stat_rx(sc, &rs);
|
|
|
|
- /*
|
|
- * If we're asked to flush receive queue, directly
|
|
- * chain it back at the queue without processing it.
|
|
- */
|
|
- if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags)) {
|
|
- RX_STAT_INC(rx_drop_rxflush);
|
|
- goto requeue_drop_frag;
|
|
- }
|
|
-
|
|
memset(rxs, 0, sizeof(struct ieee80211_rx_status));
|
|
|
|
rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
|
|
@@ -1245,19 +1222,18 @@ requeue_drop_frag:
|
|
sc->rx.frag = NULL;
|
|
}
|
|
requeue:
|
|
+ list_add_tail(&bf->list, &sc->rx.rxbuf);
|
|
+ if (flush)
|
|
+ continue;
|
|
+
|
|
if (edma) {
|
|
- list_add_tail(&bf->list, &sc->rx.rxbuf);
|
|
ath_rx_edma_buf_link(sc, qtype);
|
|
} else {
|
|
- list_move_tail(&bf->list, &sc->rx.rxbuf);
|
|
ath_rx_buf_link(sc, bf);
|
|
- if (!flush)
|
|
- ath9k_hw_rxena(ah);
|
|
+ ath9k_hw_rxena(ah);
|
|
}
|
|
} while (1);
|
|
|
|
- spin_unlock_bh(&sc->rx.rxbuflock);
|
|
-
|
|
if (!(ah->imask & ATH9K_INT_RXEOL)) {
|
|
ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
|
|
ath9k_hw_set_interrupts(ah);
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
|
|
@@ -4586,14 +4586,14 @@ static int ar9003_hw_cal_pier_get(struct
|
|
return 0;
|
|
}
|
|
|
|
-static int ar9003_hw_power_control_override(struct ath_hw *ah,
|
|
- int frequency,
|
|
- int *correction,
|
|
- int *voltage, int *temperature)
|
|
+static void ar9003_hw_power_control_override(struct ath_hw *ah,
|
|
+ int frequency,
|
|
+ int *correction,
|
|
+ int *voltage, int *temperature)
|
|
{
|
|
- int tempSlope = 0;
|
|
+ int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0;
|
|
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
|
|
- int f[8], t[8], i;
|
|
+ int f[8], t[8], t1[3], t2[3], i;
|
|
|
|
REG_RMW(ah, AR_PHY_TPC_11_B0,
|
|
(correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
|
|
@@ -4624,38 +4624,108 @@ static int ar9003_hw_power_control_overr
|
|
* enable temperature compensation
|
|
* Need to use register names
|
|
*/
|
|
- if (frequency < 4000)
|
|
- tempSlope = eep->modalHeader2G.tempSlope;
|
|
- else if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
|
|
- for (i = 0; i < 8; i++) {
|
|
- t[i] = eep->base_ext1.tempslopextension[i];
|
|
- f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
|
|
- }
|
|
- tempSlope = ar9003_hw_power_interpolate((s32) frequency,
|
|
- f, t, 8);
|
|
- } else if (eep->base_ext2.tempSlopeLow != 0) {
|
|
- t[0] = eep->base_ext2.tempSlopeLow;
|
|
- f[0] = 5180;
|
|
- t[1] = eep->modalHeader5G.tempSlope;
|
|
- f[1] = 5500;
|
|
- t[2] = eep->base_ext2.tempSlopeHigh;
|
|
- f[2] = 5785;
|
|
- tempSlope = ar9003_hw_power_interpolate((s32) frequency,
|
|
- f, t, 3);
|
|
- } else
|
|
- tempSlope = eep->modalHeader5G.tempSlope;
|
|
+ if (frequency < 4000) {
|
|
+ temp_slope = eep->modalHeader2G.tempSlope;
|
|
+ } else {
|
|
+ if (AR_SREV_9550(ah)) {
|
|
+ t[0] = eep->base_ext1.tempslopextension[2];
|
|
+ t1[0] = eep->base_ext1.tempslopextension[3];
|
|
+ t2[0] = eep->base_ext1.tempslopextension[4];
|
|
+ f[0] = 5180;
|
|
+
|
|
+ t[1] = eep->modalHeader5G.tempSlope;
|
|
+ t1[1] = eep->base_ext1.tempslopextension[0];
|
|
+ t2[1] = eep->base_ext1.tempslopextension[1];
|
|
+ f[1] = 5500;
|
|
+
|
|
+ t[2] = eep->base_ext1.tempslopextension[5];
|
|
+ t1[2] = eep->base_ext1.tempslopextension[6];
|
|
+ t2[2] = eep->base_ext1.tempslopextension[7];
|
|
+ f[2] = 5785;
|
|
+
|
|
+ temp_slope = ar9003_hw_power_interpolate(frequency,
|
|
+ f, t, 3);
|
|
+ temp_slope1 = ar9003_hw_power_interpolate(frequency,
|
|
+ f, t1, 3);
|
|
+ temp_slope2 = ar9003_hw_power_interpolate(frequency,
|
|
+ f, t2, 3);
|
|
+
|
|
+ goto tempslope;
|
|
+ }
|
|
+
|
|
+ if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
|
|
+ for (i = 0; i < 8; i++) {
|
|
+ t[i] = eep->base_ext1.tempslopextension[i];
|
|
+ f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
|
|
+ }
|
|
+ temp_slope = ar9003_hw_power_interpolate((s32) frequency,
|
|
+ f, t, 8);
|
|
+ } else if (eep->base_ext2.tempSlopeLow != 0) {
|
|
+ t[0] = eep->base_ext2.tempSlopeLow;
|
|
+ f[0] = 5180;
|
|
+ t[1] = eep->modalHeader5G.tempSlope;
|
|
+ f[1] = 5500;
|
|
+ t[2] = eep->base_ext2.tempSlopeHigh;
|
|
+ f[2] = 5785;
|
|
+ temp_slope = ar9003_hw_power_interpolate((s32) frequency,
|
|
+ f, t, 3);
|
|
+ } else {
|
|
+ temp_slope = eep->modalHeader5G.tempSlope;
|
|
+ }
|
|
+ }
|
|
|
|
- REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
|
|
+tempslope:
|
|
+ if (AR_SREV_9550(ah)) {
|
|
+ /*
|
|
+ * AR955x has tempSlope register for each chain.
|
|
+ * Check whether temp_compensation feature is enabled or not.
|
|
+ */
|
|
+ if (eep->baseEepHeader.featureEnable & 0x1) {
|
|
+ if (frequency < 4000) {
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ eep->base_ext2.tempSlopeLow);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ temp_slope);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ eep->base_ext2.tempSlopeHigh);
|
|
+ } else {
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ temp_slope);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ temp_slope1);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM,
|
|
+ temp_slope2);
|
|
+ }
|
|
+ } else {
|
|
+ /*
|
|
+ * If temp compensation is not enabled,
|
|
+ * set all registers to 0.
|
|
+ */
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM, 0);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM, 0);
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM, 0);
|
|
+ }
|
|
+ } else {
|
|
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
|
|
+ AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
|
|
+ }
|
|
|
|
if (AR_SREV_9462_20(ah))
|
|
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
|
|
- AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
|
|
+ AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);
|
|
|
|
|
|
REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
|
|
temperature[0]);
|
|
-
|
|
- return 0;
|
|
}
|
|
|
|
/* Apply the recorded correction values. */
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
|
|
@@ -68,7 +68,7 @@ static const int m2ThreshExt_off = 127;
|
|
static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
|
|
{
|
|
u16 bMode, fracMode = 0, aModeRefSel = 0;
|
|
- u32 freq, channelSel = 0, reg32 = 0;
|
|
+ u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
|
|
struct chan_centers centers;
|
|
int loadSynthChannel;
|
|
|
|
@@ -77,9 +77,6 @@ static int ar9003_hw_set_channel(struct
|
|
|
|
if (freq < 4800) { /* 2 GHz, fractional mode */
|
|
if (AR_SREV_9330(ah)) {
|
|
- u32 chan_frac;
|
|
- u32 div;
|
|
-
|
|
if (ah->is_clk_25mhz)
|
|
div = 75;
|
|
else
|
|
@@ -89,34 +86,40 @@ static int ar9003_hw_set_channel(struct
|
|
chan_frac = (((freq * 4) % div) * 0x20000) / div;
|
|
channelSel = (channelSel << 17) | chan_frac;
|
|
} else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
|
|
- u32 chan_frac;
|
|
-
|
|
/*
|
|
- * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
|
|
+ * freq_ref = 40 / (refdiva >> amoderefsel);
|
|
+ * where refdiva=1 and amoderefsel=0
|
|
* ndiv = ((chan_mhz * 4) / 3) / freq_ref;
|
|
* chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
|
|
*/
|
|
channelSel = (freq * 4) / 120;
|
|
chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
|
|
channelSel = (channelSel << 17) | chan_frac;
|
|
- } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
|
|
+ } else if (AR_SREV_9340(ah)) {
|
|
if (ah->is_clk_25mhz) {
|
|
- u32 chan_frac;
|
|
-
|
|
channelSel = (freq * 2) / 75;
|
|
chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
|
|
channelSel = (channelSel << 17) | chan_frac;
|
|
- } else
|
|
+ } else {
|
|
channelSel = CHANSEL_2G(freq) >> 1;
|
|
- } else
|
|
+ }
|
|
+ } else if (AR_SREV_9550(ah)) {
|
|
+ if (ah->is_clk_25mhz)
|
|
+ div = 75;
|
|
+ else
|
|
+ div = 120;
|
|
+
|
|
+ channelSel = (freq * 4) / div;
|
|
+ chan_frac = (((freq * 4) % div) * 0x20000) / div;
|
|
+ channelSel = (channelSel << 17) | chan_frac;
|
|
+ } else {
|
|
channelSel = CHANSEL_2G(freq);
|
|
+ }
|
|
/* Set to 2G mode */
|
|
bMode = 1;
|
|
} else {
|
|
if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
|
|
ah->is_clk_25mhz) {
|
|
- u32 chan_frac;
|
|
-
|
|
channelSel = freq / 75;
|
|
chan_frac = ((freq % 75) * 0x20000) / 75;
|
|
channelSel = (channelSel << 17) | chan_frac;
|
|
@@ -586,32 +589,19 @@ static void ar9003_hw_init_bb(struct ath
|
|
ath9k_hw_synth_delay(ah, chan, synthDelay);
|
|
}
|
|
|
|
-static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
|
|
+void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
|
|
{
|
|
- switch (rx) {
|
|
- case 0x5:
|
|
+ if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
|
|
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
|
|
AR_PHY_SWAP_ALT_CHAIN);
|
|
- case 0x3:
|
|
- case 0x1:
|
|
- case 0x2:
|
|
- case 0x7:
|
|
- REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
|
|
- REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
|
|
- break;
|
|
- default:
|
|
- break;
|
|
- }
|
|
+
|
|
+ REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
|
|
+ REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
|
|
|
|
if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
|
|
- REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
|
|
- else
|
|
- REG_WRITE(ah, AR_SELFGEN_MASK, tx);
|
|
+ tx = 3;
|
|
|
|
- if (tx == 0x5) {
|
|
- REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
|
|
- AR_PHY_SWAP_ALT_CHAIN);
|
|
- }
|
|
+ REG_WRITE(ah, AR_SELFGEN_MASK, tx);
|
|
}
|
|
|
|
/*
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
|
|
@@ -1028,7 +1028,7 @@
|
|
#define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
|
|
#define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
|
|
#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
|
|
-#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
|
|
+#define AR_PHY_TPC_19_B2 (AR_SM2_BASE + 0x240)
|
|
#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
|
|
#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
|
|
|
|
--- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
|
|
@@ -23,16 +23,16 @@
|
|
static const u32 ar955x_1p0_radio_postamble[][5] = {
|
|
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
{0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
|
|
- {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x06345f2a, 0x06345f2a},
|
|
- {0x000160ac, 0xa4647c00, 0xa4647c00, 0xa4646800, 0xa4646800},
|
|
- {0x000160b0, 0x01885f52, 0x01885f52, 0x04accf3a, 0x04accf3a},
|
|
- {0x00016104, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
|
|
+ {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a},
|
|
+ {0x000160ac, 0xa4647c00, 0xa4647c00, 0x24647c00, 0x24647c00},
|
|
+ {0x000160b0, 0x01885f52, 0x01885f52, 0x01885f52, 0x01885f52},
|
|
+ {0x00016104, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
|
|
{0x0001610c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
|
|
{0x00016140, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
|
|
- {0x00016504, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
|
|
+ {0x00016504, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
|
|
{0x0001650c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
|
|
{0x00016540, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
|
|
- {0x00016904, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
|
|
+ {0x00016904, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
|
|
{0x0001690c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
|
|
{0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
|
|
};
|
|
@@ -69,15 +69,15 @@ static const u32 ar955x_1p0_baseband_pos
|
|
{0x0000a204, 0x005c0ec0, 0x005c0ec4, 0x005c0ec4, 0x005c0ec0},
|
|
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
|
|
{0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
|
|
- {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
|
|
+ {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
|
|
{0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
|
|
{0x0000a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018},
|
|
{0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
|
|
{0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
|
|
{0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
|
|
- {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
|
|
+ {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01010e0e, 0x01010e0e},
|
|
{0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
|
|
- {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
|
|
+ {0x0000a264, 0x00000e0e, 0x00000e0e, 0x01000e0e, 0x01000e0e},
|
|
{0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
|
|
{0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
|
|
{0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
|
|
@@ -125,7 +125,7 @@ static const u32 ar955x_1p0_radio_core[]
|
|
{0x00016094, 0x00000000},
|
|
{0x000160a0, 0x0a108ffe},
|
|
{0x000160a4, 0x812fc370},
|
|
- {0x000160a8, 0x423c8000},
|
|
+ {0x000160a8, 0x423c8100},
|
|
{0x000160b4, 0x92480080},
|
|
{0x000160c0, 0x006db6d0},
|
|
{0x000160c4, 0x6db6db60},
|
|
@@ -134,7 +134,7 @@ static const u32 ar955x_1p0_radio_core[]
|
|
{0x00016100, 0x11999601},
|
|
{0x00016108, 0x00080010},
|
|
{0x00016144, 0x02084080},
|
|
- {0x00016148, 0x000080c0},
|
|
+ {0x00016148, 0x00008040},
|
|
{0x00016280, 0x01800804},
|
|
{0x00016284, 0x00038dc5},
|
|
{0x00016288, 0x00000000},
|
|
@@ -178,7 +178,7 @@ static const u32 ar955x_1p0_radio_core[]
|
|
{0x00016500, 0x11999601},
|
|
{0x00016508, 0x00080010},
|
|
{0x00016544, 0x02084080},
|
|
- {0x00016548, 0x000080c0},
|
|
+ {0x00016548, 0x00008040},
|
|
{0x00016780, 0x00000000},
|
|
{0x00016784, 0x00000000},
|
|
{0x00016788, 0x00400705},
|
|
@@ -218,7 +218,7 @@ static const u32 ar955x_1p0_radio_core[]
|
|
{0x00016900, 0x11999601},
|
|
{0x00016908, 0x00080010},
|
|
{0x00016944, 0x02084080},
|
|
- {0x00016948, 0x000080c0},
|
|
+ {0x00016948, 0x00008040},
|
|
{0x00016b80, 0x00000000},
|
|
{0x00016b84, 0x00000000},
|
|
{0x00016b88, 0x00400705},
|
|
@@ -245,9 +245,9 @@ static const u32 ar955x_1p0_radio_core[]
|
|
|
|
static const u32 ar955x_1p0_modes_xpa_tx_gain_table[][9] = {
|
|
/* Addr 5G_HT20_L 5G_HT40_L 5G_HT20_M 5G_HT40_M 5G_HT20_H 5G_HT40_H 2G_HT40 2G_HT20 */
|
|
- {0x0000a2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
- {0x0000a2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
- {0x0000a2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
|
|
+ {0x0000a2dc, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
+ {0x0000a2e0, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
+ {0x0000a2e4, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffffe0f0, 0xffffe0f0},
|
|
{0x0000a2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
|
|
{0x0000a410, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050da, 0x000050da},
|
|
{0x0000a500, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000000, 0x00000000},
|
|
@@ -256,63 +256,63 @@ static const u32 ar955x_1p0_modes_xpa_tx
|
|
{0x0000a50c, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c000006, 0x0c000006},
|
|
{0x0000a510, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x0f00000a, 0x0f00000a},
|
|
{0x0000a514, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x1300000c, 0x1300000c},
|
|
- {0x0000a518, 0x19004008, 0x19004008, 0x19004008, 0x19004008, 0x18004008, 0x18004008, 0x1700000e, 0x1700000e},
|
|
- {0x0000a51c, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1c00400a, 0x1c00400a, 0x1b000064, 0x1b000064},
|
|
- {0x0000a520, 0x230020a2, 0x230020a2, 0x210020a2, 0x210020a2, 0x200020a2, 0x200020a2, 0x1f000242, 0x1f000242},
|
|
- {0x0000a524, 0x2500006e, 0x2500006e, 0x2500006e, 0x2500006e, 0x2400006e, 0x2400006e, 0x23000229, 0x23000229},
|
|
- {0x0000a528, 0x29022221, 0x29022221, 0x28022221, 0x28022221, 0x27022221, 0x27022221, 0x270002a2, 0x270002a2},
|
|
- {0x0000a52c, 0x2d00062a, 0x2d00062a, 0x2c00062a, 0x2c00062a, 0x2a00062a, 0x2a00062a, 0x2c001203, 0x2c001203},
|
|
- {0x0000a530, 0x340220a5, 0x340220a5, 0x320220a5, 0x320220a5, 0x2f0220a5, 0x2f0220a5, 0x30001803, 0x30001803},
|
|
- {0x0000a534, 0x380022c5, 0x380022c5, 0x350022c5, 0x350022c5, 0x320022c5, 0x320022c5, 0x33000881, 0x33000881},
|
|
- {0x0000a538, 0x3b002486, 0x3b002486, 0x39002486, 0x39002486, 0x36002486, 0x36002486, 0x38001809, 0x38001809},
|
|
- {0x0000a53c, 0x3f00248a, 0x3f00248a, 0x3d00248a, 0x3d00248a, 0x3a00248a, 0x3a00248a, 0x3a000814, 0x3a000814},
|
|
- {0x0000a540, 0x4202242c, 0x4202242c, 0x4102242c, 0x4102242c, 0x3f02242c, 0x3f02242c, 0x3f001a0c, 0x3f001a0c},
|
|
- {0x0000a544, 0x490044c6, 0x490044c6, 0x460044c6, 0x460044c6, 0x420044c6, 0x420044c6, 0x43001a0e, 0x43001a0e},
|
|
- {0x0000a548, 0x4d024485, 0x4d024485, 0x4a024485, 0x4a024485, 0x46024485, 0x46024485, 0x46001812, 0x46001812},
|
|
- {0x0000a54c, 0x51044483, 0x51044483, 0x4e044483, 0x4e044483, 0x4a044483, 0x4a044483, 0x49001884, 0x49001884},
|
|
- {0x0000a550, 0x5404a40c, 0x5404a40c, 0x5204a40c, 0x5204a40c, 0x4d04a40c, 0x4d04a40c, 0x4d001e84, 0x4d001e84},
|
|
- {0x0000a554, 0x57024632, 0x57024632, 0x55024632, 0x55024632, 0x52024632, 0x52024632, 0x50001e69, 0x50001e69},
|
|
- {0x0000a558, 0x5c00a634, 0x5c00a634, 0x5900a634, 0x5900a634, 0x5600a634, 0x5600a634, 0x550006f4, 0x550006f4},
|
|
- {0x0000a55c, 0x5f026832, 0x5f026832, 0x5d026832, 0x5d026832, 0x5a026832, 0x5a026832, 0x59000ad3, 0x59000ad3},
|
|
- {0x0000a560, 0x6602b012, 0x6602b012, 0x6202b012, 0x6202b012, 0x5d02b012, 0x5d02b012, 0x5e000ad5, 0x5e000ad5},
|
|
- {0x0000a564, 0x6e02d0e1, 0x6e02d0e1, 0x6802d0e1, 0x6802d0e1, 0x6002d0e1, 0x6002d0e1, 0x61001ced, 0x61001ced},
|
|
- {0x0000a568, 0x7202b4c4, 0x7202b4c4, 0x6c02b4c4, 0x6c02b4c4, 0x6502b4c4, 0x6502b4c4, 0x660018d4, 0x660018d4},
|
|
- {0x0000a56c, 0x75007894, 0x75007894, 0x70007894, 0x70007894, 0x6b007894, 0x6b007894, 0x660018d4, 0x660018d4},
|
|
- {0x0000a570, 0x7b025c74, 0x7b025c74, 0x75025c74, 0x75025c74, 0x70025c74, 0x70025c74, 0x660018d4, 0x660018d4},
|
|
- {0x0000a574, 0x8300bcb5, 0x8300bcb5, 0x7a00bcb5, 0x7a00bcb5, 0x7600bcb5, 0x7600bcb5, 0x660018d4, 0x660018d4},
|
|
- {0x0000a578, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
|
|
- {0x0000a57c, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a518, 0x1700002b, 0x1700002b, 0x1700002b, 0x1700002b, 0x1600002b, 0x1600002b, 0x1700000e, 0x1700000e},
|
|
+ {0x0000a51c, 0x1b00002d, 0x1b00002d, 0x1b00002d, 0x1b00002d, 0x1a00002d, 0x1a00002d, 0x1b000064, 0x1b000064},
|
|
+ {0x0000a520, 0x20000031, 0x20000031, 0x1f000031, 0x1f000031, 0x1e000031, 0x1e000031, 0x1f000242, 0x1f000242},
|
|
+ {0x0000a524, 0x24000051, 0x24000051, 0x23000051, 0x23000051, 0x23000051, 0x23000051, 0x23000229, 0x23000229},
|
|
+ {0x0000a528, 0x27000071, 0x27000071, 0x27000071, 0x27000071, 0x26000071, 0x26000071, 0x270002a2, 0x270002a2},
|
|
+ {0x0000a52c, 0x2b000092, 0x2b000092, 0x2b000092, 0x2b000092, 0x2b000092, 0x2b000092, 0x2c001203, 0x2c001203},
|
|
+ {0x0000a530, 0x3000028c, 0x3000028c, 0x2f00028c, 0x2f00028c, 0x2e00028c, 0x2e00028c, 0x30001803, 0x30001803},
|
|
+ {0x0000a534, 0x34000290, 0x34000290, 0x33000290, 0x33000290, 0x32000290, 0x32000290, 0x33000881, 0x33000881},
|
|
+ {0x0000a538, 0x37000292, 0x37000292, 0x36000292, 0x36000292, 0x35000292, 0x35000292, 0x38001809, 0x38001809},
|
|
+ {0x0000a53c, 0x3b02028d, 0x3b02028d, 0x3a02028d, 0x3a02028d, 0x3902028d, 0x3902028d, 0x3a000814, 0x3a000814},
|
|
+ {0x0000a540, 0x3f020291, 0x3f020291, 0x3e020291, 0x3e020291, 0x3d020291, 0x3d020291, 0x3f001a0c, 0x3f001a0c},
|
|
+ {0x0000a544, 0x44020490, 0x44020490, 0x43020490, 0x43020490, 0x42020490, 0x42020490, 0x43001a0e, 0x43001a0e},
|
|
+ {0x0000a548, 0x48020492, 0x48020492, 0x47020492, 0x47020492, 0x46020492, 0x46020492, 0x46001812, 0x46001812},
|
|
+ {0x0000a54c, 0x4c020692, 0x4c020692, 0x4b020692, 0x4b020692, 0x4a020692, 0x4a020692, 0x49001884, 0x49001884},
|
|
+ {0x0000a550, 0x50020892, 0x50020892, 0x4f020892, 0x4f020892, 0x4e020892, 0x4e020892, 0x4d001e84, 0x4d001e84},
|
|
+ {0x0000a554, 0x53040891, 0x53040891, 0x53040891, 0x53040891, 0x52040891, 0x52040891, 0x50001e69, 0x50001e69},
|
|
+ {0x0000a558, 0x58040893, 0x58040893, 0x57040893, 0x57040893, 0x56040893, 0x56040893, 0x550006f4, 0x550006f4},
|
|
+ {0x0000a55c, 0x5c0408b4, 0x5c0408b4, 0x5a0408b4, 0x5a0408b4, 0x5a0408b4, 0x5a0408b4, 0x59000ad3, 0x59000ad3},
|
|
+ {0x0000a560, 0x610408b6, 0x610408b6, 0x5e0408b6, 0x5e0408b6, 0x5e0408b6, 0x5e0408b6, 0x5e000ad5, 0x5e000ad5},
|
|
+ {0x0000a564, 0x670408f6, 0x670408f6, 0x620408f6, 0x620408f6, 0x620408f6, 0x620408f6, 0x61001ced, 0x61001ced},
|
|
+ {0x0000a568, 0x6a040cf6, 0x6a040cf6, 0x66040cf6, 0x66040cf6, 0x66040cf6, 0x66040cf6, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a56c, 0x6d040d76, 0x6d040d76, 0x6a040d76, 0x6a040d76, 0x6a040d76, 0x6a040d76, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a570, 0x70060db6, 0x70060db6, 0x6e060db6, 0x6e060db6, 0x6e060db6, 0x6e060db6, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a574, 0x730a0df6, 0x730a0df6, 0x720a0df6, 0x720a0df6, 0x720a0df6, 0x720a0df6, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a578, 0x770a13f6, 0x770a13f6, 0x760a13f6, 0x760a13f6, 0x760a13f6, 0x760a13f6, 0x660018d4, 0x660018d4},
|
|
+ {0x0000a57c, 0x770a13f6, 0x770a13f6, 0x760a13f6, 0x760a13f6, 0x760a13f6, 0x760a13f6, 0x660018d4, 0x660018d4},
|
|
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
- {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03804000, 0x03804000},
|
|
- {0x0000a610, 0x04c08c01, 0x04c08c01, 0x04808b01, 0x04808b01, 0x04808a01, 0x04808a01, 0x0300ca02, 0x0300ca02},
|
|
- {0x0000a614, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00000e04, 0x00000e04},
|
|
- {0x0000a618, 0x04010c01, 0x04010c01, 0x03c10b01, 0x03c10b01, 0x03810a01, 0x03810a01, 0x03014000, 0x03014000},
|
|
- {0x0000a61c, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x00000000, 0x00000000},
|
|
- {0x0000a620, 0x04010303, 0x04010303, 0x03c10303, 0x03c10303, 0x03810303, 0x03810303, 0x00000000, 0x00000000},
|
|
- {0x0000a624, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03014000, 0x03014000},
|
|
- {0x0000a628, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x03804c05, 0x03804c05},
|
|
- {0x0000a62c, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x0701de06, 0x0701de06},
|
|
- {0x0000a630, 0x03418000, 0x03418000, 0x03018000, 0x03018000, 0x02c18000, 0x02c18000, 0x07819c07, 0x07819c07},
|
|
- {0x0000a634, 0x03815004, 0x03815004, 0x03414f04, 0x03414f04, 0x03414e04, 0x03414e04, 0x0701dc07, 0x0701dc07},
|
|
- {0x0000a638, 0x03005302, 0x03005302, 0x02c05202, 0x02c05202, 0x02805202, 0x02805202, 0x0701dc07, 0x0701dc07},
|
|
- {0x0000a63c, 0x04c09302, 0x04c09302, 0x04809202, 0x04809202, 0x04809202, 0x04809202, 0x0701dc07, 0x0701dc07},
|
|
- {0x0000b2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
- {0x0000b2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
- {0x0000b2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
|
|
+ {0x0000a60c, 0x02c04b01, 0x02c04b01, 0x02c04b01, 0x02c04b01, 0x02c04b01, 0x02c04b01, 0x03804000, 0x03804000},
|
|
+ {0x0000a610, 0x04008b01, 0x04008b01, 0x04008b01, 0x04008b01, 0x03c08b01, 0x03c08b01, 0x0300ca02, 0x0300ca02},
|
|
+ {0x0000a614, 0x05811403, 0x05811403, 0x05411303, 0x05411303, 0x05411303, 0x05411303, 0x00000e04, 0x00000e04},
|
|
+ {0x0000a618, 0x05811604, 0x05811604, 0x05411504, 0x05411504, 0x05411504, 0x05411504, 0x03014000, 0x03014000},
|
|
+ {0x0000a61c, 0x05811604, 0x05811604, 0x05411504, 0x05411504, 0x05411504, 0x05411504, 0x00000000, 0x00000000},
|
|
+ {0x0000a620, 0x05811604, 0x05811604, 0x05411504, 0x05411504, 0x05411504, 0x05411504, 0x00000000, 0x00000000},
|
|
+ {0x0000a624, 0x05811604, 0x05811604, 0x05411504, 0x05411504, 0x05411504, 0x05411504, 0x03014000, 0x03014000},
|
|
+ {0x0000a628, 0x05811604, 0x05811604, 0x05411504, 0x05411504, 0x05411504, 0x05411504, 0x03804c05, 0x03804c05},
|
|
+ {0x0000a62c, 0x06815604, 0x06815604, 0x06415504, 0x06415504, 0x06015504, 0x06015504, 0x0701de06, 0x0701de06},
|
|
+ {0x0000a630, 0x07819a05, 0x07819a05, 0x07419905, 0x07419905, 0x07019805, 0x07019805, 0x07819c07, 0x07819c07},
|
|
+ {0x0000a634, 0x07819e06, 0x07819e06, 0x07419d06, 0x07419d06, 0x07019c06, 0x07019c06, 0x0701dc07, 0x0701dc07},
|
|
+ {0x0000a638, 0x07819e06, 0x07819e06, 0x07419d06, 0x07419d06, 0x07019c06, 0x07019c06, 0x0701dc07, 0x0701dc07},
|
|
+ {0x0000a63c, 0x07819e06, 0x07819e06, 0x07419d06, 0x07419d06, 0x07019c06, 0x07019c06, 0x0701dc07, 0x0701dc07},
|
|
+ {0x0000b2dc, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
+ {0x0000b2e0, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
+ {0x0000b2e4, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffffe0f0, 0xffffe0f0},
|
|
{0x0000b2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
|
|
- {0x0000c2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
- {0x0000c2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
- {0x0000c2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
|
|
+ {0x0000c2dc, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xffff6aaa, 0xfffd5aaa, 0xfffd5aaa},
|
|
+ {0x0000c2e0, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffdcccc, 0xfffe9ccc, 0xfffe9ccc},
|
|
+ {0x0000c2e4, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffe3b0f0, 0xffffe0f0, 0xffffe0f0},
|
|
{0x0000c2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
|
|
{0x00016044, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
|
|
- {0x00016048, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
|
|
+ {0x00016048, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
|
|
{0x00016280, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01808e84, 0x01808e84},
|
|
{0x00016444, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
|
|
- {0x00016448, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
|
|
+ {0x00016448, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
|
|
{0x00016844, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
|
|
- {0x00016848, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
|
|
+ {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
|
|
};
|
|
|
|
static const u32 ar955x_1p0_mac_core[][2] = {
|
|
@@ -846,7 +846,7 @@ static const u32 ar955x_1p0_baseband_cor
|
|
{0x0000a44c, 0x00000001},
|
|
{0x0000a450, 0x00010000},
|
|
{0x0000a458, 0x00000000},
|
|
- {0x0000a644, 0x3fad9d74},
|
|
+ {0x0000a644, 0xbfad9d74},
|
|
{0x0000a648, 0x0048060a},
|
|
{0x0000a64c, 0x00003c37},
|
|
{0x0000a670, 0x03020100},
|
|
@@ -1277,7 +1277,7 @@ static const u32 ar955x_1p0_modes_fast_c
|
|
{0x0000801c, 0x148ec02b, 0x148ec057},
|
|
{0x00008318, 0x000044c0, 0x00008980},
|
|
{0x00009e00, 0x0372131c, 0x0372131c},
|
|
- {0x0000a230, 0x0000000b, 0x00000016},
|
|
+ {0x0000a230, 0x0000400b, 0x00004016},
|
|
{0x0000a254, 0x00000898, 0x00001130},
|
|
};
|
|
|
|
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
|
|
@@ -347,6 +347,8 @@ void ath9k_htc_txcompletion_cb(struct ht
|
|
endpoint->ep_callbacks.tx(endpoint->ep_callbacks.priv,
|
|
skb, htc_hdr->endpoint_id,
|
|
txok);
|
|
+ } else {
|
|
+ kfree_skb(skb);
|
|
}
|
|
}
|
|
|
|
--- a/net/wireless/reg.c
|
|
+++ b/net/wireless/reg.c
|
|
@@ -142,8 +142,8 @@ static void rcu_free_regdom(const struct
|
|
|
|
static struct regulatory_request *get_last_request(void)
|
|
{
|
|
- return rcu_dereference_protected(last_request,
|
|
- lockdep_is_held(®_mutex));
|
|
+ return rcu_dereference_check(last_request,
|
|
+ lockdep_is_held(®_mutex));
|
|
}
|
|
|
|
/* Used to queue up regulatory hints */
|
|
@@ -1125,7 +1125,9 @@ static bool is_ht40_allowed(struct ieee8
|
|
if (chan->flags & IEEE80211_CHAN_DISABLED)
|
|
return false;
|
|
/* This would happen when regulatory rules disallow HT40 completely */
|
|
- return !(chan->flags & IEEE80211_CHAN_NO_HT40);
|
|
+ if ((chan->flags & IEEE80211_CHAN_NO_HT40) == IEEE80211_CHAN_NO_HT40)
|
|
+ return false;
|
|
+ return true;
|
|
}
|
|
|
|
static void reg_process_ht_flags_channel(struct wiphy *wiphy,
|
|
@@ -1850,7 +1852,7 @@ static void restore_regulatory_settings(
|
|
mutex_lock(&cfg80211_mutex);
|
|
mutex_lock(®_mutex);
|
|
|
|
- reset_regdomains(true, cfg80211_world_regdom);
|
|
+ reset_regdomains(true, &world_regdom);
|
|
restore_alpha2(alpha2, reset_user);
|
|
|
|
/*
|
|
@@ -2251,14 +2253,21 @@ int set_regdom(const struct ieee80211_re
|
|
|
|
int reg_device_uevent(struct device *dev, struct kobj_uevent_env *env)
|
|
{
|
|
- struct regulatory_request *lr = get_last_request();
|
|
+ struct regulatory_request *lr;
|
|
+ u8 alpha2[2];
|
|
+ bool add = false;
|
|
|
|
+ rcu_read_lock();
|
|
+ lr = get_last_request();
|
|
if (lr && !lr->processed) {
|
|
- if (add_uevent_var(env, "COUNTRY=%c%c",
|
|
- lr->alpha2[0], lr->alpha2[1]))
|
|
- return -ENOMEM;
|
|
+ memcpy(alpha2, lr->alpha2, 2);
|
|
+ add = true;
|
|
}
|
|
+ rcu_read_unlock();
|
|
|
|
+ if (add)
|
|
+ return add_uevent_var(env, "COUNTRY=%c%c",
|
|
+ alpha2[0], alpha2[1]);
|
|
return 0;
|
|
}
|
|
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
|
|
@@ -967,7 +967,7 @@ static bool ar9003_hw_init_cal(struct at
|
|
struct ath9k_hw_cal_data *caldata = ah->caldata;
|
|
bool txiqcal_done = false, txclcal_done = false;
|
|
bool is_reusable = true, status = true;
|
|
- bool run_rtt_cal = false, run_agc_cal;
|
|
+ bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
|
|
bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
|
|
u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
|
|
AR_PHY_AGC_CONTROL_FLTR_CAL |
|
|
@@ -977,6 +977,8 @@ static bool ar9003_hw_init_cal(struct at
|
|
AR_PHY_CL_TAB_1,
|
|
AR_PHY_CL_TAB_2 };
|
|
|
|
+ ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
|
|
+
|
|
if (rtt) {
|
|
if (!ar9003_hw_rtt_restore(ah, chan))
|
|
run_rtt_cal = true;
|
|
@@ -1013,7 +1015,8 @@ static bool ar9003_hw_init_cal(struct at
|
|
}
|
|
}
|
|
|
|
- if (!(ah->enabled_cals & TX_IQ_CAL))
|
|
+ if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
|
|
+ !(ah->enabled_cals & TX_IQ_CAL))
|
|
goto skip_tx_iqcal;
|
|
|
|
/* Do Tx IQ Calibration */
|
|
@@ -1033,21 +1036,22 @@ static bool ar9003_hw_init_cal(struct at
|
|
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
|
|
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
|
|
txiqcal_done = run_agc_cal = true;
|
|
- goto skip_tx_iqcal;
|
|
- } else if (caldata && !caldata->done_txiqcal_once)
|
|
+ } else if (caldata && !caldata->done_txiqcal_once) {
|
|
run_agc_cal = true;
|
|
+ sep_iq_cal = true;
|
|
+ }
|
|
|
|
+skip_tx_iqcal:
|
|
if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
|
|
ar9003_mci_init_cal_req(ah, &is_reusable);
|
|
|
|
- if (!(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))) {
|
|
+ if (sep_iq_cal) {
|
|
txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
|
|
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
|
|
udelay(5);
|
|
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
|
|
}
|
|
|
|
-skip_tx_iqcal:
|
|
if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
|
|
/* Calibrate the AGC */
|
|
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
|
|
@@ -744,6 +744,186 @@ static const u32 ar9300Modes_high_ob_db_
|
|
{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
};
|
|
|
|
+static const u32 ar9300Modes_mixed_ob_db_tx_gain_table_2p2[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
|
+ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
|
|
+ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
|
|
+ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
|
|
+ {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
|
|
+ {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
|
|
+ {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
|
|
+ {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
|
|
+ {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603},
|
|
+ {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02},
|
|
+ {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04},
|
|
+ {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x26000a20, 0x26000a20},
|
|
+ {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2a000e20, 0x2a000e20},
|
|
+ {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
|
|
+ {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
|
|
+ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
|
|
+ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
|
|
+ {0x0000a544, 0x52022470, 0x52022470, 0x3b001861, 0x3b001861},
|
|
+ {0x0000a548, 0x55022490, 0x55022490, 0x3e001a81, 0x3e001a81},
|
|
+ {0x0000a54c, 0x59022492, 0x59022492, 0x42001a83, 0x42001a83},
|
|
+ {0x0000a550, 0x5d022692, 0x5d022692, 0x44001c84, 0x44001c84},
|
|
+ {0x0000a554, 0x61022892, 0x61022892, 0x48001ce3, 0x48001ce3},
|
|
+ {0x0000a558, 0x65024890, 0x65024890, 0x4c001ce5, 0x4c001ce5},
|
|
+ {0x0000a55c, 0x69024892, 0x69024892, 0x50001ce9, 0x50001ce9},
|
|
+ {0x0000a560, 0x6e024c92, 0x6e024c92, 0x54001ceb, 0x54001ceb},
|
|
+ {0x0000a564, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a568, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a56c, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a570, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a574, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a578, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a57c, 0x74026e92, 0x74026e92, 0x56001eec, 0x56001eec},
|
|
+ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
|
|
+ {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
|
|
+ {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
|
|
+ {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
|
|
+ {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
|
|
+ {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
|
|
+ {0x0000a598, 0x21802220, 0x21802220, 0x15800402, 0x15800402},
|
|
+ {0x0000a59c, 0x27802223, 0x27802223, 0x19800404, 0x19800404},
|
|
+ {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
|
|
+ {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
|
|
+ {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
|
|
+ {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
|
|
+ {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
|
|
+ {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
|
|
+ {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
|
|
+ {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
|
|
+ {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
|
|
+ {0x0000a5c4, 0x52822470, 0x52822470, 0x3b801861, 0x3b801861},
|
|
+ {0x0000a5c8, 0x55822490, 0x55822490, 0x3e801a81, 0x3e801a81},
|
|
+ {0x0000a5cc, 0x59822492, 0x59822492, 0x42801a83, 0x42801a83},
|
|
+ {0x0000a5d0, 0x5d822692, 0x5d822692, 0x44801c84, 0x44801c84},
|
|
+ {0x0000a5d4, 0x61822892, 0x61822892, 0x48801ce3, 0x48801ce3},
|
|
+ {0x0000a5d8, 0x65824890, 0x65824890, 0x4c801ce5, 0x4c801ce5},
|
|
+ {0x0000a5dc, 0x69824892, 0x69824892, 0x50801ce9, 0x50801ce9},
|
|
+ {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x54801ceb, 0x54801ceb},
|
|
+ {0x0000a5e4, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5e8, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5ec, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5f0, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5f4, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5f8, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a5fc, 0x74826e92, 0x74826e92, 0x56801eec, 0x56801eec},
|
|
+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
|
|
+ {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
|
|
+ {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
|
|
+ {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
|
|
+ {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
|
|
+ {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
|
|
+ {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
|
|
+ {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
|
|
+ {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
|
|
+ {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
|
|
+ {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
|
|
+ {0x0000b2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000c2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x00016044, 0x012492d4, 0x012492d4, 0x056db2e4, 0x056db2e4},
|
|
+ {0x00016048, 0x66480001, 0x66480001, 0x8e480001, 0x8e480001},
|
|
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016444, 0x012492d4, 0x012492d4, 0x056db2e4, 0x056db2e4},
|
|
+ {0x00016448, 0x66480001, 0x66480001, 0x8e480001, 0x8e480001},
|
|
+ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016844, 0x012492d4, 0x012492d4, 0x056db2e4, 0x056db2e4},
|
|
+ {0x00016848, 0x66480001, 0x66480001, 0x8e480001, 0x8e480001},
|
|
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+};
|
|
+
|
|
+static const u32 ar9300Modes_type5_tx_gain_table_2p2[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
|
+ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
|
|
+ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
|
|
+ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
|
|
+ {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
|
|
+ {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
|
|
+ {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
|
|
+ {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
|
|
+ {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
|
|
+ {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
|
|
+ {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
|
|
+ {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
|
|
+ {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
|
|
+ {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
|
|
+ {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
|
|
+ {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
|
|
+ {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
|
|
+ {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
|
|
+ {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
|
|
+ {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
|
|
+ {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
|
|
+ {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
|
|
+ {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
|
|
+ {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
|
|
+ {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
|
|
+ {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
|
|
+ {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
|
|
+ {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
|
|
+ {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
|
|
+ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
|
|
+ {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
|
|
+ {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
|
|
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
|
|
+ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
|
|
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+};
|
|
+
|
|
static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
|
|
/* Addr allmodes */
|
|
{0x0000a000, 0x00010000},
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
|
|
@@ -507,28 +507,59 @@ static void ar9003_tx_gain_table_mode4(s
|
|
else if (AR_SREV_9580(ah))
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
ar9580_1p0_mixed_ob_db_tx_gain_table);
|
|
+ else
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
|
|
+}
|
|
+
|
|
+static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
|
|
+{
|
|
+ if (AR_SREV_9485_11(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9485Modes_green_ob_db_tx_gain_1_1);
|
|
+ else if (AR_SREV_9340(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9340Modes_ub124_tx_gain_table_1p0);
|
|
+ else if (AR_SREV_9580(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9580_1p0_type5_tx_gain_table);
|
|
+ else if (AR_SREV_9300_22(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9300Modes_type5_tx_gain_table_2p2);
|
|
+}
|
|
+
|
|
+static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
|
|
+{
|
|
+ if (AR_SREV_9340(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
|
|
+ else if (AR_SREV_9485_11(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9485Modes_green_spur_ob_db_tx_gain_1_1);
|
|
+ else if (AR_SREV_9580(ah))
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
+ ar9580_1p0_type6_tx_gain_table);
|
|
}
|
|
|
|
+typedef void (*ath_txgain_tab)(struct ath_hw *ah);
|
|
+
|
|
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
|
{
|
|
- switch (ar9003_hw_get_tx_gain_idx(ah)) {
|
|
- case 0:
|
|
- default:
|
|
- ar9003_tx_gain_table_mode0(ah);
|
|
- break;
|
|
- case 1:
|
|
- ar9003_tx_gain_table_mode1(ah);
|
|
- break;
|
|
- case 2:
|
|
- ar9003_tx_gain_table_mode2(ah);
|
|
- break;
|
|
- case 3:
|
|
- ar9003_tx_gain_table_mode3(ah);
|
|
- break;
|
|
- case 4:
|
|
- ar9003_tx_gain_table_mode4(ah);
|
|
- break;
|
|
- }
|
|
+ static const ath_txgain_tab modes[] = {
|
|
+ ar9003_tx_gain_table_mode0,
|
|
+ ar9003_tx_gain_table_mode1,
|
|
+ ar9003_tx_gain_table_mode2,
|
|
+ ar9003_tx_gain_table_mode3,
|
|
+ ar9003_tx_gain_table_mode4,
|
|
+ ar9003_tx_gain_table_mode5,
|
|
+ ar9003_tx_gain_table_mode6,
|
|
+ };
|
|
+ int idx = ar9003_hw_get_tx_gain_idx(ah);
|
|
+
|
|
+ if (idx >= ARRAY_SIZE(modes))
|
|
+ idx = 0;
|
|
+
|
|
+ modes[idx](ah);
|
|
}
|
|
|
|
static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
|
|
@@ -673,7 +704,7 @@ void ar9003_hw_attach_ops(struct ath_hw
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
|
|
- priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
|
|
+ ar9003_hw_init_mode_regs(ah);
|
|
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
|
|
|
|
ops->config_pci_powersave = ar9003_hw_configpcipowersave;
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
|
|
@@ -1172,6 +1172,106 @@ static const u32 ar9340Modes_mixed_ob_db
|
|
{0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
|
|
};
|
|
|
|
+static const u32 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03eaac5a, 0x03eaac5a},
|
|
+ {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03f330ac, 0x03f330ac},
|
|
+ {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03fc3f00, 0x03fc3f00},
|
|
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ffc000, 0x03ffc000},
|
|
+ {0x0000a394, 0x00000444, 0x00000444, 0x00000404, 0x00000404},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
|
+ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a504, 0x06000003, 0x06000003, 0x02000001, 0x02000001},
|
|
+ {0x0000a508, 0x0a000020, 0x0a000020, 0x05000003, 0x05000003},
|
|
+ {0x0000a50c, 0x10000023, 0x10000023, 0x0a000005, 0x0a000005},
|
|
+ {0x0000a510, 0x16000220, 0x16000220, 0x0e000201, 0x0e000201},
|
|
+ {0x0000a514, 0x1c000223, 0x1c000223, 0x11000203, 0x11000203},
|
|
+ {0x0000a518, 0x21002220, 0x21002220, 0x14000401, 0x14000401},
|
|
+ {0x0000a51c, 0x27002223, 0x27002223, 0x18000403, 0x18000403},
|
|
+ {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000602, 0x1b000602},
|
|
+ {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000802, 0x1f000802},
|
|
+ {0x0000a528, 0x34022225, 0x34022225, 0x21000620, 0x21000620},
|
|
+ {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x25000820, 0x25000820},
|
|
+ {0x0000a530, 0x3e02222c, 0x3e02222c, 0x29000822, 0x29000822},
|
|
+ {0x0000a534, 0x4202242a, 0x4202242a, 0x2d000824, 0x2d000824},
|
|
+ {0x0000a538, 0x4702244a, 0x4702244a, 0x30000828, 0x30000828},
|
|
+ {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x3400082a, 0x3400082a},
|
|
+ {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38000849, 0x38000849},
|
|
+ {0x0000a544, 0x5302266c, 0x5302266c, 0x3b000a2c, 0x3b000a2c},
|
|
+ {0x0000a548, 0x5702286c, 0x5702286c, 0x3e000e2b, 0x3e000e2b},
|
|
+ {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42000e2d, 0x42000e2d},
|
|
+ {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4500124a, 0x4500124a},
|
|
+ {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4900124c, 0x4900124c},
|
|
+ {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c00126c, 0x4c00126c},
|
|
+ {0x0000a55c, 0x7002708c, 0x7002708c, 0x4f00128c, 0x4f00128c},
|
|
+ {0x0000a560, 0x7302b08a, 0x7302b08a, 0x52001290, 0x52001290},
|
|
+ {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001292, 0x56001292},
|
|
+ {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
|
|
+ {0x0000a584, 0x06800003, 0x06800003, 0x02800001, 0x02800001},
|
|
+ {0x0000a588, 0x0a800020, 0x0a800020, 0x05800003, 0x05800003},
|
|
+ {0x0000a58c, 0x10800023, 0x10800023, 0x0a800005, 0x0a800005},
|
|
+ {0x0000a590, 0x16800220, 0x16800220, 0x0e800201, 0x0e800201},
|
|
+ {0x0000a594, 0x1c800223, 0x1c800223, 0x11800203, 0x11800203},
|
|
+ {0x0000a598, 0x21820220, 0x21820220, 0x14800401, 0x14800401},
|
|
+ {0x0000a59c, 0x27820223, 0x27820223, 0x18800403, 0x18800403},
|
|
+ {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800602, 0x1b800602},
|
|
+ {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800802, 0x1f800802},
|
|
+ {0x0000a5a8, 0x34822225, 0x34822225, 0x21800620, 0x21800620},
|
|
+ {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x25800820, 0x25800820},
|
|
+ {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x29800822, 0x29800822},
|
|
+ {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2d800824, 0x2d800824},
|
|
+ {0x0000a5b8, 0x4782244a, 0x4782244a, 0x30800828, 0x30800828},
|
|
+ {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x3480082a, 0x3480082a},
|
|
+ {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38800849, 0x38800849},
|
|
+ {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b800a2c, 0x3b800a2c},
|
|
+ {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e800e2b, 0x3e800e2b},
|
|
+ {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42800e2d, 0x42800e2d},
|
|
+ {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4580124a, 0x4580124a},
|
|
+ {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4980124c, 0x4980124c},
|
|
+ {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c80126c, 0x4c80126c},
|
|
+ {0x0000a5dc, 0x7086308c, 0x7086308c, 0x4f80128c, 0x4f80128c},
|
|
+ {0x0000a5e0, 0x738a308a, 0x738a308a, 0x52801290, 0x52801290},
|
|
+ {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801292, 0x56801292},
|
|
+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a614, 0x01404000, 0x01404000, 0x01404501, 0x01404501},
|
|
+ {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
|
|
+ {0x0000a61c, 0x02008802, 0x02008802, 0x01404501, 0x01404501},
|
|
+ {0x0000a620, 0x0300cc03, 0x0300cc03, 0x03c0cf02, 0x03c0cf02},
|
|
+ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03c0cf03, 0x03c0cf03},
|
|
+ {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04011004, 0x04011004},
|
|
+ {0x0000a62c, 0x03810c03, 0x03810c03, 0x05419405, 0x05419405},
|
|
+ {0x0000a630, 0x03810e04, 0x03810e04, 0x05419506, 0x05419506},
|
|
+ {0x0000a634, 0x03810e04, 0x03810e04, 0x05419506, 0x05419506},
|
|
+ {0x0000a638, 0x03810e04, 0x03810e04, 0x05419506, 0x05419506},
|
|
+ {0x0000a63c, 0x03810e04, 0x03810e04, 0x05419506, 0x05419506},
|
|
+ {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03eaac5a, 0x03eaac5a},
|
|
+ {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03f330ac, 0x03f330ac},
|
|
+ {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03fc3f00, 0x03fc3f00},
|
|
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ffc000, 0x03ffc000},
|
|
+ {0x00016044, 0x022492db, 0x022492db, 0x022492db, 0x022492db},
|
|
+ {0x00016048, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
|
|
+ {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
|
|
+ {0x00016288, 0xf0318000, 0xf0318000, 0xf0318000, 0xf0318000},
|
|
+ {0x00016444, 0x022492db, 0x022492db, 0x022492db, 0x022492db},
|
|
+ {0x00016448, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
|
|
+};
|
|
+
|
|
static const u32 ar9340_1p0_mac_core[][2] = {
|
|
/* Addr allmodes */
|
|
{0x00000008, 0x00000000},
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
|
|
@@ -260,6 +260,79 @@ static const u32 ar9485Modes_high_power_
|
|
{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
|
|
};
|
|
|
|
+static const u32 ar9485Modes_green_ob_db_tx_gain_1_1[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
|
|
+ {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
|
|
+ {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006},
|
|
+ {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201},
|
|
+ {0x0000a508, 0x0c002e00, 0x0c002e00, 0x06000203, 0x06000203},
|
|
+ {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401},
|
|
+ {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403},
|
|
+ {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405},
|
|
+ {0x0000a518, 0x25020ec0, 0x25020ec0, 0x15000604, 0x15000604},
|
|
+ {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x18000605, 0x18000605},
|
|
+ {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000a04, 0x1c000a04},
|
|
+ {0x0000a524, 0x35001fc4, 0x35001fc4, 0x21000a06, 0x21000a06},
|
|
+ {0x0000a528, 0x3c022f04, 0x3c022f04, 0x29000a24, 0x29000a24},
|
|
+ {0x0000a52c, 0x41023e85, 0x41023e85, 0x2f000e21, 0x2f000e21},
|
|
+ {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000e20, 0x31000e20},
|
|
+ {0x0000a534, 0x4d023f01, 0x4d023f01, 0x33000e20, 0x33000e20},
|
|
+ {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
|
|
+ {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
|
|
+ {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
|
|
+ {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
|
|
+ {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
|
|
+ {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
|
|
+ {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
|
|
+ {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
|
|
+ {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
|
|
+ {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
|
+ {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
|
|
+ {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
|
|
+ {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
|
|
+ {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
|
|
+ {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
|
|
+};
|
|
+
|
|
static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
|
|
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
|
|
@@ -450,6 +523,79 @@ static const u32 ar9485Modes_low_ob_db_t
|
|
|
|
#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
|
|
|
|
+static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
|
|
+ {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
|
|
+ {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006},
|
|
+ {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201},
|
|
+ {0x0000a508, 0x0c002e00, 0x0c002e00, 0x07000203, 0x07000203},
|
|
+ {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401},
|
|
+ {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403},
|
|
+ {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405},
|
|
+ {0x0000a518, 0x25020ec0, 0x25020ec0, 0x14000406, 0x14000406},
|
|
+ {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1800040a, 0x1800040a},
|
|
+ {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000460, 0x1c000460},
|
|
+ {0x0000a524, 0x35001fc4, 0x35001fc4, 0x22000463, 0x22000463},
|
|
+ {0x0000a528, 0x3c022f04, 0x3c022f04, 0x26000465, 0x26000465},
|
|
+ {0x0000a52c, 0x41023e85, 0x41023e85, 0x2e0006e0, 0x2e0006e0},
|
|
+ {0x0000a530, 0x48023ec6, 0x48023ec6, 0x310006e0, 0x310006e0},
|
|
+ {0x0000a534, 0x4d023f01, 0x4d023f01, 0x330006e0, 0x330006e0},
|
|
+ {0x0000a538, 0x53023f4b, 0x53023f4b, 0x3e0008e3, 0x3e0008e3},
|
|
+ {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x410008e5, 0x410008e5},
|
|
+ {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x430008e6, 0x430008e6},
|
|
+ {0x0000a544, 0x6502feca, 0x6502feca, 0x4a0008ec, 0x4a0008ec},
|
|
+ {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4e0008f1, 0x4e0008f1},
|
|
+ {0x0000a54c, 0x7203feca, 0x7203feca, 0x520008f3, 0x520008f3},
|
|
+ {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x54000eed, 0x54000eed},
|
|
+ {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x58000ef1, 0x58000ef1},
|
|
+ {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5c000ef3, 0x5c000ef3},
|
|
+ {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x60000ef5, 0x60000ef5},
|
|
+ {0x0000a560, 0x900fff0b, 0x900fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a564, 0x960fffcb, 0x960fffcb, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x62000ef6, 0x62000ef6},
|
|
+ {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
|
|
+ {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
|
|
+ {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
|
|
+ {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
|
|
+ {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
|
|
+ {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
|
|
+ {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
|
|
+};
|
|
+
|
|
static const u32 ar9485_1_1[][2] = {
|
|
/* Addr allmodes */
|
|
{0x0000a580, 0x00000000},
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
|
|
@@ -685,6 +685,82 @@ static const u32 ar9580_1p0_mixed_ob_db_
|
|
|
|
#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
|
|
|
|
+#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
|
|
+
|
|
+static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
|
|
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
|
+ {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
|
+ {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
|
|
+ {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
|
|
+ {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
|
|
+ {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
|
|
+ {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
|
|
+ {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
|
|
+ {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
|
|
+ {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
|
|
+ {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
|
|
+ {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
|
|
+ {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
|
|
+ {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
|
|
+ {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
|
|
+ {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
|
|
+ {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
|
|
+ {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
|
|
+ {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
|
|
+ {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
|
|
+ {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
|
|
+ {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
|
|
+ {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
|
|
+ {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
|
|
+ {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
|
|
+ {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
|
|
+ {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
|
+ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
|
+ {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
|
+ {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
|
|
+ {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
|
|
+ {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
|
|
+ {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
|
|
+ {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
|
|
+ {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
|
|
+ {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
|
+ {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
|
+ {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
|
+ {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
|
+ {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
|
+ {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
|
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
|
+ {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+ {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
|
+ {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
|
+ {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
|
+};
|
|
+
|
|
static const u32 ar9580_1p0_soc_preamble[][2] = {
|
|
/* Addr allmodes */
|
|
{0x000040a4, 0x00a0c1c9},
|
|
--- a/drivers/net/wireless/ath/ath9k/reg.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/reg.h
|
|
@@ -789,6 +789,7 @@
|
|
#define AR_SREV_REVISION_9271_11 1
|
|
#define AR_SREV_VERSION_9300 0x1c0
|
|
#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
|
|
+#define AR_SREV_REVISION_9300_22 3
|
|
#define AR_SREV_VERSION_9330 0x200
|
|
#define AR_SREV_REVISION_9330_10 0
|
|
#define AR_SREV_REVISION_9330_11 1
|
|
@@ -869,6 +870,9 @@
|
|
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
|
|
#define AR_SREV_9300_20_OR_LATER(_ah) \
|
|
((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
|
|
+#define AR_SREV_9300_22(_ah) \
|
|
+ (AR_SREV_9300(ah) && \
|
|
+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_22))
|
|
|
|
#define AR_SREV_9330(_ah) \
|
|
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
|
|
--- a/net/mac80211/mlme.c
|
|
+++ b/net/mac80211/mlme.c
|
|
@@ -199,11 +199,11 @@ static u32 ieee80211_config_ht_tx(struct
|
|
case NL80211_CHAN_WIDTH_40:
|
|
if (sdata->vif.bss_conf.chandef.chan->center_freq >
|
|
sdata->vif.bss_conf.chandef.center_freq1 &&
|
|
- chan->flags & IEEE80211_CHAN_NO_HT40PLUS)
|
|
+ chan->flags & IEEE80211_CHAN_NO_HT40MINUS)
|
|
disable_40 = true;
|
|
if (sdata->vif.bss_conf.chandef.chan->center_freq <
|
|
sdata->vif.bss_conf.chandef.center_freq1 &&
|
|
- chan->flags & IEEE80211_CHAN_NO_HT40MINUS)
|
|
+ chan->flags & IEEE80211_CHAN_NO_HT40PLUS)
|
|
disable_40 = true;
|
|
break;
|
|
default:
|
|
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
|
|
@@ -18,6 +18,7 @@
|
|
#include "hw-ops.h"
|
|
#include "../regd.h"
|
|
#include "ar9002_phy.h"
|
|
+#include "ar5008_initvals.h"
|
|
|
|
/* All code below is for AR5008, AR9001, AR9002 */
|
|
|
|
@@ -43,23 +44,16 @@ static const int m2ThreshLowExt_off = 12
|
|
static const int m1ThreshExt_off = 127;
|
|
static const int m2ThreshExt_off = 127;
|
|
|
|
+static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
|
|
+static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
|
|
+static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
|
|
+static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
|
|
+static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
|
|
|
|
-static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
|
|
- int col)
|
|
-{
|
|
- int i;
|
|
-
|
|
- for (i = 0; i < array->ia_rows; i++)
|
|
- bank[i] = INI_RA(array, i, col);
|
|
-}
|
|
-
|
|
-
|
|
-#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
|
|
- ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
|
|
-
|
|
-static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
|
|
- u32 *data, unsigned int *writecnt)
|
|
+static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
|
|
{
|
|
+ struct ar5416IniArray *array = &ah->iniBank6;
|
|
+ u32 *data = ah->analogBank6Data;
|
|
int r;
|
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
@@ -165,7 +159,7 @@ static void ar5008_hw_force_bias(struct
|
|
ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
|
|
|
|
/* write Bank 6 with new params */
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
|
|
+ ar5008_write_bank6(ah, ®_writes);
|
|
}
|
|
|
|
/**
|
|
@@ -469,31 +463,16 @@ static void ar5008_hw_spur_mitigate(stru
|
|
*/
|
|
static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
|
|
{
|
|
-#define ATH_ALLOC_BANK(bank, size) do { \
|
|
- bank = devm_kzalloc(ah->dev, sizeof(u32) * size, GFP_KERNEL); \
|
|
- if (!bank) \
|
|
- goto error; \
|
|
- } while (0);
|
|
-
|
|
- struct ath_common *common = ath9k_hw_common(ah);
|
|
+ int size = ah->iniBank6.ia_rows * sizeof(u32);
|
|
|
|
if (AR_SREV_9280_20_OR_LATER(ah))
|
|
return 0;
|
|
|
|
- ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
|
|
- ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
|
|
+ ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
|
|
+ if (!ah->analogBank6Data)
|
|
+ return -ENOMEM;
|
|
|
|
return 0;
|
|
-#undef ATH_ALLOC_BANK
|
|
-error:
|
|
- ath_err(common, "Cannot allocate RF banks\n");
|
|
- return -ENOMEM;
|
|
}
|
|
|
|
|
|
@@ -517,6 +496,7 @@ static bool ar5008_hw_set_rf_regs(struct
|
|
u32 ob5GHz = 0, db5GHz = 0;
|
|
u32 ob2GHz = 0, db2GHz = 0;
|
|
int regWrites = 0;
|
|
+ int i;
|
|
|
|
/*
|
|
* Software does not need to program bank data
|
|
@@ -529,25 +509,8 @@ static bool ar5008_hw_set_rf_regs(struct
|
|
/* Setup rf parameters */
|
|
eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
|
|
|
|
- /* Setup Bank 0 Write */
|
|
- ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
|
|
-
|
|
- /* Setup Bank 1 Write */
|
|
- ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
|
|
-
|
|
- /* Setup Bank 2 Write */
|
|
- ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
|
|
-
|
|
- /* Setup Bank 6 Write */
|
|
- ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
|
|
- modesIndex);
|
|
- {
|
|
- int i;
|
|
- for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
|
|
- ah->analogBank6Data[i] =
|
|
- INI_RA(&ah->iniBank6TPC, i, modesIndex);
|
|
- }
|
|
- }
|
|
+ for (i = 0; i < ah->iniBank6.ia_rows; i++)
|
|
+ ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
|
|
|
|
/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
|
|
if (eepMinorRev >= 2) {
|
|
@@ -568,22 +531,13 @@ static bool ar5008_hw_set_rf_regs(struct
|
|
}
|
|
}
|
|
|
|
- /* Setup Bank 7 Setup */
|
|
- ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
|
|
-
|
|
/* Write Analog registers */
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
|
|
- regWrites);
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
|
|
- regWrites);
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
|
|
- regWrites);
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
|
|
- regWrites);
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
|
|
- regWrites);
|
|
- REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
|
|
- regWrites);
|
|
+ REG_WRITE_ARRAY(&bank0, 1, regWrites);
|
|
+ REG_WRITE_ARRAY(&bank1, 1, regWrites);
|
|
+ REG_WRITE_ARRAY(&bank2, 1, regWrites);
|
|
+ REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
|
|
+ ar5008_write_bank6(ah, ®Writes);
|
|
+ REG_WRITE_ARRAY(&bank7, 1, regWrites);
|
|
|
|
return true;
|
|
}
|
|
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
|
|
@@ -23,13 +23,13 @@
|
|
|
|
/* General hardware code for the A5008/AR9001/AR9002 hadware families */
|
|
|
|
-static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
|
|
+static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9271(ah)) {
|
|
INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
|
|
INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
|
|
INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
|
|
- return;
|
|
+ return 0;
|
|
}
|
|
|
|
if (ah->config.pcie_clock_req)
|
|
@@ -67,12 +67,10 @@ static void ar9002_hw_init_mode_regs(str
|
|
} else if (AR_SREV_9100_OR_LATER(ah)) {
|
|
INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
|
|
INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
|
|
- INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
|
|
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
|
|
} else {
|
|
INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
|
|
INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
|
|
- INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
|
|
INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
|
|
}
|
|
|
|
@@ -80,20 +78,11 @@ static void ar9002_hw_init_mode_regs(str
|
|
/* Common for AR5416, AR913x, AR9160 */
|
|
INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
|
|
|
|
- INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
|
|
- INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
|
|
- INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
|
|
- INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
|
|
- INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
|
|
-
|
|
- /* Common for AR5416, AR9160 */
|
|
- if (!AR_SREV_9100(ah))
|
|
- INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
|
|
-
|
|
/* Common for AR913x, AR9160 */
|
|
if (!AR_SREV_5416(ah))
|
|
- INIT_INI_ARRAY(&ah->iniBank6TPC,
|
|
- ar5416Bank6TPC_9100);
|
|
+ INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
|
|
+ else
|
|
+ INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
|
|
}
|
|
|
|
/* iniAddac needs to be modified for these chips */
|
|
@@ -104,7 +93,7 @@ static void ar9002_hw_init_mode_regs(str
|
|
|
|
data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
|
|
if (!data)
|
|
- return;
|
|
+ return -ENOMEM;
|
|
|
|
memcpy(data, addac->ia_array, size);
|
|
addac->ia_array = data;
|
|
@@ -120,6 +109,7 @@ static void ar9002_hw_init_mode_regs(str
|
|
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
|
ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
|
|
}
|
|
+ return 0;
|
|
}
|
|
|
|
static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
|
|
@@ -415,7 +405,10 @@ int ar9002_hw_attach_ops(struct ath_hw *
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
int ret;
|
|
|
|
- priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
|
|
+ ret = ar9002_hw_init_mode_regs(ah);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
|
|
|
|
ops->config_pci_powersave = ar9002_hw_configpcipowersave;
|
|
--- a/drivers/net/wireless/ath/ath9k/hw.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/hw.c
|
|
@@ -54,11 +54,6 @@ static void ath9k_hw_init_cal_settings(s
|
|
ath9k_hw_private_ops(ah)->init_cal_settings(ah);
|
|
}
|
|
|
|
-static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
|
|
-{
|
|
- ath9k_hw_private_ops(ah)->init_mode_regs(ah);
|
|
-}
|
|
-
|
|
static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
|
|
struct ath9k_channel *chan)
|
|
{
|
|
@@ -208,7 +203,7 @@ void ath9k_hw_synth_delay(struct ath_hw
|
|
udelay(hw_delay + BASE_ACTIVATE_DELAY);
|
|
}
|
|
|
|
-void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
|
|
+void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
|
|
int column, unsigned int *writecnt)
|
|
{
|
|
int r;
|
|
@@ -554,10 +549,8 @@ static int ath9k_hw_post_init(struct ath
|
|
ah->eep_ops->get_eeprom_ver(ah),
|
|
ah->eep_ops->get_eeprom_rev(ah));
|
|
|
|
- if (ah->config.enable_ani) {
|
|
- ath9k_hw_ani_setup(ah);
|
|
+ if (ah->config.enable_ani)
|
|
ath9k_hw_ani_init(ah);
|
|
- }
|
|
|
|
return 0;
|
|
}
|
|
@@ -670,8 +663,6 @@ static int __ath9k_hw_init(struct ath_hw
|
|
if (!AR_SREV_9300_20_OR_LATER(ah))
|
|
ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
|
|
|
|
- ath9k_hw_init_mode_regs(ah);
|
|
-
|
|
if (!ah->is_pciexpress)
|
|
ath9k_hw_disablepcie(ah);
|
|
|
|
--- a/drivers/net/wireless/ath/ath9k/hw.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/hw.h
|
|
@@ -599,7 +599,6 @@ struct ath_hw_radar_conf {
|
|
* @init_cal_settings: setup types of calibrations supported
|
|
* @init_cal: starts actual calibration
|
|
*
|
|
- * @init_mode_regs: Initializes mode registers
|
|
* @init_mode_gain_regs: Initialize TX/RX gain registers
|
|
*
|
|
* @rf_set_freq: change frequency
|
|
@@ -618,7 +617,6 @@ struct ath_hw_private_ops {
|
|
void (*init_cal_settings)(struct ath_hw *ah);
|
|
bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
|
|
- void (*init_mode_regs)(struct ath_hw *ah);
|
|
void (*init_mode_gain_regs)(struct ath_hw *ah);
|
|
void (*setup_calibration)(struct ath_hw *ah,
|
|
struct ath9k_cal_list *currCal);
|
|
@@ -810,14 +808,7 @@ struct ath_hw {
|
|
struct ath_hw_ops ops;
|
|
|
|
/* Used to program the radio on non single-chip devices */
|
|
- u32 *analogBank0Data;
|
|
- u32 *analogBank1Data;
|
|
- u32 *analogBank2Data;
|
|
- u32 *analogBank3Data;
|
|
u32 *analogBank6Data;
|
|
- u32 *analogBank6TPCData;
|
|
- u32 *analogBank7Data;
|
|
- u32 *bank6Temp;
|
|
|
|
int coverage_class;
|
|
u32 slottime;
|
|
@@ -826,10 +817,6 @@ struct ath_hw {
|
|
/* ANI */
|
|
u32 proc_phyerr;
|
|
u32 aniperiod;
|
|
- int totalSizeDesired[5];
|
|
- int coarse_high[5];
|
|
- int coarse_low[5];
|
|
- int firpwr[5];
|
|
enum ath9k_ani_cmd ani_function;
|
|
u32 ani_skip_count;
|
|
|
|
@@ -852,14 +839,8 @@ struct ath_hw {
|
|
|
|
struct ar5416IniArray iniModes;
|
|
struct ar5416IniArray iniCommon;
|
|
- struct ar5416IniArray iniBank0;
|
|
struct ar5416IniArray iniBB_RfGain;
|
|
- struct ar5416IniArray iniBank1;
|
|
- struct ar5416IniArray iniBank2;
|
|
- struct ar5416IniArray iniBank3;
|
|
struct ar5416IniArray iniBank6;
|
|
- struct ar5416IniArray iniBank6TPC;
|
|
- struct ar5416IniArray iniBank7;
|
|
struct ar5416IniArray iniAddac;
|
|
struct ar5416IniArray iniPcieSerdes;
|
|
#ifdef CONFIG_PM_SLEEP
|
|
@@ -975,7 +956,7 @@ void ath9k_hw_setantenna(struct ath_hw *
|
|
void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
int hw_delay);
|
|
bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
|
|
-void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
|
|
+void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
|
|
int column, unsigned int *writecnt);
|
|
u32 ath9k_hw_reverse_bits(u32 val, u32 n);
|
|
u16 ath9k_hw_computetxtime(struct ath_hw *ah,
|
|
@@ -1062,6 +1043,7 @@ void ar9003_paprd_setup_gain_table(struc
|
|
int ar9003_paprd_init_table(struct ath_hw *ah);
|
|
bool ar9003_paprd_is_done(struct ath_hw *ah);
|
|
bool ar9003_is_paprd_enabled(struct ath_hw *ah);
|
|
+void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
|
|
|
|
/* Hardware family op attach helpers */
|
|
int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
|
|
--- a/net/mac80211/tx.c
|
|
+++ b/net/mac80211/tx.c
|
|
@@ -1677,10 +1677,10 @@ netdev_tx_t ieee80211_monitor_start_xmit
|
|
chanctx_conf =
|
|
rcu_dereference(tmp_sdata->vif.chanctx_conf);
|
|
}
|
|
- if (!chanctx_conf)
|
|
- goto fail_rcu;
|
|
-
|
|
- chan = chanctx_conf->def.chan;
|
|
+ if (chanctx_conf)
|
|
+ chan = chanctx_conf->def.chan;
|
|
+ else
|
|
+ chan = local->_oper_channel;
|
|
|
|
/*
|
|
* Frame injection is not allowed if beaconing is not allowed
|
|
--- a/drivers/net/wireless/ath/ath9k/ani.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/ani.c
|
|
@@ -152,7 +152,8 @@ static void ath9k_hw_set_ofdm_nil(struct
|
|
ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
|
|
aniState->ofdmNoiseImmunityLevel,
|
|
immunityLevel, BEACON_RSSI(ah),
|
|
- aniState->rssiThrLow, aniState->rssiThrHigh);
|
|
+ ATH9K_ANI_RSSI_THR_LOW,
|
|
+ ATH9K_ANI_RSSI_THR_HIGH);
|
|
|
|
if (!scan)
|
|
aniState->ofdmNoiseImmunityLevel = immunityLevel;
|
|
@@ -173,7 +174,7 @@ static void ath9k_hw_set_ofdm_nil(struct
|
|
|
|
weak_sig = entry_ofdm->ofdm_weak_signal_on;
|
|
if (ah->opmode == NL80211_IFTYPE_STATION &&
|
|
- BEACON_RSSI(ah) <= aniState->rssiThrHigh)
|
|
+ BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH)
|
|
weak_sig = true;
|
|
|
|
if (aniState->ofdmWeakSigDetect != weak_sig)
|
|
@@ -216,11 +217,11 @@ static void ath9k_hw_set_cck_nil(struct
|
|
|
|
ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
|
|
aniState->cckNoiseImmunityLevel, immunityLevel,
|
|
- BEACON_RSSI(ah), aniState->rssiThrLow,
|
|
- aniState->rssiThrHigh);
|
|
+ BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW,
|
|
+ ATH9K_ANI_RSSI_THR_HIGH);
|
|
|
|
if (ah->opmode == NL80211_IFTYPE_STATION &&
|
|
- BEACON_RSSI(ah) <= aniState->rssiThrLow &&
|
|
+ BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW &&
|
|
immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
|
|
immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
|
|
|
|
@@ -418,9 +419,6 @@ void ath9k_hw_ani_monitor(struct ath_hw
|
|
return;
|
|
|
|
aniState = &ah->curchan->ani;
|
|
- if (WARN_ON(!aniState))
|
|
- return;
|
|
-
|
|
if (!ath9k_hw_ani_read_counters(ah))
|
|
return;
|
|
|
|
@@ -489,23 +487,6 @@ void ath9k_hw_disable_mib_counters(struc
|
|
}
|
|
EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
|
|
|
|
-void ath9k_hw_ani_setup(struct ath_hw *ah)
|
|
-{
|
|
- int i;
|
|
-
|
|
- static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
|
|
- static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
|
|
- static const int coarseLow[] = { -64, -64, -64, -64, -70 };
|
|
- static const int firpwr[] = { -78, -78, -78, -78, -80 };
|
|
-
|
|
- for (i = 0; i < 5; i++) {
|
|
- ah->totalSizeDesired[i] = totalSizeDesired[i];
|
|
- ah->coarse_high[i] = coarseHigh[i];
|
|
- ah->coarse_low[i] = coarseLow[i];
|
|
- ah->firpwr[i] = firpwr[i];
|
|
- }
|
|
-}
|
|
-
|
|
void ath9k_hw_ani_init(struct ath_hw *ah)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
@@ -531,8 +512,6 @@ void ath9k_hw_ani_init(struct ath_hw *ah
|
|
|
|
ani->ofdmsTurn = true;
|
|
|
|
- ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
|
|
- ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
|
|
ani->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
|
|
ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
|
|
ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
|
|
--- a/drivers/net/wireless/ath/ath9k/ani.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/ani.h
|
|
@@ -104,7 +104,6 @@ struct ath9k_ani_default {
|
|
};
|
|
|
|
struct ar5416AniState {
|
|
- struct ath9k_channel *c;
|
|
u8 noiseImmunityLevel;
|
|
u8 ofdmNoiseImmunityLevel;
|
|
u8 cckNoiseImmunityLevel;
|
|
@@ -113,15 +112,9 @@ struct ar5416AniState {
|
|
u8 spurImmunityLevel;
|
|
u8 firstepLevel;
|
|
u8 ofdmWeakSigDetect;
|
|
- u8 cckWeakSigThreshold;
|
|
u32 listenTime;
|
|
- int32_t rssiThrLow;
|
|
- int32_t rssiThrHigh;
|
|
u32 ofdmPhyErrCount;
|
|
u32 cckPhyErrCount;
|
|
- int16_t pktRssi[2];
|
|
- int16_t ofdmErrRssi[2];
|
|
- int16_t cckErrRssi[2];
|
|
struct ath9k_ani_default iniDef;
|
|
};
|
|
|
|
@@ -147,7 +140,6 @@ struct ar5416Stats {
|
|
|
|
void ath9k_enable_mib_counters(struct ath_hw *ah);
|
|
void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
|
|
-void ath9k_hw_ani_setup(struct ath_hw *ah);
|
|
void ath9k_hw_ani_init(struct ath_hw *ah);
|
|
|
|
#endif /* ANI_H */
|
|
--- a/drivers/net/wireless/ath/ath9k/calib.h
|
|
+++ b/drivers/net/wireless/ath/ath9k/calib.h
|
|
@@ -33,6 +33,12 @@ struct ar5416IniArray {
|
|
u32 ia_columns;
|
|
};
|
|
|
|
+#define STATIC_INI_ARRAY(array) { \
|
|
+ .ia_array = (u32 *)(array), \
|
|
+ .ia_rows = ARRAY_SIZE(array), \
|
|
+ .ia_columns = ARRAY_SIZE(array[0]), \
|
|
+ }
|
|
+
|
|
#define INIT_INI_ARRAY(iniarray, array) do { \
|
|
(iniarray)->ia_array = (u32 *)(array); \
|
|
(iniarray)->ia_rows = ARRAY_SIZE(array); \
|
|
--- a/drivers/net/wireless/ath/ath9k/xmit.c
|
|
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
|
|
@@ -378,7 +378,7 @@ static void ath_tx_count_frames(struct a
|
|
|
|
static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
|
|
struct ath_buf *bf, struct list_head *bf_q,
|
|
- struct ath_tx_status *ts, int txok, bool retry)
|
|
+ struct ath_tx_status *ts, int txok)
|
|
{
|
|
struct ath_node *an = NULL;
|
|
struct sk_buff *skb;
|
|
@@ -490,7 +490,7 @@ static void ath_tx_complete_aggr(struct
|
|
} else if (!isaggr && txok) {
|
|
/* transmit completion */
|
|
acked_cnt++;
|
|
- } else if ((tid->state & AGGR_CLEANUP) || !retry) {
|
|
+ } else if (tid->state & AGGR_CLEANUP) {
|
|
/*
|
|
* cleanup in progress, just fail
|
|
* the un-acked sub-frames
|
|
@@ -604,6 +604,37 @@ static void ath_tx_complete_aggr(struct
|
|
ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
|
|
}
|
|
|
|
+static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
|
|
+{
|
|
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
|
|
+ return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
|
|
+}
|
|
+
|
|
+static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
|
|
+ struct ath_tx_status *ts, struct ath_buf *bf,
|
|
+ struct list_head *bf_head)
|
|
+{
|
|
+ bool txok, flush;
|
|
+
|
|
+ txok = !(ts->ts_status & ATH9K_TXERR_MASK);
|
|
+ flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
|
|
+ txq->axq_tx_inprogress = false;
|
|
+
|
|
+ txq->axq_depth--;
|
|
+ if (bf_is_ampdu_not_probing(bf))
|
|
+ txq->axq_ampdu_depth--;
|
|
+
|
|
+ if (!bf_isampdu(bf)) {
|
|
+ if (!flush)
|
|
+ ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
|
|
+ ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
|
|
+ } else
|
|
+ ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
|
|
+
|
|
+ if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
|
|
+ ath_txq_schedule(sc, txq);
|
|
+}
|
|
+
|
|
static bool ath_lookup_legacy(struct ath_buf *bf)
|
|
{
|
|
struct sk_buff *skb;
|
|
@@ -1331,23 +1362,6 @@ void ath_tx_aggr_resume(struct ath_softc
|
|
/* Queue Management */
|
|
/********************/
|
|
|
|
-static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
|
|
- struct ath_txq *txq)
|
|
-{
|
|
- struct ath_atx_ac *ac, *ac_tmp;
|
|
- struct ath_atx_tid *tid, *tid_tmp;
|
|
-
|
|
- list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
|
|
- list_del(&ac->list);
|
|
- ac->sched = false;
|
|
- list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
|
|
- list_del(&tid->list);
|
|
- tid->sched = false;
|
|
- ath_tid_drain(sc, txq, tid);
|
|
- }
|
|
- }
|
|
-}
|
|
-
|
|
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
@@ -1470,14 +1484,8 @@ int ath_cabq_update(struct ath_softc *sc
|
|
return 0;
|
|
}
|
|
|
|
-static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
|
|
-{
|
|
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
|
|
- return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
|
|
-}
|
|
-
|
|
static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
|
|
- struct list_head *list, bool retry_tx)
|
|
+ struct list_head *list)
|
|
{
|
|
struct ath_buf *bf, *lastbf;
|
|
struct list_head bf_head;
|
|
@@ -1499,16 +1507,7 @@ static void ath_drain_txq_list(struct at
|
|
|
|
lastbf = bf->bf_lastbf;
|
|
list_cut_position(&bf_head, list, &lastbf->list);
|
|
-
|
|
- txq->axq_depth--;
|
|
- if (bf_is_ampdu_not_probing(bf))
|
|
- txq->axq_ampdu_depth--;
|
|
-
|
|
- if (bf_isampdu(bf))
|
|
- ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
|
|
- retry_tx);
|
|
- else
|
|
- ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
|
|
+ ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
|
|
}
|
|
}
|
|
|
|
@@ -1518,7 +1517,7 @@ static void ath_drain_txq_list(struct at
|
|
* This assumes output has been stopped and
|
|
* we do not need to block ath_tx_tasklet.
|
|
*/
|
|
-void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
|
|
+void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
|
|
{
|
|
ath_txq_lock(sc, txq);
|
|
|
|
@@ -1526,8 +1525,7 @@ void ath_draintxq(struct ath_softc *sc,
|
|
int idx = txq->txq_tailidx;
|
|
|
|
while (!list_empty(&txq->txq_fifo[idx])) {
|
|
- ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
|
|
- retry_tx);
|
|
+ ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
|
|
|
|
INCR(idx, ATH_TXFIFO_DEPTH);
|
|
}
|
|
@@ -1536,16 +1534,12 @@ void ath_draintxq(struct ath_softc *sc,
|
|
|
|
txq->axq_link = NULL;
|
|
txq->axq_tx_inprogress = false;
|
|
- ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
|
|
-
|
|
- /* flush any pending frames if aggregation is enabled */
|
|
- if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !retry_tx)
|
|
- ath_txq_drain_pending_buffers(sc, txq);
|
|
+ ath_drain_txq_list(sc, txq, &txq->axq_q);
|
|
|
|
ath_txq_unlock_complete(sc, txq);
|
|
}
|
|
|
|
-bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
|
|
+bool ath_drain_all_txq(struct ath_softc *sc)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
|
@@ -1581,7 +1575,7 @@ bool ath_drain_all_txq(struct ath_softc
|
|
*/
|
|
txq = &sc->tx.txq[i];
|
|
txq->stopped = false;
|
|
- ath_draintxq(sc, txq, retry_tx);
|
|
+ ath_draintxq(sc, txq);
|
|
}
|
|
|
|
return !npend;
|
|
@@ -2175,28 +2169,6 @@ static void ath_tx_rc_status(struct ath_
|
|
tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
|
|
}
|
|
|
|
-static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
|
|
- struct ath_tx_status *ts, struct ath_buf *bf,
|
|
- struct list_head *bf_head)
|
|
-{
|
|
- int txok;
|
|
-
|
|
- txq->axq_depth--;
|
|
- txok = !(ts->ts_status & ATH9K_TXERR_MASK);
|
|
- txq->axq_tx_inprogress = false;
|
|
- if (bf_is_ampdu_not_probing(bf))
|
|
- txq->axq_ampdu_depth--;
|
|
-
|
|
- if (!bf_isampdu(bf)) {
|
|
- ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
|
|
- ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
|
|
- } else
|
|
- ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
|
|
-
|
|
- if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
|
|
- ath_txq_schedule(sc, txq);
|
|
-}
|
|
-
|
|
static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|