b89c81929e
BCM6338 and BCM6338 have their MSG_CONTROL register width of 8-bits instead of 16-bits. We were previously using a 16-bits write which corrupted the first byte of the TX FIFO. Also the message type was always set to Full-duplex even in the case of half-duplex messages. SVN-Revision: 32409
107 lines
3.4 KiB
Diff
107 lines
3.4 KiB
Diff
From 913c171ebfe0d589bdf6efb8fd607258c96ea54a Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 25 Jan 2012 17:39:58 +0100
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Subject: [PATCH 16/63] MIPS: BCM63XX: add TRNG peripheral definitions
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 9 +++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 14 ++++++++++++++
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2 files changed, 23 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -129,6 +129,7 @@ enum bcm63xx_regs_set {
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RSET_PCMDMA,
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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+ RSET_TRNG
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@@ -152,6 +153,7 @@ enum bcm63xx_regs_set {
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#define RSET_XTMDMA_SIZE 256
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#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
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#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
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+#define RSET_TRNG_SIZE 20
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/*
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* 6338 register sets base address
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@@ -195,6 +197,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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+#define BCM_6338_TRNG_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@@ -238,6 +241,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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+#define BCM_6345_TRNG_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@@ -278,6 +282,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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+#define BCM_6348_TRNG_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMA_BASE (0xfffe1800)
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#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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+#define BCM_6358_TRNG_BASE (0xdeadbeef)
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/*
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@@ -359,6 +365,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMA_BASE (0xb0005800)
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#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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+#define BCM_6368_TRNG_BASE (0xb0004180)
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extern const unsigned long *bcm63xx_regs_base;
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@@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, PCMDMA) \
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__GEN_RSET_BASE(__cpu, PCMDMAC) \
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__GEN_RSET_BASE(__cpu, PCMDMAS) \
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+ __GEN_RSET_BASE(__cpu, TRNG) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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@@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
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[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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+ [RSET_TRNG] = BCM_## __cpu ##_TRNG_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1099,4 +1099,18 @@
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#define SPI_SSOFFTIME_SHIFT 3
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#define SPI_BYTE_SWAP 0x80
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+/*************************************************************************
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+ * _REG relative to RSET_TRNG
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+ *************************************************************************/
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+
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+#define TRNG_CTRL 0x00
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+#define TRNG_EN (1 << 0)
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+
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+#define TRNG_STAT 0x04
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+#define TRNG_AVAIL_MASK (0xff000000)
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+
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+#define TRNG_DATA 0x08
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+#define TRNG_THRES 0x0c
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+#define TRNG_MASK 0x10
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+
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#endif /* BCM63XX_REGS_H_ */
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