672a8cd6ba
Changes include PCI fixes and various upstream pending patches. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 38624
94 lines
3.1 KiB
Diff
94 lines
3.1 KiB
Diff
From 3f75978b3742157853618c5c6dd4a5f49aa950b1 Mon Sep 17 00:00:00 2001
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From: Shawn Guo <shawn.guo@linaro.org>
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Date: Tue, 13 Aug 2013 14:10:29 +0800
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Subject: [PATCH] ARM: imx6q: use common soc revision helpers
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It calls imx_set_soc_revision() to set up soc revision in
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imx6q_init_revision(), and replaces all the occurrences of
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imx6q_revision() with common helper imx_get_soc_revision().
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/clk-imx6q.c | 5 +++--
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arch/arm/mach-imx/common.h | 1 -
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arch/arm/mach-imx/mach-imx6q.c | 13 ++++---------
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3 files changed, 7 insertions(+), 12 deletions(-)
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(str
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WARN_ON(!base);
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/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
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- if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
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+ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
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post_div_table[1].div = 1;
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post_div_table[2].div = 1;
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video_div_table[1].div = 1;
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@@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(str
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clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
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clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
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- if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
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+ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
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+ cpu_is_imx6dl()) {
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clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
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clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
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}
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--- a/arch/arm/mach-imx/common.h
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+++ b/arch/arm/mach-imx/common.h
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@@ -77,7 +77,6 @@ extern void mxc_restart(enum reboot_mode
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extern void mxc_arch_reset_init(void __iomem *);
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extern void mxc_arch_reset_init_dt(void);
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extern int mx53_revision(void);
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-extern int imx6q_revision(void);
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extern int mx53_display_revision(void);
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extern void imx_set_aips(void __iomem *);
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extern int mxc_device_init(void);
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--- a/arch/arm/mach-imx/mach-imx6q.c
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+++ b/arch/arm/mach-imx/mach-imx6q.c
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@@ -40,16 +40,10 @@
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#include "cpuidle.h"
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#include "hardware.h"
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-static u32 chip_revision;
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-
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-int imx6q_revision(void)
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-{
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- return chip_revision;
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-}
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-
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static void __init imx6q_init_revision(void)
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{
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u32 rev = imx_anatop_get_digprog();
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+ u32 chip_revision;
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switch (rev & 0xff) {
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case 0:
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@@ -66,6 +60,7 @@ static void __init imx6q_init_revision(v
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}
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mxc_set_cpu_type(rev >> 16 & 0xff);
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+ imx_set_soc_revision(chip_revision);
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}
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static void imx6q_restart(enum reboot_mode mode, const char *cmd)
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@@ -269,7 +264,7 @@ static void __init imx6q_init_late(void)
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* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
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* to run cpuidle on them.
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*/
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- if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
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+ if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
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imx6q_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
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@@ -298,7 +293,7 @@ static void __init imx6q_timer_init(void
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of_clk_init(NULL);
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clocksource_of_init();
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imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
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- imx6q_revision());
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+ imx_get_soc_revision());
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}
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static const char *imx6q_dt_compat[] __initdata = {
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