78 lines
3.3 KiB
Diff
78 lines
3.3 KiB
Diff
From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
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From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Date: Tue, 6 Jan 2015 21:26:44 +0100
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Subject: sun6i: Fix and document PLL LDO voltage selection
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The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
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their meaning reversed. This is fixed by this change-set. With this
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changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
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as setting the voltage to 1.37v (which it had done all along, even
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though stating a different target voltage).
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After changing the PLL LDO setting, it will take a little while for
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the voltage output to settle. A sdelay()-based loop waits the same
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order of magnitude as Boot1.
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Furthermore, a bit of documentation is added to clarify that the
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required setting for the PLL LDO is 1.37v as per the A31 manual.
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diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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index fa7ebd8..3a6e56e 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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@@ -24,14 +24,27 @@ void clock_init_safe(void)
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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- /* Set PLL ldo voltage without this PLL6 does not work properly */
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+ /* Set PLL ldo voltage without this PLL6 does not work properly.
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+ *
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+ * As the A31 manual states, that "before enable PLL, PLLVDD
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+ * LDO should be set to 1.37v", we need to configure this to 2.5v
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+ * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
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+ */
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clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_KEY);
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clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
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- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
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+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
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clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
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+ /* Give the PLL LDO voltage setting some time to take hold.
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+ * Notes:
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+ * 1) We need to use sdelay() as the timers aren't set up yet.
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+ * 2) The 100k iterations come from Boot1, which spin's for 100k
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+ * iterations through a loop.
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+ */
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+ sdelay(100000);
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+
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clock_set_pll1(408000000);
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writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
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diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
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index 82ed541..41a62a4 100644
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--- a/arch/arm/include/asm/arch-sunxi/prcm.h
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+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
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@@ -111,13 +111,13 @@
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#define PRCM_PLL_CTRL_LDO_OUT_MASK \
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__PRCM_PLL_CTRL_LDO_OUT(0x7)
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/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
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-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
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- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
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#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
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+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
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+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
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-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
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- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
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#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
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+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
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+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
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__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
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#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
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#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
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--
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cgit v0.10.2
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