bcm53xx: add SPI controller driver
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> SVN-Revision: 42223
This commit is contained in:
Hauke Mehrtens
parent
bcb36cd494
commit
f66a0912f7
@ -209,6 +209,9 @@ CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SMP=y
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CONFIG_SMP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPI=y
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CONFIG_SPI_BCM53XX=y
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CONFIG_SPI_MASTER=y
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CONFIG_STOP_MACHINE=y
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CONFIG_STOP_MACHINE=y
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CONFIG_SWCONFIG=y
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CONFIG_SWCONFIG=y
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CONFIG_SWIOTLB=y
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CONFIG_SWIOTLB=y
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@ -0,0 +1,435 @@
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From a59f3fa1dd4cb284171a53cb7a614ad947c544f6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Wed, 13 Aug 2014 14:11:39 +0200
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Subject: [PATCH V2] spi: bcm53xx: driver for SPI controller on Broadcom bcma
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SoC
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Broadcom 53xx ARM SoCs use bcma bus that contains various cores (AKA
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devices). If board has a serial flash, it's connected over SPI and the
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bcma bus includes a SPI controller. Example log from such a board:
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bus0: Found chip with id 53010, rev 0x00 and package 0x02
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(...)
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bus0: Core 18 found: SPI flash controller (manuf 0x4BF, id 0x50A, rev 0x01, class 0x0)
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This patch adds a bcma driver for SPI core, it registers SPI master
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controller and "bcm53xxspiflash" SPI device.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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Since RFC: Add Signed-off-by
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Update to compile on top of for-next
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V2: Use wait timeout
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Describe bcm53xxspi_calc_timeout a bit
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Use devm_spi_register_master
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Thanks Mark for your comments!
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---
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drivers/spi/Kconfig | 6 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-bcm53xx.c | 295 ++++++++++++++++++++++++++++++++++++++++++++++
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drivers/spi/spi-bcm53xx.h | 72 +++++++++++
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4 files changed, 374 insertions(+)
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create mode 100644 drivers/spi/spi-bcm53xx.c
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create mode 100644 drivers/spi/spi-bcm53xx.h
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -112,6 +112,12 @@ config SPI_AU1550
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If you say yes to this option, support will be included for the
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PSC SPI controller found on Au1550, Au1200 and Au1300 series.
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+config SPI_BCM53XX
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+ tristate "Broadcom BCM53xx SPI controller"
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+ depends on ARCH_BCM_5301X
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+ help
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+ Enable support for the SPI controller on Broadcom BCM53xx ARM SoCs.
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+
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config SPI_BCM63XX
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tristate "Broadcom BCM63xx SPI controller"
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depends on BCM63XX
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
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+obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
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obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
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obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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--- /dev/null
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+++ b/drivers/spi/spi-bcm53xx.c
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@@ -0,0 +1,295 @@
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/bcma/bcma.h>
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+#include <linux/spi/spi.h>
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+
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+#include "spi-bcm53xx.h"
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+
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+#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
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+
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+/* The longest observed required wait was 19 ms */
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+#define BCM53XXSPI_SPE_TIMEOUT_MS 80
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+
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+struct bcm53xxspi {
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+ struct bcma_device *core;
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+ struct spi_master *master;
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+
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+ size_t read_offset;
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+};
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+
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+static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
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+{
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+ return bcma_read32(b53spi->core, offset);
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+}
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+
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+static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
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+ u32 value)
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+{
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+ bcma_write32(b53spi->core, offset, value);
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+}
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+
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+static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
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+{
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+ /* Do some magic calculation based on length and buad. Add 10% and 1. */
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+ return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
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+}
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+
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+static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
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+{
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+ unsigned long deadline;
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+ u32 tmp;
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+
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+ /* SPE bit has to be 0 before we read MSPI STATUS */
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+ deadline = jiffies + BCM53XXSPI_SPE_TIMEOUT_MS * HZ / 1000;
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+ do {
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+ tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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+ if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
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+ break;
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+ udelay(5);
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+ } while (!time_after_eq(jiffies, deadline));
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+
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+ if (tmp & B53SPI_MSPI_SPCR2_SPE)
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+ goto spi_timeout;
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+
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+ /* Check status */
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+ deadline = jiffies + timeout_ms * HZ / 1000;
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+ do {
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+ tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
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+ if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
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+ return 0;
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+ }
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+
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+ cpu_relax();
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+ udelay(100);
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+ } while (!time_after_eq(jiffies, deadline));
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+
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+spi_timeout:
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
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+
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+ pr_err("Timeout waiting for SPI to be ready!\n");
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+
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+ return -EBUSY;
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+}
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+
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+static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
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+ size_t len, bool cont)
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+{
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+ u32 tmp;
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+ int i;
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+
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+ for (i = 0; i < len; i++) {
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+ /* Transmit Register File MSB */
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
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+ (unsigned int)w_buf[i]);
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+ }
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+
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+ for (i = 0; i < len; i++) {
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+ tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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+ B53SPI_CDRAM_PCS_DSCK;
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+ if (!cont && i == len - 1)
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+ tmp &= ~B53SPI_CDRAM_CONT;
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+ tmp &= ~0x1;
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+ /* Command Register File */
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
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+ }
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+
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+ /* Set queue pointers */
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
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+
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+ if (cont)
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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+
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+ /* Start SPI transfer */
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+ tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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+ tmp |= B53SPI_MSPI_SPCR2_SPE;
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+ if (cont)
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+ tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
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+
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+ /* Wait for SPI to finish */
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+ bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
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+
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+ if (!cont)
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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+
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+ b53spi->read_offset = len;
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+}
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+
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+static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
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+ size_t len, bool cont)
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+{
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+ u32 tmp;
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+ int i;
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+
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+ for (i = 0; i < b53spi->read_offset + len; i++) {
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+ tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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+ B53SPI_CDRAM_PCS_DSCK;
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+ if (!cont && i == b53spi->read_offset + len - 1)
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+ tmp &= ~B53SPI_CDRAM_CONT;
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+ tmp &= ~0x1;
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+ /* Command Register File */
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
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+ }
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+
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+ /* Set queue pointers */
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
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+ b53spi->read_offset + len - 1);
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+
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+ if (cont)
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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+
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+ /* Start SPI transfer */
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+ tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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+ tmp |= B53SPI_MSPI_SPCR2_SPE;
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+ if (cont)
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+ tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
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+
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+ /* Wait for SPI to finish */
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+ bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
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+
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+ if (!cont)
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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+
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+ for (i = 0; i < len; ++i) {
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+ int offset = b53spi->read_offset + i;
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+
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+ /* Data stored in the transmit register file LSB */
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+ r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
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+ }
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+
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+ b53spi->read_offset = 0;
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+}
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+
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+static int bcm53xxspi_transfer_one(struct spi_master *master,
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+ struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
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+ u8 *buf;
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+ size_t left;
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+
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+ if (t->tx_buf) {
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+ buf = (u8 *)t->tx_buf;
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+ left = t->len;
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+ while (left) {
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+ size_t to_write = min_t(size_t, 16, left);
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+ bool cont = left - to_write > 0;
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+
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+ bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
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+ left -= to_write;
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+ buf += to_write;
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+ }
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+ }
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+
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+ if (t->rx_buf) {
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+ buf = (u8 *)t->rx_buf;
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+ left = t->len;
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+ while (left) {
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+ size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
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+ left);
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+ bool cont = left - to_read > 0;
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+
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+ bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
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+ left -= to_read;
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+ buf += to_read;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+/**************************************************
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+ * BCMA
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+ **************************************************/
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+
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+struct spi_board_info bcm53xx_info = {
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+ .modalias = "bcm53xxspiflash",
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+};
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+
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+static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
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+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
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+ BCMA_CORETABLE_END
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+};
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+MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
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+
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+static int bcm53xxspi_bcma_probe(struct bcma_device *core)
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+{
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+ struct bcm53xxspi *b53spi;
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+ struct spi_master *master;
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+ int err;
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+
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+ if (core->bus->drv_cc.core->id.rev != 42) {
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+ pr_err("SPI on SoC with unsupported ChipCommon rev\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ master = spi_alloc_master(&core->dev, sizeof(*b53spi));
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+ if (!master)
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+ return -ENOMEM;
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+
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+ b53spi = spi_master_get_devdata(master);
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+ b53spi->master = master;
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+ b53spi->core = core;
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+
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+ master->transfer_one = bcm53xxspi_transfer_one;
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+
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+ bcma_set_drvdata(core, b53spi);
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+
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+ err = devm_spi_register_master(&core->dev, master);
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+ if (err) {
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+ spi_master_put(master);
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+ bcma_set_drvdata(core, NULL);
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+ goto out;
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+ }
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+
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+ /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
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+ spi_new_device(master, &bcm53xx_info);
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+
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+out:
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+ return err;
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+}
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+
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+static void bcm53xxspi_bcma_remove(struct bcma_device *core)
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+{
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+ struct bcm53xxspi *b53spi = bcma_get_drvdata(core);
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+
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+ spi_unregister_master(b53spi->master);
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+}
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+
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+static struct bcma_driver bcm53xxspi_bcma_driver = {
|
||||||
|
+ .name = KBUILD_MODNAME,
|
||||||
|
+ .id_table = bcm53xxspi_bcma_tbl,
|
||||||
|
+ .probe = bcm53xxspi_bcma_probe,
|
||||||
|
+ .remove = bcm53xxspi_bcma_remove,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/**************************************************
|
||||||
|
+ * Init & exit
|
||||||
|
+ **************************************************/
|
||||||
|
+
|
||||||
|
+static int __init bcm53xxspi_module_init(void)
|
||||||
|
+{
|
||||||
|
+ int err = 0;
|
||||||
|
+
|
||||||
|
+ err = bcma_driver_register(&bcm53xxspi_bcma_driver);
|
||||||
|
+ if (err)
|
||||||
|
+ pr_err("Failed to register bcma driver: %d\n", err);
|
||||||
|
+
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void __exit bcm53xxspi_module_exit(void)
|
||||||
|
+{
|
||||||
|
+ bcma_driver_unregister(&bcm53xxspi_bcma_driver);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+module_init(bcm53xxspi_module_init);
|
||||||
|
+module_exit(bcm53xxspi_module_exit);
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/drivers/spi/spi-bcm53xx.h
|
||||||
|
@@ -0,0 +1,72 @@
|
||||||
|
+#ifndef SPI_BCM53XX_H
|
||||||
|
+#define SPI_BCM53XX_H
|
||||||
|
+
|
||||||
|
+#define B53SPI_BSPI_REVISION_ID 0x000
|
||||||
|
+#define B53SPI_BSPI_SCRATCH 0x004
|
||||||
|
+#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008
|
||||||
|
+#define B53SPI_BSPI_BUSY_STATUS 0x00c
|
||||||
|
+#define B53SPI_BSPI_INTR_STATUS 0x010
|
||||||
|
+#define B53SPI_BSPI_B0_STATUS 0x014
|
||||||
|
+#define B53SPI_BSPI_B0_CTRL 0x018
|
||||||
|
+#define B53SPI_BSPI_B1_STATUS 0x01c
|
||||||
|
+#define B53SPI_BSPI_B1_CTRL 0x020
|
||||||
|
+#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024
|
||||||
|
+#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028
|
||||||
|
+#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c
|
||||||
|
+#define B53SPI_BSPI_BITS_PER_PHASE 0x030
|
||||||
|
+#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034
|
||||||
|
+#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
|
||||||
|
+#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c
|
||||||
|
+#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040
|
||||||
|
+#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044
|
||||||
|
+#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048
|
||||||
|
+#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c
|
||||||
|
+
|
||||||
|
+/* RAF */
|
||||||
|
+#define B53SPI_RAF_START_ADDR 0x100
|
||||||
|
+#define B53SPI_RAF_NUM_WORDS 0x104
|
||||||
|
+#define B53SPI_RAF_CTRL 0x108
|
||||||
|
+#define B53SPI_RAF_FULLNESS 0x10c
|
||||||
|
+#define B53SPI_RAF_WATERMARK 0x110
|
||||||
|
+#define B53SPI_RAF_STATUS 0x114
|
||||||
|
+#define B53SPI_RAF_READ_DATA 0x118
|
||||||
|
+#define B53SPI_RAF_WORD_CNT 0x11c
|
||||||
|
+#define B53SPI_RAF_CURR_ADDR 0x120
|
||||||
|
+
|
||||||
|
+/* MSPI */
|
||||||
|
+#define B53SPI_MSPI_SPCR0_LSB 0x200
|
||||||
|
+#define B53SPI_MSPI_SPCR0_MSB 0x204
|
||||||
|
+#define B53SPI_MSPI_SPCR1_LSB 0x208
|
||||||
|
+#define B53SPI_MSPI_SPCR1_MSB 0x20c
|
||||||
|
+#define B53SPI_MSPI_NEWQP 0x210
|
||||||
|
+#define B53SPI_MSPI_ENDQP 0x214
|
||||||
|
+#define B53SPI_MSPI_SPCR2 0x218
|
||||||
|
+#define B53SPI_MSPI_SPCR2_SPE 0x00000040
|
||||||
|
+#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080
|
||||||
|
+#define B53SPI_MSPI_MSPI_STATUS 0x220
|
||||||
|
+#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001
|
||||||
|
+#define B53SPI_MSPI_CPTQP 0x224
|
||||||
|
+#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */
|
||||||
|
+#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */
|
||||||
|
+#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */
|
||||||
|
+#define B53SPI_CDRAM_PCS_PCS0 0x00000001
|
||||||
|
+#define B53SPI_CDRAM_PCS_PCS1 0x00000002
|
||||||
|
+#define B53SPI_CDRAM_PCS_PCS2 0x00000004
|
||||||
|
+#define B53SPI_CDRAM_PCS_PCS3 0x00000008
|
||||||
|
+#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f
|
||||||
|
+#define B53SPI_CDRAM_PCS_DSCK 0x00000010
|
||||||
|
+#define B53SPI_CDRAM_BITSE 0x00000040
|
||||||
|
+#define B53SPI_CDRAM_CONT 0x00000080
|
||||||
|
+#define B53SPI_MSPI_WRITE_LOCK 0x380
|
||||||
|
+#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384
|
||||||
|
+
|
||||||
|
+/* Interrupt */
|
||||||
|
+#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0
|
||||||
|
+#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4
|
||||||
|
+#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8
|
||||||
|
+#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac
|
||||||
|
+#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0
|
||||||
|
+#define B53SPI_INTR_MSPI_DONE 0x3b4
|
||||||
|
+#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8
|
||||||
|
+
|
||||||
|
+#endif /* SPI_BCM53XX_H */
|
||||||
Loading…
Reference in New Issue
Block a user