ar71xx: add an irq parameter for ar724x_pcibios_init
SVN-Revision: 29105
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@ -83,7 +83,7 @@ int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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case AR71XX_SOC_AR9344:
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ret = ar724x_pcibios_init();
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ret = ar724x_pcibios_init(AR71XX_CPU_IRQ_IP2);
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break;
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break;
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default:
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default:
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@ -33,7 +33,7 @@ int ar71xx_pci_be_handler(int is_fixup);
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int ar724x_pcibios_map_irq(const struct pci_dev *dev,
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int ar724x_pcibios_map_irq(const struct pci_dev *dev,
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uint8_t slot, uint8_t pin) __init;
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uint8_t slot, uint8_t pin) __init;
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int ar724x_pcibios_init(void) __init;
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int ar724x_pcibios_init(int irq) __init;
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int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init;
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int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init;
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#else
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#else
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@ -325,7 +325,7 @@ static struct irq_chip ar724x_pci_irq_chip = {
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.irq_mask_ack = ar724x_pci_irq_mask,
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.irq_mask_ack = ar724x_pci_irq_mask,
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};
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};
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static void __init ar724x_pci_irq_init(void)
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static void __init ar724x_pci_irq_init(int irq)
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{
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 t;
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u32 t;
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@ -345,10 +345,10 @@ static void __init ar724x_pci_irq_init(void)
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irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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handle_level_irq);
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irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
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irq_set_chained_handler(irq, ar724x_pci_irq_handler);
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}
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}
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int __init ar724x_pcibios_init(void)
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int __init ar724x_pcibios_init(int irq)
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{
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{
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int ret = -ENOMEM;
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int ret = -ENOMEM;
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@ -373,7 +373,7 @@ int __init ar724x_pcibios_init(void)
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goto err_unmap_ctrl;
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goto err_unmap_ctrl;
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ar724x_pci_fixup_enable = 1;
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ar724x_pci_fixup_enable = 1;
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ar724x_pci_irq_init();
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ar724x_pci_irq_init(irq);
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register_pci_controller(&ar724x_pci_controller);
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register_pci_controller(&ar724x_pci_controller);
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return 0;
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return 0;
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