brcm63xx: add USB support for BCM63268
Add and enable USB support for the BCM63268 family of SoCs. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39323
This commit is contained in:
Jonas Gorski
parent
33f426c795
commit
6b3e1c8de6
@ -0,0 +1,71 @@
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -585,6 +585,9 @@
|
||||
#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
|
||||
#define TIMER_CTL_ENABLE_MASK (1 << 31)
|
||||
|
||||
+/* Clock reset control (63268 only) */
|
||||
+#define TIMER_CLK_RST_CTL_REG 0x2c
|
||||
+#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18)
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_WDT
|
||||
@@ -1666,6 +1669,11 @@
|
||||
#define STRAPBUS_63268_FCVO_SHIFT 21
|
||||
#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
|
||||
|
||||
+#define MISC_IDDQ_CTRL_6328_REG 0x48
|
||||
+#define MISC_IDDQ_CTRL_63268_REG 0x4c
|
||||
+
|
||||
+#define IDDQ_CTRL_63268_USBH (1 << 4)
|
||||
+
|
||||
#define MISC_STRAPBUS_6328_REG 0x240
|
||||
#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
|
||||
--- a/arch/mips/bcm63xx/clk.c
|
||||
+++ b/arch/mips/bcm63xx/clk.c
|
||||
@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask,
|
||||
bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
|
||||
}
|
||||
|
||||
+static void bcm_misc_iddq_set(u32 mask, int enable)
|
||||
+{
|
||||
+ u32 offset;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
|
||||
+ offset = MISC_IDDQ_CTRL_6328_REG;
|
||||
+ else if (BCMCPU_IS_63268())
|
||||
+ offset = MISC_IDDQ_CTRL_63268_REG;
|
||||
+ else
|
||||
+ return;
|
||||
+
|
||||
+ reg = bcm_misc_readl(offset);
|
||||
+ if (enable)
|
||||
+ reg &= ~mask;
|
||||
+ else
|
||||
+ reg |= mask;
|
||||
+ bcm_misc_writel(reg, offset);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
|
||||
*/
|
||||
@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in
|
||||
} else if (BCMCPU_IS_6368()) {
|
||||
bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
|
||||
} else if (BCMCPU_IS_63268()) {
|
||||
+ u32 reg;
|
||||
+
|
||||
bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
|
||||
+ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
|
||||
+ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
|
||||
+ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);
|
||||
+ if (enable)
|
||||
+ reg |= CLK_RST_CTL_USB_REF_CLK_EN;
|
||||
+ else
|
||||
+ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN;
|
||||
+ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
@ -0,0 +1,117 @@
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -1152,11 +1152,18 @@
|
||||
#define USBH_PRIV_SETUP_6368_REG 0x28
|
||||
#define USBH_PRIV_SETUP_IOC_SHIFT 4
|
||||
#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
|
||||
+#define USBH_PRIV_SETUP_IPP_SHIFT 5
|
||||
+#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT)
|
||||
|
||||
#define USBH_PRIV_SETUP_6318_REG 0x00
|
||||
+#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18
|
||||
#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04
|
||||
-#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27)
|
||||
-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31)
|
||||
+
|
||||
+#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27)
|
||||
+#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31)
|
||||
+#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9)
|
||||
+#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10)
|
||||
+
|
||||
#define USBH_PRIV_SIM_CTRL_6318_REG 0x20
|
||||
#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5)
|
||||
|
||||
--- a/arch/mips/bcm63xx/Kconfig
|
||||
+++ b/arch/mips/bcm63xx/Kconfig
|
||||
@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268
|
||||
bool "support 63268 CPU"
|
||||
select SYS_HAS_CPU_BMIPS4350
|
||||
select HW_HAS_PCI
|
||||
+ select BCM63XX_OHCI
|
||||
+ select BCM63XX_EHCI
|
||||
endmenu
|
||||
|
||||
source "arch/mips/bcm63xx/boards/Kconfig"
|
||||
--- a/arch/mips/bcm63xx/dev-usb-ehci.c
|
||||
+++ b/arch/mips/bcm63xx/dev-usb-ehci.c
|
||||
@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh
|
||||
int __init bcm63xx_ehci_register(void)
|
||||
{
|
||||
if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
|
||||
- !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
|
||||
+ !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())
|
||||
return 0;
|
||||
|
||||
ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
|
||||
--- a/arch/mips/bcm63xx/usb-common.c
|
||||
+++ b/arch/mips/bcm63xx/usb-common.c
|
||||
@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
|
||||
reg |= USBH_PRIV_SETUP_IOC_MASK;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
|
||||
+ } else if (BCMCPU_IS_63268()) {
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
|
||||
+ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
|
||||
+ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
|
||||
+
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
|
||||
+ reg |= USBH_PRIV_SETUP_IOC_MASK;
|
||||
+ reg &= ~USBH_PRIV_SETUP_IPP_MASK;
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
|
||||
+
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
|
||||
+ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
|
||||
+ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
|
||||
} else if (BCMCPU_IS_6318()) {
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
|
||||
+ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
|
||||
@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
|
||||
+ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
|
||||
@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
|
||||
reg |= USBH_PRIV_SETUP_IOC_MASK;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
|
||||
+ } else if (BCMCPU_IS_63268()) {
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
|
||||
+ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
|
||||
+ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
|
||||
+
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
|
||||
+ reg |= USBH_PRIV_SETUP_IOC_MASK;
|
||||
+ reg &= ~USBH_PRIV_SETUP_IPP_MASK;
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
|
||||
+
|
||||
+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);
|
||||
+ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |
|
||||
+ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);
|
||||
+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);
|
||||
} else if (BCMCPU_IS_6318()) {
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
|
||||
+ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
|
||||
@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
|
||||
+ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;
|
||||
bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
|
||||
|
||||
reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
|
||||
@ -11,7 +11,7 @@
|
||||
bcm_gpio_writel(val, GPIO_MODE_REG);
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -767,6 +767,8 @@
|
||||
@@ -770,6 +770,8 @@
|
||||
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
|
||||
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
|
||||
#define GPIO_MODE_6358_UTOPIA (1 << 12)
|
||||
|
||||
@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
|
||||
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -1083,6 +1083,19 @@
|
||||
@@ -1086,6 +1086,19 @@
|
||||
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
|
||||
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
|
||||
|
||||
|
||||
@ -115,7 +115,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
return -ENODEV;
|
||||
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||
@@ -824,6 +824,7 @@
|
||||
@@ -827,6 +827,7 @@
|
||||
#define GPIO_STRAPBUS_REG 0x40
|
||||
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
|
||||
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
|
||||
@ -123,8 +123,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
|
||||
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
|
||||
#define STRAPBUS_6368_BOOT_SEL_NAND 0
|
||||
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
|
||||
@@ -1682,6 +1683,7 @@
|
||||
#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
|
||||
@@ -1697,6 +1698,7 @@
|
||||
#define IDDQ_CTRL_63268_USBH (1 << 4)
|
||||
|
||||
#define MISC_STRAPBUS_6328_REG 0x240
|
||||
+#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user