ar71xx: allow to register the NAND flash controller on the QCA955x
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34945
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@ -38,6 +38,22 @@ static struct platform_device ath79_nfc_device = {
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},
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},
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};
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};
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static void __init ath79_nfc_init_resource(struct resource res[2],
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unsigned long base,
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unsigned long size,
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int irq)
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{
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memset(res, 0, sizeof(res));
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res[0].flags = IORESOURCE_MEM;
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res[0].start = base;
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res[0].end = base + size - 1;
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res[1].flags = IORESOURCE_IRQ;
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res[1].start = irq;
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res[1].end = irq;
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}
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static void ar934x_nfc_hw_reset(bool active)
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static void ar934x_nfc_hw_reset(bool active)
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{
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{
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if (active) {
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if (active) {
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@ -57,16 +73,34 @@ static void ar934x_nfc_hw_reset(bool active)
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static void ar934x_nfc_setup(void)
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static void ar934x_nfc_setup(void)
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{
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{
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ath79_nfc_resources[0].start = AR934X_NFC_BASE;
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ath79_nfc_resources[0].end = AR934X_NFC_BASE + AR934X_NFC_SIZE - 1;
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ath79_nfc_resources[0].flags = IORESOURCE_MEM;
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ath79_nfc_resources[1].start = ATH79_MISC_IRQ(21);
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ath79_nfc_resources[1].end = ATH79_MISC_IRQ(21);
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ath79_nfc_resources[1].flags = IORESOURCE_IRQ;
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ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
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ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset;
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ath79_nfc_init_resource(ath79_nfc_resources,
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AR934X_NFC_BASE, AR934X_NFC_SIZE,
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ATH79_MISC_IRQ(21));
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platform_device_register(&ath79_nfc_device);
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}
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static void qca955x_nfc_hw_reset(bool active)
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{
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if (active) {
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ath79_device_reset_set(QCA955X_RESET_NANDF);
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udelay(250);
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} else {
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ath79_device_reset_clear(QCA955X_RESET_NANDF);
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udelay(100);
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}
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}
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static void qca955x_nfc_setup(void)
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{
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ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset;
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ath79_nfc_init_resource(ath79_nfc_resources,
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QCA955X_NFC_BASE, QCA955X_NFC_SIZE,
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ATH79_MISC_IRQ(21));
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platform_device_register(&ath79_nfc_device);
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platform_device_register(&ath79_nfc_device);
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}
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}
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@ -95,6 +129,8 @@ void __init ath79_register_nfc(void)
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{
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{
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if (soc_is_ar934x())
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if (soc_is_ar934x())
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ar934x_nfc_setup();
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ar934x_nfc_setup();
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else if (soc_is_qca955x())
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qca955x_nfc_setup();
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else
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else
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BUG();
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BUG();
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}
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}
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