ar71xx: allow unknown multicast frames to pass to the CPU on AR934x
SVN-Revision: 35564
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9525a075c1
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2e7a4b088d
@ -209,6 +209,7 @@
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#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
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#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
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#define AR934X_REG_FLOOD_MASK 0x2c
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#define AR934X_REG_FLOOD_MASK 0x2c
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#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
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#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
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#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
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#define AR934X_REG_QM_CTRL 0x3c
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#define AR934X_REG_QM_CTRL 0x3c
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@ -580,9 +581,10 @@ static void ar7240sw_setup(struct ar7240sw *as)
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/* Enable ARP frame acknowledge */
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/* Enable ARP frame acknowledge */
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ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
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ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
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AR934X_QM_CTRL_ARP_EN);
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AR934X_QM_CTRL_ARP_EN);
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/* Enable Broadcast frames transmitted to the CPU */
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/* Enable Broadcast/Multicast frames transmitted to the CPU */
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ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
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ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
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AR934X_FLOOD_MASK_BC_DP(0));
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AR934X_FLOOD_MASK_BC_DP(0) |
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AR934X_FLOOD_MASK_MC_DP(0));
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/* Enable MIB counters */
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/* Enable MIB counters */
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ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
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ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
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