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vendor-reset
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Vega10 BACO reset should work now.

This commit is contained in:
Adam Madsen 2020-11-01 21:41:46 -06:00
parent 4ecfddfc0e
commit eb42a21118
3 changed files with 53 additions and 14 deletions
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60
src/amd/common.c
View File

@ -22,6 +22,8 @@ Place, Suite 330, Boston, MA 02111-1307 USA
#include <linux/delay.h>
#include <linux/printk.h>
#include "vendor-reset-dev.h"
#include "soc15_common.h"
#include "soc15.h"
#include "common.h"
int amd_common_pre_reset(struct vendor_reset_dev *dev)
@ -93,22 +95,58 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
return 0;
}
int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp)
static int smu_wait(struct amd_fake_dev *adev)
{
int ret = 0;
u32 timeout;
mutex_lock(&adev->private->smu_lock);
u32 ret;
int timeout;
for (timeout = 100000;
timeout &&
(RREG32(mmMP1_SMN_C2PMSG_90) & MP1_C2PMSG_90__CONTENT_MASK) == 0;
(RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) & MP1_C2PMSG_90__CONTENT_MASK) == 0;
--timeout)
udelay(1);
if ((ret = RREG32(mmMP1_SMN_C2PMSG_90)) != 0x1)
pci_info(adev->private->vdev->pdev, "SMU error 0x%x (line %d)\n",
ret, __LINE__);
if ((ret = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90)) != 0x1)
pci_info(adev->private->vdev->pdev, "SMU error 0x%x\n", ret);
mutex_unlock(&adev->private->smu_lock);
return ret != 0x1;
return ret;
}
int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp)
{
int ret = 0;
mutex_lock(&adev->private->smu_lock);
ret = smu_wait(adev);
if (ret != 0x1)
{
ret = -ETIMEDOUT;
goto out;
}
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
ret = smu_wait(adev);
if (ret != 0x01)
{
pci_err(adev->private->vdev->pdev, "Failed to send message 0x%x: return 0x%x\n", msg, ret);
goto out;
}
if (resp)
*resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
ret = ret != 0x01;
out:
mutex_unlock(&adev->private->smu_lock);
return ret;
}
int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp)
{
return smum_send_msg_to_smc_with_parameter(adev, msg, 0, resp);
}

1
src/amd/common.h
View File

@ -182,5 +182,6 @@ int amd_common_pre_reset(struct vendor_reset_dev *);
int amd_common_post_reset(struct vendor_reset_dev *);
int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp);
#endif

6
src/amd/vega10.c
View File

@ -141,7 +141,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
/* it's important we wait for the SOC to be ready */
for (timeout = 100000; timeout; --timeout)
{
sol = RREG32(mmMP0_SMN_C2PMSG_81);
sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol != 0xFFFFFFFF && sol != 0)
break;
udelay(1);
@ -150,7 +150,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
pci_info(dev->pdev, "Vega10: bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
/* collect some info for logging for now */
smu_resp = RREG32(mmMP1_SMN_C2PMSG_90);
smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
mp1_intr = (RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
@ -162,7 +162,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
smu_resp, sol, mp1_intr ? "yes" : "no",
psp_bl_ready ? "yes" : "no");
if (!sol)
if (sol == ~1L)
{
pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
return -EINVAL;