[amd] common: remove mutexes and locks
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331f44820e
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d537ed67d9
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@ -48,10 +48,6 @@ int amd_common_pre_reset(struct vendor_reset_dev *dev)
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dev->vendor_private = priv;
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priv->vdev = dev;
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spin_lock_init(&priv->pcie_lock);
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spin_lock_init(&priv->reg_lock);
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mutex_init(&priv->smu_lock);
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priv->mmio_base = pci_resource_start(pdev, 5);
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priv->mmio_size = pci_resource_len(pdev, 5);
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priv->mmio = ioremap(priv->mmio_base, priv->mmio_size);
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@ -99,7 +95,6 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
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kfree(priv);
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dev->vendor_private = NULL;
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mutex_destroy(&priv->smu_lock);
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return 0;
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}
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@ -124,8 +119,6 @@ int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg,
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{
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int ret = 0;
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mutex_lock(&adev_to_amd_private(adev)->smu_lock);
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ret = smu_wait(adev);
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if (ret != 0x1)
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{
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@ -151,7 +144,6 @@ int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg,
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ret = ret != 0x01;
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out:
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mutex_unlock(&adev_to_amd_private(adev)->smu_lock);
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return ret;
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}
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@ -36,11 +36,8 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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__out = readl(adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev_to_amd_private(adev)->reg_lock, __flags); \
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writel((reg), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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__out = readl(adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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spin_unlock_irqrestore(&adev_to_amd_private(adev)->reg_lock, __flags); \
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} \
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__out; \
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})
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@ -52,35 +49,26 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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writel(v, adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev_to_amd_private(adev)->reg_lock, __flags); \
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writel((reg), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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writel(v, adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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spin_unlock_irqrestore(&adev_to_amd_private(adev)->reg_lock, __flags); \
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} \
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} while (0)
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#define WREG32_PCIE(reg, v) \
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do \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev_to_amd_private(adev)->pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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WREG32(mmPCIE_DATA2, v); \
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(void)RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&adev_to_amd_private(adev)->pcie_lock, __flags); \
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} while (0)
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#define RREG32_PCIE(reg) \
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({ \
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unsigned long __flags; \
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u32 __tmp_read; \
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spin_lock_irqsave(&adev_to_amd_private(adev)->pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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__tmp_read = RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&adev_to_amd_private(adev)->pcie_lock, __flags); \
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__tmp_read; \
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})
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@ -120,10 +108,6 @@ struct amd_vendor_private
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resource_size_t mmio_base;
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resource_size_t mmio_size;
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uint32_t __iomem *mmio;
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spinlock_t pcie_lock;
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spinlock_t reg_lock;
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struct mutex smu_lock;
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};
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static inline struct amd_vendor_private *adev_to_amd_private(struct amd_fake_dev *adev)
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