[amd] polaris10: check if reset is needed, use BACO if possible
This commit is contained in:
Adam Madsen
parent
838ccab480
commit
c5cb424fec
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@ -2,21 +2,23 @@ vendor-reset-y += \
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src/amd/common.o \
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src/amd/compat.o \
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src/amd/firmware.o \
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src/amd/navi10.o \
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src/amd/polaris10.o \
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src/amd/vega10.o \
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src/amd/vega20.o \
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src/amd/navi10.o \
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src/amd/amdgpu/amdgpu_device.o \
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src/amd/amdgpu/amdgpu_discovery.o \
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src/amd/amdgpu/amdgpu_bios.o \
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src/amd/amdgpu/amdgpu_atomfirmware.o \
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src/amd/amdgpu/atom.o \
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src/amd/amdgpu/common_baco.o \
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src/amd/amdgpu/vega10_reg_init.o \
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src/amd/amdgpu/vega20_reg_init.o \
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src/amd/amdgpu/navi10_reg_init.o \
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src/amd/amdgpu/navi12_reg_init.o \
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src/amd/amdgpu/navi14_reg_init.o \
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src/amd/amdgpu/amdgpu_device.o \
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src/amd/amdgpu/amdgpu_discovery.o \
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src/amd/amdgpu/atom.o \
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src/amd/amdgpu/amdgpu_bios.o \
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src/amd/amdgpu/amdgpu_atomfirmware.o
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src/amd/amdgpu/polaris_baco.o \
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src/amd/amdgpu/smu7_baco.o \
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src/amd/amdgpu/vega10_reg_init.o \
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src/amd/amdgpu/vega20_reg_init.o
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ccflags-y += \
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-I$(src)/src/amd \
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@ -0,0 +1,219 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/delay.h>
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#include "common.h"
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#include "compat.h"
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#include "polaris_baco.h"
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#include "gmc/gmc_8_1_d.h"
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#include "gmc/gmc_8_1_sh_mask.h"
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#include "bif/bif_5_0_d.h"
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#include "bif/bif_5_0_sh_mask.h"
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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#include "smu/smu_7_1_3_d.h"
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#include "smu/smu_7_1_3_sh_mask.h"
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static const struct baco_cmd_entry gpio_tbl[] =
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{
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{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
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{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
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{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
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{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
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{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
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{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
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{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
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{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
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{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
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{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
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};
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static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
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{
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
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{ CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
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};
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static const struct baco_cmd_entry use_bclk_tbl[] =
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{
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
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{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
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{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
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};
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static const struct baco_cmd_entry turn_off_plls_tbl[] =
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{
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{ CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
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{ CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
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{ CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
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{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
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{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
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{ CMD_READMODIFYWRITE, 0xda2, 0x40, 0x6, 0, 0x0 },
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{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
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{ CMD_READMODIFYWRITE, 0xda2, 0x8, 0x3, 0, 0x0 },
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{ CMD_READMODIFYWRITE, 0xda2, 0x3fff00, 0x8, 0, 0x32 },
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{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
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{ CMD_READMODIFYWRITE, mmMPLL_FUNC_CNTL_2, MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK, MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT, 0, 0x0 },
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{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
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};
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static const struct baco_cmd_entry clk_req_b_tbl[] =
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{
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }
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};
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static const struct baco_cmd_entry enter_baco_tbl[] =
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{
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
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};
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#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
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static const struct baco_cmd_entry exit_baco_tbl[] =
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{
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
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{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
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{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
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};
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static const struct baco_cmd_entry clean_baco_tbl[] =
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{
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{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
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{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
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};
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static const struct baco_cmd_entry use_bclk_tbl_vg[] =
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{
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }
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};
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static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
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{
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{ CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
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{ CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
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{ CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
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{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
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{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
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{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
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{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
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{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
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{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
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{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
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};
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int polaris_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state)
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{
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enum BACO_STATE cur_state;
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smu7_baco_get_state(adev, &cur_state);
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if (cur_state == state)
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/* aisc already in the target state */
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return 0;
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if (state == BACO_STATE_IN) {
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baco_program_registers(adev, gpio_tbl, ARRAY_SIZE(gpio_tbl));
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baco_program_registers(adev, enable_fb_req_rej_tbl,
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ARRAY_SIZE(enable_fb_req_rej_tbl));
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baco_program_registers(adev, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
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baco_program_registers(adev, turn_off_plls_tbl,
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ARRAY_SIZE(turn_off_plls_tbl));
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baco_program_registers(adev, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
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if (baco_program_registers(adev, enter_baco_tbl,
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ARRAY_SIZE(enter_baco_tbl)))
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return 0;
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} else if (state == BACO_STATE_OUT) {
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/* HW requires at least 20ms between regulator off and on */
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msleep(20);
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/* Execute Hardware BACO exit sequence */
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if (baco_program_registers(adev, exit_baco_tbl,
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ARRAY_SIZE(exit_baco_tbl))) {
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if (baco_program_registers(adev, clean_baco_tbl,
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ARRAY_SIZE(clean_baco_tbl)))
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return 0;
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}
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}
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return -EINVAL;
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}
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@ -0,0 +1,30 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
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||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef __POLARIS_BACO_H__
|
||||
#define __POLARIS_BACO_H__
|
||||
#include "smu7_baco.h"
|
||||
#include "compat.h"
|
||||
|
||||
extern int polaris_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include "amd.h"
|
||||
#include "common.h"
|
||||
#include "vendor-reset-dev.h"
|
||||
#include "smu7_baco.h"
|
||||
#include "polaris_baco.h"
|
||||
|
||||
#include "bif/bif_5_0_d.h"
|
||||
#include "bif/bif_5_0_sh_mask.h"
|
||||
|
||||
#include "smu/smu_7_1_2_d.h"
|
||||
#include "smu/smu_7_1_2_sh_mask.h"
|
||||
|
||||
int smu7_baco_get_capability(struct amd_fake_dev *adev, bool *cap)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
*cap = false;
|
||||
/* we're going to assume true */
|
||||
/* if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
|
||||
return 0; */
|
||||
|
||||
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
|
||||
|
||||
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
|
||||
*cap = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int smu7_baco_get_state(struct amd_fake_dev *adev, enum BACO_STATE *state)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = RREG32(mmBACO_CNTL);
|
||||
|
||||
if (reg & BACO_CNTL__BACO_MODE_MASK)
|
||||
/* gfx has already entered BACO state */
|
||||
*state = BACO_STATE_IN;
|
||||
else
|
||||
*state = BACO_STATE_OUT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int smu7_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state)
|
||||
{
|
||||
switch (adev->vdev->info)
|
||||
{
|
||||
case AMD_POLARIS10:
|
||||
case AMD_POLARIS11:
|
||||
case AMD_POLARIS12:
|
||||
return polaris_baco_set_state(adev, state);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef __SMU7_BACO_H__
|
||||
#define __SMU7_BACO_H__
|
||||
#include "compat.h"
|
||||
#include "common_baco.h"
|
||||
|
||||
extern int smu7_baco_get_capability(struct amd_fake_dev *adev, bool *cap);
|
||||
extern int smu7_baco_get_state(struct amd_fake_dev *adev, enum BACO_STATE *state);
|
||||
extern int smu7_baco_set_state(struct amd_fake_dev *adev, enum BACO_STATE state);
|
||||
|
||||
#endif
|
||||
|
|
@ -83,6 +83,16 @@ static inline bool drm_can_sleep(void)
|
|||
#define WREG32_NO_KIQ WREG32
|
||||
#define RREG32_NO_KIQ RREG32
|
||||
|
||||
/* from amdgpu.h */
|
||||
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
|
||||
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
|
||||
#define REG_SET_FIELD(orig_val, reg, field, field_val) \
|
||||
(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
|
||||
(REG_FIELD_MASK(reg, field) & \
|
||||
((field_val) << REG_FIELD_SHIFT(reg, field))))
|
||||
#define REG_GET_FIELD(value, reg, field) \
|
||||
(((value)®_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
|
||||
|
||||
/* from smu_cm.c */
|
||||
/*
|
||||
* Although these are defined in each ASIC's specific header file.
|
||||
|
|
|
|||
|
|
@ -17,19 +17,41 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
|||
Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "vendor-reset-dev.h"
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "bif/bif_4_1_d.h"
|
||||
#include "atom-types.h"
|
||||
#include "atombios.h"
|
||||
#include "bif/bif_4_1_d.h"
|
||||
#include "common.h"
|
||||
#include "compat.h"
|
||||
#include "polaris_baco.h"
|
||||
#include "smu/smu_7_1_1_d.h"
|
||||
#include "smu/smu_7_1_1_sh_mask.h"
|
||||
#include "smu7_baco.h"
|
||||
#include "vendor-reset-dev.h"
|
||||
|
||||
#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b /* from amdgpu.h */
|
||||
#define RREG32_SMC(reg) vi_smc_rreg(adev, reg)
|
||||
#define WREG32_SMC(reg, v) vi_smc_wreg(adev, reg, v)
|
||||
|
||||
/* from vi.c */
|
||||
static u32 vi_smc_rreg(struct amd_fake_dev *adev, u32 reg)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
|
||||
r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* not needed yet
|
||||
static void vi_smc_wreg(struct amd_fake_dev *adev, u32 reg, u32 v)
|
||||
{
|
||||
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
|
||||
WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
|
||||
}
|
||||
*/
|
||||
|
||||
static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
|
||||
{
|
||||
u32 i;
|
||||
|
|
@ -53,11 +75,28 @@ static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static bool vi_need_reset_on_init(struct amd_fake_dev *adev)
|
||||
{
|
||||
u32 clock_cntl, pc;
|
||||
|
||||
/* check if the SMC is already running */
|
||||
clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
|
||||
pc = RREG32_SMC(ixSMC_PC_C);
|
||||
vr_info(adev->vdev, "CLOCK_CNTL: 0x%x, PC: 0x%x\n", REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable), pc);
|
||||
if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
|
||||
(0x20100 <= pc))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
/* end from vi.c */
|
||||
|
||||
static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
|
||||
{
|
||||
int ret = 0;
|
||||
struct amd_vendor_private *priv = amd_private(vdev);
|
||||
struct amd_fake_dev *adev = &priv->adev;
|
||||
bool baco_capable;
|
||||
|
||||
ret = amd_fake_dev_init(adev, vdev);
|
||||
if (ret)
|
||||
|
|
@ -66,18 +105,45 @@ static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
|
|||
/* pre-firmware constant */
|
||||
adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
|
||||
|
||||
if (!vi_need_reset_on_init(adev))
|
||||
goto free_adev;
|
||||
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
|
||||
ret = vi_gpu_pci_config_reset(adev);
|
||||
|
||||
(void)smu7_baco_get_capability(adev, &baco_capable);
|
||||
if (baco_capable)
|
||||
{
|
||||
vr_info(vdev, "Performing BACO reset\n");
|
||||
ret = polaris_baco_set_state(adev, BACO_STATE_IN);
|
||||
if (ret)
|
||||
{
|
||||
vr_warn(vdev, "Failed to enter BACO: %d\n", ret);
|
||||
goto unhang;
|
||||
}
|
||||
ret = polaris_baco_set_state(adev, BACO_STATE_OUT);
|
||||
if (ret)
|
||||
vr_warn(vdev, "Failed to exit BACO: %d\n", ret);
|
||||
}
|
||||
else
|
||||
{
|
||||
vr_info(vdev, "Performing reset via PCI config\n");
|
||||
ret = vi_gpu_pci_config_reset(adev);
|
||||
if (ret)
|
||||
vr_warn(vdev, "Reset via PCI config failed: %d\n", ret);
|
||||
}
|
||||
|
||||
unhang:
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
|
||||
|
||||
free_adev:
|
||||
amd_fake_dev_fini(adev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct vendor_reset_ops amd_polaris10_ops = {
|
||||
.version = {1, 0},
|
||||
.probe = amd_common_probe,
|
||||
.pre_reset = amd_common_pre_reset,
|
||||
.reset = amd_polaris10_reset,
|
||||
.post_reset = amd_common_post_reset,
|
||||
.version = {1, 1},
|
||||
.probe = amd_common_probe,
|
||||
.pre_reset = amd_common_pre_reset,
|
||||
.reset = amd_polaris10_reset,
|
||||
.post_reset = amd_common_post_reset,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue