Collect some precondition info
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b7554f9035
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@ -28,6 +28,14 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "common.h"
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#include "common.h"
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#include "common_baco.h"
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#include "common_baco.h"
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/* MP Apertures, from smu9_smumgr.c */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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extern int vega10_reg_base_init(struct amd_fake_dev *adev);
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extern int vega10_reg_base_init(struct amd_fake_dev *adev);
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/* drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c */
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/* drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c */
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@ -119,7 +127,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev;
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struct amd_fake_dev *adev;
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int ret, timeout;
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int ret, timeout;
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u32 sol;
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u32 sol, smu_resp, mp1_intr, psp_bl_ready;
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priv->adev = (struct amd_fake_dev){
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priv->adev = (struct amd_fake_dev){
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.dev = &dev->pdev->dev,
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.dev = &dev->pdev->dev,
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@ -139,11 +147,26 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
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udelay(1);
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udelay(1);
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}
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}
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if (!sol)
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pci_info(dev->pdev, "Vega10: bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
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{
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pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
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/* collect some info for logging for now */
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return -EINVAL;
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smu_resp = RREG32(mmMP1_SMN_C2PMSG_90);
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}
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mp1_intr = (RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
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psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L);
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pci_info(
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dev->pdev,
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"Vega10: SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
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smu_resp, sol, mp1_intr ? "yes" : "no",
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psp_bl_ready ? "yes" : "no");
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// if (!sol)
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// {
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// pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
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// return -EINVAL;
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// }
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pci_info(dev->pdev, "Vega10: Entering BACO\n");
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pci_info(dev->pdev, "Vega10: Entering BACO\n");
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ret = vega10_baco_set_state(adev, BACO_STATE_IN);
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ret = vega10_baco_set_state(adev, BACO_STATE_IN);
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