AMD: I think that's Navi.

.gitignore

@@ -5,3 +5,4 @@
 *.o
 *.symvers
 *.order
+*.d

src/amd/Makefile

@@ -9,6 +9,8 @@ vendor-reset-y += \
 	src/amd/amdgpu/common_baco.o \
 	src/amd/amdgpu/vega10_reg_init.o \
 	src/amd/amdgpu/navi10_reg_init.o \
+	src/amd/amdgpu/navi12_reg_init.o \
+	src/amd/amdgpu/navi14_reg_init.o \
 	src/amd/amdgpu/amdgpu_device.o \
 	src/amd/amdgpu/amdgpu_discovery.o \
 	src/amd/amdgpu/atom.o \

src/amd/amd.h

@@ -16,7 +16,20 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 Place, Suite 330, Boston, MA 02111-1307 USA
 */
 
-extern struct vendor_reset_ops amd_polaris10_ops;
+enum amd_device_type
-extern struct vendor_reset_ops amd_vega10_ops;
+{
-extern struct vendor_reset_ops amd_vega20_ops;
+  AMD_POLARIS10,
-extern struct vendor_reset_ops amd_navi10_ops;
+  AMD_POLARIS11,
+  AMD_POLARIS12,
+  AMD_VEGA10,
+  AMD_VEGA12,
+  AMD_VEGA20,
+  AMD_NAVI10,
+  AMD_NAVI12,
+  AMD_NAVI14,
+};
+
+extern const struct vendor_reset_ops amd_polaris10_ops;
+extern const struct vendor_reset_ops amd_vega10_ops;
+extern const struct vendor_reset_ops amd_vega20_ops;
+extern const struct vendor_reset_ops amd_navi10_ops;

src/amd/amdgpu/include/smu_v11_0.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V11_0_H__
+#define __SMU_V11_0_H__
+
+#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
+#define SMU11_DRIVER_IF_VERSION_NV10 0x36
+#define SMU11_DRIVER_IF_VERSION_NV12 0x33
+#define SMU11_DRIVER_IF_VERSION_NV14 0x36
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
+
+/* MP Apertures */
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS 0x3010024
+#define smnMP0_FW_INTF 0x30101c0
+#define smnMP1_PUB_CTRL 0x3010b14
+
+#define TEMP_RANGE_MIN (0)
+#define TEMP_RANGE_MAX (80 * 1000)
+
+#define SMU11_TOOL_SIZE 0x19000
+
+#define MAX_DPM_LEVELS 16
+#define MAX_PCIE_CONF 2
+
+#define CTF_OFFSET_EDGE 5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
+
+#endif

src/amd/amdgpu/navi12_reg_init.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "compat.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "navi12_ip_offset.h"
+
+int navi12_reg_base_init(struct amd_fake_dev *adev)
+{
+	/* HW has more IP blocks,  only initialized the blocks needed by driver */
+	uint32_t i;
+	for (i = 0; i < MAX_INSTANCE; ++i)
+	{
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
+	}
+	return 0;
+}

src/amd/amdgpu/navi14_reg_init.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "compat.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "navi14_ip_offset.h"
+
+int navi14_reg_base_init(struct amd_fake_dev *adev)
+{
+	int i;
+
+	for (i = 0; i < MAX_INSTANCE; ++i)
+	{
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
+	}
+
+	return 0;
+}

src/amd/common.c

@@ -25,6 +25,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
 #include "soc15_common.h"
 #include "soc15.h"
 #include "common.h"
+#include "compat.h"
 
 int amd_common_pre_reset(struct vendor_reset_dev *dev)
 {
@@ -98,7 +99,7 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
   return 0;
 }
 
-static int smu_wait(struct amd_fake_dev *adev)
+int smu_wait(struct amd_fake_dev *adev)
 {
   u32 ret;
   int timeout;
@@ -152,4 +153,44 @@ out:
 int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp)
 {
   return smum_send_msg_to_smc_with_parameter(adev, msg, 0, resp);
+}
+
+/* from amdgpu_atombios.c */
+void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev,
+                                              bool hung)
+{
+  u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
+
+  if (hung)
+    tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
+  else
+    tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
+
+  WREG32(adev->bios_scratch_reg_offset + 3, tmp);
+}
+
+/* from amdgpu_psp.c */
+int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index,
+                 uint32_t reg_val, uint32_t mask, bool check_changed)
+{
+  uint32_t val;
+  int i;
+
+  for (i = 0; i < 100000; i++)
+  {
+    val = RREG32(reg_index);
+    if (check_changed)
+    {
+      if (val != reg_val)
+        return 0;
+    }
+    else
+    {
+      if ((val & mask) == reg_val)
+        return 0;
+    }
+    udelay(1);
+  }
+
+  return -ETIME;
 }

src/amd/common.h

@@ -144,6 +144,12 @@ int amd_common_pre_reset(struct vendor_reset_dev *);
 int amd_common_post_reset(struct vendor_reset_dev *);
 
 int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
-int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp);
+int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg,
+                                        uint32_t parameter, uint32_t *resp);
+
+void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung);
+
+int smu_wait(struct amd_fake_dev *adev);
+int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index, uint32_t reg_val, uint32_t mask, bool check_changed);
 
 #endif

src/amd/navi10.c

@@ -17,20 +17,34 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 Place, Suite 330, Boston, MA 02111-1307 USA
 */
 
+#include <linux/delay.h>
+
 #include "vendor-reset-dev.h"
 
+#include "amd.h"
 #include "common.h"
 #include "firmware.h"
 #include "amdgpu_discovery.h"
+#include "smu_v11_0.h"
+#include "mp/mp_11_0_offset.h"
+#include "mp/mp_11_0_sh_mask.h"
+#include "nbio_2_3_offset.h"
+#include "psp_gfx_if.h"
 #include "nv.h"
 
+#define log_prefix "Navi10/12/14: "
+#define nv_info(fmt, arg...) pci_info(dev->pdev, log_prefix fmt, ##arg)
+#define nv_warn(fmt, arg...) pci_warn(dev->pdev, log_prefix fmt, ##arg)
+#define nv_err(fmt, arg...) pci_err(dev->pdev, log_prefix fmt, ##arg)
+
 extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
 
 static int amd_navi10_reset(struct vendor_reset_dev *dev)
 {
   struct amd_vendor_private *priv = amd_private(dev);
   struct amd_fake_dev *adev;
-  int ret;
+  int ret = 0, timeout;
+  u32 sol, smu_resp, mp1_intr, psp_bl_ready, tmp, offset;
 
   adev = &priv->adev;
   ret = amd_fake_dev_init(adev, dev);
@@ -40,26 +54,208 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
   ret = amdgpu_discovery_reg_base_init(adev);
   if (ret < 0)
   {
-    pci_info(dev->pdev,
+    nv_info("amdgpu_discovery_reg_base_init failed, using legacy method\n");
-             "amdgpu_discovery_reg_base_init failed, using legacy method\n");
+    switch (dev->info)
-    navi10_reg_base_init(adev);
+    {
+    case AMD_NAVI10:
+      navi10_reg_base_init(adev);
+      break;
+    case AMD_NAVI12:
+      navi12_reg_base_init(adev);
+      break;
+    case AMD_NAVI14:
+      navi14_reg_base_init(adev);
+      break;
+    default:
+      pci_err(dev->pdev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device);
+      return -ENOTSUPP;
+    }
   }
 
   if (!amdgpu_get_bios(adev))
   {
-    pci_err(dev->pdev, "amdgpu_get_bios failed: %d\n", ret);
+    nv_err("amdgpu_get_bios failed: %d\n", ret);
     ret = -ENOTSUPP;
-    goto adev_free;
+    goto free_adev;
   }
 
   ret = atom_bios_init(adev);
   if (ret)
   {
-    pci_err(dev->pdev, "atom_bios_init failed: %d\n", ret);
+    nv_err("atom_bios_init failed: %d\n", ret);
-    goto adev_free;
+    goto free_adev;
   }
 
-adev_free:
+  /* it's important we wait for the SOC to be ready */
+  for (timeout = 100000; timeout; --timeout)
+  {
+    sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+    if (sol != 0xFFFFFFFF && sol != 0)
+      break;
+    udelay(1);
+  }
+
+  if (sol == ~1L)
+  {
+    nv_warn("Timed out waiting for SOL to be valid\n");
+    /* continuing anyway because sometimes it can still be reset from here */
+  }
+
+  nv_info("bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
+
+  /* collect some info for logging for now */
+  smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+  mp1_intr = (RREG32_PCIE(MP1_Public |
+                          (smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
+              MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
+  psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L);
+  nv_info("SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
+          smu_resp, sol, mp1_intr ? "yes" : "no",
+          psp_bl_ready ? "yes" : "no");
+
+  /* okay, if we're in this state, we're probably reset */
+  if (sol == 0x0 && !mp1_intr && psp_bl_ready)
+    goto free_adev;
+
+  /* this tells the drivers nvram is lost and everything needs to be reset */
+  nv_info("Clearing scratch regs 6 and 7\n");
+  WREG32(adev->bios_scratch_reg_offset + 6, 0);
+  WREG32(adev->bios_scratch_reg_offset + 7, 0);
+
+  /* it only makes sense to reset mp1 if it's running
+	 * XXX: is this even necessary? in early testing, I ran into
+	 * situations where MP1 was alive but not responsive, but in
+	 * later testing I have not been able to replicate this scenario.
+	 */
+  if (smu_resp != 0x01 && mp1_intr)
+  {
+    nv_info("MP1 reset\n");
+    WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
+                1 & MP1_SMN_PUB_CTRL__RESET_MASK);
+    WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
+                1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
+
+    nv_info("wait for MP1\n");
+    for (timeout = 100000; timeout; --timeout)
+    {
+      tmp = RREG32_PCIE(MP1_Public |
+                        (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+      if ((tmp &
+           MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+          MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+        break;
+      udelay(1);
+    }
+
+    if (!timeout &&
+        !((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+          MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT))
+    {
+      nv_warn("timed out waiting for MP1 reset\n");
+    }
+
+    smu_wait(adev);
+    smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+    nv_info("SMU resp reg: %x\n", tmp);
+  }
+
+  /*
+	 * again, this only makes sense if we have an SMU to talk to
+	 * some of these may fail, that's okay. we're just turning off as many
+	 * things as possible
+	 */
+  if (mp1_intr)
+  {
+    smu_wait(adev);
+
+    /* disallowgfx_off or something */
+    nv_info("gfx off\n");
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A);
+    smu_wait(adev);
+
+    /* stop SMC */
+    nv_info("Prep Reset\n");
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
+    /* PPSMC_MSG_PrepareMp1ForReset */
+    WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x33);
+    smu_wait(adev);
+  }
+
+  nv_info("begin psp mode 1 reset\n");
+  amdgpu_atombios_scratch_regs_engine_hung(adev, true);
+
+  pci_save_state(dev->pdev);
+
+  /* check validity of PSP before reset */
+  nv_info("PSP wait\n");
+  offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
+  tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
+  if (tmp)
+    nv_warn("timed out waiting for PSP to reach valid state, but continuing anyway\n");
+
+  /* reset command */
+  nv_info("do mode1 reset\n");
+  WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
+  msleep(500);
+
+  /* wait for ACK */
+  nv_info("PSP wait\n");
+  offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
+  tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
+  if (tmp)
+  {
+    nv_warn("PSP did not acknowledger reset\n");
+    ret = -EINVAL;
+    goto out;
+  }
+
+  nv_info("mode1 reset succeeded\n");
+
+  pci_restore_state(dev->pdev);
+
+  for (timeout = 100000; timeout; --timeout)
+  {
+    tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
+
+    if (tmp != 0xffffffff)
+      break;
+    udelay(1);
+  }
+  nv_info("memsize: %x\n", tmp);
+
+  /* 
+	 * this takes a long time :( 
+	 */
+  for (timeout = 100; timeout; --timeout)
+  {
+    /* see if PSP bootloader comes back */
+    if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
+      break;
+
+    nv_info("PSP bootloader flags? %x, timeout: %s\n",
+            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no");
+
+    msleep(100);
+  }
+
+  if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L))
+  {
+    nv_warn("timed out waiting for PSP bootloader to respond after reset\n");
+    ret = -ETIME;
+  }
+  else
+    nv_info("PSP mode1 reset successful\n");
+
+  pci_restore_state(dev->pdev);
+
+out:
+  amdgpu_atombios_scratch_regs_engine_hung(adev, false);
+
+free_adev:
   amd_fake_dev_fini(adev);
 
   return ret;

src/amd/polaris10.c

@@ -25,7 +25,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
 #include "common.h"
 #include "compat.h"
 
-#define bios_scratch_reg_offset mmBIOS_SCRATCH_0
 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b /* from amdgpu.h */
 
 /* from vi.c */
@@ -52,20 +51,6 @@ static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
   return -EINVAL;
 }
 
-static inline void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung)
-{
-  u32 tmp;
-
-  tmp = RREG32(bios_scratch_reg_offset + 3);
-
-  if (hung)
-    tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-  else
-    tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-
-  WREG32(bios_scratch_reg_offset + 3, tmp);
-}
-
 static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
 {
   int ret = 0;
@@ -76,6 +61,9 @@ static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
   if (ret)
     return ret;
 
+  /* pre-firmware constant */
+  adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
+
   amdgpu_atombios_scratch_regs_engine_hung(adev, true);
   ret = vi_gpu_pci_config_reset(adev);
   amdgpu_atombios_scratch_regs_engine_hung(adev, false);

src/amd/vega10.c

@@ -126,7 +126,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
 {
   struct amd_vendor_private *priv = amd_private(dev);
   struct amd_fake_dev *adev;
-  int ret, timeout;
+  int ret = 0, timeout;
   u32 sol, smu_resp, mp1_intr, psp_bl_ready;
   enum BACO_STATE baco_state;
 
@@ -168,12 +168,13 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
   if (sol == ~1L && baco_state != BACO_STATE_IN)
   {
     pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
-    return -EINVAL;
+    ret = -EINVAL;
+    goto free_adev;
   }
 
   /* if there's no sign of life we usually can't reset */
   if (!sol)
-    return 0;
+    goto free_adev;
 
   if (baco_state == BACO_STATE_OUT)
   {

src/device-db.h

@@ -18,91 +18,96 @@ Place, Suite 330, Boston, MA 02111-1307 USA
 
 #include "amd/amd.h"
 
-#define AMD_POLARIS10(op)            \
+#define _AMD_POLARIS10(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x67C0, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C0, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C1, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C1, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C2, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C2, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C4, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C4, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C7, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C7, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67D0, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67D0, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67DF, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67DF, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C8, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C8, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67C9, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67C9, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67CA, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67CA, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67CC, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67CC, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x67CF, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67CF, op, AMD_POLARIS10}, \
-    {PCI_VENDOR_ID_ATI, 0x6FDF, op}
+    {PCI_VENDOR_ID_ATI, 0x6FDF, op, AMD_POLARIS10}
 
-#define AMD_POLARIS11(op)            \
+#define _AMD_POLARIS11(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x67E0, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67E0, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67E3, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67E3, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67E8, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67E8, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67EB, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67EB, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67EF, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67EF, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67FF, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67FF, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67E1, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67E1, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67E7, op}, \
+    {PCI_VENDOR_ID_ATI, 0x67E7, op, AMD_POLARIS11}, \
-    {PCI_VENDOR_ID_ATI, 0x67E9, op}
+    {PCI_VENDOR_ID_ATI, 0x67E9, op, AMD_POLARIS11}
 
-#define AMD_POLARIS12(op)            \
+#define _AMD_POLARIS12(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x6980, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6980, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6981, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6981, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6985, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6985, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6986, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6986, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6987, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6987, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6995, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6995, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x6997, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6997, op, AMD_POLARIS12}, \
-    {PCI_VENDOR_ID_ATI, 0x699F, op}
+    {PCI_VENDOR_ID_ATI, 0x699F, op, AMD_POLARIS12}
 
-#define AMD_VEGA10(op)               \
+#define _AMD_VEGA10(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x6860, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6860, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6861, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6861, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6862, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6862, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6863, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6863, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6864, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6864, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6867, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6867, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6868, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6868, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x6869, op}, \
+    {PCI_VENDOR_ID_ATI, 0x6869, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686a, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686a, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686b, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686b, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686c, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686c, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686d, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686d, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686e, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686e, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x686f, op}, \
+    {PCI_VENDOR_ID_ATI, 0x686f, op, AMD_VEGA10}, \
-    {PCI_VENDOR_ID_ATI, 0x687f, op}
+    {PCI_VENDOR_ID_ATI, 0x687f, op, AMD_VEGA10}
 
-#define AMD_VEGA20(op)               \
+#define _AMD_VEGA20(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x66a0, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a0, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66a1, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a1, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66a2, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a2, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66a3, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a3, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66a4, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a4, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66a7, op}, \
+    {PCI_VENDOR_ID_ATI, 0x66a7, op, AMD_VEGA20}, \
-    {PCI_VENDOR_ID_ATI, 0x66af, op}
+    {PCI_VENDOR_ID_ATI, 0x66af, op, AMD_VEGA20}
 
-#define AMD_NAVI10(op)               \
+#define _AMD_NAVI10(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x7310, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7310, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x7312, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7312, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x7318, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7318, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x7319, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7319, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x731a, op}, \
+    {PCI_VENDOR_ID_ATI, 0x731a, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x731b, op}, \
+    {PCI_VENDOR_ID_ATI, 0x731b, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x731e, op}, \
+    {PCI_VENDOR_ID_ATI, 0x731e, op, AMD_NAVI10}, \
-    {PCI_VENDOR_ID_ATI, 0x731f, op}
+    {PCI_VENDOR_ID_ATI, 0x731f, op, AMD_NAVI10}
 
-#define AMD_NAVI14(op)               \
+#define _AMD_NAVI14(op)                          \
-    {PCI_VENDOR_ID_ATI, 0x7340, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7340, op, AMD_NAVI14}, \
-    {PCI_VENDOR_ID_ATI, 0x7341, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7341, op, AMD_NAVI14}, \
-    {PCI_VENDOR_ID_ATI, 0x7347, op}, \
+    {PCI_VENDOR_ID_ATI, 0x7347, op, AMD_NAVI14}, \
-    {PCI_VENDOR_ID_ATI, 0x734F, op}
+    {PCI_VENDOR_ID_ATI, 0x734F, op, AMD_NAVI14}
+
+#define _AMD_NAVI12(op)                          \
+    {PCI_VENDOR_ID_ATI, 0x7360, op, AMD_NAVI12}, \
+    {PCI_VENDOR_ID_ATI, 0x7362, op, AMD_NAVI12}
 
 static struct vendor_reset_cfg vendor_reset_devices[] = {
-    AMD_POLARIS10(&amd_polaris10_ops),
+    _AMD_POLARIS10(&amd_polaris10_ops),
-    AMD_POLARIS11(&amd_polaris10_ops),
+    _AMD_POLARIS11(&amd_polaris10_ops),
-    AMD_POLARIS12(&amd_polaris10_ops),
+    _AMD_POLARIS12(&amd_polaris10_ops),
-    AMD_VEGA10(&amd_vega10_ops),
+    _AMD_VEGA10(&amd_vega10_ops),
-    AMD_VEGA20(&amd_vega20_ops),
+    _AMD_VEGA20(&amd_vega20_ops),
-    AMD_NAVI10(&amd_navi10_ops),
+    _AMD_NAVI10(&amd_navi10_ops),
-    AMD_NAVI14(&amd_navi10_ops),
+    _AMD_NAVI14(&amd_navi10_ops),
+    _AMD_NAVI12(&amd_navi10_ops),
     {0},
 };

src/hooks.c

@@ -43,6 +43,7 @@ static int hooked_pci_dev_specific_reset(struct pci_dev *dev, int probe)
   if (cfg->vendor)
   {
     vdev.pdev = dev;
+    vdev.info = cfg->info;
 
     if (cfg->ops->pre_reset && (ret = cfg->ops->pre_reset(&vdev)) && ret)
       return ret;

src/vendor-reset-dev.h

@@ -27,6 +27,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
 struct vendor_reset_dev
 {
   struct pci_dev *pdev;
+  unsigned long info;
 
   int reset_ret;
 
@@ -54,6 +55,9 @@ struct vendor_reset_cfg
 
   /* the reset operations */
   const struct vendor_reset_ops * ops;
+
+  /* device type for combined ops */
+  unsigned long info;
 };
 
 #endif

src/vendor-reset.c

@@ -68,6 +68,7 @@ static long vendor_reset_ioctl_reset(struct file * filp, unsigned long arg)
   }
 
   vdev.pdev = pcidev;
+  vdev.info = entry->info;
 
   /* we probably always want to lock the device */
   if (!pci_cfg_access_trylock(pcidev))