AMD: I think that's Navi.
This commit is contained in:
Adam Madsen
parent
1e5120caa4
commit
8d5922b434
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@ -5,3 +5,4 @@
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*.o
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*.symvers
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*.order
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*.d
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@ -9,6 +9,8 @@ vendor-reset-y += \
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src/amd/amdgpu/common_baco.o \
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src/amd/amdgpu/vega10_reg_init.o \
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src/amd/amdgpu/navi10_reg_init.o \
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src/amd/amdgpu/navi12_reg_init.o \
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src/amd/amdgpu/navi14_reg_init.o \
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src/amd/amdgpu/amdgpu_device.o \
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src/amd/amdgpu/amdgpu_discovery.o \
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src/amd/amdgpu/atom.o \
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@ -16,7 +16,20 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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extern struct vendor_reset_ops amd_polaris10_ops;
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extern struct vendor_reset_ops amd_vega10_ops;
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extern struct vendor_reset_ops amd_vega20_ops;
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extern struct vendor_reset_ops amd_navi10_ops;
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enum amd_device_type
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{
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AMD_POLARIS10,
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AMD_POLARIS11,
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AMD_POLARIS12,
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AMD_VEGA10,
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AMD_VEGA12,
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AMD_VEGA20,
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AMD_NAVI10,
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AMD_NAVI12,
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AMD_NAVI14,
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};
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extern const struct vendor_reset_ops amd_polaris10_ops;
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extern const struct vendor_reset_ops amd_vega10_ops;
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extern const struct vendor_reset_ops amd_vega20_ops;
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extern const struct vendor_reset_ops amd_navi10_ops;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,57 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SMU_V11_0_H__
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#define __SMU_V11_0_H__
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#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
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#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
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#define SMU11_DRIVER_IF_VERSION_NV10 0x36
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#define SMU11_DRIVER_IF_VERSION_NV12 0x33
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#define SMU11_DRIVER_IF_VERSION_NV14 0x36
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#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
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#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP0_FW_INTF 0x30101c0
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#define smnMP1_PUB_CTRL 0x3010b14
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#define TEMP_RANGE_MIN (0)
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#define TEMP_RANGE_MAX (80 * 1000)
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#define SMU11_TOOL_SIZE 0x19000
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#define MAX_DPM_LEVELS 16
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#define MAX_PCIE_CONF 2
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#define CTF_OFFSET_EDGE 5
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#define CTF_OFFSET_HOTSPOT 5
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#define CTF_OFFSET_MEM 5
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,53 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "compat.h"
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#include "nv.h"
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#include "soc15_common.h"
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#include "navi12_ip_offset.h"
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int navi12_reg_base_init(struct amd_fake_dev *adev)
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{
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/* HW has more IP blocks, only initialized the blocks needed by driver */
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uint32_t i;
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for (i = 0; i < MAX_INSTANCE; ++i)
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{
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adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
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adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
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adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
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adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
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adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
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adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
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adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
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adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
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adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
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adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
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adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
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adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
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adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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}
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return 0;
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}
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@ -0,0 +1,54 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "compat.h"
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#include "nv.h"
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#include "soc15_common.h"
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#include "navi14_ip_offset.h"
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int navi14_reg_base_init(struct amd_fake_dev *adev)
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{
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int i;
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for (i = 0; i < MAX_INSTANCE; ++i)
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{
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adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
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adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
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adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
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adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
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adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
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adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
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adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
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adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
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adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
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adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
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adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
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adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
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adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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}
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return 0;
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}
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@ -25,6 +25,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "soc15_common.h"
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#include "soc15.h"
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#include "common.h"
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#include "compat.h"
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int amd_common_pre_reset(struct vendor_reset_dev *dev)
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{
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@ -98,7 +99,7 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
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return 0;
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}
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static int smu_wait(struct amd_fake_dev *adev)
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int smu_wait(struct amd_fake_dev *adev)
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{
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u32 ret;
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int timeout;
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@ -152,4 +153,44 @@ out:
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int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp)
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{
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return smum_send_msg_to_smc_with_parameter(adev, msg, 0, resp);
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}
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/* from amdgpu_atombios.c */
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void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev,
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bool hung)
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{
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u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
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if (hung)
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tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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else
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tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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WREG32(adev->bios_scratch_reg_offset + 3, tmp);
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}
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/* from amdgpu_psp.c */
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int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index,
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uint32_t reg_val, uint32_t mask, bool check_changed)
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{
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uint32_t val;
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int i;
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for (i = 0; i < 100000; i++)
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{
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val = RREG32(reg_index);
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if (check_changed)
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{
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if (val != reg_val)
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return 0;
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}
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else
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{
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if ((val & mask) == reg_val)
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return 0;
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}
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udelay(1);
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}
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return -ETIME;
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}
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@ -144,6 +144,12 @@ int amd_common_pre_reset(struct vendor_reset_dev *);
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int amd_common_post_reset(struct vendor_reset_dev *);
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int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
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int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg, uint32_t parameter, uint32_t *resp);
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int smum_send_msg_to_smc_with_parameter(struct amd_fake_dev *adev, uint16_t msg,
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uint32_t parameter, uint32_t *resp);
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void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung);
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int smu_wait(struct amd_fake_dev *adev);
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int psp_wait_for(struct amd_fake_dev *adev, uint32_t reg_index, uint32_t reg_val, uint32_t mask, bool check_changed);
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#endif
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214
src/amd/navi10.c
214
src/amd/navi10.c
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@ -17,20 +17,34 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
|||
Place, Suite 330, Boston, MA 02111-1307 USA
|
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*/
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#include <linux/delay.h>
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#include "vendor-reset-dev.h"
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#include "amd.h"
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#include "common.h"
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#include "firmware.h"
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#include "amdgpu_discovery.h"
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#include "smu_v11_0.h"
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#include "mp/mp_11_0_offset.h"
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#include "mp/mp_11_0_sh_mask.h"
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#include "nbio_2_3_offset.h"
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#include "psp_gfx_if.h"
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#include "nv.h"
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#define log_prefix "Navi10/12/14: "
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#define nv_info(fmt, arg...) pci_info(dev->pdev, log_prefix fmt, ##arg)
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#define nv_warn(fmt, arg...) pci_warn(dev->pdev, log_prefix fmt, ##arg)
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#define nv_err(fmt, arg...) pci_err(dev->pdev, log_prefix fmt, ##arg)
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extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
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static int amd_navi10_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev;
|
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int ret;
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int ret = 0, timeout;
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u32 sol, smu_resp, mp1_intr, psp_bl_ready, tmp, offset;
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adev = &priv->adev;
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ret = amd_fake_dev_init(adev, dev);
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|
|
@ -40,26 +54,208 @@ static int amd_navi10_reset(struct vendor_reset_dev *dev)
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ret = amdgpu_discovery_reg_base_init(adev);
|
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if (ret < 0)
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{
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pci_info(dev->pdev,
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"amdgpu_discovery_reg_base_init failed, using legacy method\n");
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navi10_reg_base_init(adev);
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nv_info("amdgpu_discovery_reg_base_init failed, using legacy method\n");
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switch (dev->info)
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{
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case AMD_NAVI10:
|
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navi10_reg_base_init(adev);
|
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break;
|
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case AMD_NAVI12:
|
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navi12_reg_base_init(adev);
|
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break;
|
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case AMD_NAVI14:
|
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navi14_reg_base_init(adev);
|
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break;
|
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default:
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pci_err(dev->pdev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device);
|
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return -ENOTSUPP;
|
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}
|
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}
|
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|
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if (!amdgpu_get_bios(adev))
|
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{
|
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pci_err(dev->pdev, "amdgpu_get_bios failed: %d\n", ret);
|
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nv_err("amdgpu_get_bios failed: %d\n", ret);
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ret = -ENOTSUPP;
|
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goto adev_free;
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goto free_adev;
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}
|
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|
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ret = atom_bios_init(adev);
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if (ret)
|
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{
|
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pci_err(dev->pdev, "atom_bios_init failed: %d\n", ret);
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goto adev_free;
|
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nv_err("atom_bios_init failed: %d\n", ret);
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goto free_adev;
|
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}
|
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|
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adev_free:
|
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/* it's important we wait for the SOC to be ready */
|
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for (timeout = 100000; timeout; --timeout)
|
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{
|
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sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
|
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if (sol != 0xFFFFFFFF && sol != 0)
|
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break;
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udelay(1);
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}
|
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|
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if (sol == ~1L)
|
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{
|
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nv_warn("Timed out waiting for SOL to be valid\n");
|
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/* continuing anyway because sometimes it can still be reset from here */
|
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}
|
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|
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nv_info("bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
|
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|
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/* collect some info for logging for now */
|
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
|
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mp1_intr = (RREG32_PCIE(MP1_Public |
|
||||
(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
|
||||
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
|
||||
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
|
||||
psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L);
|
||||
nv_info("SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
|
||||
smu_resp, sol, mp1_intr ? "yes" : "no",
|
||||
psp_bl_ready ? "yes" : "no");
|
||||
|
||||
/* okay, if we're in this state, we're probably reset */
|
||||
if (sol == 0x0 && !mp1_intr && psp_bl_ready)
|
||||
goto free_adev;
|
||||
|
||||
/* this tells the drivers nvram is lost and everything needs to be reset */
|
||||
nv_info("Clearing scratch regs 6 and 7\n");
|
||||
WREG32(adev->bios_scratch_reg_offset + 6, 0);
|
||||
WREG32(adev->bios_scratch_reg_offset + 7, 0);
|
||||
|
||||
/* it only makes sense to reset mp1 if it's running
|
||||
* XXX: is this even necessary? in early testing, I ran into
|
||||
* situations where MP1 was alive but not responsive, but in
|
||||
* later testing I have not been able to replicate this scenario.
|
||||
*/
|
||||
if (smu_resp != 0x01 && mp1_intr)
|
||||
{
|
||||
nv_info("MP1 reset\n");
|
||||
WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
|
||||
1 & MP1_SMN_PUB_CTRL__RESET_MASK);
|
||||
WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
|
||||
1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
|
||||
|
||||
nv_info("wait for MP1\n");
|
||||
for (timeout = 100000; timeout; --timeout)
|
||||
{
|
||||
tmp = RREG32_PCIE(MP1_Public |
|
||||
(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
|
||||
if ((tmp &
|
||||
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
|
||||
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (!timeout &&
|
||||
!((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
|
||||
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT))
|
||||
{
|
||||
nv_warn("timed out waiting for MP1 reset\n");
|
||||
}
|
||||
|
||||
smu_wait(adev);
|
||||
smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
|
||||
nv_info("SMU resp reg: %x\n", tmp);
|
||||
}
|
||||
|
||||
/*
|
||||
* again, this only makes sense if we have an SMU to talk to
|
||||
* some of these may fail, that's okay. we're just turning off as many
|
||||
* things as possible
|
||||
*/
|
||||
if (mp1_intr)
|
||||
{
|
||||
smu_wait(adev);
|
||||
|
||||
/* disallowgfx_off or something */
|
||||
nv_info("gfx off\n");
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A);
|
||||
smu_wait(adev);
|
||||
|
||||
/* stop SMC */
|
||||
nv_info("Prep Reset\n");
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
|
||||
/* PPSMC_MSG_PrepareMp1ForReset */
|
||||
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x33);
|
||||
smu_wait(adev);
|
||||
}
|
||||
|
||||
nv_info("begin psp mode 1 reset\n");
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
|
||||
|
||||
pci_save_state(dev->pdev);
|
||||
|
||||
/* check validity of PSP before reset */
|
||||
nv_info("PSP wait\n");
|
||||
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
|
||||
tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
|
||||
if (tmp)
|
||||
nv_warn("timed out waiting for PSP to reach valid state, but continuing anyway\n");
|
||||
|
||||
/* reset command */
|
||||
nv_info("do mode1 reset\n");
|
||||
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
|
||||
msleep(500);
|
||||
|
||||
/* wait for ACK */
|
||||
nv_info("PSP wait\n");
|
||||
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
|
||||
tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
|
||||
if (tmp)
|
||||
{
|
||||
nv_warn("PSP did not acknowledger reset\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
nv_info("mode1 reset succeeded\n");
|
||||
|
||||
pci_restore_state(dev->pdev);
|
||||
|
||||
for (timeout = 100000; timeout; --timeout)
|
||||
{
|
||||
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
|
||||
|
||||
if (tmp != 0xffffffff)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
nv_info("memsize: %x\n", tmp);
|
||||
|
||||
/*
|
||||
* this takes a long time :(
|
||||
*/
|
||||
for (timeout = 100; timeout; --timeout)
|
||||
{
|
||||
/* see if PSP bootloader comes back */
|
||||
if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
|
||||
break;
|
||||
|
||||
nv_info("PSP bootloader flags? %x, timeout: %s\n",
|
||||
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no");
|
||||
|
||||
msleep(100);
|
||||
}
|
||||
|
||||
if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L))
|
||||
{
|
||||
nv_warn("timed out waiting for PSP bootloader to respond after reset\n");
|
||||
ret = -ETIME;
|
||||
}
|
||||
else
|
||||
nv_info("PSP mode1 reset successful\n");
|
||||
|
||||
pci_restore_state(dev->pdev);
|
||||
|
||||
out:
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
|
||||
|
||||
free_adev:
|
||||
amd_fake_dev_fini(adev);
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
#include "common.h"
|
||||
#include "compat.h"
|
||||
|
||||
#define bios_scratch_reg_offset mmBIOS_SCRATCH_0
|
||||
#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b /* from amdgpu.h */
|
||||
|
||||
/* from vi.c */
|
||||
|
|
@ -52,20 +51,6 @@ static int vi_gpu_pci_config_reset(struct amd_fake_dev *adev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void amdgpu_atombios_scratch_regs_engine_hung(struct amd_fake_dev *adev, bool hung)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = RREG32(bios_scratch_reg_offset + 3);
|
||||
|
||||
if (hung)
|
||||
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
|
||||
else
|
||||
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
|
||||
|
||||
WREG32(bios_scratch_reg_offset + 3, tmp);
|
||||
}
|
||||
|
||||
static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
|
@ -76,6 +61,9 @@ static int amd_polaris10_reset(struct vendor_reset_dev *vdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* pre-firmware constant */
|
||||
adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
|
||||
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
|
||||
ret = vi_gpu_pci_config_reset(adev);
|
||||
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
|
|||
{
|
||||
struct amd_vendor_private *priv = amd_private(dev);
|
||||
struct amd_fake_dev *adev;
|
||||
int ret, timeout;
|
||||
int ret = 0, timeout;
|
||||
u32 sol, smu_resp, mp1_intr, psp_bl_ready;
|
||||
enum BACO_STATE baco_state;
|
||||
|
||||
|
|
@ -168,12 +168,13 @@ static int amd_vega10_reset(struct vendor_reset_dev *dev)
|
|||
if (sol == ~1L && baco_state != BACO_STATE_IN)
|
||||
{
|
||||
pci_warn(dev->pdev, "Vega10: Timed out waiting for SOL to be valid\n");
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto free_adev;
|
||||
}
|
||||
|
||||
/* if there's no sign of life we usually can't reset */
|
||||
if (!sol)
|
||||
return 0;
|
||||
goto free_adev;
|
||||
|
||||
if (baco_state == BACO_STATE_OUT)
|
||||
{
|
||||
|
|
|
|||
161
src/device-db.h
161
src/device-db.h
|
|
@ -18,91 +18,96 @@ Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
|
||||
#include "amd/amd.h"
|
||||
|
||||
#define AMD_POLARIS10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C0, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C1, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C2, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C4, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C7, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67D0, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67DF, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C8, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C9, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CA, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CC, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CF, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6FDF, op}
|
||||
#define _AMD_POLARIS10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C0, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C1, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C2, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C4, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C7, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67D0, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67DF, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C8, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67C9, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CA, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CC, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67CF, op, AMD_POLARIS10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6FDF, op, AMD_POLARIS10}
|
||||
|
||||
#define AMD_POLARIS11(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E0, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E3, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E8, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67EB, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67EF, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67FF, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E1, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E7, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E9, op}
|
||||
#define _AMD_POLARIS11(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E0, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E3, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E8, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67EB, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67EF, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67FF, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E1, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E7, op, AMD_POLARIS11}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x67E9, op, AMD_POLARIS11}
|
||||
|
||||
#define AMD_POLARIS12(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x6980, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6981, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6985, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6986, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6987, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6995, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6997, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x699F, op}
|
||||
#define _AMD_POLARIS12(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x6980, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6981, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6985, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6986, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6987, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6995, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6997, op, AMD_POLARIS12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x699F, op, AMD_POLARIS12}
|
||||
|
||||
#define AMD_VEGA10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x6860, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6861, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6862, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6863, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6864, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6867, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6868, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6869, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686a, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686b, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686c, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686d, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686e, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686f, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x687f, op}
|
||||
#define _AMD_VEGA10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x6860, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6861, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6862, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6863, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6864, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6867, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6868, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x6869, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686a, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686b, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686c, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686d, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686e, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x686f, op, AMD_VEGA10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x687f, op, AMD_VEGA10}
|
||||
|
||||
#define AMD_VEGA20(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a0, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a1, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a2, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a3, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a4, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a7, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66af, op}
|
||||
#define _AMD_VEGA20(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a0, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a1, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a2, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a3, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a4, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66a7, op, AMD_VEGA20}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x66af, op, AMD_VEGA20}
|
||||
|
||||
#define AMD_NAVI10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x7310, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7312, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7318, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7319, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731a, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731b, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731e, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731f, op}
|
||||
#define _AMD_NAVI10(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x7310, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7312, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7318, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7319, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731a, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731b, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731e, op, AMD_NAVI10}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x731f, op, AMD_NAVI10}
|
||||
|
||||
#define AMD_NAVI14(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x7340, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7341, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7347, op}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x734F, op}
|
||||
#define _AMD_NAVI14(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x7340, op, AMD_NAVI14}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7341, op, AMD_NAVI14}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7347, op, AMD_NAVI14}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x734F, op, AMD_NAVI14}
|
||||
|
||||
#define _AMD_NAVI12(op) \
|
||||
{PCI_VENDOR_ID_ATI, 0x7360, op, AMD_NAVI12}, \
|
||||
{PCI_VENDOR_ID_ATI, 0x7362, op, AMD_NAVI12}
|
||||
|
||||
static struct vendor_reset_cfg vendor_reset_devices[] = {
|
||||
AMD_POLARIS10(&amd_polaris10_ops),
|
||||
AMD_POLARIS11(&amd_polaris10_ops),
|
||||
AMD_POLARIS12(&amd_polaris10_ops),
|
||||
AMD_VEGA10(&amd_vega10_ops),
|
||||
AMD_VEGA20(&amd_vega20_ops),
|
||||
AMD_NAVI10(&amd_navi10_ops),
|
||||
AMD_NAVI14(&amd_navi10_ops),
|
||||
_AMD_POLARIS10(&amd_polaris10_ops),
|
||||
_AMD_POLARIS11(&amd_polaris10_ops),
|
||||
_AMD_POLARIS12(&amd_polaris10_ops),
|
||||
_AMD_VEGA10(&amd_vega10_ops),
|
||||
_AMD_VEGA20(&amd_vega20_ops),
|
||||
_AMD_NAVI10(&amd_navi10_ops),
|
||||
_AMD_NAVI14(&amd_navi10_ops),
|
||||
_AMD_NAVI12(&amd_navi10_ops),
|
||||
{0},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ static int hooked_pci_dev_specific_reset(struct pci_dev *dev, int probe)
|
|||
if (cfg->vendor)
|
||||
{
|
||||
vdev.pdev = dev;
|
||||
vdev.info = cfg->info;
|
||||
|
||||
if (cfg->ops->pre_reset && (ret = cfg->ops->pre_reset(&vdev)) && ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
struct vendor_reset_dev
|
||||
{
|
||||
struct pci_dev *pdev;
|
||||
unsigned long info;
|
||||
|
||||
int reset_ret;
|
||||
|
||||
|
|
@ -54,6 +55,9 @@ struct vendor_reset_cfg
|
|||
|
||||
/* the reset operations */
|
||||
const struct vendor_reset_ops * ops;
|
||||
|
||||
/* device type for combined ops */
|
||||
unsigned long info;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ static long vendor_reset_ioctl_reset(struct file * filp, unsigned long arg)
|
|||
}
|
||||
|
||||
vdev.pdev = pcidev;
|
||||
vdev.info = entry->info;
|
||||
|
||||
/* we probably always want to lock the device */
|
||||
if (!pci_cfg_access_trylock(pcidev))
|
||||
|
|
|
|||
Loading…
Reference in New Issue