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cd86f6c24d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.60 All patches automatically rebased. Build system: x86/64 Build-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: x86/64/AMD Cezanne, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia <therealgraysky@proton.me>
47 lines
2.1 KiB
Diff
47 lines
2.1 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Mon, 15 Feb 2021 23:59:26 +0100
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Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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GPHY needs to be enabled to succesfully probe & setup switch port
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connected to it. Otherwise hardcoding PHY OUI would be required.
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Before:
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brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
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After:
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brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
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brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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drivers/net/dsa/bcm_sf2.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/net/dsa/bcm_sf2.c
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+++ b/drivers/net/dsa/bcm_sf2.c
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@@ -1522,10 +1522,14 @@ static int bcm_sf2_sw_probe(struct platf
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rev = reg_readl(priv, REG_PHY_REVISION);
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priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
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+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
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+
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ret = b53_switch_register(dev);
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if (ret)
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goto out_mdio;
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+ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
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+
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dev_info(&pdev->dev,
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"Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
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priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
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