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f8ea89c2d4
SBL will configure IPQ807x cores to boot at 800MHz as a safe default frequency that is provided by GPLL0, but GPLL0 is not currently configured as a possible parent in the APSS clock driver not being passed to it via DTS which will then cause the kernel to not properly identify the current CPU frequency during booting and will think that CPU is currently at XO frequency of 19.2MHz instead of 800MHz cores are actually at and print: cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 19200 KHz, changing to: 1017600 KHz So, lets import patches pending upstream to prevent GPLL scaling and feed the GPLL0 clock to APSS clock driver so we get: cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 800000 KHz, changing to: 1017600 KHz This is mostly cosmetic fix, but with all of the possible SBL and FW versions there could be edge cases resolved by this and not scaling GPLL-s anymore. Signed-off-by: Robert Marko <robimarko@gmail.com> |
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| .. | ||
| files/arch/arm64/boot/dts/qcom | ||
| image | ||
| ipq807x | ||
| patches-6.1 | ||
| config-6.1 | ||
| Makefile | ||