Martin Blumenstingl 2683cca592 lantiq: dts: vr9: Add missing properties to the CPU port on the switch ... The CPU port should define the phy-mode and and a PHY phandle or fixed-link to indicate how the CPU port is connected to the SoC's Ethernet controller. On xRX200 this is all internal connection, so use phy-mode = "internal" along with a fixed-link that matches the definition inside &eth0. Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports"). when these properties are missing. Adding the properties before OpenWrt is updated to Linux 6.0 is harmless. Suggested-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>		2022-10-10 21:51:05 +02:00
..
ase
base-files
falcon
files	lantiq: dts: vr9: Add missing properties to the CPU port on the switch	2022-10-10 21:51:05 +02:00
image
patches-5.10	kernel: bump 5.10 to 5.10.147	2022-10-09 22:18:24 +02:00
xrx200	ltq-vdsl-app: rename to ltq-vdsl-vr9-app	2022-09-17 17:39:23 +02:00
xway
xway_legacy
config-5.10	kernel: Activate CONFIG_GPIOLIB in generic configuration	2022-08-10 21:36:17 +02:00
Makefile
modules.mk