73 lines
1.8 KiB
Diff
73 lines
1.8 KiB
Diff
From 42145b7a823530f57983fb6e6897f40c0be278d5 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Mon, 18 Sep 2023 16:14:49 +0200
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Subject: [PATCH] arm64: dts: rockchip: add PCIe network controller to rock-5b
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Enable the RTL8125 network controller, which is connected via
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PCIe.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20230918141451.131247-2-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
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@@ -43,6 +43,15 @@
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#cooling-cells = <2>;
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};
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+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_pcie2x1l2";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc_3v3_s3>;
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+ };
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+
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vcc5v0_host: vcc5v0-host-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_host";
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@@ -77,6 +86,10 @@
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};
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};
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+&combphy0_ps {
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+ status = "okay";
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+};
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+
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&cpu_b0 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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@@ -203,6 +216,14 @@
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};
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};
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+&pcie2x1l2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_2_rst>;
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+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
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+ status = "okay";
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+};
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+
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&pinctrl {
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hym8563 {
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hym8563_int: hym8563-int {
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@@ -216,6 +237,12 @@
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};
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};
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+ pcie2 {
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+ pcie2_2_rst: pcie2-2-rst {
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+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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usb {
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vcc5v0_host_en: vcc5v0-host-en {
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rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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