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f2a8763587
I recently added support for the NorthStar ARM BCM53xx SoCs to the upstream U-Boot. This is a back port on top of the 2023.04 version already imported to OpenWrt with the 5 necessary upstream patches. This is needed to create a small U-Boot for the BCM53xx-based D-Link DIR-890L and I think also the DIR-885L, so that a recent (bigger) kernel can be loaded and executed from the SEAMA partitions on these devices. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
81 lines
2.6 KiB
Diff
81 lines
2.6 KiB
Diff
From d75483f8892f3a0dfb8f5aa4147e72c02c8b034c Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 7 Apr 2023 15:40:05 +0200
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Subject: [PATCH 2/5] mtd: rawnand: nand_base: Handle algorithm selection
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For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
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D-Link DIR-885L and DIR-890L routers, we need to explicitly
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select the ECC like this in the device tree:
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nand-ecc-algo = "bch";
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nand-ecc-strength = <1>;
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nand-ecc-step-size = <512>;
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This is handled by the Linux kernel but U-Boot core does
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not respect this. Fix it up by parsing the algorithm and
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preserve the behaviour using this property to select
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software BCH as far as possible.
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Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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Acked-by: William Zhang <william.zhang@broadcom.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
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Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
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Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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---
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drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++----
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1 file changed, 25 insertions(+), 4 deletions(-)
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--- a/drivers/mtd/nand/raw/nand_base.c
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+++ b/drivers/mtd/nand/raw/nand_base.c
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@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
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static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
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{
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int ret, ecc_mode = -1, ecc_strength, ecc_step;
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+ int ecc_algo = NAND_ECC_UNKNOWN;
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const char *str;
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ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
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@@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info
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ecc_mode = NAND_ECC_SOFT_BCH;
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}
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- if (ecc_mode == NAND_ECC_SOFT) {
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- str = ofnode_read_string(node, "nand-ecc-algo");
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- if (str && !strcmp(str, "bch"))
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- ecc_mode = NAND_ECC_SOFT_BCH;
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+ str = ofnode_read_string(node, "nand-ecc-algo");
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+ if (str) {
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+ /*
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+ * If we are in NAND_ECC_SOFT mode, just alter the
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+ * soft mode to BCH here. No change of algorithm.
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+ */
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+ if (ecc_mode == NAND_ECC_SOFT) {
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+ if (!strcmp(str, "bch"))
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+ ecc_mode = NAND_ECC_SOFT_BCH;
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+ } else {
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+ if (!strcmp(str, "bch")) {
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+ ecc_algo = NAND_ECC_BCH;
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+ } else if (!strcmp(str, "hamming")) {
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+ ecc_algo = NAND_ECC_HAMMING;
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+ }
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+ }
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}
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ecc_strength = ofnode_read_s32_default(node,
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@@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info
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return -EINVAL;
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}
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+ /*
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+ * Chip drivers may have assigned default algorithms here,
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+ * onlt override it if we have found something explicitly
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+ * specified in the device tree.
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+ */
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+ if (ecc_algo != NAND_ECC_UNKNOWN)
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+ chip->ecc.algo = ecc_algo;
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+
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if (ecc_mode >= 0)
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chip->ecc.mode = ecc_mode;
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