mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-12 18:05:15 +00:00
124 lines
3.5 KiB
Diff
124 lines
3.5 KiB
Diff
From 5971a2f283d21eab36d7de24d35301f081f83418 Mon Sep 17 00:00:00 2001
|
|
From: Reinder de Haan <patchesrdh@mveas.com>
|
|
Date: Tue, 3 Nov 2015 15:14:20 +0100
|
|
Subject: [PATCH] ARM: dts: sun8i: Add usbphy and usb host controller nodes
|
|
|
|
Add nodes describing the H3's usbphy and usb host controller nodes.
|
|
|
|
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
|
|
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
---
|
|
arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 101 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
@@ -362,6 +362,107 @@
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
+ usbphy: phy@01c19400 {
|
|
+ compatible = "allwinner,sun8i-h3-usb-phy";
|
|
+ reg = <0x01c19400 0x2c>,
|
|
+ <0x01c1a800 0x4>,
|
|
+ <0x01c1b800 0x4>,
|
|
+ <0x01c1c800 0x4>,
|
|
+ <0x01c1d800 0x4>;
|
|
+ reg-names = "phy_ctrl",
|
|
+ "pmu0",
|
|
+ "pmu1",
|
|
+ "pmu2",
|
|
+ "pmu3";
|
|
+ clocks = <&usb_clk 8>,
|
|
+ <&usb_clk 9>,
|
|
+ <&usb_clk 10>,
|
|
+ <&usb_clk 11>;
|
|
+ clock-names = "usb0_phy",
|
|
+ "usb1_phy",
|
|
+ "usb2_phy",
|
|
+ "usb3_phy";
|
|
+ resets = <&usb_clk 0>,
|
|
+ <&usb_clk 1>,
|
|
+ <&usb_clk 2>,
|
|
+ <&usb_clk 3>;
|
|
+ reset-names = "usb0_reset",
|
|
+ "usb1_reset",
|
|
+ "usb2_reset",
|
|
+ "usb3_reset";
|
|
+ status = "disabled";
|
|
+ #phy-cells = <1>;
|
|
+ };
|
|
+
|
|
+ ehci1: usb@01c1b000 {
|
|
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
|
|
+ reg = <0x01c1b000 0x100>;
|
|
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 25>, <&bus_gates 29>;
|
|
+ resets = <&ahb_rst 25>, <&ahb_rst 29>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ohci1: usb@01c1b400 {
|
|
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
|
|
+ reg = <0x01c1b400 0x100>;
|
|
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 29>, <&bus_gates 25>,
|
|
+ <&usb_clk 17>;
|
|
+ resets = <&ahb_rst 29>, <&ahb_rst 25>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ehci2: usb@01c1c000 {
|
|
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
|
|
+ reg = <0x01c1c000 0x100>;
|
|
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 26>, <&bus_gates 30>;
|
|
+ resets = <&ahb_rst 26>, <&ahb_rst 30>;
|
|
+ phys = <&usbphy 2>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ohci2: usb@01c1c400 {
|
|
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
|
|
+ reg = <0x01c1c400 0x100>;
|
|
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 30>, <&bus_gates 26>,
|
|
+ <&usb_clk 18>;
|
|
+ resets = <&ahb_rst 30>, <&ahb_rst 26>;
|
|
+ phys = <&usbphy 2>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ehci3: usb@01c1d000 {
|
|
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
|
|
+ reg = <0x01c1d000 0x100>;
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 27>, <&bus_gates 31>;
|
|
+ resets = <&ahb_rst 27>, <&ahb_rst 31>;
|
|
+ phys = <&usbphy 3>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ohci3: usb@01c1d400 {
|
|
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
|
|
+ reg = <0x01c1d400 0x100>;
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 31>, <&bus_gates 27>,
|
|
+ <&usb_clk 19>;
|
|
+ resets = <&ahb_rst 31>, <&ahb_rst 27>;
|
|
+ phys = <&usbphy 3>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun8i-h3-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|