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git://git.openwrt.org/openwrt/openwrt.git
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8c6f00ef4f
Refresh patches.
Remove upstreamed patches:
- backport/096-mips-math-emu-Write-protect-delay-slot-emulation-pages.patch
- pending/510-f2fs-fix-sanity_check_raw_super-on-big-endian-machines.patch
- brcm2708/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
Compile-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Runtime-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
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Date: Fri, 7 Jun 2013 18:35:22 -0500
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Subject: MIPS: r4k_cache: use more efficient cache blast
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Optimize the compiler output for larger cache blast cases that are
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common for DMA-based networking.
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Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -683,16 +683,48 @@ static inline void prot##extra##blast_##
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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+ unsigned long lsize_2 = lsize * 2; \
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+ unsigned long lsize_3 = lsize * 3; \
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+ unsigned long lsize_4 = lsize * 4; \
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+ unsigned long lsize_5 = lsize * 5; \
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+ unsigned long lsize_6 = lsize * 6; \
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+ unsigned long lsize_7 = lsize * 7; \
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+ unsigned long lsize_8 = lsize * 8; \
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unsigned long addr = start & ~(lsize - 1); \
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- unsigned long aend = (end - 1) & ~(lsize - 1); \
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+ unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
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+ int lines = (aend - addr) / lsize; \
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\
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__##pfx##flush_prologue \
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\
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- while (1) { \
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+ while (lines >= 8) { \
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+ prot##cache_op(hitop, addr); \
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+ prot##cache_op(hitop, addr + lsize); \
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+ prot##cache_op(hitop, addr + lsize_2); \
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+ prot##cache_op(hitop, addr + lsize_3); \
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+ prot##cache_op(hitop, addr + lsize_4); \
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+ prot##cache_op(hitop, addr + lsize_5); \
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+ prot##cache_op(hitop, addr + lsize_6); \
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+ prot##cache_op(hitop, addr + lsize_7); \
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+ addr += lsize_8; \
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+ lines -= 8; \
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+ } \
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+ \
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+ if (lines & 0x4) { \
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+ prot##cache_op(hitop, addr); \
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+ prot##cache_op(hitop, addr + lsize); \
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+ prot##cache_op(hitop, addr + lsize_2); \
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+ prot##cache_op(hitop, addr + lsize_3); \
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+ addr += lsize_4; \
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+ } \
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+ \
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+ if (lines & 0x2) { \
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+ prot##cache_op(hitop, addr); \
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+ prot##cache_op(hitop, addr + lsize); \
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+ addr += lsize_2; \
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+ } \
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+ \
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+ if (lines & 0x1) { \
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prot##cache_op(hitop, addr); \
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- if (addr == aend) \
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- break; \
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- addr += lsize; \
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} \
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\
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__##pfx##flush_epilogue \
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