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git://git.openwrt.org/openwrt/openwrt.git
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186 lines
5.2 KiB
Diff
186 lines
5.2 KiB
Diff
From 34e65b6f310234cf3e3629bd3d896a4f84df71f4 Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Fri, 26 Aug 2016 16:09:00 -0400
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Subject: [PATCH] rtl8xxxu: Implement rtl8188eu_power_off()
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This makes the driver match the poweroff sequence of the vendor driver
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and allows the firmware to reload correctly upon rmmod/insmod.
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However the device still doesn't receive data upon reloading.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 136 ++++++++++++++++++++-
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 2 +
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2 files changed, 137 insertions(+), 1 deletion(-)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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@@ -1191,6 +1191,71 @@ exit:
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return ret;
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}
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+static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+
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+ /* 0x04[12:11] = 01 enable WL suspend */
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+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
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+ val8 &= ~BIT(0);
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+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
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+ val8 |= BIT(7);
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+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
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+
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+ return 0;
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+}
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+
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+static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv)
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+{
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+ struct device *dev = &priv->udev->dev;
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+ u8 val8;
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+ u16 val16;
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+ u32 val32;
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+ int retry, retval;
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+
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+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0x7f);
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+
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+ retry = 100;
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+ retval = -EBUSY;
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+ /*
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+ * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
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+ */
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+ do {
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+ val32 = rtl8xxxu_read32(priv, 0x05f8);
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+ if (!val32) {
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+ retval = 0;
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+ break;
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+ }
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+ } while (retry--);
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+
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+ if (!retry) {
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+ dev_warn(dev, "Failed to flush TX queue\n");
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+ retval = -EBUSY;
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+ goto out;
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+ }
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+
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+ /* Disable CCK and OFDM, clock gated */
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+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
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+ val8 &= ~SYS_FUNC_BBRSTB;
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+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
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+
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+ udelay(2);
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+
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+ /* Reset MAC TRX */
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+ val16 = rtl8xxxu_read16(priv, REG_CR);
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+ val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE);
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+ rtl8xxxu_write16(priv, REG_CR, val16);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
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+ val8 |= DUAL_TSF_TX_OK;
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+ rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
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+
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+out:
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+ return retval;
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+}
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+
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static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv)
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{
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u16 val16;
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@@ -1221,6 +1286,75 @@ exit:
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return ret;
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}
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+void rtl8188eu_power_off(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+ u16 val16;
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+
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+ rtl8xxxu_flush_fifo(priv);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
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+ val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
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+ rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
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+
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+ /* Turn off RF */
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+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
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+
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+ rtl8188eu_active_to_lps(priv);
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+
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+ /* Reset Firmware if running in RAM */
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+ if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
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+ rtl8xxxu_firmware_self_reset(priv);
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+
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+ /* Reset MCU */
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+ val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
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+ val16 &= ~SYS_FUNC_CPU_ENABLE;
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+ rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
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+
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+ /* Reset MCU ready status */
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+ rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
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+
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+ /* 32K_CTRL looks to be very 8188e specific */
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+ val8 = rtl8xxxu_read8(priv, REG_32K_CTRL);
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+ val8 &= ~BIT(0);
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+ rtl8xxxu_write8(priv, REG_32K_CTRL, val8);
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+
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+ rtl8188eu_active_to_emu(priv);
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+ rtl8188eu_emu_to_disabled(priv);
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+
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+ /* Reset MCU IO Wrapper */
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+ val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
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+ val8 &= ~BIT(3);
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+ rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
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+ val8 |= BIT(3);
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+ rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
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+
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+ /* Vendor driver refers to GPIO_IN */
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+ val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL);
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+ /* Vendor driver refers to GPIO_OUT */
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+ rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val8);
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+ rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, 0xff);
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+
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+ val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL);
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+ rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 << 4);
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+ val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1);
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+ rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 | 0x0f);
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+
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+ /*
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+ * Set LNA, TRSW, EX_PA Pin to output mode
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+ * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver
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+ */
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+ rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808);
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+
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+ rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x00);
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+
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+ val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
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+ val16 |= APS_FSMCO_ENABLE_POWERDOWN | APS_FSMCO_HW_POWERDOWN;
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+ rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
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+}
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+
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static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv)
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{
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rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
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@@ -1265,7 +1399,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
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.parse_efuse = rtl8188eu_parse_efuse,
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.load_firmware = rtl8188eu_load_firmware,
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.power_on = rtl8188eu_power_on,
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- .power_off = rtl8xxxu_power_off,
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+ .power_off = rtl8188eu_power_off,
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.reset_8051 = rtl8188eu_reset_8051,
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.llt_init = rtl8xxxu_init_llt_table,
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.init_phy_bb = rtl8188eu_init_phy_bb,
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
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@@ -418,6 +418,8 @@
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#define REG_MBIST_START 0x0174
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#define REG_MBIST_DONE 0x0178
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#define REG_MBIST_FAIL 0x017c
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+/* 8188EU */
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+#define REG_32K_CTRL 0x0194
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#define REG_C2HEVT_MSG_NORMAL 0x01a0
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/* 8192EU/8723BU/8812 */
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#define REG_C2HEVT_CMD_ID_8723B 0x01ae
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