211 lines
5.7 KiB
Diff
211 lines
5.7 KiB
Diff
From 466ed24fb22342f3ae1c10758a6a0c6a8c081b2d Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Thu, 30 Apr 2020 11:07:05 +0200
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Subject: [PATCH] net: phy: mdio: add IPQ4019 MDIO driver
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This patch adds the driver for the MDIO interface
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inside of Qualcomm IPQ40xx series SoC-s.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Cc: Luka Perkov <luka.perkov@sartura.hr>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/Kconfig | 7 ++
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/mdio-ipq4019.c | 160 +++++++++++++++++++++++++++++++++
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3 files changed, 168 insertions(+)
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create mode 100644 drivers/net/phy/mdio-ipq4019.c
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -156,6 +156,13 @@ config MDIO_I2C
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This is library mode.
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+config MDIO_IPQ4019
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+ tristate "Qualcomm IPQ4019 MDIO interface support"
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+ depends on HAS_IOMEM && OF_MDIO
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+ help
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+ This driver supports the MDIO interface found in Qualcomm
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+ IPQ40xx series Soc-s.
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+
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config MDIO_MOXART
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tristate "MOXA ART MDIO interface support"
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depends on ARCH_MOXART || COMPILE_TEST
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
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obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
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obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
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obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
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+obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
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obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
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obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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--- /dev/null
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+++ b/drivers/net/phy/mdio-ipq4019.c
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@@ -0,0 +1,160 @@
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+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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+/* Copyright (c) 2015, The Linux Foundation. All rights reserved. */
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+/* Copyright (c) 2020 Sartura Ltd. */
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+
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+#include <linux/delay.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/of_address.h>
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+#include <linux/of_mdio.h>
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+#include <linux/phy.h>
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+#include <linux/platform_device.h>
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+
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+#define MDIO_ADDR_REG 0x44
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+#define MDIO_DATA_WRITE_REG 0x48
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+#define MDIO_DATA_READ_REG 0x4c
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+#define MDIO_CMD_REG 0x50
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+#define MDIO_CMD_ACCESS_BUSY BIT(16)
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+#define MDIO_CMD_ACCESS_START BIT(8)
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+#define MDIO_CMD_ACCESS_CODE_READ 0
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+#define MDIO_CMD_ACCESS_CODE_WRITE 1
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+
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+#define ipq4019_MDIO_TIMEOUT 10000
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+#define ipq4019_MDIO_SLEEP 10
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+
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+struct ipq4019_mdio_data {
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+ void __iomem *membase;
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+};
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+
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+static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
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+{
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+ struct ipq4019_mdio_data *priv = bus->priv;
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+ unsigned int busy;
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+
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+ return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,
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+ (busy & MDIO_CMD_ACCESS_BUSY) == 0,
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+ ipq4019_MDIO_SLEEP, ipq4019_MDIO_TIMEOUT);
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+}
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+
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+static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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+{
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+ struct ipq4019_mdio_data *priv = bus->priv;
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+ unsigned int cmd;
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+
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+ /* Reject clause 45 */
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+ if (regnum & MII_ADDR_C45)
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+ return -EOPNOTSUPP;
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+
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+ if (ipq4019_mdio_wait_busy(bus))
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+ return -ETIMEDOUT;
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+
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+ /* issue the phy address and reg */
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+ writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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+
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+ cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
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+
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+ /* issue read command */
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+ writel(cmd, priv->membase + MDIO_CMD_REG);
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+
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+ /* Wait read complete */
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+ if (ipq4019_mdio_wait_busy(bus))
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+ return -ETIMEDOUT;
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+
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+ /* Read and return data */
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+ return readl(priv->membase + MDIO_DATA_READ_REG);
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+}
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+
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+static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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+ u16 value)
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+{
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+ struct ipq4019_mdio_data *priv = bus->priv;
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+ unsigned int cmd;
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+
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+ /* Reject clause 45 */
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+ if (regnum & MII_ADDR_C45)
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+ return -EOPNOTSUPP;
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+
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+ if (ipq4019_mdio_wait_busy(bus))
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+ return -ETIMEDOUT;
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+
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+ /* issue the phy address and reg */
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+ writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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+
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+ /* issue write data */
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+ writel(value, priv->membase + MDIO_DATA_WRITE_REG);
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+
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+ cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
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+ /* issue write command */
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+ writel(cmd, priv->membase + MDIO_CMD_REG);
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+
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+ /* Wait write complete */
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+ if (ipq4019_mdio_wait_busy(bus))
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+ return -ETIMEDOUT;
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+
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+ return 0;
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+}
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+
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+static int ipq4019_mdio_probe(struct platform_device *pdev)
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+{
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+ struct ipq4019_mdio_data *priv;
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+ struct mii_bus *bus;
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+ int ret;
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+
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+ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
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+ if (!bus)
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+ return -ENOMEM;
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+
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+ priv = bus->priv;
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+
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+ priv->membase = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(priv->membase))
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+ return PTR_ERR(priv->membase);
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+
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+ bus->name = "ipq4019_mdio";
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+ bus->read = ipq4019_mdio_read;
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+ bus->write = ipq4019_mdio_write;
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+ bus->parent = &pdev->dev;
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+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
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+
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+ ret = of_mdiobus_register(bus, pdev->dev.of_node);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
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+ return ret;
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+ }
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+
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+ platform_set_drvdata(pdev, bus);
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+
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+ return 0;
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+}
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+
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+static int ipq4019_mdio_remove(struct platform_device *pdev)
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+{
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+ struct mii_bus *bus = platform_get_drvdata(pdev);
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+
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+ mdiobus_unregister(bus);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id ipq4019_mdio_dt_ids[] = {
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+ { .compatible = "qcom,ipq4019-mdio" },
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+ { }
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+};
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+MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids);
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+
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+static struct platform_driver ipq4019_mdio_driver = {
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+ .probe = ipq4019_mdio_probe,
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+ .remove = ipq4019_mdio_remove,
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+ .driver = {
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+ .name = "ipq4019-mdio",
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+ .of_match_table = ipq4019_mdio_dt_ids,
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+ },
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+};
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+
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+module_platform_driver(ipq4019_mdio_driver);
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+
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+MODULE_DESCRIPTION("ipq4019 MDIO interface driver");
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+MODULE_AUTHOR("Qualcomm Atheros");
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+MODULE_LICENSE("Dual BSD/GPL");
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