mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-27 00:52:36 +00:00
83b1e40561
Removed since added upstream:
bcm27xx:
950-0428-staging-vchiq_arm-Add-a-matching-unregister-call.patch
lantiq:
0800-spi-lantiq-ssc-Fix-warning-by-using-WQ_MEM_RECLAI.patch
Manually adjusted patches:
layerscape:
801-audio-0005-Revert-ASoC-fsl_sai-Add-support-for-SAI-new-version.patch
Build-tested: ath79/generic, ramips, lantiq/xrx200, lantiq/xway,
mvebu/cortexa9, sunxi/a53
Run-tested: ipq806x (R7800), layerscape (LS1012A-FRDM, LS1046A-RDB)
Building on layerscape is only possible with workaround from PR #3179.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Tested-By: John Audia <graysky@archlinux.us> [ipq806x]
Tested-by: Pawel Dembicki <paweldembicki@gmail.com> [layerscape]
362 lines
10 KiB
Diff
362 lines
10 KiB
Diff
From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 13 Mar 2020 18:52:13 +0100
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Subject: cpufreq: qcom: Add support for krait based socs
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In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
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that has KRAIT processors the voltage/current value of each OPP
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varies based on the silicon variant in use.
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The required OPP related data is determined based on
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the efuse value. This is similar to the existing code for
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kryo cores. So adding support for krait cores here.
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
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drivers/cpufreq/Kconfig.arm | 2 +-
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drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 191 +++++++++++++++++++--
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4 files changed, 183 insertions(+), 18 deletions(-)
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--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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@@ -19,7 +19,8 @@ In 'cpu' nodes:
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In 'operating-points-v2' table:
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- compatible: Should be
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- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
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+ - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
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+ apq8064, ipq8064, msm8960 and ipq8074.
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Optional properties:
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--------------------
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--- a/drivers/cpufreq/Kconfig.arm
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+++ b/drivers/cpufreq/Kconfig.arm
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@@ -135,7 +135,7 @@ config ARM_OMAP2PLUS_CPUFREQ
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config ARM_QCOM_CPUFREQ_NVMEM
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tristate "Qualcomm nvmem based CPUFreq"
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- depends on ARM64
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+ depends on ARCH_QCOM
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depends on QCOM_QFPROM
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depends on QCOM_SMEM
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select PM_OPP
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -138,6 +138,11 @@ static const struct of_device_id blackli
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{ .compatible = "ti,am43", },
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{ .compatible = "ti,dra7", },
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+ { .compatible = "qcom,ipq8064", },
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+ { .compatible = "qcom,apq8064", },
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+ { .compatible = "qcom,msm8974", },
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+ { .compatible = "qcom,msm8960", },
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+
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{ }
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};
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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int (*get_version)(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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struct qcom_cpufreq_drv *drv);
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const char **genpd_names;
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};
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struct qcom_cpufreq_drv {
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- struct opp_table **opp_tables;
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+ struct opp_table **names_opp_tables;
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+ struct opp_table **hw_opp_tables;
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struct opp_table **genpd_opp_tables;
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u32 versions;
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const struct qcom_cpufreq_match_data *data;
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@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
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static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
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+static void get_krait_bin_format_a(struct device *cpu_dev,
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+ int *speed, int *pvs, int *pvs_ver,
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+ struct nvmem_cell *pvs_nvmem, u8 *buf)
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+{
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+ u32 pte_efuse;
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+
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+ pte_efuse = *((u32 *)buf);
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+
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+ *speed = pte_efuse & 0xf;
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+ if (*speed == 0xf)
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+ *speed = (pte_efuse >> 4) & 0xf;
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+
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+ if (*speed == 0xf) {
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+ *speed = 0;
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+ dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
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+ } else {
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+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
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+ }
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+
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+ *pvs = (pte_efuse >> 10) & 0x7;
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+ if (*pvs == 0x7)
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+ *pvs = (pte_efuse >> 13) & 0x7;
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+
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+ if (*pvs == 0x7) {
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+ *pvs = 0;
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+ dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
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+ } else {
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+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
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+ }
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+}
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+
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+static void get_krait_bin_format_b(struct device *cpu_dev,
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+ int *speed, int *pvs, int *pvs_ver,
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+ struct nvmem_cell *pvs_nvmem, u8 *buf)
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+{
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+ u32 pte_efuse, redundant_sel;
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+
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+ pte_efuse = *((u32 *)buf);
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+ redundant_sel = (pte_efuse >> 24) & 0x7;
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+
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+ *pvs_ver = (pte_efuse >> 4) & 0x3;
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+
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+ switch (redundant_sel) {
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+ case 1:
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+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
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+ *speed = (pte_efuse >> 27) & 0xf;
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+ break;
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+ case 2:
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+ *pvs = (pte_efuse >> 27) & 0xf;
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+ *speed = pte_efuse & 0x7;
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+ break;
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+ default:
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+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
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+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
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+ *speed = pte_efuse & 0x7;
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+ }
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+
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+ /* Check SPEED_BIN_BLOW_STATUS */
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+ if (pte_efuse & BIT(3)) {
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+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
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+ } else {
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+ dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
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+ *speed = 0;
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+ }
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+
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+ /* Check PVS_BLOW_STATUS */
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+ pte_efuse = *(((u32 *)buf) + 4);
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+ pte_efuse &= BIT(21);
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+ if (pte_efuse) {
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+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
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+ } else {
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+ dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
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+ *pvs = 0;
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+ }
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+
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+ dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
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+}
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+
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static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
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{
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size_t len;
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@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre
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static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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struct qcom_cpufreq_drv *drv)
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{
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size_t len;
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u8 *speedbin;
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enum _msm8996_version msm8996_version;
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+ *pvs_name = NULL;
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msm8996_version = qcom_cpufreq_get_msm_id();
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if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
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@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio
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return 0;
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}
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+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
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+ struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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+ struct qcom_cpufreq_drv *drv)
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+{
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+ int speed = 0, pvs = 0, pvs_ver = 0;
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+ u8 *speedbin;
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+ size_t len;
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+
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+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
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+
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+ if (IS_ERR(speedbin))
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+ return PTR_ERR(speedbin);
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+
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+ switch (len) {
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+ case 4:
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+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
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+ speedbin_nvmem, speedbin);
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+ break;
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+ case 8:
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+ get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
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+ speedbin_nvmem, speedbin);
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+ break;
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+ default:
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+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
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+ return -ENODEV;
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+ }
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+
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+ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
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+ speed, pvs, pvs_ver);
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+
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+ drv->versions = (1 << speed);
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+
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+ kfree(speedbin);
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+ return 0;
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+}
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+
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static const struct qcom_cpufreq_match_data match_data_kryo = {
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.get_version = qcom_cpufreq_kryo_name_version,
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};
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+static const struct qcom_cpufreq_match_data match_data_krait = {
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+ .get_version = qcom_cpufreq_krait_name_version,
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+};
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+
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static const char *qcs404_genpd_names[] = { "cpr", NULL };
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static const struct qcom_cpufreq_match_data match_data_qcs404 = {
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@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla
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struct nvmem_cell *speedbin_nvmem;
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struct device_node *np;
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struct device *cpu_dev;
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+ char *pvs_name = "speedXX-pvsXX-vXX";
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unsigned cpu;
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const struct of_device_id *match;
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int ret;
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@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
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if (!np)
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return -ENOENT;
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- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
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+ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
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if (!ret) {
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of_node_put(np);
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return -ENOENT;
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@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla
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goto free_drv;
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}
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- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
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+ ret = drv->data->get_version(cpu_dev,
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+ speedbin_nvmem, &pvs_name, drv);
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if (ret) {
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nvmem_cell_put(speedbin_nvmem);
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goto free_drv;
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@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla
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}
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of_node_put(np);
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- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
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+ drv->names_opp_tables = kcalloc(num_possible_cpus(),
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+ sizeof(*drv->names_opp_tables),
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GFP_KERNEL);
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- if (!drv->opp_tables) {
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+ if (!drv->names_opp_tables) {
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ret = -ENOMEM;
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goto free_drv;
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}
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+ drv->hw_opp_tables = kcalloc(num_possible_cpus(),
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+ sizeof(*drv->hw_opp_tables),
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+ GFP_KERNEL);
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+ if (!drv->hw_opp_tables) {
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+ ret = -ENOMEM;
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+ goto free_opp_names;
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+ }
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drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
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sizeof(*drv->genpd_opp_tables),
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@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla
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}
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if (drv->data->get_version) {
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- drv->opp_tables[cpu] =
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- dev_pm_opp_set_supported_hw(cpu_dev,
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- &drv->versions, 1);
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- if (IS_ERR(drv->opp_tables[cpu])) {
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- ret = PTR_ERR(drv->opp_tables[cpu]);
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+
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+ if (pvs_name) {
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+ drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
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+ cpu_dev,
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+ pvs_name);
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+ if (IS_ERR(drv->names_opp_tables[cpu])) {
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+ ret = PTR_ERR(drv->names_opp_tables[cpu]);
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+ dev_err(cpu_dev, "Failed to add OPP name %s\n",
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+ pvs_name);
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+ goto free_opp;
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+ }
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+ }
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+
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+ drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
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+ cpu_dev, &drv->versions, 1);
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+ if (IS_ERR(drv->hw_opp_tables[cpu])) {
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+ ret = PTR_ERR(drv->hw_opp_tables[cpu]);
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dev_err(cpu_dev,
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"Failed to set supported hardware\n");
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goto free_genpd_opp;
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@@ -259,11 +404,18 @@ free_genpd_opp:
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kfree(drv->genpd_opp_tables);
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free_opp:
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for_each_possible_cpu(cpu) {
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- if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
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+ if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
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+ break;
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+ dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
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+ }
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+ for_each_possible_cpu(cpu) {
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+ if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
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break;
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- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
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+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
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}
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- kfree(drv->opp_tables);
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+ kfree(drv->hw_opp_tables);
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+free_opp_names:
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+ kfree(drv->names_opp_tables);
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free_drv:
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kfree(drv);
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@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl
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platform_device_unregister(cpufreq_dt_pdev);
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for_each_possible_cpu(cpu) {
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- if (drv->opp_tables[cpu])
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- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
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+ if (drv->names_opp_tables[cpu])
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+ dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
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+ if (drv->hw_opp_tables[cpu])
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+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
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if (drv->genpd_opp_tables[cpu])
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dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
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}
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- kfree(drv->opp_tables);
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+ kfree(drv->names_opp_tables);
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+ kfree(drv->hw_opp_tables);
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kfree(drv->genpd_opp_tables);
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kfree(drv);
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@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp
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{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
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{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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+ { .compatible = "qcom,ipq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,apq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,msm8974", .data = &match_data_krait },
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+ { .compatible = "qcom,msm8960", .data = &match_data_krait },
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{},
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};
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