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git://git.openwrt.org/openwrt/openwrt.git
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f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
264 lines
7.9 KiB
Diff
264 lines
7.9 KiB
Diff
From d7805757c75c76e9518fc1023a29f0c4eed5b581 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 22:59:56 +0200
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Subject: [PATCH] net: dsa: qca8k: handle error with qca8k_write operation
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qca8k_write can fail. Rework any user to handle error values and
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correctly return.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 102 ++++++++++++++++++++++++++--------------
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1 file changed, 67 insertions(+), 35 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -168,7 +168,7 @@ exit:
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return val;
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}
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-static void
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+static int
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qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
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{
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struct mii_bus *bus = priv->bus;
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@@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32
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exit:
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mutex_unlock(&bus->mdio_lock);
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+ return ret;
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}
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static u32
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@@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
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- qca8k_write(priv, reg, val);
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-
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- return 0;
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+ return qca8k_write(priv, reg, val);
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}
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static const struct regmap_range qca8k_readable_ranges[] = {
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@@ -367,6 +366,7 @@ static int
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qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
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{
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u32 reg;
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+ int ret;
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/* Set the command and FDB index */
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reg = QCA8K_ATU_FUNC_BUSY;
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@@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv
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}
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/* Write the function register triggering the table access */
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- qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
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+ ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
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+ if (ret)
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+ return ret;
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/* wait for completion */
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if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
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@@ -447,6 +449,7 @@ static int
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qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
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{
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u32 reg;
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+ int ret;
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/* Set the command and VLAN index */
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reg = QCA8K_VTU_FUNC1_BUSY;
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@@ -454,7 +457,9 @@ qca8k_vlan_access(struct qca8k_priv *pri
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reg |= vid << QCA8K_VTU_FUNC1_VID_S;
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/* Write the function register triggering the table access */
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- qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
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+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
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+ if (ret)
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+ return ret;
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/* wait for completion */
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if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))
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@@ -502,7 +507,9 @@ qca8k_vlan_add(struct qca8k_priv *priv,
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reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
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QCA8K_VTU_FUNC0_EG_MODE_S(port);
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- qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
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+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
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+ if (ret)
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+ return ret;
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ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
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out:
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@@ -545,7 +552,9 @@ qca8k_vlan_del(struct qca8k_priv *priv,
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if (del) {
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ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
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} else {
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- qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
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+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
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+ if (ret)
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+ return ret;
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ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
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}
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@@ -555,15 +564,20 @@ out:
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return ret;
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}
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-static void
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+static int
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qca8k_mib_init(struct qca8k_priv *priv)
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{
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+ int ret;
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+
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mutex_lock(&priv->reg_mutex);
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qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
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qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
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qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
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- qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
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+
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+ ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
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+
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mutex_unlock(&priv->reg_mutex);
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+ return ret;
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}
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static void
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@@ -600,6 +614,7 @@ static int
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qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
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{
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u32 phy, val;
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+ int ret;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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@@ -613,7 +628,9 @@ qca8k_mdio_write(struct qca8k_priv *priv
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QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
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QCA8K_MDIO_MASTER_DATA(data);
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- qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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+ ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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+ if (ret)
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+ return ret;
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return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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@@ -623,6 +640,7 @@ static int
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qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
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{
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u32 phy, val;
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+ int ret;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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@@ -635,7 +653,9 @@ qca8k_mdio_read(struct qca8k_priv *priv,
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QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
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QCA8K_MDIO_MASTER_REG_ADDR(regnum);
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- qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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+ ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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+ if (ret)
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+ return ret;
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if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY))
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@@ -766,12 +786,18 @@ qca8k_setup(struct dsa_switch *ds)
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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/* Enable MIB counters */
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- qca8k_mib_init(priv);
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+ ret = qca8k_mib_init(priv);
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+ if (ret)
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+ dev_warn(priv->dev, "mib init failed");
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/* Enable QCA header mode on the cpu port */
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- qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
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- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
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- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
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+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
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+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
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+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
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+ if (ret) {
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+ dev_err(priv->dev, "failed enabling QCA header mode");
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+ return ret;
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+ }
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/* Disable forwarding by default on all ports */
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for (i = 0; i < QCA8K_NUM_PORTS; i++)
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@@ -783,11 +809,13 @@ qca8k_setup(struct dsa_switch *ds)
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qca8k_port_set_status(priv, i, 0);
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/* Forward all unknown frames to CPU port for Linux processing */
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- qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
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- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
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- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
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- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
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+ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
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+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
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+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
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+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
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+ if (ret)
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+ return ret;
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/* Setup connection between CPU port & user ports */
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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@@ -815,16 +843,20 @@ qca8k_setup(struct dsa_switch *ds)
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qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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0xfff << shift,
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QCA8K_PORT_VID_DEF << shift);
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- qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
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- QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
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- QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
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+ ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
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+ QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
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+ QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
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+ if (ret)
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+ return ret;
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}
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}
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/* Setup our port MTUs to match power on defaults */
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for (i = 0; i < QCA8K_NUM_PORTS; i++)
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priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
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- qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
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+ ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
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+ if (ret)
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+ dev_warn(priv->dev, "failed setting MTU settings");
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/* Flush the FDB table */
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qca8k_fdb_flush(priv);
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@@ -1140,8 +1172,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds,
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
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- int ret = 0;
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u32 reg;
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+ int ret;
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mutex_lock(&priv->reg_mutex);
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reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
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@@ -1154,7 +1186,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds,
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reg |= lpi_en;
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else
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reg &= ~lpi_en;
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- qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
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+ ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
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exit:
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mutex_unlock(&priv->reg_mutex);
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@@ -1284,9 +1316,7 @@ qca8k_port_change_mtu(struct dsa_switch
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mtu = priv->port_mtu[i];
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/* Include L2 header / FCS length */
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- qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
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-
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- return 0;
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+ return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
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}
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static int
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