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git://git.openwrt.org/openwrt/openwrt.git
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123 lines
3.8 KiB
Diff
123 lines
3.8 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Subject: [PATCH] USB: bcma: improve USB 2.0 PHY support for BCM4709 and
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BCM47094
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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--- a/drivers/usb/host/bcma-hcd.c
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+++ b/drivers/usb/host/bcma-hcd.c
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@@ -31,6 +31,17 @@
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#include <linux/usb/ohci_pdriver.h>
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#include <linux/usb/xhci_pdriver.h>
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+/* DMU (Device Management Unit) */
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+#define BCMA_DMU_CRU_USB2_CONTROL 0x0164
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT 2
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT 12
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+#define BCMA_DMU_CRU_CLKSET_KEY 0x0180
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+#define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
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+#define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
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+#define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
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+
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MODULE_AUTHOR("Hauke Mehrtens");
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MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
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MODULE_LICENSE("GPL");
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@@ -167,10 +178,35 @@ static void bcma_hcd_init_chip_mips(stru
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}
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}
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+static u32 bcma_hcd_usb_ref_clk_get_rate(void __iomem *dmu)
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+{
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+ u32 val, ndiv, pdiv, ch2_mdiv, ch2_freq;
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+
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+ /* get divider integer from the cru_genpll_control5 */
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+ val = ioread32(dmu + 0x154);
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+ ndiv = (val >> 20) & 0x3ff;
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+ if (ndiv == 0)
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+ ndiv = 1 << 10;
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+
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+ /* get pdiv and ch2_mdiv from the cru_genpll_control6 */
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+ val = ioread32(dmu + 0x158);
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+ pdiv = (val >> 24) & 0x7;
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+ pdiv = (pdiv == 0) ? (1 << 3) : pdiv;
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+
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+ ch2_mdiv = val & 0xff;
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+ ch2_mdiv = (ch2_mdiv == 0) ? (1 << 8) : ch2_mdiv;
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+
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+ /* calculate ch2_freq based on 25MHz reference clock */
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+ ch2_freq = (25000000 / (pdiv * ch2_mdiv)) * ndiv;
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+
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+ return ch2_freq;
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+}
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+
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static void bcma_hcd_init_chip_arm_phy(struct bcma_device *dev)
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{
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struct bcma_device *arm_core;
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void __iomem *dmu;
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+ u32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;
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arm_core = bcma_find_core(dev->bus, BCMA_CORE_ARMCA9);
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if (!arm_core) {
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@@ -184,14 +220,29 @@ static void bcma_hcd_init_chip_arm_phy(s
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return;
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}
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+ ref_clk_rate = bcma_hcd_usb_ref_clk_get_rate(dmu);
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+
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+ usb2ctl = ioread32(dmu + BCMA_DMU_CRU_USB2_CONTROL);
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+
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+ usb_pll_pdiv = usb2ctl;
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+ usb_pll_pdiv &= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK;
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+ usb_pll_pdiv >>= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT;
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+ if (!usb_pll_pdiv)
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+ usb_pll_pdiv = 1 << 3;
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+
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+ /* Calculate ndiv based on a solid 1920 MHz that is for USB2 PHY */
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+ usb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;
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+
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/* Unlock DMU PLL settings */
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- iowrite32(0x0000ea68, dmu + 0x180);
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+ iowrite32(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);
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/* Write USB 2.0 PLL control setting */
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- iowrite32(0x00dd10c3, dmu + 0x164);
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+ usb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;
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+ usb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;
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+ iowrite32(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);
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/* Lock DMU PLL settings */
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- iowrite32(0x00000000, dmu + 0x180);
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+ iowrite32(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);
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iounmap(dmu);
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}
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@@ -219,15 +270,17 @@ static void bcma_hcd_init_chip_arm_hc(st
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static void bcma_hcd_init_chip_arm(struct bcma_device *dev)
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{
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+ struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo;
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+
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bcma_core_enable(dev, 0);
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- if (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4707 ||
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- dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM53018) {
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- if (dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4707 ||
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- dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4708)
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- bcma_hcd_init_chip_arm_phy(dev);
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+ if (chipinfo->id == BCMA_CHIP_ID_BCM4707 ||
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+ chipinfo->id == BCMA_CHIP_ID_BCM47094 ||
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+ chipinfo->id == BCMA_CHIP_ID_BCM53018) {
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+ bcma_hcd_init_chip_arm_phy(dev);
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- bcma_hcd_init_chip_arm_hc(dev);
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+ if (1) /* TODO: Exclude BCM53573 */
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+ bcma_hcd_init_chip_arm_hc(dev);
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}
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}
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