595 lines
10 KiB
Diff
595 lines
10 KiB
Diff
From: Felix Fietkau <nbd@openwrt.org>
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Date: Wed, 8 Jul 2015 13:56:37 +0200
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Subject: [PATCH] Add PowerPC soft-float support
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Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different
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instruction set for floating point operations (SPE).
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Executing regular PowerPC floating point instructions results in
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"Illegal instruction" errors.
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Make it possible to run these devices in soft-float mode.
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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---
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create mode 100644 src/fenv/powerpc/fenv-sf.c
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--- a/arch/powerpc/bits/fenv.h
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+++ b/arch/powerpc/bits/fenv.h
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@@ -1,3 +1,7 @@
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+#ifdef _SOFT_FLOAT
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+#define FE_ALL_EXCEPT 0
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+#define FE_TONEAREST 0
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+#else
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#define FE_TONEAREST 0
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#define FE_TOWARDZERO 1
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#define FE_UPWARD 2
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@@ -24,6 +28,7 @@
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#define FE_ALL_INVALID 0x01f80700
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#endif
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+#endif
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typedef unsigned fexcept_t;
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typedef double fenv_t;
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--- a/arch/powerpc/reloc.h
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+++ b/arch/powerpc/reloc.h
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@@ -1,4 +1,10 @@
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-#define LDSO_ARCH "powerpc"
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+#ifdef _SOFT_FLOAT
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+#define FP_SUFFIX "-sf"
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+#else
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+#define FP_SUFFIX ""
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+#endif
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+
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+#define LDSO_ARCH "powerpc" FP_SUFFIX
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#define TPOFF_K (-0x7000)
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--- a/configure
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+++ b/configure
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@@ -604,6 +604,10 @@ trycppif "_MIPSEL || __MIPSEL || __MIPSE
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trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
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fi
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+if test "$ARCH" = "powerpc" ; then
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+trycppif _SOFT_FLOAT "$t" && SUBARCH=${SUBARCH}-sf
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+fi
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+
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test "$ARCH" = "microblaze" && trycppif __MICROBLAZEEL__ "$t" \
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&& SUBARCH=${SUBARCH}el
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--- /dev/null
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+++ b/src/fenv/powerpc/fenv-sf.c
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@@ -0,0 +1,3 @@
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+#ifdef _SOFT_FLOAT
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+#include "../fenv.c"
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+#endif
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--- /dev/null
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+++ b/src/fenv/powerpc/fenv.S
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@@ -0,0 +1,129 @@
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+#ifndef _SOFT_FLOAT
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+.global feclearexcept
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+.type feclearexcept,@function
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+feclearexcept:
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+ andis. 3,3,0x3e00
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+ /* if (r3 & FE_INVALID) r3 |= all_invalid_flags */
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+ andis. 0,3,0x2000
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+ stwu 1,-16(1)
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+ beq- 0,1f
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+ oris 3,3,0x01f8
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+ ori 3,3,0x0700
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+1:
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+ /*
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+ * note: fpscr contains various fpu status and control
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+ * flags and we dont check if r3 may alter other flags
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+ * than the exception related ones
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+ * ufpscr &= ~r3
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+ */
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+ mffs 0
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+ stfd 0,8(1)
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+ lwz 9,12(1)
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+ andc 9,9,3
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+ stw 9,12(1)
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+ lfd 0,8(1)
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+ mtfsf 255,0
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+
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+ /* return 0 */
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+ li 3,0
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+ addi 1,1,16
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+ blr
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+
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+.global feraiseexcept
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+.type feraiseexcept,@function
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+feraiseexcept:
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+ andis. 3,3,0x3e00
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+ /* if (r3 & FE_INVALID) r3 |= software_invalid_flag */
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+ andis. 0,3,0x2000
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+ stwu 1,-16(1)
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+ beq- 0,1f
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+ ori 3,3,0x0400
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+1:
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+ /* fpscr |= r3 */
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+ mffs 0
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+ stfd 0,8(1)
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+ lwz 9,12(1)
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+ or 9,9,3
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+ stw 9,12(1)
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+ lfd 0,8(1)
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+ mtfsf 255,0
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+
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+ /* return 0 */
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+ li 3,0
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+ addi 1,1,16
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+ blr
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+
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+.global fetestexcept
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+.type fetestexcept,@function
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+fetestexcept:
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+ andis. 3,3,0x3e00
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+ /* return r3 & fpscr */
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+ stwu 1,-16(1)
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+ mffs 0
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+ stfd 0,8(1)
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+ lwz 9,12(1)
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+ addi 1,1,16
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+ and 3,3,9
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+ blr
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+
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+.global fegetround
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+.type fegetround,@function
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+fegetround:
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+ /* return fpscr & 3 */
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+ stwu 1,-16(1)
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+ mffs 0
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+ stfd 0,8(1)
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+ lwz 3,12(1)
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+ addi 1,1,16
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+ clrlwi 3,3,30
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+ blr
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+
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+.global __fesetround
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+.type __fesetround,@function
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+__fesetround:
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+ /*
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+ * note: invalid input is not checked, r3 < 4 must hold
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+ * fpscr = (fpscr & -4U) | r3
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+ */
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+ stwu 1,-16(1)
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+ mffs 0
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+ stfd 0,8(1)
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+ lwz 9,12(1)
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+ clrrwi 9,9,2
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+ or 9,9,3
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+ stw 9,12(1)
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+ lfd 0,8(1)
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+ mtfsf 255,0
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+
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+ /* return 0 */
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+ li 3,0
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+ addi 1,1,16
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+ blr
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+
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+.global fegetenv
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+.type fegetenv,@function
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+fegetenv:
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+ /* *r3 = fpscr */
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+ mffs 0
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+ stfd 0,0(3)
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+ /* return 0 */
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+ li 3,0
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+ blr
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+
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+.global fesetenv
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+.type fesetenv,@function
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+fesetenv:
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+ cmpwi 3, -1
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+ bne 1f
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+ mflr 4
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+ bl 2f
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+ .zero 8
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+2: mflr 3
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+ mtlr 4
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+1: /* fpscr = *r3 */
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+ lfd 0,0(3)
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+ mtfsf 255,0
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+ /* return 0 */
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+ li 3,0
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+ blr
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+#endif
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--- a/src/fenv/powerpc/fenv.s
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+++ /dev/null
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@@ -1,123 +0,0 @@
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-.global feclearexcept
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-.type feclearexcept,@function
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-feclearexcept:
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- andis. 3,3,0x3e00
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- # if (r3 & FE_INVALID) r3 |= all_invalid_flags
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- andis. 0,3,0x2000
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- stwu 1,-16(1)
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- beq- 0,1f
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- oris 3,3,0x01f8
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- ori 3,3,0x0700
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-1:
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- # note: fpscr contains various fpu status and control
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- # flags and we dont check if r3 may alter other flags
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- # than the exception related ones
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- # fpscr &= ~r3
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- mffs 0
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- stfd 0,8(1)
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- lwz 9,12(1)
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- andc 9,9,3
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- stw 9,12(1)
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- lfd 0,8(1)
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- mtfsf 255,0
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-
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- # return 0
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- li 3,0
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- addi 1,1,16
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- blr
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-
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-.global feraiseexcept
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-.type feraiseexcept,@function
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-feraiseexcept:
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- andis. 3,3,0x3e00
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- # if (r3 & FE_INVALID) r3 |= software_invalid_flag
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- andis. 0,3,0x2000
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- stwu 1,-16(1)
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- beq- 0,1f
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- ori 3,3,0x0400
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-1:
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- # fpscr |= r3
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- mffs 0
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- stfd 0,8(1)
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- lwz 9,12(1)
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- or 9,9,3
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- stw 9,12(1)
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- lfd 0,8(1)
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- mtfsf 255,0
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-
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- # return 0
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- li 3,0
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- addi 1,1,16
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- blr
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-
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-.global fetestexcept
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-.type fetestexcept,@function
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-fetestexcept:
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- andis. 3,3,0x3e00
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- # return r3 & fpscr
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- stwu 1,-16(1)
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- mffs 0
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- stfd 0,8(1)
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- lwz 9,12(1)
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- addi 1,1,16
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- and 3,3,9
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- blr
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-
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-.global fegetround
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-.type fegetround,@function
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-fegetround:
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- # return fpscr & 3
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- stwu 1,-16(1)
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- mffs 0
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- stfd 0,8(1)
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- lwz 3,12(1)
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- addi 1,1,16
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- clrlwi 3,3,30
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- blr
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-
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-.global __fesetround
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-.type __fesetround,@function
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-__fesetround:
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- # note: invalid input is not checked, r3 < 4 must hold
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- # fpscr = (fpscr & -4U) | r3
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- stwu 1,-16(1)
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- mffs 0
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- stfd 0,8(1)
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- lwz 9,12(1)
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- clrrwi 9,9,2
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- or 9,9,3
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- stw 9,12(1)
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- lfd 0,8(1)
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- mtfsf 255,0
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-
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- # return 0
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- li 3,0
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- addi 1,1,16
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- blr
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-
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-.global fegetenv
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-.type fegetenv,@function
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-fegetenv:
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- # *r3 = fpscr
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- mffs 0
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- stfd 0,0(3)
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- # return 0
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- li 3,0
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- blr
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-
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-.global fesetenv
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-.type fesetenv,@function
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-fesetenv:
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- cmpwi 3, -1
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- bne 1f
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- mflr 4
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- bl 2f
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- .zero 8
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-2: mflr 3
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- mtlr 4
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-1: # fpscr = *r3
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- lfd 0,0(3)
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- mtfsf 255,0
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- # return 0
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- li 3,0
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- blr
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--- /dev/null
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+++ b/src/setjmp/powerpc/longjmp.S
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@@ -0,0 +1,69 @@
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+ .global _longjmp
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+ .global longjmp
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+ .type _longjmp,@function
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+ .type longjmp,@function
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+_longjmp:
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+longjmp:
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+ /*
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+ * void longjmp(jmp_buf env, int val);
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+ * put val into return register and restore the env saved in setjmp
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+ * if val(r4) is 0, put 1 there.
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+ */
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+ /* 0) move old return address into r0 */
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+ lwz 0, 0(3)
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+ /* 1) put it into link reg */
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+ mtlr 0
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+ /* 2 ) restore stack ptr */
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+ lwz 1, 4(3)
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+ /* 3) restore control reg */
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+ lwz 0, 8(3)
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+ mtcr 0
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+ /* 4) restore r14-r31 */
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+ lwz 14, 12(3)
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+ lwz 15, 16(3)
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+ lwz 16, 20(3)
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+ lwz 17, 24(3)
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+ lwz 18, 28(3)
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+ lwz 19, 32(3)
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+ lwz 20, 36(3)
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+ lwz 21, 40(3)
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+ lwz 22, 44(3)
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+ lwz 23, 48(3)
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+ lwz 24, 52(3)
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+ lwz 25, 56(3)
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+ lwz 26, 60(3)
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+ lwz 27, 64(3)
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+ lwz 28, 68(3)
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+ lwz 29, 72(3)
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+ lwz 30, 76(3)
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+ lwz 31, 80(3)
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+#ifndef _SOFT_FLOAT
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+ lfd 14,88(3)
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+ lfd 15,96(3)
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+ lfd 16,104(3)
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+ lfd 17,112(3)
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+ lfd 18,120(3)
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+ lfd 19,128(3)
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+ lfd 20,136(3)
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+ lfd 21,144(3)
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+ lfd 22,152(3)
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+ lfd 23,160(3)
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+ lfd 24,168(3)
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+ lfd 25,176(3)
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+ lfd 26,184(3)
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+ lfd 27,192(3)
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+ lfd 28,200(3)
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+ lfd 29,208(3)
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+ lfd 30,216(3)
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+ lfd 31,224(3)
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+#endif
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+ /* 5) put val into return reg r3 */
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+ mr 3, 4
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+
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+ /* 6) check if return value is 0, make it 1 in that case */
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+ cmpwi cr7, 4, 0
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+ bne cr7, 1f
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+ li 3, 1
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+1:
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+ blr
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+
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--- a/src/setjmp/powerpc/longjmp.s
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+++ /dev/null
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@@ -1,65 +0,0 @@
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- .global _longjmp
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- .global longjmp
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- .type _longjmp,@function
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- .type longjmp,@function
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-_longjmp:
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-longjmp:
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-# void longjmp(jmp_buf env, int val);
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-# put val into return register and restore the env saved in setjmp
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-# if val(r4) is 0, put 1 there.
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- # 0) move old return address into r0
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- lwz 0, 0(3)
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- # 1) put it into link reg
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- mtlr 0
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- #2 ) restore stack ptr
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- lwz 1, 4(3)
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- #3) restore control reg
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- lwz 0, 8(3)
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- mtcr 0
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- #4) restore r14-r31
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- lwz 14, 12(3)
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- lwz 15, 16(3)
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- lwz 16, 20(3)
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- lwz 17, 24(3)
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- lwz 18, 28(3)
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- lwz 19, 32(3)
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- lwz 20, 36(3)
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- lwz 21, 40(3)
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- lwz 22, 44(3)
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- lwz 23, 48(3)
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- lwz 24, 52(3)
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- lwz 25, 56(3)
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- lwz 26, 60(3)
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- lwz 27, 64(3)
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- lwz 28, 68(3)
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- lwz 29, 72(3)
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- lwz 30, 76(3)
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- lwz 31, 80(3)
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- lfd 14,88(3)
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- lfd 15,96(3)
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- lfd 16,104(3)
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- lfd 17,112(3)
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- lfd 18,120(3)
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- lfd 19,128(3)
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- lfd 20,136(3)
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- lfd 21,144(3)
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- lfd 22,152(3)
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- lfd 23,160(3)
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- lfd 24,168(3)
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- lfd 25,176(3)
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- lfd 26,184(3)
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- lfd 27,192(3)
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- lfd 28,200(3)
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- lfd 29,208(3)
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- lfd 30,216(3)
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- lfd 31,224(3)
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- #5) put val into return reg r3
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- mr 3, 4
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-
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- #6) check if return value is 0, make it 1 in that case
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- cmpwi cr7, 4, 0
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- bne cr7, 1f
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- li 3, 1
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-1:
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- blr
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-
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--- /dev/null
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+++ b/src/setjmp/powerpc/setjmp.S
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@@ -0,0 +1,63 @@
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+ .global ___setjmp
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+ .hidden ___setjmp
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+ .global __setjmp
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+ .global _setjmp
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+ .global setjmp
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+ .type __setjmp,@function
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+ .type _setjmp,@function
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+ .type setjmp,@function
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+___setjmp:
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+__setjmp:
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+_setjmp:
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+setjmp:
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+ /* 0) store IP int 0, then into the jmpbuf pointed to by r3 (first arg) */
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+ mflr 0
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+ stw 0, 0(3)
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+ /* 1) store reg1 (SP) */
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+ stw 1, 4(3)
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+ /* 2) store cr */
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+ mfcr 0
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+ stw 0, 8(3)
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+ /* 3) store r14-31 */
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+ stw 14, 12(3)
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+ stw 15, 16(3)
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+ stw 16, 20(3)
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+ stw 17, 24(3)
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+ stw 18, 28(3)
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+ stw 19, 32(3)
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+ stw 20, 36(3)
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+ stw 21, 40(3)
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+ stw 22, 44(3)
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+ stw 23, 48(3)
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+ stw 24, 52(3)
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+ stw 25, 56(3)
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+ stw 26, 60(3)
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+ stw 27, 64(3)
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+ stw 28, 68(3)
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+ stw 29, 72(3)
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+ stw 30, 76(3)
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+ stw 31, 80(3)
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+#ifndef _SOFT_FLOAT
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+ stfd 14,88(3)
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+ stfd 15,96(3)
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+ stfd 16,104(3)
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+ stfd 17,112(3)
|
|
+ stfd 18,120(3)
|
|
+ stfd 19,128(3)
|
|
+ stfd 20,136(3)
|
|
+ stfd 21,144(3)
|
|
+ stfd 22,152(3)
|
|
+ stfd 23,160(3)
|
|
+ stfd 24,168(3)
|
|
+ stfd 25,176(3)
|
|
+ stfd 26,184(3)
|
|
+ stfd 27,192(3)
|
|
+ stfd 28,200(3)
|
|
+ stfd 29,208(3)
|
|
+ stfd 30,216(3)
|
|
+ stfd 31,224(3)
|
|
+#endif
|
|
+ /* 4) set return value to 0 */
|
|
+ li 3, 0
|
|
+ /* 5) return */
|
|
+ blr
|
|
--- a/src/setjmp/powerpc/setjmp.s
|
|
+++ /dev/null
|
|
@@ -1,61 +0,0 @@
|
|
- .global ___setjmp
|
|
- .hidden ___setjmp
|
|
- .global __setjmp
|
|
- .global _setjmp
|
|
- .global setjmp
|
|
- .type __setjmp,@function
|
|
- .type _setjmp,@function
|
|
- .type setjmp,@function
|
|
-___setjmp:
|
|
-__setjmp:
|
|
-_setjmp:
|
|
-setjmp:
|
|
- # 0) store IP int 0, then into the jmpbuf pointed to by r3 (first arg)
|
|
- mflr 0
|
|
- stw 0, 0(3)
|
|
- # 1) store reg1 (SP)
|
|
- stw 1, 4(3)
|
|
- # 2) store cr
|
|
- mfcr 0
|
|
- stw 0, 8(3)
|
|
- # 3) store r14-31
|
|
- stw 14, 12(3)
|
|
- stw 15, 16(3)
|
|
- stw 16, 20(3)
|
|
- stw 17, 24(3)
|
|
- stw 18, 28(3)
|
|
- stw 19, 32(3)
|
|
- stw 20, 36(3)
|
|
- stw 21, 40(3)
|
|
- stw 22, 44(3)
|
|
- stw 23, 48(3)
|
|
- stw 24, 52(3)
|
|
- stw 25, 56(3)
|
|
- stw 26, 60(3)
|
|
- stw 27, 64(3)
|
|
- stw 28, 68(3)
|
|
- stw 29, 72(3)
|
|
- stw 30, 76(3)
|
|
- stw 31, 80(3)
|
|
- stfd 14,88(3)
|
|
- stfd 15,96(3)
|
|
- stfd 16,104(3)
|
|
- stfd 17,112(3)
|
|
- stfd 18,120(3)
|
|
- stfd 19,128(3)
|
|
- stfd 20,136(3)
|
|
- stfd 21,144(3)
|
|
- stfd 22,152(3)
|
|
- stfd 23,160(3)
|
|
- stfd 24,168(3)
|
|
- stfd 25,176(3)
|
|
- stfd 26,184(3)
|
|
- stfd 27,192(3)
|
|
- stfd 28,200(3)
|
|
- stfd 29,208(3)
|
|
- stfd 30,216(3)
|
|
- stfd 31,224(3)
|
|
- # 4) set return value to 0
|
|
- li 3, 0
|
|
- # 5) return
|
|
- blr
|