51 lines
1.7 KiB
Diff
51 lines
1.7 KiB
Diff
From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
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From: Sam Shih <sam.shih@mediatek.com>
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Date: Sun, 17 Dec 2023 21:50:07 +0000
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Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
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Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
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of the previously hardcoded PCW_CHG_MASK macro if set.
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This will needed for clocks on the MT7988 SoC.
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mediatek/clk-pll.c | 5 +++--
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drivers/clk/mediatek/clk-pll.h | 1 +
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2 files changed, 4 insertions(+), 2 deletions(-)
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--- a/drivers/clk/mediatek/clk-pll.c
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+++ b/drivers/clk/mediatek/clk-pll.c
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@@ -23,7 +23,7 @@
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#define CON0_BASE_EN BIT(0)
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#define CON0_PWR_ON BIT(0)
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#define CON0_ISO_EN BIT(1)
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-#define PCW_CHG_MASK BIT(31)
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+#define PCW_CHG_BIT 31
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#define AUDPLL_TUNER_EN BIT(31)
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@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct
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pll->data->pcw_shift);
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val |= pcw << pll->data->pcw_shift;
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writel(val, pll->pcw_addr);
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- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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+ chg = readl(pll->pcw_chg_addr) |
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+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
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writel(chg, pll->pcw_chg_addr);
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if (pll->tuner_addr)
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writel(val + 1, pll->tuner_addr);
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--- a/drivers/clk/mediatek/clk-pll.h
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+++ b/drivers/clk/mediatek/clk-pll.h
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@@ -48,6 +48,7 @@ struct mtk_pll_data {
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const char *parent_name;
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u32 en_reg;
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u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
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+ u8 pcw_chg_bit;
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};
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/*
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