mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-25 16:13:05 +00:00
b1f21329d4
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. It shares most of the stuff with its external counterpart, however it is modified for the SoC. Namely, it doesn't have second CPU port (Port 6), so it has 6 ports instead of 7. It also has no built-in PHY-s but rather requires external PSGMII based companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry out calibration before using them. PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which unfortunately requires some magic values as the datasheet doesnt document the bits that are being set or the register at all. Since its built-in it is MMIO like other peripherals and doesn't have its own MDIO bus but depends on the SoC provided one. CPU connection is at Port 0 and it uses some kind of a internal connection and no traditional RGMII/SGMII. It also doesn't use in-band tagging like other qca8k switches so a shinfo based tagger is used. This is based on the current OpenWrt qca8k version that has been imported from generic target. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
99 lines
2.1 KiB
Diff
99 lines
2.1 KiB
Diff
From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robert.marko@sartura.hr>
|
|
Date: Mon, 1 Nov 2021 18:15:04 +0100
|
|
Subject: [PATCH] arm: dts: ipq4019: add switch node
|
|
|
|
Since the built-in IPQ40xx switch now has a driver, add the required node
|
|
for it to work.
|
|
|
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
|
|
1 file changed, 78 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -590,6 +590,82 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ switch: switch@c000000 {
|
|
+ compatible = "qca,ipq4019-qca8337n";
|
|
+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
|
|
+ reg-names = "base", "psgmii_phy";
|
|
+ resets = <&gcc ESS_PSGMII_ARES>;
|
|
+ reset-names = "psgmii_rst";
|
|
+ mdio = <&mdio>;
|
|
+ psgmii-ethphy = <&psgmiiphy>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ port@0 { /* MAC0 */
|
|
+ reg = <0>;
|
|
+ label = "cpu";
|
|
+ ethernet = <&gmac>;
|
|
+ phy-mode = "internal";
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ pause;
|
|
+ asym-pause;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ swport1: port@1 { /* MAC1 */
|
|
+ reg = <1>;
|
|
+ label = "lan1";
|
|
+ phy-handle = <ðphy0>;
|
|
+ phy-mode = "psgmii";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ swport2: port@2 { /* MAC2 */
|
|
+ reg = <2>;
|
|
+ label = "lan2";
|
|
+ phy-handle = <ðphy1>;
|
|
+ phy-mode = "psgmii";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ swport3: port@3 { /* MAC3 */
|
|
+ reg = <3>;
|
|
+ label = "lan3";
|
|
+ phy-handle = <ðphy2>;
|
|
+ phy-mode = "psgmii";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ swport4: port@4 { /* MAC4 */
|
|
+ reg = <4>;
|
|
+ label = "lan4";
|
|
+ phy-handle = <ðphy3>;
|
|
+ phy-mode = "psgmii";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ swport5: port@5 { /* MAC5 */
|
|
+ reg = <5>;
|
|
+ label = "wan";
|
|
+ phy-handle = <ðphy4>;
|
|
+ phy-mode = "psgmii";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
gmac: ethernet@c080000 {
|
|
compatible = "qcom,ipq4019-ess-edma";
|
|
reg = <0xc080000 0x8000>;
|