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git://git.openwrt.org/openwrt/openwrt.git
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129 lines
4.1 KiB
Diff
129 lines
4.1 KiB
Diff
From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 4 Jan 2022 12:07:46 +0000
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Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
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access
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Implement read and write access to IEEE 802.3 Clause 45 Ethernet
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phy registers while making use of new mdiobus_c45_regad and
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mdiobus_c45_devad helpers.
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Tested on the Ubiquiti UniFi 6 LR access point featuring
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MediaTek MT7622BV WiSoC with Aquantia AQR112C.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
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2 files changed, 60 insertions(+), 13 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -196,13 +196,35 @@ static int _mtk_mdio_write(struct mtk_et
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if (ret < 0)
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return ret;
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- mtk_w32(eth, PHY_IAC_ACCESS |
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- PHY_IAC_START_C22 |
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- PHY_IAC_CMD_WRITE |
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- PHY_IAC_REG(phy_reg) |
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- PHY_IAC_ADDR(phy_addr) |
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- PHY_IAC_DATA(write_data),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_ADDR |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
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+ MTK_PHY_IAC);
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+
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+ ret = mtk_mdio_busy_wait(eth);
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+ if (ret < 0)
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+ return ret;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_WRITE |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(write_data),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C22 |
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+ PHY_IAC_CMD_WRITE |
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+ PHY_IAC_REG(phy_reg) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(write_data),
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+ MTK_PHY_IAC);
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+ }
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ret = mtk_mdio_busy_wait(eth);
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if (ret < 0)
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@@ -219,12 +241,33 @@ static int _mtk_mdio_read(struct mtk_eth
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if (ret < 0)
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return ret;
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- mtk_w32(eth, PHY_IAC_ACCESS |
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- PHY_IAC_START_C22 |
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- PHY_IAC_CMD_C22_READ |
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- PHY_IAC_REG(phy_reg) |
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- PHY_IAC_ADDR(phy_addr),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_ADDR |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
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+ MTK_PHY_IAC);
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+
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+ ret = mtk_mdio_busy_wait(eth);
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+ if (ret < 0)
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+ return ret;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_READ |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C22 |
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+ PHY_IAC_CMD_C22_READ |
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+ PHY_IAC_REG(phy_reg) |
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+ PHY_IAC_ADDR(phy_addr),
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+ MTK_PHY_IAC);
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+ }
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ret = mtk_mdio_busy_wait(eth);
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if (ret < 0)
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@@ -683,6 +726,7 @@ static int mtk_mdio_init(struct mtk_eth
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eth->mii_bus->name = "mdio";
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eth->mii_bus->read = mtk_mdio_read;
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eth->mii_bus->write = mtk_mdio_write;
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+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
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eth->mii_bus->priv = eth;
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eth->mii_bus->parent = eth->dev;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -322,9 +322,12 @@
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#define PHY_IAC_ADDR_MASK GENMASK(24, 20)
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#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
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#define PHY_IAC_CMD_MASK GENMASK(19, 18)
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+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
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#define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
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#define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
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+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
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#define PHY_IAC_START_MASK GENMASK(17, 16)
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+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
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#define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
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#define PHY_IAC_DATA_MASK GENMASK(15, 0)
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#define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
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