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105 lines
2.2 KiB
Diff
105 lines
2.2 KiB
Diff
From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Wed, 27 Oct 2021 00:57:06 +0800
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Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Define the Realtek RTL8365MB switch without interrupt support on the device
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tree of Asus RT-AC88U.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++
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1 file changed, 77 insertions(+)
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--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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@@ -93,6 +93,83 @@
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gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
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};
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};
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+
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+ switch {
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+ compatible = "realtek,rtl8365mb";
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+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
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+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
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+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
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+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
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+ realtek,disable-leds;
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+ dsa,member = <1 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan5";
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+ phy-handle = <ðphy0>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan6";
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+ phy-handle = <ðphy1>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan7";
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+ phy-handle = <ðphy2>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan8";
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+ phy-handle = <ðphy3>;
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&sw0_p5>;
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+ phy-mode = "rgmii";
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+ tx-internal-delay-ps = <2000>;
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+ rx-internal-delay-ps = <2000>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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+
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+ mdio {
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+ compatible = "realtek,smi-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethphy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+
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+ ethphy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+
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+ ethphy2: ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+
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+ ethphy3: ethernet-phy@3 {
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+ reg = <3>;
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+ };
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+ };
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+ };
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};
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&srab {
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