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8fb15ea52a
Copy dts/files/patches/configs from 5.10 to 5.15. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [refresh with updated DGS-1210 dts files] Signed-off-by: Sander Vanheule <sander@svanheule.net>
325 lines
6.4 KiB
Plaintext
325 lines
6.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
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model = "Zyxel XGS1250-12 Switch";
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aliases {
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led-boot = &led_pwr_sys;
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led-failsafe = &led_pwr_sys;
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led-running = &led_pwr_sys;
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led-upgrade = &led_pwr_sys;
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};
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keys {
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compatible = "gpio-keys";
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mode {
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label = "reset";
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gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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/* i2c of the SFP cage: port 12 */
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i2c0: i2c-rtl9300 {
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compatible = "realtek,rtl9300-i2c";
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reg = <0x1b00036c 0x3c>;
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#address-cells = <1>;
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#size-cells = <0>;
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sda-pin = <10>;
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scl-pin = <8>;
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clock-frequency = <100000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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sfp0: sfp-p12 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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led_set: led_set@0 {
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compatible = "realtek,rtl9300-leds";
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led_set0 = <0x0000 0xffff 0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps
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led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G)
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// (5G, 10/100) (10G, 5G, 2.5G)
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led_set2 = <0x0000 0xffff 0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x10000>;
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};
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0xf0000 0x10000>;
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read-only;
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};
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partition@100000 {
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label = "jffs";
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reg = <0x100000 0x100000>;
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};
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partition@200000 {
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label = "jffs2";
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reg = <0x200000 0x100000>;
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};
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partition@b300000 {
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label = "firmware";
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reg = <0x300000 0xce0000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x93001250>;
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};
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partition@fe0000 {
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label = "log";
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reg = <0xfe0000 0x20000>;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* External RTL8218D PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 0>;
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sds = < 2 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 7>;
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};
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/* External Aquantia 113C PHYs */
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 8>;
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sds = < 6 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <2 8>;
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sds = < 7 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy26: ethernet-phy@26 {
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reg = <26>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <3 8>;
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sds = < 8 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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/* SFP Ports */
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phy27: ethernet-phy@27 {
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compatible = "ethernet-phy-ieee802.3-c22";
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phy-is-integrated;
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reg = <27>;
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rtl9300,smi-address = <4 0>;
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sds = < 9 >;
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};
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-handle = <&phy0>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&phy1>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-handle = <&phy2>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&phy3>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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phy-handle = <&phy4>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@5 {
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reg = <5>;
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label = "lan6";
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phy-handle = <&phy5>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@6 {
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reg = <6>;
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label = "lan7";
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phy-handle = <&phy6>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@7 {
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reg = <7>;
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label = "lan8";
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phy-handle = <&phy7>;
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phy-mode = "xgmii";
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led-set = <0>;
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};
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-mode = "usxgmii";
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phy-handle = <&phy24>;
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led-set = <1>;
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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phy-mode = "usxgmii";
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phy-handle = <&phy25>;
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led-set = <1>;
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};
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port@26 {
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reg = <26>;
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label = "lan11";
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phy-mode = "usxgmii";
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phy-handle = <&phy26>;
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led-set = <1>;
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};
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port@27 {
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reg = <27>;
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label = "lan12";
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phy-mode = "10gbase-r";
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phy-handle = <&phy27>;
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sfp = <&sfp0>;
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led-set = <2>;
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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};
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