251 lines
7.0 KiB
Diff
251 lines
7.0 KiB
Diff
From ee990c664fad993275b2615d0ff06af5d04922f0 Mon Sep 17 00:00:00 2001
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From: William Qiu <william.qiu@starfivetech.com>
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Date: Wed, 15 Feb 2023 19:32:47 +0800
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Subject: [PATCH 108/122] mmc: starfive: Add sdio/emmc driver support
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Add sdio/emmc driver support for StarFive JH7110 soc.
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Tested-by: Conor Dooley <conor.dooley@microchip.com>
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Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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---
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MAINTAINERS | 6 +
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drivers/mmc/host/Kconfig | 10 ++
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drivers/mmc/host/Makefile | 1 +
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drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
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4 files changed, 203 insertions(+)
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create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -19664,6 +19664,12 @@ S: Maintained
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F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
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F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
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+STARFIVE JH7110 MMC/SD/SDIO DRIVER
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+M: William Qiu <william.qiu@starfivetech.com>
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+S: Supported
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+F: Documentation/devicetree/bindings/mmc/starfive*
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+F: drivers/mmc/host/dw_mmc-starfive.c
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+
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STARFIVE JH7110 PLL CLOCK DRIVER
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M: Xingyu Wu <xingyu.wu@starfivetech.com>
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S: Supported
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--- a/drivers/mmc/host/Kconfig
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+++ b/drivers/mmc/host/Kconfig
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@@ -872,6 +872,16 @@ config MMC_DW_ROCKCHIP
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on RK3066, RK3188 and RK3288 SoC's.
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+config MMC_DW_STARFIVE
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+ tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
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+ depends on SOC_STARFIVE
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+ depends on MMC_DW
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+ select MMC_DW_PLTFM
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+ help
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+ This selects support for StarFive JH7110 SoC specific extensions to the
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+ Synopsys DesignWare Memory Card Interface driver. Select this option
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+ for platforms based on StarFive JH7110 SoC.
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+
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config MMC_SH_MMCIF
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tristate "SuperH Internal MMCIF support"
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depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
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--- a/drivers/mmc/host/Makefile
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+++ b/drivers/mmc/host/Makefile
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@@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_m
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obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
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+obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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obj-$(CONFIG_MMC_VUB300) += vub300.o
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--- /dev/null
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+++ b/drivers/mmc/host/dw_mmc-starfive.c
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@@ -0,0 +1,186 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * StarFive Designware Mobile Storage Host Controller Driver
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+ *
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+ * Copyright (c) 2022 StarFive Technology Co., Ltd.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/mmc/host.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+
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+#include "dw_mmc.h"
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+#include "dw_mmc-pltfm.h"
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+
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+#define ALL_INT_CLR 0x1ffff
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+#define MAX_DELAY_CHAIN 32
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+
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+struct starfive_priv {
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+ struct device *dev;
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+ struct regmap *reg_syscon;
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+ u32 syscon_offset;
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+ u32 syscon_shift;
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+ u32 syscon_mask;
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+};
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+
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+static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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+{
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+ int ret;
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+ unsigned int clock;
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+
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+ if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
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+ clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
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+ ret = clk_set_rate(host->ciu_clk, clock);
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+ if (ret)
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+ dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
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+ host->bus_hz = clk_get_rate(host->ciu_clk);
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+ } else {
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+ dev_dbg(host->dev, "Using the internal divider\n");
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+ }
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+}
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+
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+static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
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+ u32 opcode)
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+{
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+ static const int grade = MAX_DELAY_CHAIN;
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+ struct dw_mci *host = slot->host;
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+ struct starfive_priv *priv = host->priv;
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+ int rise_point = -1, fall_point = -1;
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+ int err, prev_err;
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+ int i;
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+ bool found = 0;
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+ u32 regval;
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+
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+ /*
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+ * Use grade as the max delay chain, and use the rise_point and
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+ * fall_point to ensure the best sampling point of a data input
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+ * signals.
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+ */
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+ for (i = 0; i < grade; i++) {
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+ regval = i << priv->syscon_shift;
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+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
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+ priv->syscon_mask, regval);
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+ if (err)
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+ return err;
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+ mci_writel(host, RINTSTS, ALL_INT_CLR);
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+
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+ err = mmc_send_tuning(slot->mmc, opcode, NULL);
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+ if (!err)
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+ found = 1;
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+
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+ if (i > 0) {
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+ if (err && !prev_err)
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+ fall_point = i - 1;
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+ if (!err && prev_err)
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+ rise_point = i;
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+ }
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+
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+ if (rise_point != -1 && fall_point != -1)
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+ goto tuning_out;
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+
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+ prev_err = err;
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+ err = 0;
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+ }
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+
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+tuning_out:
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+ if (found) {
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+ if (rise_point == -1)
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+ rise_point = 0;
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+ if (fall_point == -1)
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+ fall_point = grade - 1;
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+ if (fall_point < rise_point) {
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+ if ((rise_point + fall_point) >
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+ (grade - 1))
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+ i = fall_point / 2;
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+ else
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+ i = (rise_point + grade - 1) / 2;
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+ } else {
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+ i = (rise_point + fall_point) / 2;
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+ }
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+
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+ regval = i << priv->syscon_shift;
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+ err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
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+ priv->syscon_mask, regval);
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+ if (err)
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+ return err;
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+ mci_writel(host, RINTSTS, ALL_INT_CLR);
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+
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+ dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
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+ } else {
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+ dev_err(host->dev, "No valid delay chain! use default\n");
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+ err = -EINVAL;
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+ }
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+
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+ mci_writel(host, RINTSTS, ALL_INT_CLR);
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+ return err;
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+}
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+
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+static int dw_mci_starfive_parse_dt(struct dw_mci *host)
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+{
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+ struct of_phandle_args args;
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+ struct starfive_priv *priv;
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+ int ret;
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+
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+ priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
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+ "starfive,sysreg", 3, 0, &args);
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+ if (ret) {
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+ dev_err(host->dev, "Failed to parse starfive,sysreg\n");
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+ return -EINVAL;
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+ }
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+
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+ priv->reg_syscon = syscon_node_to_regmap(args.np);
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+ of_node_put(args.np);
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+ if (IS_ERR(priv->reg_syscon))
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+ return PTR_ERR(priv->reg_syscon);
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+
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+ priv->syscon_offset = args.args[0];
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+ priv->syscon_shift = args.args[1];
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+ priv->syscon_mask = args.args[2];
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+
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+ host->priv = priv;
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+
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+ return 0;
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+}
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+
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+static const struct dw_mci_drv_data starfive_data = {
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+ .common_caps = MMC_CAP_CMD23,
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+ .set_ios = dw_mci_starfive_set_ios,
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+ .parse_dt = dw_mci_starfive_parse_dt,
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+ .execute_tuning = dw_mci_starfive_execute_tuning,
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+};
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+
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+static const struct of_device_id dw_mci_starfive_match[] = {
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+ { .compatible = "starfive,jh7110-mmc",
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+ .data = &starfive_data },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
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+
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+static int dw_mci_starfive_probe(struct platform_device *pdev)
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+{
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+ return dw_mci_pltfm_register(pdev, &starfive_data);
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+}
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+
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+static struct platform_driver dw_mci_starfive_driver = {
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+ .probe = dw_mci_starfive_probe,
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+ .remove = dw_mci_pltfm_remove,
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+ .driver = {
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+ .name = "dwmmc_starfive",
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+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
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+ .of_match_table = dw_mci_starfive_match,
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+ },
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+};
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+module_platform_driver(dw_mci_starfive_driver);
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+
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+MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
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+MODULE_LICENSE("GPL");
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+MODULE_ALIAS("platform:dwmmc_starfive");
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