182 lines
5.0 KiB
Diff
182 lines
5.0 KiB
Diff
From 3d555cfd72df1a02849565f281149d321e0f8425 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Thu, 6 Apr 2023 19:11:40 +0800
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Subject: [PATCH 094/122] dt-binding: pci: add JH7110 PCIe dt-binding
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documents.
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Add PCIe controller driver dt-binding documents
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for StarFive JH7110 SoC platform.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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---
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.../bindings/pci/starfive,jh7110-pcie.yaml | 163 ++++++++++++++++++
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1 file changed, 163 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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@@ -0,0 +1,163 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 PCIe 2.0 host controller
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+
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+maintainers:
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+ - Minda Chen <minda.chen@starfivetech.com>
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+
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+allOf:
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+ - $ref: /schemas/pci/pci-bus.yaml#
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+ - $ref: /schemas/interrupt-controller/msi-controller.yaml#
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-pcie
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+
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+ reg:
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+ maxItems: 2
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+
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+ reg-names:
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+ items:
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+ - const: reg
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+ - const: config
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+
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+ msi-parent: true
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+
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+ interrupts:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 4
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+
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+ clock-names:
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+ items:
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+ - const: noc
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+ - const: tl
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+ - const: axi_mst0
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+ - const: apb
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+
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+ resets:
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+ items:
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+ - description: AXI MST0 reset
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+ - description: AXI SLAVE reset
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+ - description: AXI SLAVE0 reset
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+ - description: PCIE BRIDGE reset
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+ - description: PCIE CORE reset
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+ - description: PCIE APB reset
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+
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+ reset-names:
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+ items:
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+ - const: mst0
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+ - const: slv0
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+ - const: slv
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+ - const: brg
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+ - const: core
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+ - const: apb
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+
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+ starfive,stg-syscon:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ items:
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+ items:
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+ - description: phandle to System Register Controller stg_syscon node.
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+ - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
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+ - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
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+ - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
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+ - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
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+ description:
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+ The phandle to System Register Controller syscon node and the offset
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+ of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
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+ for PCIe.
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+
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+ pwren-gpios:
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+ description: Should specify the GPIO for controlling the PCI bus device power on.
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+ maxItems: 1
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+
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+ reset-gpios:
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+ maxItems: 1
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+
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+ phys:
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+ maxItems: 1
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+
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+ interrupt-controller:
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+ type: object
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+ properties:
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+ '#address-cells':
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+ const: 0
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+
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+ '#interrupt-cells':
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+ const: 1
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+
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+ interrupt-controller: true
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+
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+ required:
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+ - '#address-cells'
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+ - '#interrupt-cells'
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+ - interrupt-controller
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+
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+ additionalProperties: false
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+
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+required:
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+ - reg
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+ - reg-names
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+ - "#interrupt-cells"
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+ - interrupts
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+ - interrupt-map-mask
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+ - interrupt-map
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+ - clocks
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+ - clock-names
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+ - resets
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+ - msi-controller
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ bus {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ pcie0: pcie@2B000000 {
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+ compatible = "starfive,jh7110-pcie";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ reg = <0x0 0x2B000000 0x0 0x1000000>,
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+ <0x9 0x40000000 0x0 0x10000000>;
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+ reg-names = "reg", "config";
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+ device_type = "pci";
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+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
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+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <56>;
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
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+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
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+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
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+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
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+ msi-parent = <&pcie0>;
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+ msi-controller;
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+ clocks = <&syscrg 86>,
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+ <&stgcrg 10>,
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+ <&stgcrg 8>,
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+ <&stgcrg 9>;
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+ clock-names = "noc", "tl", "axi_mst0", "apb";
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+ resets = <&stgcrg 11>,
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+ <&stgcrg 12>,
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+ <&stgcrg 13>,
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+ <&stgcrg 14>,
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+ <&stgcrg 15>,
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+ <&stgcrg 16>;
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+
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+ pcie_intc0: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+ };
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