69 lines
1.7 KiB
Diff
69 lines
1.7 KiB
Diff
From 2ebd77fa8fb95f60b275cefb98ea7d6f4df06e55 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Thu, 18 May 2023 19:27:44 +0800
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Subject: [PATCH 087/122] dt-bindings: phy: Add StarFive JH7110 USB PHY
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Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
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1 file changed, 50 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
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@@ -0,0 +1,50 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 USB 2.0 PHY
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+
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+maintainers:
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+ - Minda Chen <minda.chen@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-usb-phy
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#phy-cells":
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+ const: 0
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+
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+ clocks:
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+ items:
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+ - description: PHY 125m
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+ - description: app 125m
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+
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+ clock-names:
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+ items:
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+ - const: 125m
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+ - const: app_125m
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - "#phy-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ phy@10200000 {
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+ compatible = "starfive,jh7110-usb-phy";
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+ reg = <0x10200000 0x10000>;
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+ clocks = <&syscrg 95>,
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+ <&stgcrg 6>;
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+ clock-names = "125m", "app_125m";
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+ #phy-cells = <0>;
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+ };
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