541 lines
16 KiB
Diff
541 lines
16 KiB
Diff
From 3fbdabd59bac0978536fb11b1b9deb81559f1c54 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Mon, 20 Mar 2023 21:54:32 +0800
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Subject: [PATCH 060/122] clocksource: Add StarFive timer driver
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Add timer driver for the StarFive JH7110 SoC.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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drivers/clocksource/Kconfig | 12 +
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drivers/clocksource/Makefile | 1 +
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drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
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drivers/clocksource/timer-starfive.h | 96 +++++++
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4 files changed, 499 insertions(+)
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create mode 100644 drivers/clocksource/timer-starfive.c
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create mode 100644 drivers/clocksource/timer-starfive.h
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -630,6 +630,18 @@ config RISCV_TIMER
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is accessed via both the SBI and the rdcycle instruction. This is
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required for all RISC-V systems.
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+config STARFIVE_TIMER
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+ bool "Timer for the STARFIVE SoCs"
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+ depends on ARCH_STARFIVE || COMPILE_TEST
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+ select TIMER_OF
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+ select CLKSRC_MMIO
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+ default ARCH_STARFIVE
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+ help
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+ This enables the timer for StarFive SoCs. On RISC-V platform,
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+ the system has started RISCV_TIMER. But you can also use this timer
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+ to do a lot more on StarFive SoCs. This timer can provide high
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+ precision and four channels to use in JH7110 SoC.
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+
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config CLINT_TIMER
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bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK && RISCV
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--- a/drivers/clocksource/Makefile
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+++ b/drivers/clocksource/Makefile
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@@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-
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obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
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obj-$(CONFIG_X86_NUMACHIP) += numachip.o
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obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
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+obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
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obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
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obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
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obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
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--- /dev/null
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+++ b/drivers/clocksource/timer-starfive.c
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@@ -0,0 +1,390 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Starfive Timer driver
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+ *
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ *
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+ * Author:
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+ * Xingyu Wu <xingyu.wu@starfivetech.com>
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+ * Samin Guo <samin.guo@starfivetech.com>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/clockchips.h>
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+#include <linux/clocksource.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/irq.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/reset.h>
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+#include <linux/sched_clock.h>
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+
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+#include "timer-starfive.h"
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+
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+static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
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+ .ctrl = STARFIVE_TIMER_JH7110_CTL,
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+ .load = STARFIVE_TIMER_JH7110_LOAD,
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+ .enable = STARFIVE_TIMER_JH7110_ENABLE,
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+ .reload = STARFIVE_TIMER_JH7110_RELOAD,
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+ .value = STARFIVE_TIMER_JH7110_VALUE,
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+ .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
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+ .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
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+ .channel_num = STARFIVE_TIMER_CH_4,
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+ .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
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+ STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
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+};
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+
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+static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
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+{
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+ return container_of(evt, struct starfive_clkevt, evt);
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+}
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+
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+/* 0:continuous-run mode, 1:single-run mode */
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+static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
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+{
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+ writel(mod, clkevt->ctrl);
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+}
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+
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+/* Interrupt Mask Register, 0:Unmask, 1:Mask */
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+static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
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+{
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+ writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
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+}
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+
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+static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
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+{
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+ writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
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+}
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+
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+/*
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+ * BIT(0): Read value represent channel intr status.
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+ * Write 1 to this bit to clear interrupt. Write 0 has no effects.
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+ * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
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+ */
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+static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
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+{
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+ u32 value;
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+ int ret;
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+
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+ /* waiting interrupt can be to clearing */
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+ ret = readl_poll_timeout_atomic(clkevt->intclr, value,
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+ !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
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+ STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
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+ if (!ret)
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+ writel(0x1, clkevt->intclr);
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+
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+ return ret;
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+}
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+
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+/*
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+ * The initial value to be loaded into the
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+ * counter and is also used as the reload value.
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+ * val = clock rate --> 1s
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+ */
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+static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
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+{
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+ writel(val, clkevt->load);
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+}
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+
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+static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
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+{
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+ return readl(clkevt->value);
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+}
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+
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+/*
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+ * Write RELOAD register to reload preset value to counter.
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+ * (Write 0 and write 1 are both ok)
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+ */
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+static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
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+{
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+ writel(0, clkevt->reload);
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+}
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+
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+static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
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+{
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+ writel(STARFIVE_TIMER_ENA, clkevt->enable);
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+}
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+
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+static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
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+{
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+ writel(STARFIVE_TIMER_DIS, clkevt->enable);
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+}
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+
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+static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
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+{
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+ int ret;
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+
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+ starfive_timer_int_disable(clkevt);
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+ ret = starfive_timer_int_clear(clkevt);
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+ if (ret)
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+ return ret;
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+
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+ starfive_timer_int_enable(clkevt);
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+ starfive_timer_enable(clkevt);
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+
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+ return 0;
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+}
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+
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+static int starfive_timer_shutdown(struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ starfive_timer_disable(clkevt);
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+ return starfive_timer_int_clear(clkevt);
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+}
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+
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+static void starfive_timer_suspend(struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ clkevt->reload_val = starfive_timer_get_val(clkevt);
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+ starfive_timer_shutdown(evt);
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+}
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+
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+static void starfive_timer_resume(struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ starfive_timer_set_load(clkevt, clkevt->reload_val);
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+ starfive_timer_set_reload(clkevt);
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+ starfive_timer_int_enable(clkevt);
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+ starfive_timer_enable(clkevt);
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+}
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+
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+static int starfive_timer_tick_resume(struct clock_event_device *evt)
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+{
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+ starfive_timer_resume(evt);
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+
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+ return 0;
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+}
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+
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+static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
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+{
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+ int ret;
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+
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+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
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+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
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+ ret = starfive_timer_int_init_enable(clkevt);
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+ if (ret)
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+ return ret;
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+
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+ return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
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+ STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
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+ clocksource_mmio_readl_down);
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+}
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+
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+/* IRQ handler for the timer */
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+static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
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+{
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+ struct clock_event_device *evt = (struct clock_event_device *)priv;
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ if (starfive_timer_int_clear(clkevt))
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+ return IRQ_NONE;
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+
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+ if (evt->event_handler)
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+ evt->event_handler(evt);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int starfive_timer_set_periodic(struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ starfive_timer_disable(clkevt);
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+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
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+ starfive_timer_set_load(clkevt, clkevt->periodic);
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+
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+ return starfive_timer_int_init_enable(clkevt);
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+}
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+
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+static int starfive_timer_set_oneshot(struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ starfive_timer_disable(clkevt);
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+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
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+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
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+
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+ return starfive_timer_int_init_enable(clkevt);
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+}
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+
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+static int starfive_timer_set_next_event(unsigned long next,
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+ struct clock_event_device *evt)
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+{
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+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
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+
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+ starfive_timer_disable(clkevt);
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+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
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+ starfive_timer_set_load(clkevt, next);
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+ starfive_timer_enable(clkevt);
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+
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+ return 0;
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+}
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+
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+static void starfive_set_clockevent(struct clock_event_device *evt)
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+{
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+ evt->features = CLOCK_EVT_FEAT_PERIODIC |
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+ CLOCK_EVT_FEAT_ONESHOT |
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+ CLOCK_EVT_FEAT_DYNIRQ;
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+ evt->set_state_shutdown = starfive_timer_shutdown;
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+ evt->set_state_periodic = starfive_timer_set_periodic;
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+ evt->set_state_oneshot = starfive_timer_set_oneshot;
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+ evt->set_state_oneshot_stopped = starfive_timer_shutdown;
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+ evt->tick_resume = starfive_timer_tick_resume;
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+ evt->set_next_event = starfive_timer_set_next_event;
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+ evt->suspend = starfive_timer_suspend;
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+ evt->resume = starfive_timer_resume;
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+ evt->rating = STARFIVE_CLOCKEVENT_RATING;
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+}
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+
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+static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
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+{
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+ clkevt->rate = clk_get_rate(clkevt->clk);
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+ clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
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+
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+ starfive_set_clockevent(&clkevt->evt);
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+ clkevt->evt.name = clkevt->name;
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+ clkevt->evt.irq = clkevt->irq;
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+ clkevt->evt.cpumask = cpu_possible_mask;
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+
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+ clockevents_config_and_register(&clkevt->evt, clkevt->rate,
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+ STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
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+}
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+
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+static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
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+ struct starfive_clkevt *clkevt,
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+ void __iomem *base, int ch)
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+{
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+ void __iomem *channel_base;
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+
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+ channel_base = base + timer->channel_base[ch];
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+ clkevt->base = channel_base;
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+ clkevt->ctrl = channel_base + timer->ctrl;
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+ clkevt->load = channel_base + timer->load;
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+ clkevt->enable = channel_base + timer->enable;
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+ clkevt->reload = channel_base + timer->reload;
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+ clkevt->value = channel_base + timer->value;
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+ clkevt->intclr = channel_base + timer->intclr;
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+ clkevt->intmask = channel_base + timer->intmask;
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+}
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+
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+static int __init starfive_timer_probe(struct platform_device *pdev)
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+{
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+ const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
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+ char name[10];
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+ struct starfive_timer_priv *priv;
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+ struct starfive_clkevt *clkevt;
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+ struct clk *pclk;
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+ struct reset_control *rst;
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+ int ch;
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+ int ret;
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+
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+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
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+ GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ priv->base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(priv->base))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
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+ "failed to map registers\n");
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+
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+ rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
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+ if (IS_ERR(rst))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
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+
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+ pclk = devm_clk_get_enabled(&pdev->dev, "apb");
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+ if (IS_ERR(pclk))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
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+ "failed to get & enable apb clock\n");
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+
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+ ret = reset_control_deassert(rst);
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+ if (ret)
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+ goto err;
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+
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+ priv->dev = &pdev->dev;
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+ platform_set_drvdata(pdev, priv);
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+
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+ for (ch = 0; ch < timer_base->channel_num; ch++) {
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+ clkevt = &priv->clkevt[ch];
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+ snprintf(name, sizeof(name), "ch%d", ch);
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+
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+ starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
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+ /* Ensure timers are disabled */
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+ starfive_timer_disable(clkevt);
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+
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+ rst = devm_reset_control_get_exclusive(&pdev->dev, name);
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+ if (IS_ERR(rst)) {
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+ ret = PTR_ERR(rst);
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+ goto err;
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+ }
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+
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+ clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
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+ if (IS_ERR(clkevt->clk)) {
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+ ret = PTR_ERR(clkevt->clk);
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+ goto err;
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+ }
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+
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+ ret = reset_control_deassert(rst);
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+ if (ret)
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+ goto ch_err;
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+
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+ clkevt->irq = platform_get_irq(pdev, ch);
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+ if (clkevt->irq < 0) {
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+ ret = clkevt->irq;
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+ goto ch_err;
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+ }
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+
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+ snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
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+ starfive_clockevents_register(clkevt);
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+
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+ ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
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+ IRQF_TIMER | IRQF_IRQPOLL,
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+ clkevt->name, &clkevt->evt);
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+ if (ret)
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+ goto ch_err;
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+
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+ ret = starfive_clocksource_init(clkevt);
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+ if (ret)
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+ goto ch_err;
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+ }
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+
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+ return 0;
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+
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+ch_err:
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+ /* Only unregister the failed channel and the rest timer channels continue to work. */
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+ clk_disable_unprepare(clkevt->clk);
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+err:
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+ /* If no other channel successfully registers, pclk should be disabled. */
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+ if (!ch)
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+ clk_disable_unprepare(pclk);
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+
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+ return ret;
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+}
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+
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+static const struct of_device_id starfive_timer_match[] = {
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+ { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
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+ { /* sentinel */ }
|
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+};
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+MODULE_DEVICE_TABLE(of, starfive_timer_match);
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+
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+static struct platform_driver starfive_timer_driver = {
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+ .probe = starfive_timer_probe,
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+ .driver = {
|
|
+ .name = "starfive-timer",
|
|
+ .of_match_table = starfive_timer_match,
|
|
+ },
|
|
+};
|
|
+module_platform_driver(starfive_timer_driver);
|
|
+
|
|
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
|
|
+MODULE_DESCRIPTION("StarFive timer driver");
|
|
+MODULE_LICENSE("GPL");
|
|
--- /dev/null
|
|
+++ b/drivers/clocksource/timer-starfive.h
|
|
@@ -0,0 +1,96 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/*
|
|
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
|
|
+ */
|
|
+
|
|
+#ifndef __STARFIVE_TIMER_H__
|
|
+#define __STARFIVE_TIMER_H__
|
|
+
|
|
+/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
|
|
+#define STARFIVE_TIMER_CH_LEN 0x40
|
|
+#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
|
|
+
|
|
+#define STARFIVE_CLOCK_SOURCE_RATING 200
|
|
+#define STARFIVE_VALID_BITS 32
|
|
+#define STARFIVE_DELAY_US 0
|
|
+#define STARFIVE_TIMEOUT_US 10000
|
|
+#define STARFIVE_CLOCKEVENT_RATING 300
|
|
+#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
|
|
+#define STARFIVE_TIMER_MIN_TICKS 0xf
|
|
+
|
|
+#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
|
|
+#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
|
|
+#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
|
|
+#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
|
|
+#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
|
|
+#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
|
|
+#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
|
|
+#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
|
|
+#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
|
|
+
|
|
+enum STARFIVE_TIMER_CH {
|
|
+ STARFIVE_TIMER_CH_0 = 0,
|
|
+ STARFIVE_TIMER_CH_1,
|
|
+ STARFIVE_TIMER_CH_2,
|
|
+ STARFIVE_TIMER_CH_3,
|
|
+ STARFIVE_TIMER_CH_4,
|
|
+ STARFIVE_TIMER_CH_5,
|
|
+ STARFIVE_TIMER_CH_6,
|
|
+ STARFIVE_TIMER_CH_7,
|
|
+ STARFIVE_TIMER_CH_MAX
|
|
+};
|
|
+
|
|
+enum STARFIVE_TIMER_INTMASK {
|
|
+ STARFIVE_TIMER_INTMASK_DIS = 0,
|
|
+ STARFIVE_TIMER_INTMASK_ENA = 1
|
|
+};
|
|
+
|
|
+enum STARFIVE_TIMER_MOD {
|
|
+ STARFIVE_TIMER_MOD_CONTIN = 0,
|
|
+ STARFIVE_TIMER_MOD_SINGLE = 1
|
|
+};
|
|
+
|
|
+enum STARFIVE_TIMER_CTL_EN {
|
|
+ STARFIVE_TIMER_DIS = 0,
|
|
+ STARFIVE_TIMER_ENA = 1
|
|
+};
|
|
+
|
|
+struct starfive_timer_chan_base {
|
|
+ /* Resgister */
|
|
+ unsigned int ctrl;
|
|
+ unsigned int load;
|
|
+ unsigned int enable;
|
|
+ unsigned int reload;
|
|
+ unsigned int value;
|
|
+ unsigned int intclr;
|
|
+ unsigned int intmask;
|
|
+
|
|
+ unsigned int channel_num; /* timer channel numbers */
|
|
+ unsigned int channel_base[];
|
|
+};
|
|
+
|
|
+struct starfive_clkevt {
|
|
+ struct clock_event_device evt;
|
|
+ struct clk *clk;
|
|
+ char name[20];
|
|
+ int irq;
|
|
+ u32 periodic;
|
|
+ u32 rate;
|
|
+ u32 reload_val;
|
|
+ void __iomem *base;
|
|
+ void __iomem *ctrl;
|
|
+ void __iomem *load;
|
|
+ void __iomem *enable;
|
|
+ void __iomem *reload;
|
|
+ void __iomem *value;
|
|
+ void __iomem *intclr;
|
|
+ void __iomem *intmask;
|
|
+};
|
|
+
|
|
+struct starfive_timer_priv {
|
|
+ struct device *dev;
|
|
+ void __iomem *base;
|
|
+ struct starfive_clkevt clkevt[];
|
|
+};
|
|
+
|
|
+#endif /* __STARFIVE_TIMER_H__ */
|