483 lines
17 KiB
Diff
483 lines
17 KiB
Diff
From c960c73ee9fdaae51fcd8a14d44d576b1cf522b7 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:13 +0800
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Subject: [PATCH 001/122] dt-bindings: clock: Add StarFive JH7110 system clock
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and reset generator
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Add bindings for the system clock and reset generator (SYSCRG) on the
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JH7110 RISC-V SoC by StarFive Ltd.
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../clock/starfive,jh7110-syscrg.yaml | 104 +++++++++
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.../dt-bindings/clock/starfive,jh7110-crg.h | 203 ++++++++++++++++++
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.../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++
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3 files changed, 449 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
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create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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@@ -0,0 +1,104 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 System Clock and Reset Generator
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+
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+maintainers:
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+ - Emil Renner Berthing <kernel@esmil.dk>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-syscrg
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ oneOf:
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+ - items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: GMAC1 RMII reference or GMAC1 RGMII RX
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+ - description: External I2S TX bit clock
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+ - description: External I2S TX left/right channel clock
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+ - description: External I2S RX bit clock
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+ - description: External I2S RX left/right channel clock
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+ - description: External TDM clock
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+ - description: External audio master clock
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+
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+ - items:
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+ - description: Main Oscillator (24 MHz)
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+ - description: GMAC1 RMII reference
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+ - description: GMAC1 RGMII RX
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+ - description: External I2S TX bit clock
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+ - description: External I2S TX left/right channel clock
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+ - description: External I2S RX bit clock
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+ - description: External I2S RX left/right channel clock
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+ - description: External TDM clock
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+ - description: External audio master clock
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+
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+ clock-names:
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+ oneOf:
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+ - items:
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+ - const: osc
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+ - enum:
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+ - gmac1_rmii_refin
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+ - gmac1_rgmii_rxin
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+ - const: i2stx_bclk_ext
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+ - const: i2stx_lrck_ext
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+ - const: i2srx_bclk_ext
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+ - const: i2srx_lrck_ext
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+ - const: tdm_ext
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+ - const: mclk_ext
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+
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+ - items:
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+ - const: osc
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+ - const: gmac1_rmii_refin
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+ - const: gmac1_rgmii_rxin
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+ - const: i2stx_bclk_ext
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+ - const: i2stx_lrck_ext
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+ - const: i2srx_bclk_ext
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+ - const: i2srx_lrck_ext
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+ - const: tdm_ext
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+ - const: mclk_ext
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+
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+ '#clock-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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+
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+ '#reset-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - '#clock-cells'
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+ - '#reset-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ clock-controller@13020000 {
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+ compatible = "starfive,jh7110-syscrg";
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+ reg = <0x13020000 0x10000>;
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+ clocks = <&osc>, <&gmac1_rmii_refin>,
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+ <&gmac1_rgmii_rxin>,
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+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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+ <&tdm_ext>, <&mclk_ext>;
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+ clock-names = "osc", "gmac1_rmii_refin",
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+ "gmac1_rgmii_rxin",
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+ "i2stx_bclk_ext", "i2stx_lrck_ext",
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+ "i2srx_bclk_ext", "i2srx_lrck_ext",
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+ "tdm_ext", "mclk_ext";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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--- /dev/null
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+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
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@@ -0,0 +1,203 @@
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+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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+/*
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+ * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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+
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+/* SYSCRG clocks */
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+#define JH7110_SYSCLK_CPU_ROOT 0
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+#define JH7110_SYSCLK_CPU_CORE 1
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+#define JH7110_SYSCLK_CPU_BUS 2
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+#define JH7110_SYSCLK_GPU_ROOT 3
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+#define JH7110_SYSCLK_PERH_ROOT 4
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+#define JH7110_SYSCLK_BUS_ROOT 5
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+#define JH7110_SYSCLK_NOCSTG_BUS 6
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+#define JH7110_SYSCLK_AXI_CFG0 7
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+#define JH7110_SYSCLK_STG_AXIAHB 8
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+#define JH7110_SYSCLK_AHB0 9
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+#define JH7110_SYSCLK_AHB1 10
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+#define JH7110_SYSCLK_APB_BUS 11
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+#define JH7110_SYSCLK_APB0 12
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+#define JH7110_SYSCLK_PLL0_DIV2 13
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+#define JH7110_SYSCLK_PLL1_DIV2 14
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+#define JH7110_SYSCLK_PLL2_DIV2 15
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+#define JH7110_SYSCLK_AUDIO_ROOT 16
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+#define JH7110_SYSCLK_MCLK_INNER 17
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+#define JH7110_SYSCLK_MCLK 18
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+#define JH7110_SYSCLK_MCLK_OUT 19
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+#define JH7110_SYSCLK_ISP_2X 20
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+#define JH7110_SYSCLK_ISP_AXI 21
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+#define JH7110_SYSCLK_GCLK0 22
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+#define JH7110_SYSCLK_GCLK1 23
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+#define JH7110_SYSCLK_GCLK2 24
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+#define JH7110_SYSCLK_CORE 25
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+#define JH7110_SYSCLK_CORE1 26
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+#define JH7110_SYSCLK_CORE2 27
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+#define JH7110_SYSCLK_CORE3 28
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+#define JH7110_SYSCLK_CORE4 29
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+#define JH7110_SYSCLK_DEBUG 30
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+#define JH7110_SYSCLK_RTC_TOGGLE 31
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+#define JH7110_SYSCLK_TRACE0 32
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+#define JH7110_SYSCLK_TRACE1 33
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+#define JH7110_SYSCLK_TRACE2 34
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+#define JH7110_SYSCLK_TRACE3 35
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+#define JH7110_SYSCLK_TRACE4 36
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+#define JH7110_SYSCLK_TRACE_COM 37
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+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
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+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
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+#define JH7110_SYSCLK_OSC_DIV2 40
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+#define JH7110_SYSCLK_PLL1_DIV4 41
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+#define JH7110_SYSCLK_PLL1_DIV8 42
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+#define JH7110_SYSCLK_DDR_BUS 43
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+#define JH7110_SYSCLK_DDR_AXI 44
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+#define JH7110_SYSCLK_GPU_CORE 45
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+#define JH7110_SYSCLK_GPU_CORE_CLK 46
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+#define JH7110_SYSCLK_GPU_SYS_CLK 47
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+#define JH7110_SYSCLK_GPU_APB 48
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+#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
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+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
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+#define JH7110_SYSCLK_ISP_TOP_CORE 51
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+#define JH7110_SYSCLK_ISP_TOP_AXI 52
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+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
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+#define JH7110_SYSCLK_HIFI4_CORE 54
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+#define JH7110_SYSCLK_HIFI4_AXI 55
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+#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
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+#define JH7110_SYSCLK_AXI_CFG1_AHB 57
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+#define JH7110_SYSCLK_VOUT_SRC 58
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+#define JH7110_SYSCLK_VOUT_AXI 59
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+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
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+#define JH7110_SYSCLK_VOUT_TOP_AHB 61
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+#define JH7110_SYSCLK_VOUT_TOP_AXI 62
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+#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
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+#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
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+#define JH7110_SYSCLK_JPEGC_AXI 65
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+#define JH7110_SYSCLK_CODAJ12_AXI 66
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+#define JH7110_SYSCLK_CODAJ12_CORE 67
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+#define JH7110_SYSCLK_CODAJ12_APB 68
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+#define JH7110_SYSCLK_VDEC_AXI 69
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+#define JH7110_SYSCLK_WAVE511_AXI 70
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+#define JH7110_SYSCLK_WAVE511_BPU 71
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+#define JH7110_SYSCLK_WAVE511_VCE 72
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+#define JH7110_SYSCLK_WAVE511_APB 73
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+#define JH7110_SYSCLK_VDEC_JPG 74
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+#define JH7110_SYSCLK_VDEC_MAIN 75
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+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
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+#define JH7110_SYSCLK_VENC_AXI 77
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+#define JH7110_SYSCLK_WAVE420L_AXI 78
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+#define JH7110_SYSCLK_WAVE420L_BPU 79
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+#define JH7110_SYSCLK_WAVE420L_VCE 80
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+#define JH7110_SYSCLK_WAVE420L_APB 81
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+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
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+#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
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+#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
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+#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
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+#define JH7110_SYSCLK_AXIMEM2_AXI 86
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+#define JH7110_SYSCLK_QSPI_AHB 87
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+#define JH7110_SYSCLK_QSPI_APB 88
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+#define JH7110_SYSCLK_QSPI_REF_SRC 89
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+#define JH7110_SYSCLK_QSPI_REF 90
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+#define JH7110_SYSCLK_SDIO0_AHB 91
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+#define JH7110_SYSCLK_SDIO1_AHB 92
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+#define JH7110_SYSCLK_SDIO0_SDCARD 93
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+#define JH7110_SYSCLK_SDIO1_SDCARD 94
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+#define JH7110_SYSCLK_USB_125M 95
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+#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
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+#define JH7110_SYSCLK_GMAC1_AHB 97
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+#define JH7110_SYSCLK_GMAC1_AXI 98
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+#define JH7110_SYSCLK_GMAC_SRC 99
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+#define JH7110_SYSCLK_GMAC1_GTXCLK 100
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+#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
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+#define JH7110_SYSCLK_GMAC1_PTP 102
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+#define JH7110_SYSCLK_GMAC1_RX 103
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+#define JH7110_SYSCLK_GMAC1_RX_INV 104
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+#define JH7110_SYSCLK_GMAC1_TX 105
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+#define JH7110_SYSCLK_GMAC1_TX_INV 106
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+#define JH7110_SYSCLK_GMAC1_GTXC 107
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+#define JH7110_SYSCLK_GMAC0_GTXCLK 108
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+#define JH7110_SYSCLK_GMAC0_PTP 109
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+#define JH7110_SYSCLK_GMAC_PHY 110
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+#define JH7110_SYSCLK_GMAC0_GTXC 111
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+#define JH7110_SYSCLK_IOMUX_APB 112
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+#define JH7110_SYSCLK_MAILBOX_APB 113
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+#define JH7110_SYSCLK_INT_CTRL_APB 114
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+#define JH7110_SYSCLK_CAN0_APB 115
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+#define JH7110_SYSCLK_CAN0_TIMER 116
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+#define JH7110_SYSCLK_CAN0_CAN 117
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+#define JH7110_SYSCLK_CAN1_APB 118
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+#define JH7110_SYSCLK_CAN1_TIMER 119
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+#define JH7110_SYSCLK_CAN1_CAN 120
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+#define JH7110_SYSCLK_PWM_APB 121
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+#define JH7110_SYSCLK_WDT_APB 122
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+#define JH7110_SYSCLK_WDT_CORE 123
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+#define JH7110_SYSCLK_TIMER_APB 124
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+#define JH7110_SYSCLK_TIMER0 125
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+#define JH7110_SYSCLK_TIMER1 126
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+#define JH7110_SYSCLK_TIMER2 127
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+#define JH7110_SYSCLK_TIMER3 128
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+#define JH7110_SYSCLK_TEMP_APB 129
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+#define JH7110_SYSCLK_TEMP_CORE 130
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+#define JH7110_SYSCLK_SPI0_APB 131
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+#define JH7110_SYSCLK_SPI1_APB 132
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+#define JH7110_SYSCLK_SPI2_APB 133
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+#define JH7110_SYSCLK_SPI3_APB 134
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+#define JH7110_SYSCLK_SPI4_APB 135
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+#define JH7110_SYSCLK_SPI5_APB 136
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+#define JH7110_SYSCLK_SPI6_APB 137
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+#define JH7110_SYSCLK_I2C0_APB 138
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+#define JH7110_SYSCLK_I2C1_APB 139
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+#define JH7110_SYSCLK_I2C2_APB 140
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+#define JH7110_SYSCLK_I2C3_APB 141
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+#define JH7110_SYSCLK_I2C4_APB 142
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+#define JH7110_SYSCLK_I2C5_APB 143
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+#define JH7110_SYSCLK_I2C6_APB 144
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+#define JH7110_SYSCLK_UART0_APB 145
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+#define JH7110_SYSCLK_UART0_CORE 146
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+#define JH7110_SYSCLK_UART1_APB 147
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+#define JH7110_SYSCLK_UART1_CORE 148
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+#define JH7110_SYSCLK_UART2_APB 149
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+#define JH7110_SYSCLK_UART2_CORE 150
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+#define JH7110_SYSCLK_UART3_APB 151
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+#define JH7110_SYSCLK_UART3_CORE 152
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+#define JH7110_SYSCLK_UART4_APB 153
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+#define JH7110_SYSCLK_UART4_CORE 154
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+#define JH7110_SYSCLK_UART5_APB 155
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+#define JH7110_SYSCLK_UART5_CORE 156
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+#define JH7110_SYSCLK_PWMDAC_APB 157
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+#define JH7110_SYSCLK_PWMDAC_CORE 158
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+#define JH7110_SYSCLK_SPDIF_APB 159
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+#define JH7110_SYSCLK_SPDIF_CORE 160
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+#define JH7110_SYSCLK_I2STX0_APB 161
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+#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
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+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
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+#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
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+#define JH7110_SYSCLK_I2STX0_BCLK 165
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+#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
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+#define JH7110_SYSCLK_I2STX0_LRCK 167
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+#define JH7110_SYSCLK_I2STX1_APB 168
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+#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
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+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
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+#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
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+#define JH7110_SYSCLK_I2STX1_BCLK 172
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+#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
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+#define JH7110_SYSCLK_I2STX1_LRCK 174
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+#define JH7110_SYSCLK_I2SRX_APB 175
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+#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
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+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
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+#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
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+#define JH7110_SYSCLK_I2SRX_BCLK 179
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+#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
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+#define JH7110_SYSCLK_I2SRX_LRCK 181
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+#define JH7110_SYSCLK_PDM_DMIC 182
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+#define JH7110_SYSCLK_PDM_APB 183
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+#define JH7110_SYSCLK_TDM_AHB 184
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+#define JH7110_SYSCLK_TDM_APB 185
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+#define JH7110_SYSCLK_TDM_INTERNAL 186
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+#define JH7110_SYSCLK_TDM_TDM 187
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+#define JH7110_SYSCLK_TDM_TDM_INV 188
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+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
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+
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+#define JH7110_SYSCLK_END 190
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+
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+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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--- /dev/null
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+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
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@@ -0,0 +1,142 @@
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+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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+/*
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+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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+
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+/* SYSCRG resets */
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+#define JH7110_SYSRST_JTAG_APB 0
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+#define JH7110_SYSRST_SYSCON_APB 1
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+#define JH7110_SYSRST_IOMUX_APB 2
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+#define JH7110_SYSRST_BUS 3
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+#define JH7110_SYSRST_DEBUG 4
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+#define JH7110_SYSRST_CORE0 5
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+#define JH7110_SYSRST_CORE1 6
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+#define JH7110_SYSRST_CORE2 7
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+#define JH7110_SYSRST_CORE3 8
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+#define JH7110_SYSRST_CORE4 9
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+#define JH7110_SYSRST_CORE0_ST 10
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+#define JH7110_SYSRST_CORE1_ST 11
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+#define JH7110_SYSRST_CORE2_ST 12
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+#define JH7110_SYSRST_CORE3_ST 13
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+#define JH7110_SYSRST_CORE4_ST 14
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+#define JH7110_SYSRST_TRACE0 15
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+#define JH7110_SYSRST_TRACE1 16
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+#define JH7110_SYSRST_TRACE2 17
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+#define JH7110_SYSRST_TRACE3 18
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+#define JH7110_SYSRST_TRACE4 19
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+#define JH7110_SYSRST_TRACE_COM 20
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+#define JH7110_SYSRST_GPU_APB 21
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+#define JH7110_SYSRST_GPU_DOMA 22
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+#define JH7110_SYSRST_NOC_BUS_APB 23
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+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
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+#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
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+#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
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+#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
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+#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
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+#define JH7110_SYSRST_NOC_BUS_DDRC 29
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+#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
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+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
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+
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+#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
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+#define JH7110_SYSRST_AXI_CFG1_AHB 33
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+#define JH7110_SYSRST_AXI_CFG1_MAIN 34
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+#define JH7110_SYSRST_AXI_CFG0_MAIN 35
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+#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
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+#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
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+#define JH7110_SYSRST_DDR_AXI 38
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+#define JH7110_SYSRST_DDR_OSC 39
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+#define JH7110_SYSRST_DDR_APB 40
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+#define JH7110_SYSRST_ISP_TOP 41
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+#define JH7110_SYSRST_ISP_TOP_AXI 42
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+#define JH7110_SYSRST_VOUT_TOP_SRC 43
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+#define JH7110_SYSRST_CODAJ12_AXI 44
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+#define JH7110_SYSRST_CODAJ12_CORE 45
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+#define JH7110_SYSRST_CODAJ12_APB 46
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+#define JH7110_SYSRST_WAVE511_AXI 47
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+#define JH7110_SYSRST_WAVE511_BPU 48
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+#define JH7110_SYSRST_WAVE511_VCE 49
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+#define JH7110_SYSRST_WAVE511_APB 50
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+#define JH7110_SYSRST_VDEC_JPG 51
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+#define JH7110_SYSRST_VDEC_MAIN 52
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+#define JH7110_SYSRST_AXIMEM0_AXI 53
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+#define JH7110_SYSRST_WAVE420L_AXI 54
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+#define JH7110_SYSRST_WAVE420L_BPU 55
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+#define JH7110_SYSRST_WAVE420L_VCE 56
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+#define JH7110_SYSRST_WAVE420L_APB 57
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+#define JH7110_SYSRST_AXIMEM1_AXI 58
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+#define JH7110_SYSRST_AXIMEM2_AXI 59
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+#define JH7110_SYSRST_INTMEM 60
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+#define JH7110_SYSRST_QSPI_AHB 61
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+#define JH7110_SYSRST_QSPI_APB 62
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+#define JH7110_SYSRST_QSPI_REF 63
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+
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+#define JH7110_SYSRST_SDIO0_AHB 64
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+#define JH7110_SYSRST_SDIO1_AHB 65
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+#define JH7110_SYSRST_GMAC1_AXI 66
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+#define JH7110_SYSRST_GMAC1_AHB 67
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+#define JH7110_SYSRST_MAILBOX_APB 68
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+#define JH7110_SYSRST_SPI0_APB 69
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+#define JH7110_SYSRST_SPI1_APB 70
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+#define JH7110_SYSRST_SPI2_APB 71
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+#define JH7110_SYSRST_SPI3_APB 72
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+#define JH7110_SYSRST_SPI4_APB 73
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+#define JH7110_SYSRST_SPI5_APB 74
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+#define JH7110_SYSRST_SPI6_APB 75
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+#define JH7110_SYSRST_I2C0_APB 76
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+#define JH7110_SYSRST_I2C1_APB 77
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+#define JH7110_SYSRST_I2C2_APB 78
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+#define JH7110_SYSRST_I2C3_APB 79
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+#define JH7110_SYSRST_I2C4_APB 80
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+#define JH7110_SYSRST_I2C5_APB 81
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+#define JH7110_SYSRST_I2C6_APB 82
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+#define JH7110_SYSRST_UART0_APB 83
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+#define JH7110_SYSRST_UART0_CORE 84
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+#define JH7110_SYSRST_UART1_APB 85
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+#define JH7110_SYSRST_UART1_CORE 86
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+#define JH7110_SYSRST_UART2_APB 87
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+#define JH7110_SYSRST_UART2_CORE 88
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+#define JH7110_SYSRST_UART3_APB 89
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+#define JH7110_SYSRST_UART3_CORE 90
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+#define JH7110_SYSRST_UART4_APB 91
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+#define JH7110_SYSRST_UART4_CORE 92
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+#define JH7110_SYSRST_UART5_APB 93
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+#define JH7110_SYSRST_UART5_CORE 94
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+#define JH7110_SYSRST_SPDIF_APB 95
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+
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+#define JH7110_SYSRST_PWMDAC_APB 96
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+#define JH7110_SYSRST_PDM_DMIC 97
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+#define JH7110_SYSRST_PDM_APB 98
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+#define JH7110_SYSRST_I2SRX_APB 99
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+#define JH7110_SYSRST_I2SRX_BCLK 100
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+#define JH7110_SYSRST_I2STX0_APB 101
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+#define JH7110_SYSRST_I2STX0_BCLK 102
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+#define JH7110_SYSRST_I2STX1_APB 103
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+#define JH7110_SYSRST_I2STX1_BCLK 104
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+#define JH7110_SYSRST_TDM_AHB 105
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+#define JH7110_SYSRST_TDM_CORE 106
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+#define JH7110_SYSRST_TDM_APB 107
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+#define JH7110_SYSRST_PWM_APB 108
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+#define JH7110_SYSRST_WDT_APB 109
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+#define JH7110_SYSRST_WDT_CORE 110
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+#define JH7110_SYSRST_CAN0_APB 111
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+#define JH7110_SYSRST_CAN0_CORE 112
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+#define JH7110_SYSRST_CAN0_TIMER 113
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+#define JH7110_SYSRST_CAN1_APB 114
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+#define JH7110_SYSRST_CAN1_CORE 115
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+#define JH7110_SYSRST_CAN1_TIMER 116
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+#define JH7110_SYSRST_TIMER_APB 117
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+#define JH7110_SYSRST_TIMER0 118
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+#define JH7110_SYSRST_TIMER1 119
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+#define JH7110_SYSRST_TIMER2 120
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+#define JH7110_SYSRST_TIMER3 121
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+#define JH7110_SYSRST_INT_CTRL_APB 122
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+#define JH7110_SYSRST_TEMP_APB 123
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+#define JH7110_SYSRST_TEMP_CORE 124
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+#define JH7110_SYSRST_JTAG_CERTIFICATION 125
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+
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+#define JH7110_SYSRST_END 126
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+
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+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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