mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-23 15:12:50 +00:00
c98819a9e6
The "/dts-v1/;" identifier is supposed to be present once at the top of a device tree file after the includes have been processed. Like done for other targets recently, put the dts-v1 statement into the top-level SoC-based DTSI files, and remove all other occurences. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
108 lines
1.9 KiB
Plaintext
108 lines
1.9 KiB
Plaintext
/dts-v1/;
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "brcm,bcm6338";
|
|
|
|
aliases {
|
|
pflash = &pflash;
|
|
gpio0 = &gpio0;
|
|
serial0 = &uart0;
|
|
spi0 = &lsspi;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "brcm,bmips3300", "mips,mips4Kc";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
cpu_intc: interrupt-controller {
|
|
#address-cells = <0>;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
memory { device_type = "memory"; reg = <0 0>; };
|
|
|
|
pflash: nor@1fc00000 {
|
|
compatible = "cfi-flash";
|
|
reg = <0x1fc00000 0x400000>;
|
|
bank-width = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ubus@fff00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&periph_intc>;
|
|
|
|
periph_intc: interrupt-controller@fffe000c {
|
|
compatible = "brcm,bcm6345-l1-intc";
|
|
reg = <0xfffe000c 0x8>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <2>;
|
|
};
|
|
|
|
ext_intc: interrupt-controller@fffe0014 {
|
|
compatible = "brcm,bcm6345-ext-intc";
|
|
reg = <0xfffe0014 0x4>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&cpu_intc>;
|
|
interrupts = <3>, <4>, <5>, <6>;
|
|
};
|
|
|
|
gpio0: gpio-controller@fffe0404 {
|
|
compatible = "brcm,bcm6345-gpio";
|
|
reg = <0xfffe0404 4>, <0xfffe040c 4>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <8>;
|
|
};
|
|
|
|
uart0: serial@fffe0300 {
|
|
compatible = "brcm,bcm6345-uart";
|
|
reg = <0xfffe0300 0x18>;
|
|
|
|
interrupt-parent = <&periph_intc>;
|
|
interrupts = <2>;
|
|
|
|
/* clocks = <&periph_clk>; */
|
|
/* clock-names = "refclk"; */
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
lsspi: spi@fffe0c00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "brcm,bcm6348-spi";
|
|
reg = <0xfffe0c00 0x40>;
|
|
interrupts = <1>;
|
|
/* clocks = <&clkctl 9>; */
|
|
};
|
|
};
|
|
};
|