174 lines
3.9 KiB
Diff
174 lines
3.9 KiB
Diff
From 9e8ac4fc7125795ac5e8834aaf454fd45b99c580 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Mon, 25 Jul 2022 10:53:03 +0800
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Subject: [PATCH 46/71] mtd: mtk-snand: add NMBM support for SPL
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Add NMBM support for mtk-snand SPL loader
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mtd/mtk-snand/mtk-snand-spl.c | 127 ++++++++++++++++++++++++++
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1 file changed, 127 insertions(+)
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--- a/drivers/mtd/mtk-snand/mtk-snand-spl.c
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+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c
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@@ -13,12 +13,134 @@
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#include <mtd.h>
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#include <watchdog.h>
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+#include <nmbm/nmbm.h>
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+
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#include "mtk-snand.h"
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static struct mtk_snand *snf;
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static struct mtk_snand_chip_info cinfo;
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static u32 oobavail;
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+#ifdef CONFIG_ENABLE_NAND_NMBM
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+static struct nmbm_instance *ni;
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+
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+static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob,
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+ enum nmbm_oob_mode mode)
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+{
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+ int ret;
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+ bool raw = mode == NMBM_MODE_RAW ? true : false;
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+
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+ if (mode == NMBM_MODE_AUTO_OOB) {
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+ ret = mtk_snand_read_page_auto_oob(snf, addr, buf, oob,
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+ oobavail, NULL, false);
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+ } else {
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+ ret = mtk_snand_read_page(snf, addr, buf, oob, raw);
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+ }
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+
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+ if (ret == -EBADMSG)
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+ return 1;
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+ else if (ret >= 0)
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+ return 0;
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+
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+ return ret;
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+}
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+
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+static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf,
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+ const void *oob, enum nmbm_oob_mode mode)
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+{
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+ bool raw = mode == NMBM_MODE_RAW ? true : false;
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+
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+ if (mode == NMBM_MODE_AUTO_OOB) {
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+ return mtk_snand_write_page_auto_oob(snf, addr, buf, oob,
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+ oobavail, NULL, false);
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+ }
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+
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+ return mtk_snand_write_page(snf, addr, buf, oob, raw);
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+}
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+
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+static int nmbm_lower_erase_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_erase_block(snf, addr);
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+}
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+
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+static int nmbm_lower_is_bad_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_block_isbad(snf, addr);
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+}
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+
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+static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr)
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+{
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+ return mtk_snand_block_markbad(snf, addr);
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+}
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+
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+static void nmbm_lower_log(void *arg, enum nmbm_log_category level,
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+ const char *fmt, va_list ap)
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+{
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+ vprintf(fmt, ap);
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+}
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+
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+static int nmbm_init(void)
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+{
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+ struct nmbm_lower_device nld;
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+ size_t ni_size;
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+ int ret;
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+
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+ memset(&nld, 0, sizeof(nld));
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+
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+ nld.flags = NMBM_F_CREATE;
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+ nld.max_ratio = CONFIG_NMBM_MAX_RATIO;
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+ nld.max_reserved_blocks = CONFIG_NMBM_MAX_BLOCKS;
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+
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+ nld.size = cinfo.chipsize;
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+ nld.erasesize = cinfo.blocksize;
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+ nld.writesize = cinfo.pagesize;
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+ nld.oobsize = cinfo.sparesize;
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+ nld.oobavail = oobavail;
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+
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+ nld.read_page = nmbm_lower_read_page;
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+ nld.write_page = nmbm_lower_write_page;
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+ nld.erase_block = nmbm_lower_erase_block;
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+ nld.is_bad_block = nmbm_lower_is_bad_block;
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+ nld.mark_bad_block = nmbm_lower_mark_bad_block;
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+
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+ nld.logprint = nmbm_lower_log;
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+
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+ ni_size = nmbm_calc_structure_size(&nld);
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+ ni = malloc(ni_size);
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+ if (!ni) {
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+ printf("Failed to allocate memory (0x%u) for NMBM instance\n",
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+ ni_size);
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+ return -ENOMEM;
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+ }
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+
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+ memset(ni, 0, ni_size);
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+
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+ printf("Initializing NMBM ...\n");
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+
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+ ret = nmbm_attach(&nld, ni);
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+ if (ret) {
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+ ni = NULL;
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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+{
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+ size_t retlen;
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+
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+ if (!ni)
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+ return -ENODEV;
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+
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+ nmbm_read_range(ni, offs, size, dst, NMBM_MODE_PLACE_OOB, &retlen);
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+ if (retlen != size)
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+ return -EIO;
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+
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+ return 0;
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+}
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+
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+#else
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static u8 *page_cache;
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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@@ -60,6 +182,7 @@ int nand_spl_load_image(uint32_t offs, u
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return ret;
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}
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+#endif
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void nand_init(void)
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{
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@@ -105,11 +228,15 @@ void nand_init(void)
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printf("SPI-NAND: %s (%uMB)\n", cinfo.model,
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(u32)(cinfo.chipsize >> 20));
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+#ifdef CONFIG_ENABLE_NAND_NMBM
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+ nmbm_init();
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+#else
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page_cache = malloc(cinfo.pagesize + cinfo.sparesize);
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if (!page_cache) {
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mtk_snand_cleanup(snf);
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printf("mtk-snand-spl: failed to allocate page cache\n");
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}
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+#endif
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}
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void nand_deselect(void)
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